A communication configuration method, apparatus, device, system, program product, and medium

Abstract

The application discloses a communication configuration method, device, equipment, system, program product and medium, and relates to the technical field of communication, and the method comprises the following steps: a first device acquires a first delay information report message sent by a second device through a PCIe link; the first delay information report message comprises protocol stack processing delay and system response time of the second device; according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message, the transaction concurrency capability of the first device is determined; according to the transaction concurrency capability, the system resources corresponding to the peripheral component interconnect express link in the first device are configured; in the application, the PCIe transaction round-trip delay between the first device and the second device can be accurately determined, and then the required transaction concurrency capability can be accurately determined and matched with corresponding system resources, so that the system resource configuration is optimized on the basis of ensuring the efficiency of the PCIe link.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a communication configuration method and device, a peripheral component interconnect express (PCIe) device, a PCIe system, a computer program product and a computer readable medium. BACKGROUND

[0002] At present, with excellent performance and innovative serial connection mechanism, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) technology has become a general standard for connecting computer hardware devices; with the advantages of high performance, low delay and flexibility, it has established itself as the mainstream interface in the field of data transmission. The application range of PCIe technology is extremely wide, covering solid state drives (SSDs), graphics processing units (GPUs), network interface cards (NICs) and other devices, providing powerful data transmission capabilities for modern computer systems.

[0003] The outstanding transaction feature is one of the key mechanisms in PCIe technology for improving data transmission efficiency and reducing delay. By allowing PCIe devices to continue sending new transactions while waiting for responses, reducing idle time and improving bus utilization, higher throughput and lower latency are achieved, meeting the needs of modern computer systems for high-speed data transmission. As shown in Figure 1 For example, in the example, the transaction concurrency capability of device S is n, which can be considered as the number of PCIe read transactions (MRd) initiated by device S consecutively before receiving the response message Cpld from device T. Usually, in order to fully utilize the bandwidth provided by the PCIe bus physical link and reduce link idle time, designers expect the transaction concurrency capability n of device S to be large enough to offset the round-trip delay between device S and device T. However, in related technologies, it is difficult to accurately determine the transaction concurrency capability of PCIe devices, resulting in problems such as waste of PCIe link resources, and idle and waste of system resources.

[0004] Therefore, how to accurately determine the transaction concurrency capability of PCIe devices, ensure the efficiency of PCIe links and optimize the configuration of system resources is a problem that needs to be solved urgently. SUMMARY

[0005] The purpose of the present application is to provide a communication configuration method and device, a peripheral component interconnect express (PCIe) device, a PCIe system, a computer program product and a computer readable medium, to accurately determine the transaction concurrency capability of PCIe devices, ensure the efficiency of PCIe links and optimize the configuration of system resources.

[0006] To solve the above technical problems, the application provides a communication configuration method, comprising:

[0007] The first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link; wherein the first device and the second device are both peripheral component interconnect express devices, and the first latency information report message comprises protocol stack processing latency and system response time of the second device;

[0008] According to the protocol stack processing latency and system response time of the first device and the protocol stack processing latency and system response time of the second device in the first latency information report message, the transaction concurrency capability of the first device is determined;

[0009] According to the transaction concurrency capability, system resources corresponding to the peripheral component interconnect express link in the first device are configured; wherein the system resources comprise at least one of buffer size, transaction tag number, lookup table specification and driver queue number.

[0010] In another aspect, the first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link, comprising:

[0011] The first device sends a second latency information report message to the second device through the peripheral component interconnect express link; wherein the second latency information report message comprises protocol stack processing latency and system response time of the first device, and the first device is a latency information report initiator;

[0012] The first latency information report message returned by the second device is received.

[0013] In another aspect, the first device sends a second latency information report message to the second device through the peripheral component interconnect express link, comprising:

[0014] After the first device and the second device enter a normal working state, the first device sends the second latency information report message to the second device through the peripheral component interconnect express link.

[0015] In another aspect, after the first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link, further comprising:

[0016] The first device returns a second latency information report message to the second device through the peripheral component interconnect express link; wherein the second latency information report message comprises protocol stack processing latency and system response time of the first device, and the second device is a latency information report initiator.

[0017] In another aspect, the first latency information report message is a data packet in the form of a message transaction layer packet or a data link layer packet of a peripheral component interconnect express protocol.

[0018] In another aspect, when the first latency information report message is a data packet in the form of the message transaction layer packet, the first latency information report message comprises: a protocol stack processing latency field, a system response time field, and a protocol definition field; wherein the protocol definition field comprises at least one of a data packet format field, a data packet type field, a transaction class field, a message transaction layer packet digest field, an error identification field, a property field, an additional transaction type field, a length field, a requester identification field, a transaction tag field, and a message encoding field.

[0019] In another aspect, the first latency information report message is a 16-byte data packet, and the first latency information report message further comprises a reserved bit field.

[0020] In another aspect, the first 4 bytes of the first latency information report message comprise the data packet format field, the data packet type field, the transaction class field, the message transaction layer packet digest field, the error identification field, the property field, the additional transaction type field, and the length field, the 5th to 8th bytes of the first latency information report message comprise the requester identification field, the transaction tag field, and the message encoding field, the 9th to 12th bytes of the first latency information report message comprise the protocol stack processing latency field and the system response time field, and the 13th to 16th bytes of the first latency information report message comprise the reserved bit field.

[0021] In another aspect, the data packet format field is binary 001; the data packet type field is binary 10100, the transaction class field is 0, the property field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message encoding field is binary 00010100.

[0022] In another aspect, the first device obtains a first latency information report message sent by a second device through a peripheral component interconnect express link, comprising:

[0023] The first device obtains the first latency information report message sent by the second device through the peripheral component interconnect express link at a preset time interval.

[0024] In another aspect, the determining the transactional concurrency capability of the first device according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device comprises:

[0025] determining a transactional round-trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device;

[0026] determining the transactional concurrency capability of the first device according to the transactional round-trip delay and the number of lanes, single-lane transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component interconnect express link obtained.

[0027] In another aspect, the determining a transactional round-trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device comprises:

[0028] calculating the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain the transactional round-trip delay.

[0029] In another aspect, the determining the transactional concurrency capability of the first device according to the transactional round-trip delay and the number of lanes, single-lane transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component interconnect express link obtained comprises:

[0030] calculating the transactional concurrency capability of the first device by ; wherein, R link is the single-lane transmission rate, N lane is the number of lanes, L t is the transactional round-trip delay, E enc is the physical layer coding efficiency, S packet is the transaction layer packet length, and a is a preset parameter.

[0031] In another aspect, the calculating the transactional concurrency capability of the first device by comprises:

[0032] the calculation result of is rounded up to obtain the transactional concurrency capability of the first device.

[0033] In another aspect, the unit of the transaction layer packet length is byte, and a is 8.

[0034] The application further provides a communication configuration device applied to a first device, comprising:

[0035] The acquisition module is configured to receive a first delay information report message sent by a second device through a peripheral component interconnect express link, wherein the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message comprises protocol stack processing delay and system response time of the second device.

[0036] The determination module is configured to determine transaction concurrency capability of the first device according to protocol stack processing delay and system response time of the first device and protocol stack processing delay and system response time of the second device in the first delay information report message.

[0037] The configuration module is configured to configure system resources corresponding to the peripheral component interconnect express link in the first device according to the transaction concurrency capability, wherein the system resources comprise at least one of buffer size, transaction tag number, lookup table specification and driver queue number.

[0038] The application further provides a peripheral component interconnect express device, comprising:

[0039] The memory is configured to store a computer program.

[0040] The processor is configured to execute the computer program to realize steps of the communication configuration method.

[0041] The application further provides a peripheral component interconnect express system, comprising a first peripheral component interconnect express device and a second peripheral component interconnect express device.

[0042] The first peripheral component interconnect express device and the second peripheral component interconnect express device are connected through a peripheral component interconnect express bus, and the first peripheral component interconnect express device and the second peripheral component interconnect express device are both the peripheral component interconnect express device.

[0043] The application further provides a computer program product, comprising computer program / instruction, which realizes steps of the communication configuration method when executed by a processor.

[0044] In addition, the application further provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes steps of the communication configuration method when executed by a processor.

[0045] The communication configuration method provided by the application comprises the following steps: a first device acquires a first delay information report message sent by a second device through a peripheral component interconnect express link; wherein, the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message comprises protocol stack processing delay and system response time of the second device; the transaction concurrency capability of the first device is determined according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device in the first delay information report message; and the system resource corresponding to the peripheral component interconnect express link in the first device is configured according to the transaction concurrency capability; wherein, the system resource comprises at least one of buffer size, transaction tag number, lookup table specification and driver queue number.

[0046] It can be seen that, by acquiring the first delay information report message sent by the second device through the peripheral component interconnect express link, the first device can acquire the protocol stack processing delay and system response time of the second device, so that the first device can obtain the accurate PCIe transaction round-trip delay with the second device, and then accurately determine the required transaction concurrency capability and match the corresponding system resource, which can optimize the configuration of the system resource on the basis of ensuring the efficiency of the PCIe link and avoid the idling and waste of the system resource. In addition, the application also provides a communication configuration device, a peripheral component interconnect express device, a peripheral component interconnect express system, a computer program product and a computer readable medium, which also have the above beneficial effects. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute the embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.

[0048] Figure 1 It is a schematic diagram of a PCIe read transaction concurrency process;

[0049] Figure 2 It is a flow chart of the communication configuration method provided by the embodiment of the application;

[0050] Figure 3 It is a flow chart of another communication configuration method provided by the embodiment of the application;

[0051] Figure 4 It is a schematic diagram of a LIR message format provided by the embodiment of the application;

[0052] Figure 5An application diagram of the LIR mechanism of another communication configuration method provided by the embodiment of the present application is shown in FIG. 1.

[0053] Figure 6 A structure diagram of a communication configuration device provided by the embodiment of the present application is shown in FIG. 2.

[0054] Figure 7 A simple structure diagram of a peripheral component interconnect express device provided by the embodiment of the present application is shown in FIG. 3.

[0055] Figure 8 A specific structure diagram of a peripheral component interconnect express device provided by the embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0057] In the related art, the relationship between the transaction concurrency capability O n and the transaction round-trip delay L t can be represented by the following formula:

[0058] ;

[0059] wherein, O n may represent the concurrency number of outstanding transactions, i.e., the transaction concurrency capability; R link may represent the single-channel transmission rate of the PCIe physical link; N lane may represent the number of channels of the PCIe physical link; L t may represent the round-trip delay of the transaction (i.e., the transaction round-trip delay), such as in units of nanoseconds (ns); E enc may represent the physical layer coding efficiency of the PCIe, such as the physical layer coding efficiency of 8b / 10b coding can be 0.8, and the physical layer coding efficiency of 128b / 130b coding can be approximately 1 (i.e., 100%); S packet may represent the TLP (Transaction Layer Packet, transaction layer packet) data packet length (i.e., the data packet size), such as in units of bytes.

[0060] According to the above formula, the transaction concurrency capability required for different round-trip delays under a typical PCIe bus configuration can be calculated, and the results are shown in Table 1 below. It is obvious that as the transaction round-trip delay between two PCIe devices (such as device S and device T in Figure 1 , increases, the transaction concurrency capability (i.e., the number of transaction concurrency) required also increases. This is because a larger transaction round-trip delay means that the data packet needs more time to complete a round trip, so the system needs to maintain more unfinished transactions to maintain the continuity of the data flow.

[0061] Table 1: Transaction concurrency capability required for a typical PCIe bus configuration

[0062]

[0063] It has been found through experiments that after the completion of PCIe link training, the single-channel transmission rate, channel number, data packet length, and coding efficiency of the PCIe link are determined; however, the transaction round-trip delay of PCIe can still be affected by the following main factors: 1) bus transmission delay: the transmission time of the data packet on the PCIe bus, which is related to the PCIe physical rate, the number of channels, and the length of the transmitted data packet, etc. 2) protocol stack processing delay: the PCIe protocol stack is divided into application layer, transaction layer, data link layer, and physical layer according to function, each layer has its specific function and responsibility; different manufacturers design and implement PCIe controllers according to the PCIe protocol hierarchy, resulting in significant differences in processing delay of each layer; the protocol stack processing delay can cover both ends of the link PCIe devices, such as device S (i.e., the source device) and device T (i.e., the target device) in Figure 1 ; 3) target device system response delay: the bus transmission and DDR (memory) access delay of the target system where the PCIe controller is located together constitute the system response delay of the target device. 4) PCIe system connection topology: the round-trip delay of the switch (Switch), re-timer (Retimer), and other system components between the two ends of the PCIe device.

[0064] In summary, the transaction round-trip delay is closely related to the device deployment environment; the same PCIe device deployed in different PCIe systems may have a large difference in transaction round-trip delay. In the related art, there is a lack of an effective means to accurately measure the transaction round-trip delay, so that the designer usually estimates the transaction round-trip delay in advance according to a relatively conservative scenario in the system design stage to ensure the bandwidth and utilization of the PCIe link; the greater the estimated transaction round-trip delay, the higher the transaction concurrency capability that the PCIe device needs to support, and the more system resources (such as buffer, lookup table and driver queue, etc.) required by the PCIe protocol stack and the system. This prediction method has certain limitations: if the estimated transaction round-trip delay is less than the actual deployment environment, the PCIe link bandwidth cannot be fully utilized, the system optimal performance cannot be achieved, and the PCIe link resources are wasted; if the estimated transaction round-trip delay is greater than the actual deployment environment, it may lead to idle and waste of system resources, and increase the cost of hardware ownership.

[0065] Therefore, the embodiment of the application accurately calculates the transaction round-trip delay of the PCIe, so that the PCIe device can accurately determine the required transaction concurrency capability and match the corresponding system resources, thereby realizing the optimal configuration of the system resources on the basis of ensuring the efficiency of the PCIe link.

[0066] Specifically, please refer to Figure 2 , Figure 2 The flowchart of a communication configuration method provided by the embodiment of the application. The method can include:

[0067] Step 101: The first device acquires the first delay information report message sent by the second device through the peripheral component interconnect express link; wherein the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message includes the protocol stack processing delay of the second device and the system response time.

[0068] It can be understood that the first device and the second device in the embodiment can both be PCIe devices, and the first device and the second device can be connected through a PCIe link. The first delay information report message in the embodiment can be a latency information report (LIR) message sent by the second device to the first device through the PCIe link. The first device can acquire the protocol stack processing delay of the second device and the system response time by receiving the first delay information report message sent by the second device, so that the first device can acquire the accurate transaction round-trip delay with the second device to accurately determine the transaction concurrency capability.

[0069] Among them, the protocol stack processing latency can be the cumulative processing latency of the PCIe controller integrated in the PCIe device at the physical layer, data link layer, transaction layer, and application layer; the system response time can be the sum of the transmission latency of the system bus and the memory access latency corresponding to the PCIe device.

[0070] Correspondingly, the specific method by which the first device obtains the first delay information report message sent by the second device through the peripheral component fast interconnect link in this embodiment can be set by the designer according to the practical scenario and user needs. For example, in order to enable the PCIe devices at both ends of the PCIe link to accurately determine the transaction concurrency capability of their respective PCIe transactions, a new LIR mechanism can be adopted in this embodiment, that is, a mechanism that allows PCIe devices to exchange delay information (such as protocol stack processing delay and system response time). For example, the first device, as the LIR initiator, sends the second delay information report message to the second device through the peripheral component fast interconnect link in this step; and receives the first delay information report message returned by the second device; wherein, the second delay information report message includes the protocol stack processing delay and system response time of the first device; the second delay information report message can be an LIR message sent by the first device to the second device through the PCIe link. In other words, the first device can act as the LIR initiator, first sending an LIR message (i.e., the second delay information report message) to the second device to inform the second device of its own protocol stack processing delay and system response time; then, it receives the LIR message (i.e., the first delay information report message) returned by the second device to obtain the second device's protocol stack processing delay and system response time.

[0071] Correspondingly, when the second device acts as the LIR initiator, the first device can directly receive the first delay information report message sent by the second device through the PCIe link; after receiving the first delay information report message, the first device can also return a second delay information report message to the second device through the PCIe link to inform the second device of its own protocol stack processing delay and system response time.

[0072] For example, such as Figure 3 As shown, after completing the link training and link negotiation defined in the specification, a PCIe device (such as the first or second device) can enter the normal operating state (L0 state). At this time, both the physical layer and the data link layer are in a ready state, and the PCIe device can begin normal data transmission. Afterwards, the PCIe device can send LIR messages to the peer device (i.e., the second or first device) through the PCIe link. These LIR messages include the protocol stack processing latency and system response time of the PCIe device. The PCIe device also receives LIR messages from the peer device, which include the protocol stack processing latency and system response time of the peer device.

[0073] In some embodiments, the first device can send a second delay information report message to the second device and receive a first delay information report message sent by the second device after entering the normal working state. That is, the PCIe device at one end of the PCIe link can send a LIR message to the device at the other end of the PCIe link to send its protocol stack processing delay and system response time to the device at the other end of the PCIe link after entering the normal working state (L0 state) after the link negotiation.

[0074] It should be noted that the specific data type and content of the first delay information report message in the present embodiment can be set by the designer according to the use scenario and user demand, such as the LIR message (such as the first delay information report message and the second delay information report message) can be a data packet in the form of a Message TLP (Transaction Layer Packet) or a DLLP (Data Link Layer Packet) of the PCIe protocol, that is, the first delay information report message and the second delay information report message can be transmitted in the form of a Message TLP or a DLLP defined by the PCIe specification.

[0075] For example, when the LIR message (such as the first delay information report message) is a data packet in the form of a Message TLP (message transaction layer packet) of the PCIe protocol, the first delay information report message includes a protocol stack processing delay field, a system response time field, and a protocol definition field; wherein the protocol stack processing delay field can be a field for storing the protocol stack processing delay, the system response time field can be a field for storing the system response time, and the protocol definition field can be other definition fields of the Message TLP of the PCIe protocol; such as the protocol definition field can include at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field, and a message coding field; such as Figure 4 As shown, the protocol definition field can include a data packet format field (Fmt), a data packet type field (Type), a transaction category field (TC), a message transaction layer packet summary field (TD), an error identification field (EP), an attribute field (Attr), an additional transaction type field (AT), a length field (Length), a requester identification field (Requester ID), a transaction tag field (Tag), a message coding field (Message Code), and a reserved bit field (R, Rsv, and Reserved).

[0076] As shown in Figure 4As shown, the packet format field (Fmt) in the LIR message can be set to a preset identifier without data load, such as Figure 4 binary 001 (i.e., 001b) for indicating that the LIR message is a message type request without data load. The packet type field (Type) in the LIR message can be a preset message request identifier, such as Figure 4 binary 10100 (i.e., 10100b) for indicating that the LIR message is a message request and is routed in a Local-Terminated at Receiver manner defined in the PCIe specification. The transaction class field (TC) in the LIR message can be set to 0, such as Figure 4 binary 000. The message transaction layer packet digest field (TD) in the LIR message can be used to indicate whether the TLP level data check is enabled. The poisoned identifier field (EP) in the LIR message can be used to indicate that the current TLP has been damaged or become invalid due to some error condition. The attribute field (Attr) in the LIR message can be used to define the additional characteristics of the TLP, which can be set to 0 in the embodiment, such as Figure 4 binary 000. The additional transaction type field (AT) in the LIR message can be used to specify the specific type of the message, which can be set to 0 in the embodiment, such as Figure 4 binary 00. The length field (Length) in the LIR message in the embodiment can be set to 0, such as binary 0000000000. The requester identifier field (Requester ID) in the LIR message can be used to represent the device identifier initiating the transaction.

[0077] Correspondingly, since the message request is a special type of transaction, it does not need to be confirmed or completed, the transaction tag field (Tag) in the LIR message in the embodiment can be set to 0, such as binary 00000000. The message code field (Message Code) in the LIR message in the embodiment can be a preset LIR message identifier, such as Figure 4The binary 00010100 indicates that the current data packet is an LIR message frame. The protocol stack processing latency field in the LIR message (United Stak Latency) can be used to record the latency of the PCIe protocol stack processing request of the PCIe device (i.e., the protocol stack processing latency), which can be in nanoseconds. The system response time field in the LIR message (System Response Latency) is used to record the response time of the system in which the PCIe device is located to the request (i.e., the system response time), which can be in nanoseconds.

[0078] Correspondingly, as shown in Figure 4 The LIR message (such as the first latency information report message) can be a 16-byte data packet in the form of a Message TLP of the PCIe protocol. The first byte to the fourth byte in the first latency information report message includes a data packet format field, a data packet type field, a transaction class field, a message transaction layer packet digest field, an error identification field, an attribute field, an additional transaction type field, and a length field. The fifth byte to the eighth byte in the first latency information report message includes a requester identification field, a transaction tag field, and a message code field. The ninth byte to the twelfth byte in the first latency information report message includes a protocol stack processing latency field and a system response time field. The thirteenth byte to the sixteenth byte in the first latency information report message includes a reserved bit field (Reserved).

[0079] Further, in the embodiment, the first device can obtain the first latency information report message sent by the second device through the peripheral component interconnect express link at a preset time interval, so that the PCIe device can dynamically adjust its operation according to real-time latency information to adapt to different latency conditions. For example, after the first device enters a normal working state (L0 state), the first device can obtain the first latency information report message sent by the second device through the peripheral component interconnect express link at a preset time interval to update the transaction concurrency capability of the first device and adjust the system resources of the PCIe link.

[0080] Step 102: determining the transaction concurrency capability of the first device according to the protocol stack processing latency and the system response time of the first device and the protocol stack processing latency and the system response time of the second device in the first latency information report message.

[0081] It can be understood that in this step, the first device can determine the transaction round-trip latency of the PCIe transaction according to the protocol stack processing latency and the system response time of the first device and the protocol stack processing latency and the system response time of the second device in the first latency information report message, and accurately determine the transaction concurrency capability of the PCIe link required by the first device.

[0082] Correspondingly, for the specific manner of determining the transaction concurrency capability of the first device according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device in the first delay information report message in this step, the designer can set it according to the practical scene and user demand, for example, the first device can determine the transaction round-trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device; and determine the transaction concurrency capability of the first device according to the transaction round-trip delay and the number of lanes, single-lane transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component interconnect express link obtained.

[0083] In this embodiment, the specific manner of obtaining the protocol stack processing delay and system response time of the first device and the number of lanes, single-lane transmission rate, physical layer coding efficiency and transaction layer packet length of the PCIe link with the second device by the first device can be set by the designer according to the use scene and user demand, for example, the same or similar way as the link negotiation and delay acquisition method of the PCIe link in the related art can be adopted, as long as the PCIe device can obtain its own protocol stack processing delay and system response time and the number of lanes, single-lane transmission rate, physical layer coding efficiency and transaction layer packet length of the PCIe link, this embodiment does not make any limitation.

[0084] Correspondingly, for the specific manner of determining the transaction round-trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device, the designer can set it, for example, the first device can calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain the transaction round-trip delay; that is, the first device can directly add the sum of the protocol stack processing delay and system response time of the first device to the sum of the protocol stack processing delay and system response time of the second device to obtain the transaction round-trip delay; for example, Figure 5 As shown in the table, the protocol stack processing delay and system response delay of device A (i.e. the first device) are 850ns and 500ns respectively, the protocol stack processing delay and system response delay of device B (i.e. the second device) are 600ns and 750ns respectively, and the transaction round-trip delay L t may be 850+500 +600+750= 2700ns. The first device can also calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain the accumulated result; and calculate the product of the accumulated result and the preset delay calculation parameter to obtain the transaction round-trip delay. This embodiment does not make any limitation.

[0085] Correspondingly, the specific manner of determining the transaction concurrency capability of the first device according to the transaction round-trip delay and the number of channels, the single-channel transmission rate, the physical layer coding efficiency and the transaction layer packet length of the peripheral component interconnect express link obtained above can be set by the designer according to the practical scene and user demand, for example, the first device can calculate the transaction concurrency capability of the first device by ; wherein, R link is the single-channel transmission rate, N lane is the number of channels, L t is the transaction round-trip delay, E enc is the physical layer coding efficiency, S packet is the transaction layer packet length, and a is a preset parameter, for example, when the unit of the transaction layer packet length is byte, a can be 8. For example, the first device can round up the calculation result of to obtain the transaction concurrency capability of the first device; the first device can also round or round down the calculation result to obtain the transaction concurrency capability of the first device; the first device can also directly take the calculation result as the transaction concurrency capability of the first device. This embodiment does not make any limitation in this regard.

[0086] For example, as shown in Figure 5 , after the device A (i.e. the first device) and the device B (i.e. the second device) complete the link training and link negotiation of the peripheral component interconnect express link, the final negotiated link configuration can be: the physical link rate (i.e. the single-channel transmission rate R link ) is 8 Gbps; the encoding mode is 128b / 130b, i.e. the physical layer coding efficiency E enc can be 1; the link width is 4 channels, i.e. the number of channels N lane is 4; the maximum data packet load (Max Payload Size) is 512 bytes, i.e. the transaction layer packet length S packet is 512 bytes. The protocol stack processing delay and the system response delay of the device A are 850 ns and 500 ns respectively, and the protocol stack processing delay and the system response delay of the device B are 600 ns and 750 ns respectively; the transaction round-trip delay L t of the peripheral component interconnect express link between the device A and the device B can be calculated to be 2700 ns. Through , the transaction concurrency capability O n can be calculated to be 21, and the device A and the device B can match the required system resources according to the calculated transaction concurrency capability O n , so as to not only fully utilize the current physical link resources, but also optimize the system resources and reduce the total cost of ownership.

[0087] It should be noted that the second device in this embodiment can also determine the transaction concurrency capability of the PCIe link required by the second device itself to correspondingly configure the system resources of the second device. For example, the second device can determine the transaction concurrency capability of the second device according to the protocol stack processing delay and system response time of the second device and the protocol stack processing delay and system response time of the second device in the received second delay information report message. The second device can also receive the transaction concurrency capability of the first device sent by the first device and take the transaction concurrency capability of the first device as the transaction concurrency capability of the second device. Correspondingly, after step 102, the first device can send the determined transaction concurrency capability of the first device to the second device. This embodiment does not make any limitation on this.

[0088] Step 103: According to the transaction concurrency capability, configure the system resources corresponding to the peripheral component interconnect link in the first device; wherein the system resources include at least one of the buffer size, the number of transaction tag numbers, the lookup table specification and the number of driver queues.

[0089] It can be understood that in this step, the first device can configure the resources (i.e. system resources) required by the PCIe system in the first device according to the determined transaction concurrency capability, so as to realize the optimal configuration of the system resources. The specific types of the system resources configured in this step can be set by the designer according to the practical scene and user demand, for example, the same or similar method as the system resource configuration method in the related art can be used, for example, the system resources can include the buffer size, the number of Tag (transaction tag) numbers, the lookup table specification and the number of driver queues.

[0090] Correspondingly, the specific way in which the first device configures the system resources corresponding to the peripheral component interconnect link in the first device according to the transaction concurrency capability in this step can be set by the designer, for example, the first device can match the corresponding system resources and configure them by using the determined transaction concurrency capability according to the pre-set correspondence between each preset transaction concurrency number and the system resources.

[0091] In this embodiment, the first device of the embodiment of the present application acquires the first delay information report message sent by the second device through the peripheral component interconnect link, so that the first device can acquire the protocol stack processing delay and system response time of the second device, thereby enabling the first device to obtain the accurate PCIe transaction round-trip delay between the first device and the second device, and further accurately determine the required transaction concurrency capability and match the corresponding system resources, which can optimize the configuration of the system resources on the basis of ensuring the efficiency of the PCIe link and avoid the idling and waste of the system resources.

[0092] Corresponding to the above method embodiments, the embodiments of the present application also provide a communication configuration device. The communication configuration device described below can be correspondingly referred to the communication configuration method described above.

[0093] Please refer to Figure 6 , Figure 6 A structural block diagram of a communication configuration device provided by the embodiments of the present application is shown in FIG. 1. The device is applied to a first device and can include:

[0094] The obtaining module 10 is configured to receive a first latency information report message sent by a second device through a peripheral component interconnect express link, wherein the first device and the second device are both peripheral component interconnect express devices, and the first latency information report message includes protocol stack processing latency and system response time of the second device.

[0095] The determining module 20 is configured to determine transaction concurrency capability of the first device according to the protocol stack processing latency and the system response time of the first device and the protocol stack processing latency and the system response time of the second device in the first latency information report message.

[0096] The configuration module 30 is configured to configure system resources corresponding to the peripheral component interconnect express link in the first device according to the transaction concurrency capability, wherein the system resources include at least one of buffer size, transaction tag number, lookup table specification and driver queue number.

[0097] In some embodiments, the obtaining module 10 can include:

[0098] The sending sub-module is configured to send a second latency information report message to the second device through the peripheral component interconnect express link, wherein the second latency information report message includes the protocol stack processing latency and the system response time of the first device, and the first device is a latency information report initiator.

[0099] The receiving sub-module is configured to receive the first latency information report message returned by the second device.

[0100] In some embodiments, the sending sub-module can be specifically configured to send the second latency information report message to the second device through the peripheral component interconnect express link by the first device after the first device and the second device enter a normal working state.

[0101] In some embodiments, the device can further include:

[0102] The sending module is configured to return a second latency information report message to the second device through the peripheral component interconnect express link, wherein the second latency information report message includes the protocol stack processing latency and the system response time of the first device, and the second device is a latency information report initiator.

[0103] In some embodiments, the first latency information report message is a data packet in the form of a message transaction layer packet or a data link layer packet adopting a peripheral component interconnect protocol.

[0104] In some embodiments, when the first latency information report message is a data packet in the form of a message transaction layer packet, the first latency information report message comprises: a protocol stack processing latency field, a system response time field and a protocol definition field; wherein the protocol definition field comprises at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet digest field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field and a message coding field.

[0105] In some embodiments, the first latency information report message is a 16-byte data packet, and the first latency information report message further comprises a reserved bit field.

[0106] In some embodiments, the first 4 bytes of the first latency information report message comprise the data packet format field, the data packet type field, the transaction category field, the message transaction layer packet digest field, the error identification field, the attribute field, the additional transaction type field and the length field, the 5th to 8th bytes of the first latency information report message comprise the requester identification field, the transaction tag field and the message coding field, the 9th to 12th bytes of the first latency information report message comprise the protocol stack processing latency field and the system response time field, and the 13th to 16th bytes of the first latency information report message comprise the reserved bit field.

[0107] In some embodiments, the data packet format field is binary 001; the data packet type field is binary 10100, the transaction category field is 0, the attribute field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message coding field is binary 00010100.

[0108] In some embodiments, the obtaining module 10 can be specifically configured to obtain, by the first device, the first latency information report message sent by the second device through the peripheral component interconnect link at a preset time interval.

[0109] In some embodiments, the determining module 20 can comprise:

[0110] a latency determining sub-module configured to determine a transaction round-trip latency according to the protocol stack processing latency and the system response time of the first device and the protocol stack processing latency and the system response time of the second device.

[0111] The concurrent determination submodule is configured to determine the transaction concurrent capability of the first device according to the transaction round-trip delay and the obtained number of channels, single-channel transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component interconnect express link.

[0112] In some embodiments, the delay determination submodule can be specifically configured to calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device, to obtain the transaction round-trip delay.

[0113] In some embodiments, the concurrent determination submodule can be specifically configured to calculate the transaction concurrent capability of the first device by ; wherein, R link is the single-channel transmission rate, N lane is the number of channels, L t is the transaction round-trip delay, E enc is the physical layer coding efficiency, S packet is the transaction layer packet length, and a is a preset parameter.

[0114] The concurrent determination submodule can be specifically configured to round up the calculation result of to obtain the transaction concurrent capability of the first device.

[0115] In some embodiments, the unit of the transaction layer packet length is byte, and a is 8.

[0116] In this embodiment, the first device obtains the first delay information report message sent by the second device through the peripheral component interconnect express link through the obtaining module 10, so that the first device can obtain the protocol stack processing delay and system response time of the second device, thereby enabling the first device to obtain the accurate PCIe transaction round-trip delay with the second device, and accurately determine the required transaction concurrent capability and match the corresponding system resources, so as to optimize the configuration of system resources on the basis of ensuring the efficiency of the PCIe link and avoid the idling and waste of system resources.

[0117] Corresponding to the above method embodiment, the embodiment of the present application also provides a peripheral component interconnect express (PCIe) device. The peripheral component interconnect express device described below can be correspondingly referred to the communication configuration method described above.

[0118] Please refer to Figure 7 , Figure 7 for a simple structure diagram of a peripheral component interconnect express device provided by the embodiment of the present application. The peripheral component interconnect express device can include:

[0119] The memory D1 is configured to store a computer program.

[0120] A processor D2 (such as a PCIe controller) configured to implement the steps of the communication configuration method provided by the above-described method embodiments when executing a computer program.

[0121] Correspondingly, please refer to Figure 8 , Figure 8 A specific structural diagram of a peripheral component interconnect express device provided by the embodiment of the present application. The peripheral component interconnect express device 310 can have great differences due to different configurations or performances, and can include one or more central processing units (CPUs) 322 (such as one or more processors) and a memory 332, one or more storage media 330 (such as one or more mass storage devices) storing application programs 342 or data 344. The memory 332 and the storage media 330 can be temporary storage or persistent storage. The programs stored in the storage media 330 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the host. Further, the central processing unit 322 can be configured to communicate with the storage media 330 and execute a series of instruction operations in the storage media 330 on the peripheral component interconnect express device 310.

[0122] The peripheral component interconnect express device 310 can further include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input / output interfaces 358, and / or one or more operating systems 341. For example, a Linux system or the like.

[0123] In the embodiment, the peripheral component interconnect express device 310 can be specifically a solid state disk, a graphics processing unit, or a network interface card.

[0124] The steps in the above-described communication configuration method can be implemented by the structure of the peripheral component interconnect express device.

[0125] Corresponding to the above method embodiments, the embodiment of the present application further provides a peripheral component interconnect express system. The peripheral component interconnect express system described below can be correspondingly referred to the communication configuration method described above.

[0126] A peripheral component interconnect express system, including: a first peripheral component interconnect express device and a second peripheral component interconnect express device;

[0127] The first peripheral component fast interconnect device and the second peripheral component fast interconnect device are connected through a peripheral component fast interconnect bus, and the first peripheral component fast interconnect device and the second peripheral component fast interconnect device are both the peripheral component fast interconnect device provided in the above embodiment, for example, the first peripheral component fast interconnect device can be the first device in the above embodiment, and the second peripheral component fast interconnect device can be the second device in the above embodiment.

[0128] Corresponding to the above method embodiments, the embodiments of the present application also provide a computer program product, and the computer program product described below can be correspondingly referred to the communication configuration method described above.

[0129] A computer program product comprises computer programs / instructions, which, when executed by a processor, implement the steps of the communication configuration method provided in the above method embodiments.

[0130] The embodiments in the specification are described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same or similar parts of each embodiment can be referred to each other. For the apparatus, device, system, computer program product and computer readable storage medium disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant part can be referred to the method part.

[0131] The above describes the communication configuration method, device, peripheral component fast interconnect device, peripheral component fast interconnect system, computer program product and computer readable medium provided by the present application in detail. The principle and implementation of the present application are described by applying specific examples in this paper. The above embodiment is only used to help understand the method of the present application and its core idea. It should be pointed out that for ordinary skilled in the art, without departing from the principle of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the protection scope of the present application.

Claims

1. A communication configuration method, characterized by, The method comprises the following steps: The first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link; wherein, the first device and the second device are both peripheral component interconnect express devices, and the first latency information report message comprises protocol stack processing latency and system response time of the second device; Transaction concurrency capability of the first device is determined according to the protocol stack processing latency and system response time of the first device and the protocol stack processing latency and system response time of the second device in the first latency information report message; System resources corresponding to the peripheral component interconnect express link in the first device are configured according to the transaction concurrency capability; wherein, the system resources comprise at least one of buffer size, transaction tag number, lookup table specification and driver queue number.

2. The communication configuration method of claim 1, wherein The first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link, comprising: The first device sends a second latency information report message to the second device through the peripheral component interconnect express link; wherein, the second latency information report message comprises protocol stack processing latency and system response time of the first device, and the first device is a latency information report initiator; The first device receives the first latency information report message returned by the second device.

3. The communication configuration method of claim 2, wherein The first device sends a second latency information report message to the second device through the peripheral component interconnect express link, comprising: After the first device and the second device enter a normal working state, the first device sends the second latency information report message to the second device through the peripheral component interconnect express link.

4. The communication configuration method of claim 1, wherein After the first device acquires a first latency information report message sent by a second device through a peripheral component interconnect express link, the method further comprises: The first device returns a second latency information report message to the second device through the peripheral component interconnect express link; wherein, the second latency information report message comprises protocol stack processing latency and system response time of the first device, and the second device is a latency information report initiator.

5. The communication configuration method of claim 1, wherein The first latency information report message is a data packet in the form of a message transaction layer packet or a data link layer packet of a peripheral component interconnect express protocol.

6. The communication configuration method of claim 5, wherein, When the first latency information report message is a data packet in the form of the message transaction layer packet, the first latency information report message comprises a protocol stack processing latency field, a system response time field and a protocol definition field; wherein, the protocol definition field comprises at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet digest field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field and a message coding field.

7. The communication configuration method of claim 6, wherein, The first latency information report message is a 16-byte data packet, and the first latency information report message further comprises a reserved bit field.

8. The communication configuration method of claim 7, wherein, The first byte to the fourth byte in the first delay information report message includes the data packet format field, the data packet type field, the transaction category field, the message transaction layer packet digest field, the error identification field, the attribute field, the additional transaction type field and the length field, the fifth byte to the eighth byte in the first delay information report message includes the requester identification field, the transaction tag field and the message encoding field, the ninth byte to the twelfth byte in the first delay information report message includes the protocol stack processing delay field and the system response time field, and the thirteenth byte to the sixteenth byte in the first delay information report message includes the reserved bit field.

9. The communication configuration method of claim 7, wherein, The data packet format field is binary 001; the data packet type field is binary 10100, the transaction category field is 0, the attribute field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message encoding field is binary 00010100.

10. The communication configuration method of claim 1, wherein, The first device obtains a first delay information report message sent by a second device through a peripheral component interconnect express link, including: The first device obtains the first delay information report message sent by the second device through the peripheral component interconnect express link at a preset time interval.

11. The communication configuration method according to any one of claims 1 to 10, wherein, The transaction concurrency capability of the first device is determined according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message, including: The transaction round-trip delay is determined according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device. The transaction concurrency capability of the first device is determined according to the transaction round-trip delay and the number of channels, the single-channel transmission rate, the physical layer coding efficiency and the transaction layer packet data packet length of the peripheral component interconnect express link obtained.

12. The communication configuration method of claim 11, wherein, The transaction round-trip delay is determined according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device, including: The sum of the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device is calculated to obtain the transaction round-trip delay.

13. The method of claim 11, wherein, The transaction concurrency capability of the first device is determined according to the transaction round-trip delay and the number of channels, the single-channel transmission rate, the physical layer coding efficiency and the transaction layer packet data packet length of the peripheral component interconnect express link obtained, including: By , the transaction concurrency capability of the first device is calculated; wherein, R link is the single-channel transmission rate, N lane is the number of channels, L t is the transaction round-trip delay, E enc is the physical layer coding efficiency, S packet is the transaction layer packet data packet length, and a is a preset parameter.

14. The communication setting method according to claim 13, characterized by, Said by , the transaction concurrency capability of the first device is calculated, comprising: The calculation result of the following equation is rounded up to obtain the transaction concurrency capability of the first device. ​ 15. The communication setting method according to claim 13, characterized by, The unit of the transaction layer packet data packet length is byte, and a is 8.

16. A communication configuration apparatus, characterized by comprising: Applied to a first device, including: An obtaining module is configured to receive a first delay information report message sent by a second device through a peripheral component interconnect express link; wherein the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message includes the protocol stack processing delay and the system response time of the second device; determining a transaction concurrency capability of the first device according to protocol stack processing delay and system response time of the first device and protocol stack processing delay and system response time of the second device in the first delay information report message; configuring system resources corresponding to the peripheral component interconnect express link in the first device according to the transaction concurrency capability, wherein the system resources include at least one of buffer size, transaction tag number, lookup table specification, and driver queue number.

17. A peripheral component quick interconnect device, comprising: comprising: a memory for storing a computer program; a processor for executing the computer program to implement the steps of the communication configuration method according to any one of claims 1 to 15.

18. A peripheral component quick interconnect system, comprising: comprising: a first peripheral component interconnect express device and a second peripheral component interconnect express device; wherein the first peripheral component interconnect express device and the second peripheral component interconnect express device are connected through a peripheral component interconnect express bus, and the first peripheral component interconnect express device and the second peripheral component interconnect express device are both the peripheral component interconnect express device according to claim 17.

19. A computer program product comprising computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to implement the steps of the communication configuration method according to any one of claims 1 to 15.

20. A computer-readable storage medium, characterized in that, The computer program / instruction is executed by the processor to implement the steps of the communication configuration method according to any one of claims 1 to 15. The computer program / instruction is executed by the processor to implement the steps of the communication configuration method according to any one of claims 1 to 15.

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