A PCIe Interrupt Verification System, Method and Device

Abstract

The present invention provides a PCIe interrupt verification system, method and device, relating to the technical field of PCIe interrupt verification. The verification system mainly includes: in a UVM verification environment, a comparison module and a module under test are constructed; the module under test includes a PCIe system under test; the PCIe system under test includes a plurality of ports; the ports include interrupt status registers; the comparison module is connected to the module under test through transaction-level modeling, and is used to trigger an interrupt for the module under test according to input parameters; collect the interrupt messages of the module under test, perform interrupt status comparison and interrupt clearing operations, and output a verification result. This solution can comprehensively and automatically combine the trigger and clearing mechanisms of various interrupt sources, thereby restoring the real usage scenario, and simply and reliably realizing system-level interrupt verification; this solution can effectively reduce the verification cost of PCIe switch system interrupt verification, and improve the verification efficiency and verification effect.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIe interrupt verification, and in particular to a PCIe interrupt verification system, method and device. Background Art

[0002] With the continuous enrichment of the application scenarios of the PCIe protocol, the types of its interrupt sources are also increasing continuously, which further increases the difficulty of PCIe network interrupt verification work.

[0003] Currently, the verification methods for PCIe interrupts are to trigger and clear a single interrupt mode of a single interrupt source. This method not only cannot restore the PCIe network interrupt situation in the real usage scenario, but also seriously restricts the efficiency and effect of PCIe network interrupt verification work. Summary of the Invention

[0004] The purpose of the present invention is to provide a PCIe interrupt verification system, method and device to solve at least one of the above technical problems existing in the prior art.

[0005] In a first aspect, to solve the above technical problems, the present invention provides a PCIe interrupt verification system, including a comparison (scoreboard, abbreviated as sb) module and a device under test (design under test, abbreviated as dut) module constructed in a UVM (Universal Verification Methodology) verification environment;

[0006] The device under test module includes a device under test PCIe system; the device under test PCIe system includes a plurality of ports; the port includes an interrupt status register (status);

[0007] The comparison module is connected to the device under test module through transaction level modeling (Transaction Level Modeling, abbreviated as TLM), and is used to trigger an interrupt for the device under test module according to input parameters; collect the interrupt message of the device under test module, perform interrupt status comparison and interrupt clearing operations, and output a verification result;

[0008] The configuration content of the comparison module includes: the ports occupied by the device under test PCIe system during interrupt verification and the connection situation (random configuration) between these ports, and the interrupt modes (random configuration) of these ports; the interrupt mode includes INTx mode or MSI mode;

[0009] The input parameters include the port number (DEVICE NUM, generally consistent with the preset device numbers of each port in the device under test PCIe system) for interrupt verification, the interrupt number and the number of interrupt triggers; the interrupt number refers to the number of the interrupt source.

[0010] Through the above system, the UVM environment can be used to simply, reliably and systematically verify the interrupt of the PCIe system to be tested. This solution can automatically simulate multiple interrupt sources and their combinations, and automatically perform triggering and clearing operations, thus reproducing the PCIe network interrupt situation in the real usage scenario, and improving the efficiency and effect of the PCIe network interrupt verification work.

[0011] In a feasible implementation manner, the interrupt status register is of the W1Clear type.

[0012] In a feasible implementation manner, an interrupt trigger function and an interrupt clearing function are instantiated in the comparison module; the interrupt trigger function is used to perform a write 1 operation on the interrupt status register so that the value of the interrupt status register changes from 0 to 1, thereby triggering an interrupt; the interrupt clearing function is preset with the address of the interrupt status register of the PCIe system to be tested and is used to perform a write 1 clearing operation on the interrupt status register so that the value of the interrupt status register changes from 1 to 0, thereby clearing the interrupt.

[0013] In a feasible implementation manner, the interrupt sources include hot plug events, link events, Dpc events, doorbell events, Gpio events, etc.

[0014] In a second aspect, based on the same inventive concept, the present application further provides a verification method using the above PCIe interrupt verification system, including the following steps:

[0015] Step 1: In the PCIe interrupt verification system, based on the port number in the input parameters, first randomly configure the ports occupied by the interrupt verification and their upstream ports to determine the connection situation of each port; then randomly configure the interrupt mode of each port; the interrupt mode includes INTx mode or MSI mode; for the ports in INTx mode, after triggering an interrupt, according to the interrupt mapping (MAPPING) rule and port number of the INTx mode, when the message of this port is forwarded to the outlet of the upstream port, a corresponding message code (MESSAGE_CODE, 8-bit binary data) is generated.

[0016] Preferably, the interrupt mapping rule specifically includes:

[0017] Classify according to the remainder of the port number divided by 4: If the remainder is 0, the generated message code is h20 / h24, that is, the INTa type; if the remainder is 1, the generated message code is h21 / h25, that is, the INTb type; if the remainder is 2, the generated message code is h22 / h26, that is, the INTc type; if the remainder is 3, the generated message code is h23 / h27, that is, the INTd type; this can evenly distribute the port numbers to the four INTx types (i.e., four interrupt lines) as much as possible, thereby reducing the computing pressure on a single interrupt line of the PCIe interrupt verification system, and then improving the interrupt verification processing efficiency.

[0018] Step 2: Based on the interrupt number and the number of interrupt triggers in the input parameters, randomly generate interrupt test cases, so that various interrupt combinations (a two-dimensional array of the total number of ports * the total number of interrupt numbers) can be obtained, covering various interrupt scenarios (for example, if there are 5 ports and 5 interrupt numbers, the interrupt combination is 5 * 5 = 25 combinations, and each interrupt trigger comes from these 25 combinations, and duplicates are allowed); the comparison module initiates the first thread and the second thread:

[0019] The first thread, based on the interrupt test case, through the interrupt trigger function, continuously writes 1 to the interrupt status register of the specified port of the module under test to trigger an interrupt:

[0020] The INTx mode port that triggers the interrupt generates an INTx interrupt message (Assert INTx);

[0021] The MSI mode port that triggers the interrupt generates an MSI message; the MSI message includes a bus-device-function number (BUS-DEVICE-FUNCTION, abbreviated as BDF number) and a vector number (vector num, 3-bit binary data); the bus-device-function number includes the port number;

[0022] The second thread continuously collects messages from the exit of the upstream port of the module under test and performs queued transmission.

[0023] Preferably, the queued transmission specifically includes:

[0024] Send the INTx message in the message to the INTx queue for comparison. The INTx message includes an INTx interrupt message (Assert INTx) or an INTx interrupt clear message (Deassert INTx); the INTx queue includes an INTa queue, an INTb queue, an INTc queue, and an INTd queue, and according to the message code, send the INTx message to the corresponding INTx queue;

[0025] Send the MSI message in the message to the MSI queue for comparison.

[0026] Step 3: The comparison module executes the interrupt clearing function for each queue respectively.

[0027] Preferably, the specific steps of Step 3 include:

[0028] In each INTx queue, the INTx message is read sequentially; the interrupt registers of each port corresponding to this queue are traversed and checked. If the value of the interrupt register is 1, a write 1 clear operation is performed; the port that has the write 1 clear operation generates an INTx interrupt clearing message (Deassert INTx).

[0029] In the MSI queue, the MSI message is read sequentially; according to the bus-device-function number and vector number of the MSI message, the port number and interrupt vector are obtained, and a write 1 clear operation is performed.

[0030] Preferably, the vector number is stored in the message header of the MSI message.

[0031] Preferably, the interrupt vector is stored in the message data of the MSI message (for example, the lower 3 bits).

[0032] Step 4: The comparison module performs an end check on each queue; the end check includes a queue element quantity check and an interrupt status register check.

[0033] Preferably, the specific steps of Step 4 include:

[0034] Step 41: Check whether the number of elements in the INTx queue is a multiple of 2. If so, proceed to Step 42; if not, generate an INTx verification failure message.

[0035] Step 42: Check whether the INTx interrupt message and the INTx interrupt clearing message appear in pairs. If so, proceed to Step 43; if not, generate an INTx verification failure message.

[0036] Step 43: Check whether the values of all interrupt status registers are all 0. If so, proceed to Step 44; if not, generate a verification failure message.

[0037] Step 44: Check whether the total number of all elements in the INTx queue and the MSI queue is less than or equal to the number of interrupt trigger times. If so, generate a verification success message; if not, generate a verification failure message. This can take into account the interrupt merging scenario.

[0038] Through the above method, by only adjusting the interrupt source content of the PCIe system (such as a switching chip) and replacing or adding the interrupt status register address in the interrupt clearing function, interrupt verification can be performed quickly and comprehensively.

[0039] In a third aspect, based on the same inventive concept, the present application also provides a PCIe interrupt verification device, including a processor, a memory, and a bus. The memory stores instructions and data that can be read by the processor, and the processor is configured to call the instructions and data in the memory to implement the PCIe interrupt verification system as described above. The bus is connected between the functional components to transmit information.

[0040] Adopting the above technical solution, the present invention has the following beneficial effects:

[0041] The PCIe interrupt verification system, method, and device provided by the present invention can comprehensively and automatically combine the trigger and clearing mechanisms of various interrupt sources, thereby restoring the real usage scenario and simply and reliably implementing system-level interrupt verification; this solution can effectively improve the verification efficiency and effect of PCIe interrupt verification. Description of the Drawings

[0042] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 A PCIe interrupt verification system diagram provided by an embodiment of the present invention;

[0044] Figure 2 A flowchart of a PCIe interrupt verification method provided by an embodiment of the present invention;

[0045] Figure 3 An example diagram of port connection situations provided by an embodiment of the present invention;

[0046] Figure 4 For Figure 2 The specific flowchart of step 4 in Detailed Embodiments

[0047] The following will clearly and completely describe the technical solutions of the present invention with reference to the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0048] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0049] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0050] The following further explains and illustrates the present invention in combination with specific embodiments.

[0051] It should also be noted that the following specific embodiments or specific implementation manners are a series of optimized setting manners listed by the present invention to further explain the specific invention content, and these setting manners can be combined with each other or used in association with each other.

[0052] Embodiment 1:

[0053] As Figure 1 shown, a PCIe interrupt verification system provided in this embodiment includes a comparison (scoreboard, abbreviated as sb) module and a device under test (design under test, abbreviated as dut) module constructed in a UVM (Universal Verification Methodology) verification environment;

[0054] The device under test module includes a PCIe system under test; the PCIe system under test includes a plurality of ports; the ports include an interrupt status register (status);

[0055] The comparison module is connected to the device under test through transaction level modeling (Transaction Level Modeling, abbreviated as TLM), and is used to trigger an interrupt for the device under test according to input parameters; collect the interrupt message of the device under test, perform interrupt status comparison and interrupt clearing operations, and output a verification result;

[0056] The configuration content of the comparison module includes: the ports occupied by the PCIe system under test during interrupt verification and the connection status between these ports (random configuration), and the interrupt modes of these ports (random configuration); the interrupt modes include INTx mode or MSI mode;

[0057] The input parameters include the port number (DEVICE NUM) for interrupt verification, the interrupt number, and the number of interrupt triggers; the interrupt number refers to the number of the interrupt source.

[0058] Through the above system, the UVM environment can be used to simply, reliably, and systematically perform interrupt verification on the PCIe system under test. This solution can automatically simulate multiple interrupt sources and their combinations, and automatically perform trigger and clear operations, thereby reproducing the PCIe network interrupt situation in the real usage scenario, and improving the efficiency and effect of the PCIe network interrupt verification work.

[0059] Further, the interrupt status register is of the W1Clear type.

[0060] Further, an interrupt trigger function and an interrupt clear function are instantiated in the comparison module; the interrupt trigger function is used to write 1 to the interrupt status register so that the value of the interrupt status register changes from 0 to 1, thereby triggering an interrupt; the interrupt clear function is preset with the address of the interrupt status register of the PCIe system under test and is used to perform a write 1 clear operation on the interrupt status register so that the value of the interrupt status register changes from 1 to 0, thereby clearing the interrupt.

[0061] Further, the interrupt sources include hot plug events, link events, Dpc events, doorbell events, and Gpio events.

[0062] Embodiment 2:

[0063] As Figure 2 shown, this embodiment provides a verification method using the above PCIe interrupt verification system, including the following steps:

[0064] Step 1. In the PCIe interrupt verification system, based on the port number in the input parameters, first randomly configure the ports occupied by the interrupt verification and their upstream ports to determine the connection status of each port, as Figure 3 shown; then randomly configure the interrupt modes of each port; the interrupt modes include INTx mode or MSI mode; for the ports in INTx mode, after triggering an interrupt, according to the interrupt mapping (MAPPING) rule of the INTx mode and the port number, when the message of this port is forwarded to the outlet of the upstream port, a corresponding message code (MESSAGE_CODE, 8-bit binary data) is generated.

[0065] Preferably, the interruption mapping rule specifically includes:

[0066] Classify according to the remainder of the port number divided by 4: If the remainder is 0, the generated message code is h20 / h24, that is, INTa type; if the remainder is 1, the generated message code is h21 / h25, that is, INTb type; if the remainder is 2, the generated message code is h22 / h26, that is, INTc type; if the remainder is 3, the generated message code is h23 / h27, that is, INTd type; this can make the port numbers be evenly distributed to four INTx types (that is, four interruption lines) as much as possible, thereby reducing the operation pressure on a single interruption line of the PCIe interruption verification system, and then improving the interruption verification processing efficiency.

[0067] Step 2: Based on the interruption number and the interruption trigger times in the input parameters, randomly generate interruption test cases, so that various interruption combination situations can be obtained, covering various interruption scenarios; the comparison module initiates the first thread and the second thread:

[0068] The first thread, based on the interruption test case, through the interruption trigger function, continuously writes 1 to the interruption status register of the specified port of the module under test to trigger an interruption:

[0069] The INTx mode port that triggers an interruption generates an INTx interruption message (Assert INTx);

[0070] The MSI mode port that triggers an interruption generates an MSI message; the MSI message includes a bus-device-function number (BUS-DEVICE-FUNCTION, abbreviated as BDF number) and a vector number (vector num, 3-bit binary data); the bus-device-function number includes the port number;

[0071] The second thread continuously collects messages from the exit of the upstream port of the module under test and performs queued transmission.

[0072] Preferably, the queued transmission specifically includes:

[0073] Send the INTx message in the message to the INTx queue to wait for comparison. The INTx message includes an INTx interruption message (Assert INTx) or an INTx interruption clearing message (Deassert INTx); the INTx queue includes an INTa queue, an INTb queue, an INTc queue, and an INTd queue, and according to the message code, send the INTx message to the corresponding INTx queue;

[0074] Send the MSI message in the message to the MSI queue to wait for comparison.

[0075] Step 3: The comparison module executes the interrupt clearing function for each queue respectively.

[0076] Preferably, the specific steps of Step 3 include:

[0077] In each INTx queue, read the INTx message in sequence; traverse and check the interrupt registers of each port corresponding to the queue. If the value of the interrupt register is 1, perform a write-1 clear operation; the port that performs the write-1 clear operation generates an INTx interrupt clearing message (Deassert INTx).

[0078] In the MSI queue, read the MSI message in sequence; obtain the port number and interrupt vector according to the bus-device-function number and vector number of the MSI message, and perform a write-1 clear operation.

[0079] Preferably, the vector number is stored in the message header of the MSI message.

[0080] Preferably, the interrupt vector is stored in the message data of the MSI message (i.e., the lower 3 bits).

[0081] Step 4: The comparison module performs an end check on each queue; the end check includes a queue element number check and an interrupt status register check.

[0082] Preferably, as Figure 4 shown, the specific steps of Step 4 include:

[0083] Step 41: Check whether the number of elements in the INTx queue is a multiple of 2. If so, execute Step 42; if not, generate an INTx verification failure message.

[0084] Step 42: Check whether the INTx interrupt message and the INTx interrupt clearing message appear in pairs. If so, execute Step 43; if not, generate an INTx verification failure message.

[0085] Step 43: Check whether the values of all interrupt status registers are all 0. If so, execute Step 44; if not, generate a verification failure message.

[0086] Step 44: Check whether the total number of all elements in the INTx queue and the MSI queue is less than or equal to the interrupt trigger times. If so, generate a verification success message; if not, generate a verification failure message. This can take into account the interrupt merging scenario.

[0087] Through the above method, only by adjusting the interrupt source content of the PCIe system (switch chip) and replacing or adding the interrupt status register address in the interrupt clearing function, can interrupt verification be performed quickly and comprehensively.

[0088] Exemplarily, for a PCIe system (chip) under test with 12 ports, including upstream ports and (downstream) ports, and 5 types of interrupt sources (hot plug event, link event, Dpc event, doorbell event, and Gpio event);

[0089] When using the traditional method for interrupt verification, at least: 12 (number of ports) * 120 (trigger order of interrupts) * 2 (whether interrupts are merged) * 5 (repeatedly trigger the same interrupt) * 2 (interrupt mode, INTx or MSI) = 28,800 test cases are required. These test cases need a large amount of manpower and working hours (estimated 4 weeks) to be written;

[0090] However, when using this solution, after building the system (estimated 1 week), only the interrupt status registers of each interrupt source need to be replaced to complete the interrupt verification, thus greatly improving the verification efficiency of interrupt verification and effectively saving the labor cost of interrupt verification.

[0091] Embodiment 3:

[0092] This embodiment provides a PCIe interrupt verification device, including a processor, a memory, and a bus. The memory stores instructions and data that can be read by the processor. The processor is used to call the instructions and data in the memory to implement the PCIe interrupt verification system as described above. The bus is connected between each functional component for transmitting information.

[0093] In another implementation manner of this solution, it can be implemented in the form of an integrated device. This device can include corresponding modules that execute each or several steps in the above-mentioned embodiments. The module can be one or more hardware modules specifically configured to execute the corresponding steps, or implemented by a processor configured to execute the corresponding steps, or stored in a computer-readable medium for implementation by the processor, or implemented through a certain combination.

[0094] The processor executes the various methods and processes described above. For example, the method embodiments in this solution can be implemented as a software program, which is tangibly included in a machine-readable medium, such as a memory. In some embodiments, part or all of the software program can be loaded and / or installed via the memory and / or communication interface. When the software program is loaded into the memory and executed by the processor, one or more steps in the method described above can be executed. Alternatively, in other embodiments, the processor can be configured to execute one of the above methods in any other appropriate manner (for example, by means of firmware).

[0095] The device can be implemented using a bus architecture. The bus architecture can include any number of interconnected buses and bridges, depending on the specific application of the hardware and overall design constraints. The bus connects various circuits of one or more processors, memories, and / or hardware modules together. The bus can also connect various other circuits such as peripherals, voltage regulators, power management circuits, external antennas, etc.

[0096] The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Component (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0097] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PCIe interrupt verification system, characterized in that Including a comparison module and a module under test built in a UVM verification environment; The module under test includes a PCIe system under test; the PCIe system under test includes a number of ports; the ports include interrupt status registers; the interrupt status registers are of the W1Clear type; The comparison module is connected to the module under test through transaction-level modeling and is used to trigger an interrupt for the module under test according to input parameters; Collect the interrupt messages of the module under test, perform interrupt status comparison and interrupt clearing operations, and output verification results; The configuration content of the comparison module includes: the ports occupied by the PCIe system under test during interrupt verification and the connection situation between these ports, and the interrupt modes of these ports; the interrupt modes include INTx mode or MSI mode; An interrupt trigger function and an interrupt clearing function are instantiated in the comparison module; the interrupt trigger function is used to write 1 to the interrupt status register, so that the value of the interrupt status register changes from 0 to 1; the interrupt clearing function is preset with the address of the interrupt status register of the PCIe system under test and is used to perform a write 1 clearing operation on the interrupt status register, so that the value of the interrupt status register changes from 1 to 0; The input parameters include the port number, interrupt number, and number of interrupt triggers for interrupt verification; the interrupt number refers to the number of the interrupt source; The verification method of the PCIe interrupt verification system includes: Step 1: In the PCIe interrupt verification system, based on the port number in the input parameters, first randomly configure the ports occupied by interrupt verification and their upstream ports to determine the connection situation of each port; then randomly configure the interrupt modes of each port; for ports in INTx mode, after triggering an interrupt, according to the interrupt mapping rule of INTx mode and the port number, when the message of this port is forwarded to the exit of the upstream port, generate a corresponding message code; Step 2: Based on the interrupt number and number of interrupt triggers in the input parameters, randomly generate interrupt test cases; the comparison module initiates a first thread and a second thread: The first thread, based on the interrupt test case, continuously writes 1 to the interrupt status register of the specified port of the module under test through the interrupt trigger function to trigger an interrupt: The INTx mode port that triggers an interrupt generates an INTx interrupt message; The MSI mode port that triggers an interrupt generates an MSI message; the MSI message includes a bus-device-function number and a vector number; the bus-device-function number includes the port number; The second thread continuously collects messages from the exit of the upstream port of the module under test and performs queued transmission; specifically includes: Send the INTx messages in the message into the INTx queue for waiting comparison, the INTx messages include INTx interrupt messages or INTx interrupt clearing messages; the INTx queue includes INTa queue, INTb queue, INTc queue, and INTd queue, and send the INTx messages into the corresponding INTx queue according to the message code; Send the MSI messages in the message into the MSI queue for waiting comparison; Step 3. The comparison module executes the interrupt clearing function for each queue respectively, which specifically includes: in each INTx queue, read INTx messages in sequence; traverse and check the interrupt registers of each port corresponding to the queue. If the value of the interrupt register is 1, perform a write-1 clearing operation; the port that undergoes the write-1 clearing operation generates an INTx interrupt clearing message. In the MSI queue, read MSI messages in sequence; based on the bus-device-function number and vector number of the MSI message, obtain the port number and interrupt vector, and perform a write-1 clearing operation. Step 4. The comparison module conducts an end check on each queue; the end check includes a queue element quantity check and an interrupt status register check.

2. The verification system according to claim 1, wherein The interrupt sources include hot plug events, link events, Dpc events, doorbell events, and Gpio events.

3. The verification system according to claim 1, wherein The vector number is stored in the message header of the MSI message; the interrupt vector is stored in the message data of the MSI message.

4. The verification system according to claim 1, characterized in that, The specific content of Step 4 includes: Step 41. Check whether the number of elements in the INTx queue is a multiple of 2: if so, execute Step 42; if not, generate an INTx verification failure message. Step 42. Check whether the INTx interrupt message and the INTx interrupt clearing message appear in pairs: if so, execute Step 43; if not, generate an INTx verification failure message. Step 43. Check whether the values of all interrupt status registers are all 0: if so, execute Step 44; if not, generate a verification failure message. Step 44. Check whether the total number of all elements in the INTx queue and the MSI queue is less than or equal to the interrupt trigger times: if so, generate a verification success message; if not, generate a verification failure message.

5. A PCIe interrupt verification device, characterized in that, It includes a processor, a memory, and a bus. The memory stores instructions and data read by the processor. The processor is used to call the instructions and data in the memory to implement the verification system as described in any one of claims 1-2. The bus is connected between each functional component for transmitting information.

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