Power consumption income evaluation method for specific gated clock scene

Abstract

The invention belongs to the field of integrated circuits, and provides a power consumption income evaluation method for a specific gated clock scene, which comprises the following steps: generating basic data; constructing an initial income evaluation model; perfecting the income evaluation model; and performing income evaluation by using the improved income evaluation model. According to the power consumption income assessment method, complex power consumption calculation is not needed, the power consumption income assessment of the gated clock can be completed through the power consumption income assessment model only through two parameters, the method is simpler and more efficient than a power consumption calculation method under the requirement of fine granularity, meanwhile, error correction is carried out in the income assessment model generation process, and the accuracy of the power consumption income assessment model is improved. And the precision is also ensured.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a power consumption benefit evaluation method. Background Art

[0002] With the development and progress of manufacturing technology, the integration of integrated circuits (the number of transistors per unit area and volume) continues to increase, which has brought about the growth of power density (power consumption per unit area), making power consumption an important parameter indicator of chips. In order to control the power consumption of integrated circuits, various optimization methods have emerged. Among them, the most common and widely used optimization technology is gated clock technology.

[0003] The power consumption of a circuit can be divided into two parts, dynamic power consumption and static power consumption. Static power consumption is the power consumption generated even if the circuit is not working after it is powered on, while dynamic power consumption is mainly generated by the charging and discharging process in the integrated circuit. In ordinary circuits, dynamic power consumption occupies a dominant position. A considerable part of dynamic power consumption is generated by the continuous change of the clock signal. The clock signal is the "heartbeat" of the circuit, which determines the working speed of the circuit. The signal change and data transmission on the circuit are synchronized by the continuous change of the clock signal between "0" and "1". The gated clock technology is to achieve the purpose of saving dynamic power consumption by disconnecting the clock of the non-working circuit.

[0004] There are a large number of registers in the circuit, which are used to record data and update or retain data with the beat of the clock signal. As long as it is in the power-on state, the data on the register will be maintained until new data is written. For a register whose data is not updated, there is no need to receive the clock signal, which wastes dynamic power consumption. For such a register, the clock of the register can be disconnected by gating the clock to achieve the purpose of saving power. In layman's terms, the gated clock technology optimizes power consumption by "locking" the clock of the register. The "lock" is the gated clock unit and the "key" is the enable signal. When the enable signal is invalid, the register cannot receive the clock, and there will be no invalid clock flips and power consumption waste.

[0005] like Figure 1 An example of a gated clock application is shown in Figure 1. Figure 1 As shown in (a), when there is no gated clock, when the signal en is invalid, the data cannot be sent to the register, and data out will not be updated. However, the clock is still connected to the register and keeps flipping, resulting in power consumption waste. Figure 1 As shown in (b), after the gated clock is deployed, when the signal en is invalid, the clock end of the register cannot receive the clock signal. At this time, the data out of the register itself will not change. The circuit function is not affected, and the invalid clock flip is eliminated, thereby reducing power consumption.

[0006] Gated clock technology can be roughly divided into two types. One is the traditional gated clock that directly deploys the gated clock on the register with the enable signal, such as Figure 1 As shown in the figure, the other is a more complex advanced clock gating, which has two basic types: (1) When the output of the register is not used under certain logical conditions (also known as invisible to subsequent use), it can be assumed that the output of the register will not affect the correct output of the circuit. At this time, such logical conditions can be used to apply clock gating. This type of clock gating is also called observability based clock gating. (2) In some cases, the output of the register will remain unchanged for 2 or more clock cycles. At this time, the register can also disconnect the clock. This type of clock gating is called stability-based clock gating. Figure 2 In the case shown, when the register FF0 of the previous stage is controlled by the gated clock unit, the data received by FF1 remains unchanged, and FF1 can also be gated at this time.

[0007] The fundamental criterion for evaluating the effect of gated clocks is whether they can save power. For various mature EDA (Electronics Design Automation) tools currently available, tools that support gated clocks often need to calculate the power consumption changes of the entire circuit in the end to obtain the benefits of gated clocks. Even if the tool itself supports benefit analysis for each gated clock deployment, it still relies on power consumption calculation to evaluate the benefits of gated clocks.

[0008] The power consumption calculation process in the traditional method is as follows. First, for EDA tools, the power consumption classification introduced above is not enough to meet the needs. When these power consumption tools perform power consumption calculations, they divide the power consumption into three parts, namely leakage power consumption, switching power consumption, and internal power consumption. Leakage power consumption corresponds to static power consumption, and switching power consumption and internal power consumption together constitute dynamic power consumption. Switching power consumption is the power consumption caused by the charging and discharging of the load capacitance at the output end of a unit in the circuit, and internal power consumption is the sum of all dynamic power consumption within a unit. During calculation, the power consumption tool will calculate the above three types of power consumption separately, specifically:

[0009] (1) For leakage current power consumption, when calculating the leakage current power consumption of a unit, the tool obtains the power consumption values ​​corresponding to all possible situations in the unit from the process library file provided by the semiconductor manufacturer, multiplies these power consumption values ​​by their corresponding probabilities and sums them up to obtain the static power consumption of the unit, and then sums up the static power consumption of all units to obtain the static power consumption of the entire circuit.

[0010] (2) For internal power consumption, the tool will calculate the internal power consumption of each pin of the unit (the input and output gateways of the unit are pins, which are different from the input and output ports of the circuit module). The internal power consumption of each pin is equal to the internal energy of the pin multiplied by the toggle rate of the pin (toggle rate, the number of signal toggles divided by the total number of clock cycles, equal to the average number of toggles per clock cycle). This internal energy is also obtained by interpolation of the power consumption table in the process library file and is related to the timing of the circuit. When calculating, each pin needs to calculate the internal power consumption corresponding to all situations, such as the internal power consumption when the input pinA has no effect on the output and when it has an effect on the output. The internal power consumption corresponding to all situations of all pins is added up to get the internal power consumption of a unit. The overall internal power consumption of the circuit is equal to the sum of the internal power consumption of all units.

[0011] (3) Flip power consumption. The flip power consumption is calculated by a formula as follows:

[0012]

[0013] Where C is the output load capacitance, V is the voltage, T is the toggle rate, and * is the multiplication operation.

[0014] The total power consumption of the circuit can be calculated through the above steps. The above method takes a long time to complete the calculation for a large-scale circuit. In practice, some other constraints are often used to ensure that the deployed gated clock has positive power consumption benefits. For example, the minimum number of bits of registers is limited to gate the clock. There are two main constraints: one is the enable constraint, which requires the enable signal to be variable; the second is the width constraint, which requires a minimum value limit for the size of the register. Registers below this size can be considered to have no benefit from gated clocks. There are some other constraints for advanced gated clocks, such as logic depth constraints, and the enable signal cannot be generated through too complex logic.

[0015] For the application scenarios of advanced gated clocks, since they are more complex than traditional gated clocks, they are often controlled by some more conservative side constraints in practice, and finally the benefits are evaluated by power consumption calculation to determine the optimization effect. For the STB (stability-based) type gated clock scenarios in advanced gated clocks, the existing method flows can be divided into the following two types: Solution (1) calculates power consumption before optimization, then determines the candidates for optimizable registers, and then screens the optimizable registers according to the gated clock related constraints. After determining which are the final optimized registers, the optimization is deployed and the power consumption is calculated to obtain the benefits; Solution (2) first determines the candidates for optimizable registers, and then screens them according to the gated clock related constraints to determine the final registers that can be optimized. The power consumption benefits are calculated for each register that implements the gated clock to confirm the benefits. Regardless of which solution is used, it is based on power consumption calculation to confirm that the deployment of the gated clock can bring power consumption benefits. In particular, if you want to achieve fine-grained gated clock power consumption benefit analysis, the method used is similar to Solution (2).

[0016] As mentioned above, the existing method for evaluating the benefits of gated clocks mainly adopts solution (1). Solution (1) guarantees benefits by using constraints, with coarse granularity, but good efficiency. Solution (2) can be used for fine-grained gated clock benefit analysis, but solution (2) relies on the aforementioned power consumption calculation method for benefit analysis, and needs to rely on multiple related parameters for calculation, which is a relatively complicated process. At the same time, such a complicated method will inevitably lead to reduced efficiency. Summary of the invention

[0017] The technical problems to be solved by the present invention are:

[0018] The present invention aims at the STB type gated clock scenario in the advanced gated clock, and proposes a power consumption benefit evaluation method that can improve the granularity of benefit evaluation without losing too much accuracy. The method is used to directly evaluate whether the gated clock can obtain the target power consumption benefit, and can achieve a balance between granularity and efficiency, solving the problem of insufficient efficiency of using complex power consumption calculations for fine-grained gated clock benefit evaluation.

[0019] Technical solution of the present invention:

[0020] A power consumption benefit evaluation method for a specific gated clock scenario includes the steps of:

[0021] Step 1. Generate basic data;

[0022] Step 2. Construct an initial revenue evaluation model;

[0023] Step 3. Improve the benefit evaluation model;

[0024] Step 4. Use the improved benefit evaluation model to conduct benefit evaluation.

[0025] Advantages and beneficial effects of the present invention:

[0026] The existing power consumption benefit evaluation method has a complex power consumption calculation process and requires many parameters. The power consumption benefit evaluation method proposed in the present invention does not require power consumption calculation. Only two parameters are needed to complete the evaluation of the power consumption benefit of the gated clock through the power consumption benefit evaluation model. It is simpler and more efficient than the power consumption calculation method under the requirement of fine granularity. At the same time, the error correction is performed during the generation process of the benefit evaluation model, and the accuracy is also guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an example of the circuit structure of an existing gated clock application, showing the changes in the circuit before and after the gated clock is deployed.

[0028] Figure 2 It is an example of a circuit structure for an STB gated clock application scenario, which is the target scenario of the present invention.

[0029] Figure 3 Yes Figure 2 An example of the circuit structure of the STB gated clock application scenario after the scenario is abstracted and simplified. In the figure, ICG represents the gated clock unit.

[0030] Figure 4 Yes Figure 3 Circuit structure example after STB gated clock deployment. Figure 3 A new gated clock unit and a 1-bit register are added to the circuit structure.

[0031] Figure 5 It is a flow chart of a revenue evaluation model obtained in an embodiment of the present invention.

[0032] Figure 6 It is a three-dimensional image composed of relevant data in the embodiment of the present invention.

[0033] Figure 7 It is an effect diagram in which the profit boundary represented by the profit evaluation model is marked on the relevant data after the profit evaluation model is initialized in the embodiment of the present invention.

[0034] Figure 8 This is an example diagram of using a generated benefit evaluation model to perform STB gated clock power consumption benefit evaluation in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Terminology explanation:

[0036] Register: A basic storage unit in a circuit that updates the stored data based on clock signals and control signals. Each register stores a binary data.

[0037] Combinational logic: A type of digital circuit in which the output data changes when the input data changes. It is not affected by the clock signal and is not rhythmic.

[0038] Register transfer level (RTL): A circuit abstraction level and hardware code description style. The described circuit uses registers to store data. Data changes are implemented through combinational logic. It does not involve specific unit connections and is implemented through register behavior description and partial structure description.

[0039] Synthesis: The process of converting a high-level abstraction hardware description into a low-level abstraction hardware description. It generally refers to logic synthesis - the process of converting RTL code into a gate-level netlist.

[0040] Electronic Design Automation tool (EDA tool): Specialized industrial software used in the chip design and manufacturing process, which can realize professional tasks in the circuit design and manufacturing process.

[0041] Netlist: A circuit file that is composed of modules connected by different units, and sub-modules can exist within the module.

[0042] Process library: A data file provided by semiconductor manufacturers to circuit designers, which records the relevant data of standard cells under a specific semiconductor manufacturing process, including information such as the timing, power consumption, and area of ​​the cell.

[0043] Hardware description language (HDL): A type of code language similar to software programming language, used to describe hardware. Hardware code implemented using HDL can be converted into a gate-level netlist through EDA tools.

[0044] Static probability (SP): The probability that a signal is 1, ranging from 0 to 1.

[0045] The present invention aims at Figure 2 The power consumption analysis of the target scenario shown in the figure was carried out to determine the basic factors affecting power consumption. Based on the collected power consumption data, a power consumption benefit evaluation model determined by two basic factors was found through fitting method. The subsequent improvement steps ensured that this model, which is much simpler than the power consumption calculation, has acceptable accuracy and does not produce excessive errors. Compared with traditional power consumption calculation, the power consumption benefit evaluation of the target scenario using this benefit evaluation model can greatly reduce the calculation complexity, improve efficiency, and have satisfactory accuracy.

[0046] The technical solution provided by the present application will be further described below in conjunction with specific embodiments and accompanying drawings. The advantages and features of the present application will become more apparent with the following description.

[0047] Will be like Figure 2 The target scenario shown in the figure is further abstracted and simplified. The target scenario can be simplified as follows Figure 3 in the form of Figure 3 ICG is Figure 2 The unit represented by the dashed box, Figure 2 The dotted box shows the specific structure of ICG.

[0048] right Figure 3 After the STB gated clock is deployed, the circuit becomes Figure 4 The main change of the circuit is the addition of two units, an ICG unit to control the register FF1 of the next stage, and a 1-bit register to transition the enable signal en to meet the timing of the correct operation of the circuit.

[0049] Figure 4 After deploying the gated clock, the power consumption change of the circuit can be expressed by the following expression:

[0050]

[0051] In the formula represents the register power consumption saved after deploying the gated clock, where represents the power saving of a 1-bit register when it is completely turned off, (1-p(en)) represents the probability that the enable signal is "0", It represents the sum of the power saved by an n-bit register, and * represents a multiplication operation. P(ICG) represents the power consumption of the newly added gated clock unit, P(FF) represents the power consumption of the newly added 1-bit register, p(en) represents the static probability (SP) of the enable signal, n represents the size of the gated register, and - represents a subtraction operation. The overall power consumption change expression can be divided into two parts: the saved power consumption and the increased power consumption. The difference between the two is caused by the circuit changes after the gated clock is deployed. If If it is greater than 0, it means that deploying gated clock can gain benefits.

[0052] It can be found that when deploying gated clocks in the target scenario, the main factors affecting power consumption are the size n of the controlled register and the SP of the enable signal.

[0053] At the same time, it can be found that as the enable signal SP increases, the result of the expression decreases; as the register size increases, the result of the expression increases, and it has an obvious monotonic change characteristic.

[0054] After clarifying the above two factors that mainly affect power consumption, based on the above theoretical basis, the technical solution of the present invention is mainly developed from the following three aspects: 1. Basic data generation; 2. Construction of initial benefit evaluation model; 3. Improvement of benefit evaluation model;

[0055] The relationship between them is: the core of the technical solution of the present invention lies in the benefit evaluation model. In order to obtain the benefit evaluation model, it is necessary to first generate basic data (circuit netlist file and power consumption data), and initialize the benefit evaluation model based on the power consumption data. After the initialization is completed, the benefit evaluation model needs to be further improved, so that the final usable benefit evaluation model can be obtained for power consumption benefit evaluation.

[0056] Step 1. Generate basic data

[0057] Step 1.1 Obtaining the circuit netlist file: Figure 3 and Figure 4 The circuit structure shown can be used to write hardware code through HDL, and use the synthesis tool to synthesize a series of netlists of registers of different sizes under a specified process library.

[0058] Step 1.2: For the netlists of the registers of different sizes in step 1.1, classify them according to whether the STB gated clock is deployed, and pair them one by one according to the register size for subsequent power consumption data generation.

[0059] Step 1.3 For a set of paired netlists (one with STB gating and one without STB gating clock), set the SP of the enable signal at a certain interval, calculate the power consumption of the netlists separately using the power consumption calculation tool, and subtract the total power consumption of the netlist with STB gating from the total power consumption of the netlist without STB gating. This can yield the power consumption benefit that can be obtained by deploying STB gating clocks for a certain register size and enable signal SP.

[0060] Step 1.4 performs the operation of step 1.3 on all paired netlists, and can collect a series of three-dimensional related data consisting of register size, enable signal SP, and power consumption benefit. This data is used to construct a data set for subsequent generation of a benefit evaluation model.

[0061] Step 2. Build an initial revenue assessment model

[0062] Performing two-step cubic spline interpolation fitting on the data set constructed in step 1 can obtain the boundary expression of the target benefit of the gated clock determined by the register size and the enable signal SP. This expression is the benefit evaluation model, which determines the maximum enable signal SP required for deploying the gated clock to achieve the target benefit under each register size. During use, according to the provided register size, a theoretical maximum SP can be obtained by substituting it into the benefit evaluation model; compare the given enable signal SP with the theoretical maximum SP. If the given enable signal SP is less than the theoretical maximum SP, it can be determined that the deployment of the gated clock can obtain the target benefit. In this way, only the two parameters of register size and enable signal SP are needed to analyze whether the gated clock can obtain the target benefit.

[0063] The cubic spline interpolation principle is as follows: The cubic spline interpolation method can express the curve in each interval with a cubic equation according to the intervals naturally divided by the existing data, so that the data points are all on the interval curve and the first-order derivative and second-order derivative are continuous. By constructing multiple spline functions such as formula (1), formula (2) and formula (3), and using the natural boundary where the second-order derivative of the endpoint is 0 for calculation, a fitting segmented curve result can be obtained. As shown in the following formula, in one of the [x i ,x i+1 ] On the segmented small interval, the curve of the interval can be expressed by S i (x) represents, S′ i (x) represents the expression S i (x) Take the first-order derivative, S″ i (x) represents the expression S i (x) is subjected to the second-order derivative, and the expression S i (x) a i represents a constant parameter, b i represents the coefficient of the first-order term, c i represents the coefficient of the quadratic term, d i Represents the cubic coefficient, i∈[0,n-1].

[0064] S i (x) = a i +b i (xx I )+c i (xx i ) 2 +d i (xx i ) 3 (1)

[0065] S′ i (x) = b i +2c i (xx i )+3di (xx i ) 2 (2)

[0066] S″ i (x) = 2c i +6d i (xx i ) (3)

[0067] For a cubic spline function, there are 4 unknowns, and n small intervals correspond to 4n unknowns. According to the interpolation conditions in n intervals, 2n equations can be obtained. The continuity of the first-order derivative and the continuity of the second-order derivative inside the n-1 point can obtain 2n-2 equations. There are also natural boundary conditions to supplement the last two equations. A total of 4n equations can be solved to obtain the corresponding piecewise fitting curve

[0068] Step 2.1: According to the obtained data set, the first step of cubic spline interpolation, i.e., cubic spline interpolation of fixed register size, is performed (according to the register size with data in the data set, cubic spline interpolation of enable signal SP and power consumption benefit is performed on the data corresponding to these register sizes), and the benefit expression corresponding to each specified register size can be obtained;

[0069] Step 2.2: According to 2.1, a series of profit expressions can be fitted to determine the corresponding target profit points under different register sizes;

[0070] Step 2.3: Perform the second step of cubic spline interpolation based on these target benefit points, that is, perform another cubic spline interpolation of fixed power consumption benefit (the power consumption benefits of the target benefit points obtained are all the same, and perform cubic spline interpolation of the enable signal SP and the register size). After the second step of cubic spline interpolation is completed, the expression corresponding to the target power consumption benefit can be obtained, that is, the benefit evaluation model.

[0071] Step 3. Improve the revenue evaluation model

[0072] For the initial profit evaluation model, the predicted SP is bound to be different from the actual SP, and the two interpolation fittings inevitably introduce certain errors to a greater or lesser extent. In order to reduce the error and improve the accuracy of the profit evaluation model, it is necessary to improve it.

[0073] Step 3.1 For the data set obtained in step 1, according to the register size data in the data set, substitute each register size into the profit evaluation model obtained in step 2 to obtain the boundary SP predicted by the profit evaluation model under each register size;

[0074] Step 3.2 uses the process adopted in step 1 to obtain the power consumption data, and substitutes the boundary SP predicted by the benefit evaluation model into the calculation to obtain the actual power consumption benefit corresponding to each predicted boundary SP.

[0075] In step 3.3, the error of the benefit evaluation model can be obtained based on the target benefit and the actual power consumption benefit obtained. For the case where the accuracy requirement is not met, the actual power consumption benefit, enable signal SP and register size N are recorded as new data in the data set, the data set is updated, and the process of step 2 is repeated to re-fit the benefit evaluation model.

[0076] The revenue evaluation model needs to meet the accuracy requirements for all register sizes of the circuit netlist in the data set. Repeat the above operation until a revenue evaluation model that meets the accuracy requirements is obtained.

[0077] Step 4. Use the improved profit evaluation model to conduct profit evaluation

[0078] After obtaining the final benefit evaluation model, it can be used when analyzing the target scenario. Only the register size and the SP of the enable signal in the target scenario are needed to quickly determine whether the deployment of the gated clock can achieve the target benefit.

[0079] When analyzing the target scenario, the benefit evaluation model is used to analyze whether the gated clock can obtain the target benefit based on the two parameters of register size and enable signal SP. Specifically:

[0080] During use, the maximum enable signal SP required for deploying the gated clock to achieve the target benefit under the register size is obtained based on the benefit evaluation model, which is used as the theoretical maximum SP; the provided enable signal SP is compared with the theoretical maximum SP. If the provided enable signal SP is less than the theoretical maximum SP, it is determined that deploying the gated clock can obtain the target benefit; otherwise, it is determined that deploying the gated clock cannot obtain the target benefit.

[0081] Example

[0082] This embodiment provides a method for evaluating the power consumption benefit of a gated clock in an STB gated clock scenario. Figure 5 A flow chart of a benefit evaluation model for obtaining power consumption benefit evaluation.

[0083] It should be noted that the specific power consumption benefit value is not specified in the embodiment. This can be set as a specific value or percentage benefit. The method of the present invention supports the fitting of non-isovalue lines, and the target power consumption benefit can be adjusted according to the actual error needs. The target benefit is uniformly used in the following embodiments to describe this specified target value. The benefit evaluation model of the present invention is for a specified process library (the power consumption data depends on the process library). For situations where different process libraries need to be used, weights can be assigned to different process library benefit evaluation models for comprehensive consideration.

[0084] In the error checking process below, it may happen that repeated checking cannot converge to the target accuracy. Some data updating methods can be flexibly adopted to improve the situation, such as limiting the update of only data points with smaller errors into the data set, or regularly (after a certain number of times) deleting the data set to only retain the data points with the smallest error. The method is not fixed and needs to be adjusted according to actual needs.

[0085] Step S1, basic data generation.

[0086] Figure 5 Obtaining basic circuit files in the process: Figure 3 and Figure 4 For the circuit structure, the hardware description language (HDL) can be used to implement hardware code programming, and then the synthesis tool can be used to synthesize a series of netlists of registers of different sizes under the specified process library according to the corresponding hardware code to obtain the required basic circuit files. The synthesis results (netlists) obtained are then classified according to whether the STB gated clock is deployed, and the basic circuit files are paired one by one according to the register size. For each pair of basic circuit files, the enable signal SP is set with a range of 0 to 1 and an interval of 0.02. The power consumption calculation software is used to calculate the power consumption, and then the power consumption value without STB gating is subtracted from the power consumption value with STB gating. The power consumption benefits under 51 different sizes of enable signals SP corresponding to each register size can be obtained. The above power consumption calculation operation is performed on all pairs of basic circuit files, and the following can be obtained in the end. Figure 6 In the data set shown, the X-axis is the register size N, the Y-axis is the enable signal SP, and the Z-axis is the power consumption benefit obtained by deploying the STB gated clock. The data conforms to the following trend: as the register size increases, the power consumption benefit increases; as the enable signal SP increases, the power consumption benefit decreases.

[0087] Step S2, initializing the profit evaluation model.

[0088] Using cubic spline interpolation, first perform one-step cubic spline interpolation in the YZ direction. For the register size N in the power consumption data, perform cubic spline interpolation of the enable signal SP and the power consumption benefit when the register size N is fixed. The interpolation method uses a cubic function to represent the curve in each interval by using the natural division interval of the data points. This curve satisfies the data points on the curve, and the first-order derivative and second-order derivative of the curve are continuous. At the same time, it also satisfies the natural condition that the second-order derivative of the endpoint is 0. Based on the above premise, a cubic function can be used to represent the curve in each enable signal SP interval. Taking the interval [0,0.02] as an example, the expression S0(x) is used to represent the curve in the interval, S′0(x) represents the first-order derivative of the expression S0(x), S″0(x) represents the second-order derivative of the expression S0(x), and a0 in the expression S0(x) represents a constant parameter, b0 represents a linear term coefficient, c0 represents a quadratic term coefficient, and s0 represents a cubic term coefficient.

[0089] S0(x)=a0+b0(x-0)+c0(x-0) 2 +d0(x-0) 3 (4)

[0090] S'0(x)=b0+2c0(x-0)+3d0(x-0) 2 (5)

[0091] S″0(x)=2c0+6d0(x-0) (6)

[0092] For such an expression, there are 4 unknowns. Extended to 50 intervals consisting of 51 points, the cubic spline interpolation has a total of 4*50 unknowns. In these 50 intervals, 2*50 equations can be obtained according to the interpolation conditions, and the internal first-order derivative continuity and second-order derivative continuity of the 51 points can obtain 2*50-2 equations. Adding the natural boundary conditions, 2 equations are supplemented, totaling 4*50 equations. Solving these equations can obtain the corresponding piecewise fitting curve. After completion, a series of fitting curves in the YZ direction can be obtained, and a point of target power consumption benefit can be found on each fitting curve. These points are gathered together, and then a step of cubic spline interpolation in the XY direction is performed to obtain the expression of the enable signal SP and the register size N under a fixed power consumption benefit. This is the original benefit evaluation model. The second step of cubic spline interpolation is completed, and the benefit evaluation model is initialized. As shown Figure 7 The figure shows the effect of initializing the benefit evaluation model based on the basic data and marking it on the power consumption data image. The red dots in the figure are discrete points obtained by the first step of cubic spline interpolation, and the red curve is the curve corresponding to the original benefit evaluation model. The power consumption benefit of each point on the curve is consistent.

[0093] Step S3, error checking (improving the benefit evaluation model).

[0094] Using the original benefit evaluation model obtained in step S2, the predicted boundary enable signal SP under each register size is obtained according to the register size in the existing basic circuit file. Based on these predicted boundary enable signal SP values, the power consumption benefit is calculated using the process in the first step to obtain the actual power consumption benefit. The actual power consumption benefit obtained is compared with the theoretical power consumption benefit corresponding to the benefit evaluation model. In the embodiment, the situation where the deviation is greater than 1% of the total power consumption of the circuit structure is considered to be unsatisfactory. For the situation that does not meet this requirement, the actual power consumption benefit, the enable signal SP and the register size N are recorded as new data in the data set, and the data set is updated. Based on the updated data set, the benefit evaluation model is generated again. The newly generated benefit evaluation model also needs to pass the error check, and the above steps are repeated until all the actual power consumption benefit values ​​are obtained and the difference between the theoretical power consumption benefit values ​​is controlled within 1% of the total power consumption of the circuit structure. At this point, a benefit evaluation model with a certain accuracy can be obtained.

[0095] Step S4. Use the improved profit evaluation model to perform profit evaluation

[0096] After obtaining the final benefit evaluation model, you can use it when analyzing the target scenario to quickly determine whether deploying the gated clock can achieve the target benefit based on the register size and the SP of the enable signal in the target scenario.

[0097] like Figure 8 The example diagram of the benefit evaluation model generated by the application in the STB gated clock analysis process is shown. The netlist analyzed in the figure uses the same process library as in step S1. The subsequent circuit analysis link performs the parsing of the netlist file and the analysis of the specific circuit. It can be implemented by other existing solutions, which is not the focus of the embodiment of the present invention and will not be repeated. Through the analysis of the circuit, the size N of each register in the circuit, the circuit connection relationship and other circuit detailed information can be obtained. Based on the results of the circuit analysis, the STB gated clock is analyzed to find the specific circuit that meets the target scenario. For the specific circuit that meets the target scenario, the benefit evaluation model is used, and the active data file is introduced to perform the benefit evaluation. The above-mentioned active data file is used to provide the SP of the enable signal. If the SP of the enable signal provided is greater than the predicted boundary value given by the same register size in the benefit evaluation model, it means that the deployment of the STB gated clock cannot obtain the target power consumption benefit, otherwise it means that the deployment of the STB gated clock can obtain the target power consumption benefit. After determining all the beneficial STB gated clock opportunities in the circuit, the netlist is modified to realize the optimized netlist, and an analysis report is given based on the circuit analysis and the analysis of the STB gated clock.

[0098] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any changes or modifications made by any person skilled in the art based on the above disclosed technical contents shall be deemed as equivalent effective embodiments and shall fall within the scope of protection of the technical solution of the present application.

Claims

1. A power consumption benefit evaluation method for a specific gated clock scenario, characterized in that: Includes steps: Step 1. Generate basic data; Step 2. Construct an initial revenue evaluation model; Step 3. Improve the benefit evaluation model; Step 4. Use the improved benefit evaluation model to conduct benefit evaluation.

2. A power consumption benefit evaluation method for a specific gated clock scenario as claimed in claim 1, characterized in that: The step 1 specifically includes: Step 1.1: Obtaining the circuit netlist file: For the circuit structure of the STB gated clock application scenario, write the hardware code through HDL, and use the synthesis tool to synthesize a series of netlists of registers of different sizes under a specified process library; Step 1.2: For the netlists of the registers of different sizes in step 1.1, classify them according to whether the STB gated clock is deployed, and pair them one by one according to the register size for the subsequent generation of power consumption data; Step 1.3: For a set of paired netlists including two netlists with STB gating and without STB gating clock, set the SP of the enable signal according to the interval, calculate the power consumption of the netlists respectively through the power consumption calculation tool, and use the total power consumption of the netlist without STB gating to subtract the total power consumption of the netlist with STB gating, and get the power consumption benefit that can be obtained by deploying STB gating clock under the conditions of a certain register size and enable signal SP; Step 1.4: Perform the operation of step 1.3 on all paired netlists to collect a series of three-dimensional related data consisting of register size, enable signal SP, and power consumption benefit. Use this data to build a data set for subsequent generation of a benefit evaluation model.

3. A power consumption benefit evaluation method for a specific gated clock scenario as claimed in claim 1, characterized in that: In step 2, a two-step cubic spline interpolation fitting is performed on the data set constructed in step 1 to obtain a gated clock target benefit boundary expression determined by the register size and the enable signal SP. This expression is the benefit evaluation model, which determines the maximum enable signal SP required to achieve the target benefit by deploying the gated clock under each register size.

4. A method for evaluating power consumption benefits for a specific clock gated scenario as claimed in claim 3, characterized in that: The step 2 specifically includes: Step 2.1: According to the obtained data set, the first step of cubic spline interpolation, i.e., cubic spline interpolation of fixed register size, is performed. Specifically, according to the register size with data in the data set, cubic spline interpolation of the enable signal SP and the power consumption benefit is performed on the data corresponding to these register sizes to obtain the benefit expression corresponding to each specified register size; Step 2.2: According to 2.1, a series of profit expressions are fitted to determine the corresponding target profit points under different register sizes; Step 2.3: Perform the second step of cubic spline interpolation based on these target benefit points, that is, perform another cubic spline interpolation of fixed power consumption benefit. Specifically, the power consumption benefits of the target benefit points obtained are consistent, and cubic spline interpolation of the enable signal SP and the register size is performed; after the second step of cubic spline interpolation is completed, the expression corresponding to the target power consumption benefit is obtained, that is, the benefit evaluation model.

5. A power consumption benefit evaluation method for a specific clock gated scenario as claimed in claim 1, characterized in that: The step 3 specifically includes: Step 3.1: For the data set obtained in step 1, according to the register size data in the data set, substitute each register size into the profit evaluation model obtained in step 2 to obtain the boundary SP predicted by the profit evaluation model under each register size; Step 3.2: Use the process adopted in step 1 to obtain the power consumption data, substitute the boundary SP predicted by the benefit evaluation model into the calculation, and obtain the actual power consumption benefit corresponding to each predicted boundary SP; Step 3.3: According to the target benefit and the actual power consumption benefit obtained, the error of the benefit evaluation model is obtained. If the accuracy requirement is not met, the actual power consumption benefit, the enable signal SP and the register size N are recorded as new data in the data set, the data set is updated, and the benefit evaluation model is refitted and generated according to the process of step 2; The benefit evaluation model needs to meet the accuracy requirements for all register sizes of the circuit netlist in the data set; repeat the above operation until a benefit evaluation model that meets the accuracy requirements is obtained.

6. A method for evaluating power consumption benefits in a specific clock gated scenario according to claim 1, characterized in that: In step 4, when analyzing the target scenario, a benefit evaluation model is used to analyze whether the gated clock can obtain the target benefit based on the two parameters of the register size and the enable signal SP, specifically: During use, the maximum enable signal SP required for deploying the gated clock to achieve the target benefit under the register size is obtained based on the benefit evaluation model, which is used as the theoretical maximum SP; the provided enable signal SP is compared with the theoretical maximum SP. If the provided enable signal SP is less than the theoretical maximum SP, it is determined that deploying the gated clock can obtain the target benefit; otherwise, it is determined that deploying the gated clock cannot obtain the target benefit.

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