Integrated circuit design system, method and computer program product

Abstract

The embodiment of the invention provides an integrated circuit design system and method and a computer program product. The method is performed at least in part by a processor and includes determining a parameter of the voltage regulator based on a design specification of the voltage regulator. The method further includes determining model parameters of a voltage regulator (VR) model of the voltage regulator based on the parameters of the voltage regulator. The VR model does not contain a non-linear circuit assembly. The method further includes simulating the voltage regulator using the model parameters of the VR model.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the semiconductor field, and more particularly, to integrated circuit design systems, methods, and computer program products. Background Art

[0002] Integrated circuit (IC) devices typically include multiple semiconductor devices represented in an IC layout (or IC layout diagram). The IC layout is generated from an IC schematic (such as an electrical diagram of the IC device). At various steps in the IC design process, from the IC schematic to the IC layout used for the actual manufacture of the IC device, various checks and tests are performed to ensure that the IC device corresponding to the IC layout can be manufactured and operates as designed. Summary of the invention

[0003] One embodiment of the present invention provides a method for integrated circuit design, which is at least partially executed by a processor and includes: determining parameters of a voltage regulator based on a design specification of the voltage regulator; determining model parameters of a voltage regulator (VR) model based on the parameters of the voltage regulator, wherein the voltage regulator model does not contain nonlinear circuit components; and performing a simulation of the voltage regulator using the model parameters of the voltage regulator model.

[0004] Another embodiment of the present invention provides an integrated circuit design system, including a processor, wherein the processor is configured to: determine model parameters of a voltage regulator (VR) model of the voltage regulator based on a design specification of the voltage regulator, and simulate the voltage regulator using the model parameters of the voltage regulator model, wherein the voltage regulator model includes: a voltage-dependent voltage source connected between an input terminal and an output terminal, and a compensation network of a capacitor and a resistor, the compensation network being connected between the output terminal and a first node, and the model parameters of the voltage regulator model include: a resistance value of the resistor in the compensation network, a capacitance value of the capacitor in the compensation network, and a voltage value of the voltage-dependent voltage source that depends on the voltage value at the first node.

[0005] Yet another embodiment of the present invention provides a computer program product, comprising a non-transitory computer-readable storage medium containing instructions therein, which, when executed by a processor, causes the processor to: determine model parameters of a voltage regulator (VR) model of the voltage regulator based on a design specification of the voltage regulator, modify network model parameters of a network model of an input network connected to an input terminal of the voltage regulator based on a duty cycle of the voltage regulator, and simulate the voltage regulator and the input network using: the model parameters of the voltage regulator model, and the modified network model parameters of the network model. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a functional flow chart of at least a portion of an IC design and fabrication process according to some embodiments.

[0008] FIG. 2A to FIG. 2B are schematic cross-sectional views of various semiconductor devices according to some embodiments.

[0009] Figure 2C to Figure 2D is a block diagram of various power delivery systems including a voltage regulator for one or more IC devices, according to some embodiments.

[0010] Figure 2E Included are Bode plots of various components in a voltage regulator according to some embodiments.

[0011] Figure 3A is a circuit diagram of a voltage regulator according to some embodiments.

[0012] Figure 3B is a circuit diagram of a multi-phase voltage regulator according to some embodiments.

[0013] Figure 4 is a flow chart of a process for configuring, modeling, and verifying a voltage regulator according to some embodiments.

[0014] FIG. 5A to FIG. 5B are circuit diagrams of various models of a power delivery system including a voltage regulator according to some embodiments.

[0015] FIG. 5C to FIG. 5D is a schematic diagram of the conductance and capacitance matrix portion for modified nodal analysis (MNA) according to some embodiments.

[0016] FIG. 6A to FIG. 6B are circuit diagrams of various models of a power delivery system including a voltage regulator according to some embodiments.

[0017] 7A to 7C is a flow chart of various processes according to some embodiments.

[0018] Figure 8 is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0019] Fig. 9is a block diagram of an IC device manufacturing system and its related IC manufacturing process according to some embodiments. DETAILED DESCRIPTION

[0020] The present invention provides many different embodiments or examples for implementing the different components of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Source / drain may refer to source or drain, depending on the context.

[0021] Additionally, for ease of description, spatially relative terms such as "below," "beneath," and "below," "above," and "above," etc. may be used herein to describe the relationship of one element or component to other elements or components illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0022] In the IC design process, the power delivery system of the designed IC device is verified once or multiple times before manufacturing. The voltage regulator is a component in this power delivery system and needs to be simulated once or multiple times during the design stage. For this simulation, a model of the voltage regulator (hereinafter referred to as "VR model") is used.

[0023] In some embodiments, the VR model is configured to not include nonlinear circuit components. Such VR models without nonlinear circuit components are sometimes referred to as linear VR models. In at least one example configuration, the linear VR model consists essentially of linear circuit components. Examples of linear circuit components in one or more embodiments include, but are not limited to, voltage sources, resistors, capacitors, inductors, and the like. Examples of nonlinear circuit components in one or more embodiments include, but are not limited to, switches, control circuits, transistors, circuits including one or more switches and / or transistors, and the like. In some embodiments, the linear VR model is used in one or more simulations of a voltage regulator and / or a power delivery system including a voltage regulator. In at least one embodiment, because the linear VR model does not include nonlinear circuit components, the linear VR model can be used to simplify one or more simulations and reduce the computing resources and / or time required to complete such simulations, thereby improving the performance of one or more computer systems or processors performing the simulations. This is an improvement over other methods of using nonlinear VR models with one or more nonlinear circuit components in simulations. Due to the nonlinear circuit components of the nonlinear VR model, such simulations are time-consuming and / or require a large amount of computing resources. In some cases, simulations using nonlinear VR models may take days to complete. In contrast, according to some embodiments, when a simulation is performed using a linear VR model, the simulation time can be reduced from days to minutes.

[0024] In some embodiments, the linear VR model makes it possible and / or feasible to jointly simulate the voltage regulator with other components of the power delivery system (e.g., an input network connected between the input of the voltage regulator and the power supply, and / or an output network connected between the output of the voltage regulator and the load (e.g., the circuit of an IC device)). In at least one embodiment, the joint simulation includes an alternating current (AC) simulation (or AC analysis). Such AC simulation of the power delivery system from the input network through the voltage regulator to the output network is not available and / or feasible according to other methods using nonlinear VR models. In some embodiments, model parameters of the linear VR model are incorporated into a modified nodal analysis (MNA) and / or netlist for simulation. As described herein, other components, effects and / or advantages are within the scope of various embodiments.

[0025] Figure 1is a functional flow chart of at least a portion of an IC design and manufacturing process 100 according to some embodiments. At least a portion of the process 100 utilizes one or more electronic design automation (EDA) tools (or EDA systems) to generate, optimize, and / or verify the design of an IC device prior to manufacturing. In some embodiments, an EDA tool is one or more sets of executable instructions for execution by one or more processors or controllers or programmed computers, as described herein, to perform the indicated functions. In at least one embodiment, the process 100 is at least partially performed by a design house of an IC manufacturing system as described herein.

[0026] In IC design generation operation 110, an IC design of an IC device is provided or configured by a circuit designer. In some embodiments, the IC design of an IC device includes an IC schematic, i.e., a circuit diagram, of the IC device. In some embodiments, the schematic is generated or provided in the form of a schematic netlist, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) netlist. Other data formats for describing the design, such as Verilog, are available in some embodiments.

[0027] At power planning operation 120, a configuration of a power delivery system for an IC device is determined or designed. In some embodiments, the power delivery system includes a voltage regulator between a power source and a load (e.g., a functional circuit of the IC device). In at least one embodiment, the power delivery system also includes at least one of an input network between the power source and the voltage regulator and an output network between the voltage regulator and the load. At power planning operation 120, a configuration of one or more of the voltage regulator, the input network, and the output network is determined and / or estimated. Example configurations of voltage regulators are described in detail in the accompanying drawings. Figure 3A , Figure 3B Described. Example configurations of at least one of the input network and the output network include, but are not limited to, through silicon vias (TSVs), interconnect structures, power grid structures, and the like. In some embodiments, the interconnect structure or TSV is configured to deliver power from one point to another. In one example, the interconnect structure includes metal patterns in one or more metal layers connected by conductive vias in one or more via layers. In at least one embodiment, the power grid structure is configured to deliver power over a wide area, such as over the entire or a portion of an IC device. In one example, the power grid structure includes elongated power rails in multiple metal layers. For example, a first power rail in a first metal layer is elongated in a first direction, while a second power rail in a different second metal layer is elongated in a second direction orthogonal to the first direction. The first power rail in the first metal layer is connected to the second power rail in the second metal layer by a conductive via located at the intersection of the first power rail and the second power rail (in a plan view). Other configurations of the input network and / or the output network are within the scope of various embodiments.

[0028] In the pre-layout verification operation 130, one or more simulations and / or analyses are performed to determine whether one or more predetermined specifications and / or requirements are met. In the pre-layout verification operation 130, the IC design of the IC device provided or configured at the IC design generation operation 110 and / or the power delivery system configured at the power planning operation 120 are simulated. If the simulation results indicate that this is predetermined, the process proceeds to the next operation. If the specifications and / or requirements are not met, the IC design and / or the power delivery system are redesigned or configured. Example simulations and / or verifications performed in the pre-layout verification operation 130 include, but are not limited to, transient simulations 132, AC simulations 134, power efficiency verification 136, and the like.

[0029] In at least one embodiment, transient simulation 132 is configured to estimate and / or evaluate the behavior of the IC device over time (i.e., in the time domain). For example, transient simulation 132 is performed to obtain transient waveforms at various nodes, and the minimum and maximum voltages of each node are extracted from the transient waveforms. The extracted minimum and maximum voltages are used to determine whether one or more predetermined specifications and / or requirements are met.

[0030] In at least one embodiment, AC simulation 134 is configured to estimate and / or evaluate the behavior of the IC device within the frequency range of the IC design, i.e., in the frequency domain. For example, a small signal is input over the entire frequency range to verify the frequency response and / or gain characteristics of the IC design, which are used to determine whether one or more predetermined specifications and / or requirements are met. In at least one embodiment, for AC simulation 134, a small signal model of a voltage regulator is used.

[0031] In at least one embodiment, power efficiency verification 136 is configured to estimate and / or evaluate whether the power efficiency of the voltage regulator or the entire power delivery system meets predetermined specifications and / or requirements. For more details on power efficiency calculation and / or verification, see Figure 4 In some embodiments, power efficiency verification 136 is configured to further estimate and / or evaluate one or more other power indicators or parameters of the voltage regulator or power delivery system. The simulations and / or verifications described in pre-layout verification operation 130 are examples. In some embodiments, pre-layout verification operation 130 includes one or more further simulations and / or verifications. In some embodiments, one or more of transient simulation 132, AC simulation 134, power efficiency verification 136 are omitted.

[0032] In a cell placement and routing (or placement and routing) operation 140, a layout of an IC device (also referred to as an "IC layout") is generated based on an IC schematic. In at least one embodiment, the cell placement and routing operation 140 is sometimes referred to as automatic placement and routing (APR). The IC layout includes the physical locations of various circuit components of the IC device and the physical locations of various networks interconnecting the circuit components. For example, the IC layout is generated in the form of a graphic design system (GDS) or GDSII file. Other data formats for describing IC device designs, such as a design exchange format (DEF), are also within the scope of various embodiments. In at least one embodiment, the IC layout is generated by an EDA tool (such as an APR tool). Example operations of the APR tool include, but are not limited to, cell placement operations and routing operations.

[0033] In a cell placement operation, the APR tool performs cell placement. Cells configured to provide predefined functions and having pre-designed layouts are stored in one or more cell libraries, such as in a library exchange format (LEF). LEF is a specification that includes design rules and information about cells in the library. In at least one embodiment, LEF is used with DEF to represent the physical layout of the IC being designed. The APR tool accesses various cells in one or more cell libraries and places these cells in an adjacent manner to generate an IC layout corresponding to the IC schematic. Each cell includes one or more circuit components and / or one or more networks. Circuit components (also referred to as "circuit devices") are active elements (also referred to as active devices) or passive elements (also referred to as passive devices). Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high voltage transistors, high frequency transistors, p-channel and / or n-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with protruding source / drains, nanosheet FETs, nanowire FETs, and the like. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. Examples of networks include, but are not limited to, vias, conductive pads, conductive traces, and conductive redistribution layers, etc. Examples of cells include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), MUX, flip-flops, BUFFs, latches, delays, clocks, memories such as static random access memories (SRAMs), decoupling capacitors, analog amplifiers, logic drivers, digital drivers, etc. In some embodiments, passive elements are examples of linear circuit components, and / or active elements are examples of nonlinear circuit components.

[0034] In the routing operation, the APR tool performs routing to route various networks of interconnected placed circuit components. Routing is performed to ensure that the interconnections or networks of the routing meet a set of constraints. For example, the routing operation includes global routing, track allocation, and detailed routing. In the global routing process, routing resources for interconnections or networks are allocated. For example, the routing area is divided into multiple sub-areas, the pins (or terminals) of the placed circuit components are mapped to the sub-areas, and the network is constructed as a sub-area set in which the interconnection is physically routable. In the track allocation process, the APR tool assigns the interconnection or network to the corresponding conductive layer of the IC layout. In the detailed routing process, the APR tool routes the interconnection or network within the specified conductive layer and global routing resources. For example, detailed physical interconnections are generated in the corresponding sub-area set defined at the global routing and the conductive layer defined at the track allocation. After the routing operation, the APR tool outputs an IC layout including the placed circuit components and the routing network. The described APR tool is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the operations are omitted before, during, or after the operation, or one or more additional operations are added.

[0035] In the post-layout verification operation 150, one or more verifications are performed after the cell placement and routing operation 140. Example verifications include, but are not limited to, layout and schematic (LVS) checks, design rule checks (DRC), timing analysis, etc. Other verification processes can be used in various embodiments. For example, an LVS check is performed by an EDA tool to ensure that the generated IC layout corresponds to the design of the IC device. For example, a DRC is performed by an EDA tool to ensure that the IC layout meets certain manufacturing design rules, that is, to ensure the manufacturability of the IC device. Timing analysis is performed to estimate and check whether the delays in multiple paths in the IC layout meet predetermined timing requirements. When the inspection and / or verification of the post-layout verification operation 150 passes, the process proceeds to the manufacturing operation 170. If the inspection or verification fails, the IC layout is modified, for example at the modification operation 160.

[0036] At modification operation 160, the IC layout is modified directly or indirectly. In some embodiments, the process returns to cell placement and routing operation 140 to modify the IC layout directly. In at least one embodiment, the process returns to IC design generation operation 110 to change the IC device design, which in turn will result in indirect modification of the IC layout. Once the IC layout has been modified one or more times, one or more verifications are performed again at post-layout verification operation 150 to ensure that the modified IC layout meets all design rules, timing requirements, etc. In some cases, the modification verification process is repeated one or more times until it is determined that the IC layout is ready for manufacturing and the process continues to manufacturing operation 170, or it is determined that despite the modifications, the IC layout still does not meet all requirements and needs to be redesigned. Figure 1 The process 100 in FIG. 1 is an example. In some embodiments, the IC device design flow 100 includes one or more further operations, and / or omits one or more operations described.

[0037] Figure 2A is a schematic cross-sectional view of a semiconductor device 200A according to some embodiments.

[0038] Semiconductor device 200A includes die or chip 210, voltage regulator 220, and substrate 230. Chip 210 and voltage regulator 220 are stacked on substrate 230 along a thickness direction (Z direction) and electrically and mechanically connected to substrate 230 in a three-dimensional (3D) IC configuration.

[0039] Chip 210 includes circuit 212, a redistribution structure including various interconnect structures 213, 214, and a plurality of bumps 216, 217. In some embodiments, chip 210 corresponds to an IC device designed and manufactured according to process 100, and / or circuit 212 corresponds to a circuit of the IC device. In at least one embodiment, chip 210 includes a system on chip (SOC). The redistribution structure of chip 210 includes a plurality of metal layers and a plurality of via layers arranged alternately in the Z direction. A group of metal patterns in one or more metal layers are connected to each other through conductive vias in the intermediate via layer to form an interconnection structure. Various interconnection structures are formed in the redistribution structure of chip 210 to connect the circuit components of circuit 212 to each other, and / or to connect to an external circuit through corresponding bumps. For example, interconnection structure 213 connects circuit 212 to bump 217, or interconnection structure 214 connects circuit 212 to bump 216. Bumps 216, 217 electrically connect and mechanically bond chip 210 to substrate 230.

[0040] The voltage regulator 220 includes a plurality of bumps 225, 227, which correspond to the input and output of the voltage regulator 220. The bumps 225, 227 electrically connect and mechanically couple the voltage regulator 220 to the substrate 230. The substrate 230 is configured to electrically connect the voltage regulator 220 to the chip 210 as described herein. In some embodiments, the voltage regulator 220 corresponds to the voltage regulator configured and / or verified in the process 100, and / or the circuit 212 corresponds to the load of the voltage regulator 200.

[0041] The substrate 230 includes a redistribution structure having various interconnect structures 235, 237 and a plurality of bumps 236, 238. In some embodiments, the redistribution structure and / or interconnect structure of the substrate 230 are configured similarly to the redistribution architecture and / or interconnect structure of the chip 210. In some embodiments, the substrate 230 includes a die or chip whose own circuit (not shown) is connected to the voltage regulator 220 and / or the circuit 212. In at least one embodiment, the substrate 230 includes an interposer configured to be bonded to another substrate, interposer, or die (not shown) via the bumps 236, 238.

[0042] The interconnect structure 235 of the substrate 230 electrically connects the bump 225 corresponding to the input of the voltage regulator 220 to the bump 236 configured to be connected to a power supply (not shown). The interconnect structure 235 and the bumps 225, 236 constitute an example of an input network connected between the input terminal of the voltage regulator 220 and the power supply. Other input network configurations are within the scope of various embodiments. In one or more embodiments, for the purpose of performing one or more simulations described herein, at least one of the bumps 225, 236 is not considered as part of the input network, wherein any effect of the bump 225 and / or the bump 236 on the simulation results is negligible. In at least one embodiment, the input network includes a TSV extending through the substrate 230 in the Z direction to replace the interconnect structure 235 or a portion thereof. In some embodiments, the semiconductor device 200A includes a more complex input network with various interconnect structures, TSVs, bumps and / or other power transmission structures. In some embodiments, for the purpose of one or more simulations described herein, the entire input network is omitted, for example, when the interconnect structure 235 or the corresponding TSV is short, or the effect on the simulation results is negligible.

[0043] The interconnect structure 237 of the substrate 230 electrically connects the bump 227 corresponding to the output of the voltage regulator 220 to the bump 217 of the chip 210. As described herein, the bump 217 is connected to the circuit 212 through the interconnect structure 213, thereby transferring power from the output of the voltage regulator 220 to the load, that is, the circuit 212 of the chip 210. The interconnect structures 237, 213 and the bumps 227, 217 constitute an example of an output network connected between the output of the voltage regulator 220 and the load. Other output network configurations are within the scope of various embodiments. In one or more embodiments, at least one of the bumps 217, 227 or the interconnect structure 213 is not considered to be part of the output network, wherein any effect of the bump 217 and / or the bump 227 and / or the interconnect structure 213 on the simulation results can be ignored. In some embodiments, the semiconductor device 200A includes a more complex output network with various interconnect structures, bumps, power grid structures and / or other power delivery structures. In some embodiments, for purposes of one or more simulations described herein, the entire output network is omitted, for example, the interconnect structures 237 , 213 are shorter, or have negligible impact on the simulation results.

[0044] The configuration of the semiconductor device 200A described is an example. Other semiconductor device configurations are within the scope of various embodiments. For example, in some embodiments, the voltage regulator 220 is stacked and bonded to the chip 210. In at least one embodiment, the voltage regulator 220 is arranged on the lower side of the substrate 230 or the lower side of the chip 210, that is, the side where the bumps 236, 238 (or bumps 216, 217) are arranged, and bonded thereto. In some embodiments, the voltage regulator 220 includes an output inductor and / or an output capacitor electrically connected to the output of the voltage regulator 200. In at least one embodiment, at least one of the output inductor or the output capacitor is connected to the output of the voltage regulator 200. Figure 2A The physically separated output inductor and / or output capacitor are connected and bonded to the chip 210, the voltage regulator 220 (such as the chip 210 and the voltage regulator 220) by a set of separate bumps. Figure 2A 2 ) or substrate 230. In at least one embodiment, at least one of the output inductor or the output capacitor is embedded in the substrate 230.

[0045] Figure 2B 2 is a schematic cross-sectional view of a semiconductor device 200B according to some embodiments. Compared to the semiconductor device 200A in which the voltage regulator 220 is a component physically separated from the chip 210 (ie, the circuit 212) including the load, the semiconductor device 200B includes the voltage regulator and the load of the voltage regulator incorporated in the same chip.

[0046] The semiconductor device 200B includes a chip 240 and a substrate 250. The chip 240 is stacked on the substrate 250 along a thickness direction (Z direction), and is electrically and mechanically connected to the substrate 250 in a three-dimensional (3D) IC configuration.

[0047] Chip 240 includes a voltage regulator 241, a circuit 242, a redistribution structure including various interconnect structures 243, 244, 247, and a plurality of bumps 245, 246. Substrate 250 includes a redistribution structure having various interconnect structures, one of which is designated as 255, and a plurality of bumps 256, 258. Interconnect structure 243 electrically connects an input terminal (not numbered) of voltage regulator 241 to bump 245, which is further connected to bump 256 configured to be connected to a power source (not shown) through interconnect structure 255. Interconnect structure 247 electrically connects an output (not numbered) of voltage regulator 241 to circuit 242. In some embodiments, voltage regulator 241 and circuit 242 correspond to voltage regulator 220 and circuit 212, that is, circuit 242 includes a load of voltage regulator 241.

[0048] The interconnect structures 243, 255 and the bumps 245, 256 constitute an example of an input network connected between the input terminal of the voltage regulator 241 and the power supply. Other input network configurations are within the scope of various embodiments. In one or more embodiments, for the purpose of performing one or more simulations described herein, at least one of the bumps 245, 256 and / or at least one of the interconnect structures 243, 255 is not considered as part of the input network, wherein any effect of the bumps 245, the bumps 256, the interconnect structure 243 and / or the interconnect structure 255 on the simulation results can be ignored. In at least one embodiment, the input network includes a TSV extending through the substrate 250 in the Z direction to replace the interconnect structure 255 or a portion thereof. In some embodiments, the semiconductor device 200B includes a more complex input network with various interconnect structures, TSVs, bumps and / or other power transmission structures. In some embodiments, the entire input network is omitted for the purpose of one or more simulations described herein.

[0049] The interconnect structure 247 constitutes an example of an output network connected between the output of the voltage regulator 241 and the load (i.e., the circuit 242). Other output network configurations are within the scope of various embodiments. In some embodiments, the semiconductor device 200B includes a more complex output network with various interconnect structures, grid structures, and / or other power delivery structures. In some embodiments, the entire output network is omitted for the purpose of one or more simulations described herein.

[0050] In some embodiments, the semiconductor device 200B further includes an output inductor and / or an output capacitor, which are connected to the Figure 2B 240 or substrate 250. In at least one embodiment, at least one of the output inductor or the output capacitor is embedded in the substrate 250.

[0051] The semiconductor devices 200A and 200B are examples of semiconductor devices including an integrated voltage regulator (IVR). In the example, the IVR is located in the same die as the load ( Figure 2B ), or external to the die containing the load but within the same package ( Figure 2A ). Other IVR configurations are within the scope of various embodiments. A non-IVR is typically a voltage regulator in a separate package and is connected to the package containing the load via metal traces on a printed circuit board (PCB). Compared to a non-IVR, an IVR is arranged closer to the load (i.e., the circuit of the IC device), thereby eliminating or at least reducing the adverse effects of parasitic inductance and / or parasitic capacitance caused by pins, bumps, packages, and PCB traces. Therefore, in one or more embodiments, an IVR may provide one or more advantages over a non-IVR, including but not limited to reduced inductance and / or capacitance of the output inductor and / or output capacitor, higher operating frequency, improved dynamic response, reduced power supply noise, etc.

[0052] Figure 2C is a block diagram of a power delivery system 200C according to some embodiments. In some embodiments, the power delivery system 200C is configured with and / or delivers power to an IC device as described herein.

[0053] The power delivery system 200C includes an input network 260, a voltage regulator (VR) 270, and an output network 280. The input network 260 is connected between a power source (represented by an input voltage Vin) and an input of the voltage regulator 270. The output network 280 is connected between the output of the voltage regulator 270 and a load 290. In some embodiments, the input network 260 corresponds to a voltage regulator 270 with respect to the load 290. FIG. 2A to FIG. 2B The one or more input networks described above, the voltage regulator 270 corresponds to one or more of the voltage regulators 220 and 241, and the output network 280 corresponds to the output network 281 of FIG. FIG. 2A to FIG. 2B One or more output networks and / or loads 290 are described corresponding to FIG. 2A to FIG. 2B One or more loads, namely circuits 212 , 242 , are depicted.

[0054] The voltage regulator 270 is configured to convert the input voltage Vin received through the input network 260 into an output voltage Vout, and transmit the output voltage Vout to the load 290 through the output network 280. In some embodiments, the voltage regulator 270 is configured to provide a stable and reliable output voltage Vout regardless of changes in the input voltage Vin and / or the load 290. In one or more embodiments described herein, the voltage regulator 270 is a buck converter configured to step down the voltage, that is, output the output voltage Vout at a voltage level or voltage value lower than the input voltage Vin.

[0055] exist Figure 2C In the example configuration of FIG. , voltage regulator 270 is an open loop voltage regulator that does not include feedback from the voltage regulator output. Figure 2D An example configuration of a closed-loop voltage regulator with feedback is described.

[0056] Figure 2D is a block diagram of a power delivery system 200D according to some embodiments. In some embodiments, the power delivery system 200D is configured to have and / or deliver power to an IC device as described herein. Figure 2C to Figure 2D Corresponding components in are denoted by the same reference numerals.

[0057] Compared to the power delivery system 200C, the power delivery system 200B includes a voltage regulator 275 as a closed-loop voltage regulator. Figure 2D In the example configuration of FIG. 2 , the closed-loop voltage regulator 275 is configured by adding a compensation circuit 273 in the feedback connection 271 in the open-loop voltage regulator 270 . Figure 3A Example circuits of an open-loop voltage regulator 270 , a compensation circuit 273 , and a closed-loop voltage regulator 275 are described.

[0058] In some embodiments, simulations described herein, for example, with respect to pre-layout verification operations 130, include joint simulations of power delivery system 200C from input network 260 through voltage regulator 270 to output network 280, or joint simulations of power delivery system 200D from input network 260 through voltage regulator 275 to output network 28. In some embodiments, at least one of input network 260 or output network 280 is omitted from simulations of pre-layout verification operations 130 as described herein.

[0059] Figure 2E Included are Bode plots 291 , 293 , 295 of various components in a voltage regulator according to some embodiments.

[0060] Each of the Bode plots 291, 293, 295 shows the relationship between the signal amplitude or gain of the corresponding component and the frequency. Specifically, the Bode plot 291 shows the relationship of an open-loop voltage regulator (such as the voltage regulator 270). The Bode plot 293 shows the relationship of a compensation circuit (such as the compensation circuit 273). The Bode plot 295 shows the relationship of a closed-loop voltage regulator (such as the voltage regulator 275). By adding the compensation circuit 273 to the open-loop voltage regulator 270 to obtain the voltage regulator 275, the Bode plot 295 is obtained as a result of the combination of the Bode plot 291 and the Bode plot 293.

[0061] Bode plot 291 with parameter F LC (also called the “pole”) and F ESR (also called "zeros"), which are determined by the output inductor and output capacitor of the open loop voltage regulator 270. The Bode plot 293 has poles called F p2 、F p3 and zero point F z1 、F z2 Multiple parameters of the pole F p3 is half of the switching frequency Fs (also referred to herein as Fsw). The remaining poles and / or zeros of the Bode plot 293 depend on the parameters of the compensation network in the compensation circuit 273. Figure 2E In the example configuration in, the compensation circuit 273 includes a Type III compensation circuit and includes a compensation network of various resistors and capacitors. By configuring the parameters of the compensation network, the desired poles and zeros can be achieved in the Bode plot 293, thereby achieving the desired frequency F0 through which the Bode plot 295 passes through the zero. The frequency F0 is sometimes referred to as the bandwidth (BW) of the voltage regulator 275. The described Type III compensation circuit is an example. Other compensation circuit configurations, such as Type I compensation circuits, Type II compensation circuits, or any other type of compensation circuit, are within the scope of various embodiments. In some embodiments where the closed-loop voltage regulator includes a Type III compensation circuit, unconditional stability of any type of output capacitor can be achieved over a wide range of equivalent series resistance (ESR) values ​​of the output capacitor.

[0062] Figure 3A is a circuit diagram of a voltage regulator 300A according to some embodiments. In some embodiments, the voltage regulator 300A corresponds to the reference Figure 1 and FIG. 2A to FIG. 2E One or more voltage regulators as described in one or more of . Figure 3A In the example configuration, voltage regulator 300A is a buck converter.

[0063] The voltage regulator 300A includes an input IN, an output OUT, power switches FET1, FET2, a drive circuit including drivers DRV1, DRV2, an output inductor LO , output capacitor C O , a feedback connection 371 , a compensation circuit including a compensation network 372 and an error amplifier EA, and a control circuit including a pulse width modulation (PWM) generator 380 .

[0064] The input IN is configured to receive an input voltage Vin from a power source. The output OUT is configured to output an output voltage Vout corresponding to the input voltage Vin to a current source I Load In some embodiments, the current source I Load The load schematically represented corresponds to load 290. In at least one embodiment, voltage regulator 300A is configured such that I Load The change in I will not cause the output voltage Vout to exceed the predetermined acceptable limit, thus meeting the voltage regulator's goal, I Load is the actual current consumed by the load (e.g. the chip's circuitry) and is expected to fluctuate depending on the chip's activity.

[0065] The power switch FET1 has a source / drain connected to the input IN, another source region / drain connected to the node 312, and a gate connected to the output of the corresponding driver DRV1. The power switch FET2 has a source / drain connected to the ground at the node 314, another source region / drain connected to the node 312, and a gate connected to the output of the corresponding driver DRV2. Sometimes, the power switches FET1 and FET2 are respectively referred to as high-side switches and low-side switches. In some embodiments, the power switches FET1, FET2 are metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs). Other switch or transistor configurations are within the scope of various embodiments.

[0066] Output inductor L O The first end of the output capacitor CO is connected to the node 312, and the second end is connected to the output OUT. The first end of the output capacitor CO is connected to the node 314, and the second end is connected to the output OUT. In some embodiments, as shown in FIG. Figure 2A , Figure 2B The output inductor L O or output capacitor C O At least one of the components is a component that is physically separated from the remaining components of the voltage regulator 300A.

[0067] The compensation network 372 is connected between the output OUT and the PWM generator 380. The compensation network 372 includes capacitors Cc1, Cc2, Cf3 and resistors Rc1, Rf1, Rf3. The first end of the resistor Rf1 is connected to the node 320, which is connected to the output OUT through the feedback connection 371, and the second end is connected to the node 322. The first end of the capacitor Cf3 is connected to the node 320, and the second end is connected to the node 321. The first end of the resistor Rf3 is connected to the node 321, and the second end is connected to the node 322. The first end of the capacitor Cc2 is connected to the node 322, and the second end is connected to the node 324. The first end of the capacitor Cc1 is connected to the node 323, and the second end is connected to the node 324. The first end of the resistor Rc1 is connected to the node 322, and the second end is connected to the node 323.

[0068] exist Figure 3A In the example configuration in FIG. 3 , the error amplifier EA is an operational amplifier. The error amplifier EA has an inverting input terminal connected to a node 322, a non-inverting input terminal configured to receive a predetermined reference voltage Vref, and an output terminal connected to a node 324. The error amplifier EA is configured to output an error voltage Ve corresponding to the output voltage Vout at an output OUT.

[0069] The PWM generator 380 includes a comparator COMP. Figure 3A In the example configuration in , the comparator COMP is an operational amplifier. The comparator COMP has an inverting input terminal configured to receive the sawtooth voltage VOSC, a non-inverting input terminal connected to the output terminal of the error amplifier EA at a node 324, and an output terminal connected to the input terminals of the drivers DRV1, DRV2. In at least one embodiment, each of the drivers DRV1, DRV2 includes one or more transistors. In some embodiments, the control circuit of the voltage regulator 300A also includes a sawtooth voltage generation circuit (not shown), which includes an oscillator and is configured to generate the sawtooth voltage VOSC. In at least one embodiment, the sawtooth voltage VOSC is provided by a sawtooth voltage generation circuit external to the voltage regulator 300A.

[0070] The comparator COMP of the PWM generator 380 is configured to compare the error voltage Ve output by the error amplifier EA with the sawtooth voltage VOSC, and output a PWM control signal d0 (sometimes also referred to as a duty cycle command) to the input terminals of the drivers DRV1 and DRV2 based on the comparison result. The input of the driver DRV1 is a non-inverting input, and therefore, the driver DRV1 is configured to drive (e.g., turn on) the power switch FET1 according to the PWM control signal d0. The input of the driver DRV2 is an inverting input, and therefore, the driver DRV2 is configured to drive (e.g., turn on) the power switch FET2 according to the inverted version of the PWM control signal d0. In some embodiments, the power switches FET1 and FET2 are not turned on by the corresponding drivers DRV1 and DRV2 at the same time.

[0071] When the power switch FET1 is turned on, the power switch FET2 is turned off. During the on-time of the power switch FET1 corresponding to the duty cycle of the PWM control signal d0, the input voltage Vin passes through the turned-on power switch TFT1 and the output inductor L O The current flows through the output inductor L O The inductor current I L0 Gradually increase. Output inductor L O and output capacitor C O Part of the energy is stored during the on-time of the power switch FET1.

[0072] When the power switch FET2 is turned on, the power switch FET1 is turned off. During the period when the power switch FET2 is turned on, the current stored in the output inductor L O and / or output capacitor C O The energy in the output is supplied to the load through the output OUT. O The inductor current I L0 The inductor current I L0 The rise and fall of is sometimes referred to as ripple current or current ripple. Due to the switching operation of the power switches FET1, FET2, the output voltage Vout has a similar voltage ripple.

[0073] The error amplifier EA is configured to generate an error voltage Ve corresponding to the output voltage Vout and the resistor and capacitor in the compensation network 372. The comparator COMP of the PWM generator 380 is configured to compare the error voltage Ve output by the error amplifier EA with the sawtooth voltage VOSC, and adjust the duty cycle of the PWM control signal d0 based on the comparison result, thereby adjusting the on-time of the power switch FET1, so as to control the output voltage Vout to be stable or substantially stable.

[0074] exist Figure 3AIn the example configuration in , the voltage regulator 300A is a closed-loop voltage regulator. In some embodiments, and the voltage regulator 300A corresponds to the closed-loop voltage regulator 275, the feedback connection 371 corresponds to the feedback connection 271, and the compensation network 372 corresponds to the compensation network of the compensation circuit 273. In at least one embodiment, the feedback connection 371 and the compensation circuit including the compensation network 372 and the error amplifier EA are omitted, and the voltage regulator 300A becomes an open-loop voltage regulator corresponding to, for example, the open-loop voltage regulator 270. The configuration and operation of the described voltage regulator 300A are examples. Other voltage regulator configurations and / or operations are within the scope of various embodiments. For example, although the control circuit of the voltage regulator 300A is described as implementing PWM control through a PWM generator 380, different controls, such as pulse frequency modulation (PFM), are implemented in one or more embodiments.

[0075] exist Figure 3A In the example configuration, the voltage regulator 300A is a single-phase voltage regulator. Figure 3B Example configurations of multiphase voltage regulators are described.

[0076] Figure 3B is a circuit diagram of a voltage regulator 300B according to some embodiments. In some embodiments, the voltage regulator 300A corresponds to the reference Figure 1 and FIG. 2A to FIG. 2E One or more voltage regulators described in one or more of . FIG. 3A to FIG. 3B Corresponding components in are denoted by the same reference numerals.

[0077] Compared to the voltage regulator 300A which is a single-phase voltage regulator, the voltage regulator 400B is a multi-phase voltage regulator including N voltage regulator circuits 341, 342, ... 34N corresponding to the N phases of the voltage regulator 300B, where N is a natural number greater than 1. When N=1, the voltage regulator 300B becomes a single-phase voltage regulator corresponding to the voltage regulator 300A. Each voltage regulator circuit 341, 342, ... 34N includes a high-side switch Q11, Q21, ... QN1, a low-side switch Q12, Q22, ... QN2, an output inductor L1, L2, ... LN, a PWM generator PWM1, PWM2, ... PWMN, configured to output a corresponding PWM control signal d1, d2, ... dN, and a sensing circuit or element schematically shown at 351, 352, ... 35N and configured to detect a corresponding inductor current IL1, IL2, ... ILN flowing through the corresponding output inductor L1, L2, ... LN. In some embodiments, for each of the voltage regulator circuits 341, 342, ... 34N, the high-side switch Q11, Q21, ... QN1 corresponds to the power switch FET1, the low-side switch Q12, Q22, ... QN2 corresponds to the power switch FET2, and the output inductor L1, L2, ... LN corresponds to the output inductor L O , inductor currents IL1, IL2, ...ILN correspond to inductor current IL0, PWM generators PWM1, PWM2, ...PWMN correspond to PWM generator 380, and PWM control signals d1, d2, ...dN correspond to PWM control signal d0.

[0078] For simplicity, Figure 3B 34N include a first driver (not shown) corresponding to the driver DRV1 and configured to drive high-side switches Q11, Q21, ... QN1 based on PWM control signals d1, d2, ... dN. Each voltage regulator circuit 341, 342, ... 34N also includes a second driver corresponding to the driver DRV2 and configured to drive low-side switches Q12, Q22, ... QN2 based on an inverted version of the PWM control signals d1, d2, ... dN. In some embodiments, the voltage regulator 300B also includes a compensation network connected between the input and output of the error amplifier EA. In the example configuration, this compensation network corresponds to the compensation network 372.

[0079] In each of the voltage regulator circuits 341, 342, ... 34N, the PWM generators PWM1, PWM2, ... PWMN are configured to generate PWM control signals d1, d2, ... dN having corresponding duty cycles and corresponding phases based on the sawtooth voltage VOSC, the error voltage Ve, and the signal corresponding to the inductor current IL1, IL2, ... ILN sensed by the sensing circuit or element 351, 352, ... 35N. In some embodiments, the phases of the PWM control signals d1, d2, ... dN are different from each other and separated from each other at intervals of 360 degrees / N. The described multi-phase voltage regulator configuration is an example. Other multi-phase voltage regulator configurations are within the scope of various embodiments.

[0080] Figure 4 is a flow chart of a process 400 of configuring, modeling, and verifying a voltage regulator according to some embodiments. In some embodiments, process 400 is performed at least in part by a computer system or processor, as described herein.

[0081] Will refer to Figure 2E , FIG. 3A to FIG. 3B , FIG. 5A to FIG. 5D describe Figure 4 400 in the process. FIG. 5A to FIG. 5B are circuit diagrams of various models of a power delivery system including a voltage regulator according to some embodiments. FIG. 5C to FIG. 5D is a partial schematic diagram of a conductance and capacitance matrix for a modified nodal analysis (MNA) for voltage regulator simulation according to some embodiments. Figure 4 , FIG. 5A to FIG. 5D The voltage regulator and / or power delivery system described corresponds to reference Figure 1 , FIG. 2A to FIG. 2E , FIG. 3A to FIG. 3B One or more voltage regulators, and / or one or more power delivery systems described in one or more of the embodiments. Figure 2E , FIG. 3A to FIG. 3B , FIG. 5A to FIG. 5D Corresponding components in the drawings are denoted by the same reference numerals. Figure 2E , FIG. 3A to FIG. 3B , FIG. 5A to FIG. 5D In the described example embodiment, Figure 4 The voltage regulator to be configured, modeled and verified in the process 400 corresponds to the voltage regulator 300A and / or the voltage regulator 400B. For simplicity, reference is made to the voltage regulator 300A in the description of the following embodiments. The described exemplary embodiments are also applicable to the voltage regulator 300B.

[0082] At operation 410 in process 400 , design specifications for a voltage regulator 300A to be configured are received.

[0083] In some embodiments, one or more design specifications are provided by a human circuit designer. In at least one embodiment, one or more design specifications are predetermined and loaded from a library and / or from a previously designed voltage regulator. In some embodiments, one or more design specifications are manually entered or automatically loaded into a computer system as described herein. Examples of design specifications include, but are not limited to, input voltage Vin, output voltage Vout (also referred to as Vo), number of phases N, switching frequency F sw 、V ovrsht 、V undrsht , △I L-per-phase(pk-pk) , Vcap ripple, V cap-ripple ,I STEP , BW, etc.

[0084] about FIG. 3A to FIG. 3B The input voltage Vin, the output voltage Vout (or Vo), and the number of phases N are described.

[0085] Switching frequency F sw is the rate at which the power switch (e.g., power switches FET1, FET2) is turned on and off. The switching period of the voltage regulator 300A is determined as 1 / Fsw. In some embodiments, the switching frequency Fsw is several hundred KHz. This is an example, and other frequency values ​​of Fsw are within the scope of various embodiments.

[0086] During the transient response, when the voltage at the output OUT exceeds the final steady-state value (e.g., the output voltage V according to the design specification), o ), a voltage overshoot occurs. Voltage overshoot is a measure of how much the voltage regulator responds beyond the desired output voltage before settling. V ovrsht is the voltage overshoot limit set in the design specification. The voltage regulator 300A will be configured so that the maximum output voltage during transient response does not exceed V ovrsht In some embodiments, V ovrsht is replaced by the overshoot percentage, which is a percentage of the steady-state value.

[0087] During the transient response, when the voltage at the output OUT drops to the final steady-state value (e.g., the output voltage V according to the design specification), o ) below, voltage undershoot occurs. Voltage undershoot is a measure of how far the voltage regulator’s response will drop below the desired output voltage before stabilizing. V undrsht is the voltage undershoot limit set in the design specification. The voltage regulator 300A will be configured so that the minimum output voltage during transient response does not drop to V undrsht In some embodiments, V undrsht The undershoot percentage is replaced by a percentage of the steady-state value.

[0088] △I L-per-phase(pk-pk) Refers to the peak-to-peak inductor ripple current per phase. It is the maximum change (or swing) in the inductor current flowing through the output inductor during a single switching cycle in the voltage regulator. For example, as described with respect to the voltage regulator 300A, when the inductor current I L0 When ΔI rises and falls accordingly during the on-time of the power switch FET1 and the on-time of the power switch FET2, L-per-phase(pk-pk) Corresponding to the inductor current I LO Similarly, in the voltage regulator 300B, for each phase, for example, for the first phase corresponding to the voltage regulator circuit 341, when the inductor current I L1 When the on-time of the high-side switch Q11 and the on-time of the low-side switch Q12 rise and fall accordingly, △I L-per-phase(pk-pk) Corresponds to the peak-to-peak swing between the maximum and minimum values ​​of the inductor current IL1. L-per-phase(pk-pk) is the maximum limit on the peak-to-peak swing of the corresponding inductor current.

[0089] V cap-ripple is the output capacitor C O The maximum limit of the peak-to-peak ripple voltage across the terminals. This design specification is used to estimate the output capacitor C required to reduce its peak-to-peak ripple voltage to below the specified limit (i.e., below Vcap ripple). O The minimum capacitance value.

[0090] I max is the maximum I of the voltage regulator 300A configuration Load .

[0091] I STEP is a voltage regulator 300A configured to handle the I Load In some embodiments, it is the maximum step change of ILoad that the voltage regulator 300A is configured to operate effectively.

[0092] BW is the bandwidth of the voltage regulator 300A. Figure 2E As shown, BW is F0, which represents the frequency range over which the voltage regulator 300A is configured to effectively respond to changes in load and / or input conditions. In some embodiments, F0 is set to F sw / 5 or F sw / 10. These are examples, and other frequency values ​​of F0 are within the scope of various embodiments.

[0093] At operations 420 , 430 in process 400 , parameters of the voltage regulator 300A to be configured are determined based on the design specifications received at operation 410 .

[0094] Specifically, in operation 420, reference Figure 3A , based on the received design specifications, the output capacitor C O The capacitance value and output inductor L O The inductance value of is determined as a parameter of the voltage regulator 300A. For simplicity, unless otherwise specified, the capacitance values, inductance values, and resistance values ​​of capacitors, inductors, and resistors are represented herein by the same reference numerals of the corresponding capacitors, inductors, and resistors.

[0095] In some embodiments, based on the received design specifications, the output capacitor C is determined using the following equation: O The capacitance value C and output inductor L O Inductance value L:

[0096] [1]

[0097] [2]L EQ =L / N (1.2)

[0098] [3]

[0099] [4]

[0100] [5]

[0101] [6]C=max(C ripple ,C ovrsht ,C undrsht ) (1.6)

[0102] [7]

[0103] [8]D=V o / V in (1.7)

[0104] [9]

[0105]

[10] m=floor(ND) (1.9)

[0106] In equation (1.7), D represents the duty cycle. In equation (1.8), △I (pk-pk) Refers to the output capacitor C O The total peak-to-peak ripple current of . In equation (1.9), “floor” represents the floor function.

[0107] In some embodiments, the output capacitor C is determined according to equations (1.1) and (1.6). OThe capacitance value C and output inductor L O The inductance value L is the minimum capacitance and inductance required to meet the design specification. In some embodiments, for example, when the output capacitor C is specified in the design specification O The capacitance value C or output inductor L O When at least one of the inductance values ​​L is greater than or equal to 0, operation 420 may be partially or entirely omitted.

[0108] In operation 430 of process 400, reference is made to Figure 3A , the resistance values ​​and capacitance values ​​of various resistors and capacitors in the compensation network 372 are determined as further parameters of the voltage regulator 300A.

[0109] In some embodiments, R f1 The resistance value of R is selected or predetermined by a human circuit designer or a computer system or processor. In at least one embodiment, R is selected or predetermined based on the technology and / or materials that will be used to manufacture the resistors and capacitors in the compensation network 372. f1 In some embodiments, based on R f1 and design specifications, the resistance and capacitance values ​​of the remaining resistors and capacitors in the compensation network 372 are determined using the following equations:

[0110]

[11]

[0111]

[12]

[0112]

[13]

[0113]

[14]

[0114]

[15]

[0115]

[16]

[0116]

[17] V saw-tooth =V ref / D (2.6)

[0117]

[18]

[0118]

[19]

[0119] Equation (2.6) is V saw-tooth The approximate value of V saw-tooth About Figure 3A Describes the sawtooth voltage V OSC In some embodiments, the sawtooth voltage V OSC With the switching frequency Fsw The same frequency is generated.

[0120] In some embodiments, for the overall response including transient and steady state, Vref=Vout=D×Vin. For transient simulation, Vref is set to ground connection, that is, the final voltage value of Vout will reach zero (which means that the transient will gradually disappear). In steady state, Vref is not grounded, and the final voltage value of Vout will reach Vref in steady state.

[0121] F in equation (2.7) LC and F in equation (2.8) ESR Also refer to Figure 2E Described, namely F LC are the poles corresponding to L and C, and F ESR is a zero point caused by the equivalent series resistance (ESR) of the output capacitor CO, which is a parasitic resistance value. In some embodiments, the ESR is a predetermined value depending on various factors including but not limited to manufacturing technology, materials, dimensions, etc.

[0122] In some embodiments, Figure 2E As shown, the resistance and capacitance values ​​of the resistors and capacitors in the compensation network 372 are selected and / or configured based on equations (2.1)-(2.5) to achieve a desired bandwidth (BW or F0) and a desired loop gain, as shown in the example Bode plot 295. In at least one embodiment, the resistance and capacitance values ​​of the resistors and capacitors in the compensation network 372 selected and / or configured based on equations (2.1)-(2.5) further achieve stability of the closed-loop voltage regulator 300A. In some embodiments, the stability of a closed-loop system (such as the closed-loop voltage regulator 300A) refers to the ability of the system to maintain its desired performance without exhibiting unbounded or oscillatory behavior over time. In other words, a stable closed-loop system will respond to any input or disturbance by settling to a steady state without diverging or oscillating uncontrollably. In some embodiments, for example, when one or more or all of the resistors and capacitors of the compensation network 372 are specified in the design specification, operation 430 is partially or entirely omitted.

[0123] At operation 440 of process 400, model parameters of the linear VR model of voltage regulator 300A are determined. FIG. 5A to FIG. 5B Example embodiments are described.

[0124] Figure 5A is a circuit diagram of a model 500A of a power delivery system 500 including a voltage regulator 300A, according to some embodiments.

[0125] Model 500A includes a network model 560 of an input network and a schematic model 570 of voltage regulator 300A. In some embodiments, the input network modeled by network model 560 corresponds to reference FIG. 2A to FIG. 2D One or more input networks described by Figure 5A In the example configuration, the power delivery system 500 does not include FIG. 2A to FIG. 2D The output network, or for the purpose of one or more simulations, such output network may be ignored.

[0126] The network model 560 includes multiple components that model the input network. Figure 5A In the example configuration of , the components include resistors 561, 564, inductor 562 and capacitor 563. Resistor 561 and inductor 562 are connected in series between the input IN and the positive terminal 511 of the power supply schematically represented by the input voltage Vin. Capacitor 563 and resistor 564 are connected in series between the input IN and the ground (e.g., node 314). The network model parameters of the network model 560 include the resistance value RLin of resistor 561, the inductance value Lin of inductor 562, the capacitance value Cin of capacitor 563, and the resistance value RCin of resistor 564. In some embodiments, the network model parameters are predetermined based on various details of the input network (such as configuration, size, material, etc.). The configuration of the network model 560 is an example. Other network model configurations are within the scope of various embodiments.

[0127] Schematic model 570 is a VR model of voltage regulator 300A and is configured based on one or more parameters determined at operations 420, 430 and / or based on one or more design specifications provided at operation 410. Schematic model 570 includes various components described with respect to voltage regulator 300A. Schematic model 570 also includes an output inductor L O and output capacitor C O Model.

[0128] In schematic model 570, the output inductor L O The output inductor L is modeled by the inductor L and the resistor DCR. The inductance of the inductor L is determined by equation (1.1). The resistor DCR represents the output inductor L. O The parasitic DC resistance value of the output inductor L O The physical and electrical configuration of the

[0129] In schematic model 570, the output capacitor C O The output capacitor C is modeled by the capacitor C, the resistor ESR, and the inductor ESL. The capacitance of the capacitor C is determined by equations (1.3) to (1.6). The resistor ESR represents the output capacitor C. OThe parasitic resistance value of the inductor is the value of the output capacitor C when modeled in the equivalent circuit. O The equivalent inductance that appears in series with an ideal capacitor (eg, C). In some embodiments, ESR and ESL are predetermined values ​​that depend on various factors including, but not limited to, the manufacturing technology, materials, size, and configuration of the output capacitor CO.

[0130] In addition to passive components, such as the various resistors, capacitors, and inductors described above, which are linear circuit components in the simulation, the schematic model 570 also includes active components or circuits, such as power switches FET1, FET2, drivers DRV1, DRV2, PWM generator 380, and error amplifier EA, which are nonlinear circuit components in the simulation. Due to the nonlinearity of the schematic model, simulations performed using the schematic model 570 may consume time and / or resources. In some embodiments, the schematic model 570 is further converted into an equivalent model, i.e., a linear VR model, to reduce the computational resources and / or time required to complete the simulation of the voltage regulator 300A.

[0131] Figure 5B is a circuit diagram of a model 500B of a power delivery system 500 according to some embodiments.

[0132] Model 500B includes a modified network model 565 of the input network and an equivalent model 575 of the voltage regulator 300A. The equivalent model 575 is a linear VR model, the model parameters of which are to be determined.

[0133] The modified network model 565 includes similar components to the network model 560. However, the network model parameters of the network model 560 are modified according to the duty cycle D of the voltage regulator 300A to become the modified network model parameters of the modified network model 565. Specifically, the modified network model parameters in the modified network model 565 include the modified resistance value D of the resistor 561. 2 ×RLin, modified inductance value D of inductor 562 2 ×Lin, modified capacitance value Cin / D of capacitor 563 2 and the modified resistance value D of resistor 564 2 ×RCin.

[0134] Equivalent model 575 is equivalent to schematic model 570 and does not include active components or circuits. In at least one embodiment, equivalent model 575 is a small signal model that can be used for AC simulations (such as AC simulation 134). Figure 5BIn the example configuration in FIG. 5 , the equivalent model 575 has no nonlinear circuit components, such as switches and transistors, and includes various resistors, capacitors, inductors, and voltage sources, which are all linear circuit components. The error amplifier EA is part of the equivalent model 575. The error amplifier EA is an operational amplifier configured to operate in the linear region, and therefore, the equivalent model 575 remains linear. In some embodiments, the error amplifier EA, i.e., the operational amplifier configured to operate in the linear region, is converted into a SPICE netlist or integrated with the rest of the network in matrix form, for example, as Figure 5C , Figure 5D shown.

[0135] Similar to the schematic model 570, the equivalent model 575 includes a capacitor C, a resistor ESR, an inductor ESL, and resistors and capacitors in the compensation network 372. The difference between the equivalent model 575 and the schematic model 570 includes a voltage source 571, a resistor 572, an inductor 573, and a resistor Rx. The voltage source 571, the resistors 572, and 573 are connected in series between the input IN and the output OUT. The resistor Rx is connected between the output OUT and the node 320. The resistance values, capacitance values, and inductance values ​​of the resistors, capacitors, and inductors in the equivalent model 575 constitute the model parameters of the equivalent model 575. In some embodiments, the voltage value of the voltage source 571 is also a model parameter of the equivalent model 575.

[0136] Resistor 572 replaces resistor DCR of schematic model 570. The resistance value of resistor 572 is determined as (DCR + R SW ) / N, where R SW is the parasitic resistance value of the power switches FET1 and FET2.

[0137] Inductor 573 replaces inductor L of schematic model 570. The inductance value of inductor 573 is LEQ determined by equation (1.2).

[0138] Resistor Rx corresponds to the parasitic resistance value of feedback connection 371. In some embodiments, the resistance value of Rx is selected or predetermined by a human circuit designer or a computer system or processor. In at least one embodiment, the resistance value of Rx is selected or predetermined based on the configuration and / or material of feedback connection 371. For example, Rx=1uΩ. Other resistance values ​​of Rx are within the scope of various embodiments.

[0139] The voltage source 571 has a voltage determined as v(d)×V in / V saw-toothWhere v(d) is the voltage at node d connected to node 324, which corresponds to the output of the error amplifier EA. In other words, the voltage value of voltage source 571 corresponds to voltage v(d). In some embodiments, voltage source 571 is a voltage dependent voltage source or voltage controller voltage source (VCVS), which is a voltage source that depends on or is controlled by another voltage in the circuit (i.e., v(d)). In other words, the voltage value of voltage source 571 depends on voltage v(d). In some embodiments, the ratio V in / V saw-tooth is a constant, therefore, the voltage value of the voltage source 571 does not depend on the input voltage Vin. In other words, the voltage value of the voltage source 571 is independent of the input voltage Vin. In some embodiments, v(d)=Ve.

[0140] Figure 5B The upper part of the equivalent model 575 in , including resistor 572 , inductor 573 , capacitor C, resistor ESR and inductor ESL, corresponds to an equivalent model of an open-loop voltage regulator, such as voltage regulator 270 . Figure 5B The lower portion of the equivalent model 575 in FIG. 5 includes the compensation network 372 and the resistor Rx, corresponding to the feedback connection and the compensation circuit therein, such as the feedback connection 271 and the compensation circuit 273. In some embodiments, the open-loop voltage regulator can be converted to a closed-loop voltage regulator by adding the lower portion of the equivalent model 575, the resistor Rx, and the voltage source 571 associated with the feedback connection to the upper portion, such as Figure 2C to Figure 2D As shown. In at least one embodiment, the upper part (i.e., the equivalent model of the open-loop voltage regulator) is present or pre-configured. By simply adding the lower part (i.e., the compensation network) and the resistor Rx to the existing or pre-configured upper part, the equivalent model 575 of the closed-loop voltage regulator 300A can be quickly obtained. In some embodiments, the configuration and / or more parameters of the compensation network are variable and / or customizable, which allows the resulting closed-loop voltage regulator to be quickly and / or easily reconfigured to meet design specifications and / or one or more further design considerations.

[0141] Model 500B also includes a plurality of nodes for defining or describing model 500B, and / or determining voltages and / or currents of the nodes in one or more simulations. For example, modified network model 565 includes node j and node j+1. Resistor 561 is connected between node j and node j+1. Inductor 562 is connected between node j+1 and input IN. Figure 5BIn the example configuration in , the ellipsis (i.e., "...") indicates that, in one or more embodiments, the modified network model 565 also includes one or more nodes having one or more passive components, such as resistors, capacitors, and / or inductors. As described above, the description and illustrated configuration of the modified network model 565 are examples, and other network model configurations are also within the scope of various embodiments.

[0142] The equivalent model 575 includes a node M between the inductor ESL and the capacitor C, a node M+1 between the capacitor C and the resistor ESR, and a node M+2 corresponding to the output OUT. The compensation network 372 also includes nodes k, k+1, k+2, k+3, k+4, k+5 corresponding to the nodes 320 to 324 and the non-inverting input of the error amplifier EA.

[0143] In some embodiments, the voltage and / or current at one or more nodes of the model 500B is predetermined or set as an input or start condition for the simulation. For example, the reference voltage Vref at node k+5 is predetermined and used as an input for the simulation. As described herein, for transient simulations, V ref is set to ground voltage, such as Figure 5B As shown, for steady-state simulation or overall response simulation, Vref=Vout=D×Vin.

[0144] In some embodiments, the results of one or more simulations include voltages and / or currents at one or more nodes of the model 500B. For example, the simulation results of the equivalent model 575 of the voltage regulator 300A alone, or the simulation results of the model 500B including the equivalent model 575 and the modified network model 565, include voltages at nodes k, k+1, k+2, k+3, k+4, and a current I on the node k+4 corresponding to the output of the error amplifier EA. OA .

[0145] At operation 450 in process 400 , model parameters of the linear VR model, ie, equivalent model 575 , are incorporated into a netlist or at least one matrix for modified node analysis (MNA).

[0146] In at least one embodiment, the model parameters of the equivalent model 575 are incorporated into a netlist that is used in one or more simulations using software such as SPICE. In some embodiments, the parameters of the equivalent model 575 are incorporated into one or more MNA matrices, examples of which are referred to herein as FIG. 5C to FIG. 5D Described.

[0147] Figure 5C is a schematic diagram of a portion of a conductance matrix 500C for an MNA according to some embodiments.

[0148] For ease of explanation, Figure 5C The portion of the conductivity matrix 500C is presented in the form of a cross table 580 having a plurality of rows 581 and a plurality of columns 582. Figure 5B As shown, each row 581 corresponds to a node in the nodes j ... M+1, M+2, k, k+1, k+2, k+3, k+4, k+5 of the model 500B. Each column 582 corresponds to a node in the nodes j ... M+1, M+2, k, k+1, k+2, k+3, k+4, k+5 of the model 500B. For simplicity, Figure 5C Not all nodes of model 500B are shown.

[0149] At the intersection of row 581 and column 582 of intersection table 580, the conductance value of a node, or a connection or link between two nodes, is provided. For example, for intersection point 583 corresponding to node k, the conductance value of node k is (1 / R f1 +1 / R f3 +1 / R x ), which corresponds to all resistors Rf1, Rf3 and Rx directly connected to node k, such as Figure 5B As another example, for the intersection 584 corresponding to the connection between node k and node k+2, the conductance value of the connection is (-1 / R f1 ), which corresponds to a resistor R connected directly between and between node k and node k+2 f1 ,like Figure 5B For example, a conductance value of 0 (zero) at intersection 585 indicates that there is no resistor directly connected to and between the corresponding nodes k and k+4. For example, a conductance value of 1 (1) at intersection 586 indicates that the corresponding nodes k+5 and k+4 are directly connected to each other without a resistor in between.

[0150] Section 587 of cross-tabulation 580 contains compensation network information corresponding to nodes k, k+1, k+2, k+3, k+4, k+5, and conductance values ​​associated with nodes k, k+1, k+2, k+3, k+4, k+5. The compensation network information in section 587 corresponds to the conductance values ​​associated with nodes k, k+1, k+2, k+3, k+4, k+5. Figure 5B The compensation network 372 described above is shown in FIG. 5. In some embodiments, the information in cross-table 580 and outside of portion 587 is included in an existing or pre-configured MNA conductivity matrix and corresponds to at least an equivalent model of an open-loop voltage regulator. In at least one embodiment, an existing or pre-configured MNA conductivity matrix can be modified by simply adding the compensation network information (e.g., portion 587) to the existing or pre-configured MNA conductivity matrix to obtain a conductivity matrix 500C in which the open-loop voltage regulator of the existing or pre-deployed MNA conductivity matrix is ​​converted to a closed-loop voltage regulator, such as Figure 5BThe upper and lower parts are described.

[0151] Figure 5D is a schematic diagram of a portion of a capacitive matrix 500D for an MNA according to some embodiments.

[0152] For ease of explanation, Figure 5D The portion of the capacitance matrix 500D in FIG. 5 is presented in the form of a cross table 590, which is similar in configuration to the cross table 580 and has multiple rows and columns. Figure 5B As shown, each row corresponds to a node in the nodes j ... M+1, M+2, k, k+1, k+2, k+3, k+4, k+5 of the model 500B. Each column corresponds to a node in the nodes j ... M+1, M+2, k, k+1, k+2, k+3, k+4, k+5 of the model 500B. For simplicity, Figure 5D Not all nodes of model 500B are shown.

[0153] At the intersection of a row and a column of the intersection table 590, a capacitance value of a node, or a connection or link between two nodes, is provided. For example, for the intersection point 593 corresponding to the node k+2, the capacitance value of the node k+2 is (C c2 +C f3 ),like Figure 5B As shown, it corresponds to all capacitors C connected directly to node k+2 c2 and C f3 As another example, for the intersection 594 corresponding to the connection between the node k+4 and the node k+2, the capacitance value of the connection is (-C c2 ), which corresponds to a capacitor C directly connected between node k+4 and node k+2 c2 ,like Figure 5B For example, the capacitance value at intersection 595 is 0 (zero) indicating that there is no capacitor directly connected to the corresponding nodes k and k+2.

[0154] Section 597 of cross-table 590 contains compensation network information corresponding to nodes k, k+1, k+2, k+3, k+4, k+5, and capacitance values ​​associated with nodes k, k+1, k+2, k+3, k+4, k+5. The compensation network information in section 597 corresponds to the capacitance values ​​associated with nodes k, k+1, k+2, k+3, k+4, k+5. Figure 5BThe compensation network 372 described above. In some embodiments, the information in the cross-table 590 and outside of the portion 597 is included in an existing or pre-configured MNA capacitance matrix and corresponds to at least an equivalent model of an open-loop voltage regulator. In at least one embodiment, by simply adding the compensation network information (e.g., portion 597) to the existing or pre-configured MNA capacitance matrix, the existing or pre-configured MNA capacitance matrix can be modified to obtain a capacitance matrix 500D, wherein the open-loop voltage regulator of the existing or pre-configured MNA capacitance matrix is ​​converted to a closed-loop voltage regulator, such as Figure 5B The upper and lower parts are described.

[0155] In some embodiments, compensation network information similar to that described with respect to portion 587 of conductance matrix 500C and portion 597 of capacitance matrix 500D is added to the netlist for use in one or more simulations. In at least one embodiment, by adding the compensation network information, a quick and easy conversion (or expansion) of an existing netlist containing open-loop voltage regulator information to a netlist containing closed-loop voltage regulator information can be achieved in a manner similar to that described with respect to conductance matrix 500C and capacitance matrix 500D.

[0156] At operation 460 in process 400 , the netlist or at least one MNA matrix including model parameters of equivalent model 575 is used in one or more simulations in pre-layout verification operations.

[0157] In some embodiments, one or more of transient simulation 462, AC simulation 464, and power efficiency verification 466 are performed at operation 460. In at least one embodiment, transient simulation 462 and AC simulation 464 correspond to transient simulation 132 and AC simulation 134, as described in reference to FIG. Figure 1 The simulation or MNA using the conductance matrix 500C and the capacitance matrix 500D provides simulation results including voltages and / or currents at various nodes of the model 500B. The simulation results section 589 is shown in FIG. 5C to FIG. 5D , and includes voltages Vk, Vk+1, Vk+2, Vk+3, Vk+4 corresponding to nodes k, k+1, k+2, k+3, k+4, and a current I at node k+4 OA ,like Figure 5B Similar simulation results can be obtained in one or more embodiments using the netlist described herein for simulation.

[0158] In some embodiments, power efficiency verification 466 corresponds to power efficiency verification 136, such as Figure 1 In at least one embodiment, the power efficiency is determined as P Load / P in =P Load / (PLoad +P Loss ), where Pin is the total power received from the power source, P Load is the useful power delivered to or consumed by the load, P Loss is the loss in the power delivery system. P Loss including one or more components, such as the switching of drivers DRV1, DRV2, the on-resistance of power switches FET1, FET2 and / or the output inductor L O and / or input capacitor C O The loss caused by the parasitic resistance. Load , P Loss and / or each of its components is determined or estimated based on the voltage and / or current at each node in the simulation results.

[0159] In at least one embodiment, the calculated power efficiency is compared to a predetermined threshold to determine whether the voltage regulator being designed and / or the power delivery system including the voltage regulator is sufficiently efficient. In at least one embodiment, the simulation results are evaluated from various aspects and / or advantages to determine whether the voltage regulator and / or the power delivery system including the voltage regulator meets one or more predetermined specifications and / or requirements.

[0160] If one or more specifications and / or requirements and / or power efficiency are not met, redesign or configure the IC design and / or the power delivery system and / or the voltage regulator. In at least one embodiment, one or more parameters of the voltage regulator are adjusted. For example, the output inductor L is adjusted. O The inductance value, output capacitor C O One or more of the capacitance value, the switching frequency Fsw, etc. are modified. Thereafter, one or more of operations 420 to 450 are performed to update the equivalent model of the voltage regulator being designed, and one or more simulations or verifications of operation 460 are re-performed using the updated equivalent model to verify whether the adjustments result in all specifications and / or requirements being met. In some embodiments, the process is repeated one or more times until it is determined that the designed voltage regulator is acceptable, or it is determined that despite the modifications / adjustments, the voltage regulator does not meet all requirements and needs to be redesigned / reconfigured.

[0161] Fig. 6A , Figure 6B is a circuit diagram of a model 600A, 600B of a power delivery system 600 including a voltage regulator according to some embodiments. In some embodiments, reference FIG. 6A to FIG. 6B The voltage regulator and / or power delivery system 600 described corresponds to the reference Figure 1 , FIG. 2A to FIG. 2E , FIG. 3A to FIG. 3BOne or more voltage regulators and / or one or more power delivery systems described in one or more of the embodiments. Figure 2E , FIG. 3A to FIG. 3B , FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B Corresponding components in the drawings are denoted by the same reference numerals. FIG. 6A to FIG. 6B In the exemplary embodiment described, the voltage regulator will Figure 4 The process 400 of FIG. 400 is configured, modeled and verified, and corresponds to the voltage regulator 300A and / or the voltage regulator 400B. For simplicity, reference is made to the voltage regulator 300A in the description of the following example embodiments. The described example embodiments are also applicable to the voltage regulator 300B.

[0162] exist Fig. 6A In FIG. 6 , power delivery system 600 is similar to power delivery system 500, but differs from power delivery system 500A in that power delivery system 600A also includes an output network. Thus, model 600A is similar to model 500A, but differs from model 500A in that model 600A also includes a network model 660 of the output network. In some embodiments, the output network modeled by network model 660 corresponds to FIG. 2A to FIG. 2D One or more output networks described in .

[0163] The network model 660 includes multiple components that model the output network. Fig. 6A In the example configuration in FIG. 1 , the components include resistors 661, 664, inductor 662, and capacitor 663. Resistor 661 and inductor 662 are connected in series between output OUT and I Load Schematically represented load positive terminal 611. Capacitor 663 and resistor 664 are connected in series between output OUT and ground (e.g., node 314). Network model parameters of network model 660 include resistance value RLout of resistor 661, inductance value Lout of inductor 662, capacitance value Cout of capacitor 663, and resistance value RCout of resistor 664. In some embodiments, network model parameters are predetermined based on various details of the output network (e.g., configuration, size, material, etc.). The configuration of network model 660 is an example. Other network model configurations are within the scope of various embodiments.

[0164] exist Figure 6B , model 600B is similar to model 500B, but differs from model 500B in that model 600B also includes a network model 660 of an output network. In some embodiments, model 600B is configured at operation 440, and / or integrated into a netlist or at least one MNA matrix at operation 450, and / or used for one or more simulations and / or verifications at operation 460.

[0165] exist FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B In the example configurations of FIG. 5 , the power delivery system 500, 600 includes an input network. In at least one embodiment (not shown), the power delivery system includes a voltage regulator as described, but without an input network, or such an input network is ignored for one or more simulation purposes.

[0166] exist FIG. 5A to FIG. 5B , FIG. 6A to FIG. 6B In the example configuration of , the power delivery system 500, 600 includes a closed-loop voltage regulator. In at least one embodiment (not shown), the power delivery system includes an open-loop voltage regulator, and a linear VR model of such an open-loop voltage regulator is used for one or more simulations in a pre-layout verification operation. An example of a linear VR model of an open-loop voltage regulator according to some embodiments is described herein with respect to the upper portion of the equivalent model 575.

[0167] In some other approaches, in order to verify the performance of the IVR and / or the system power integrity after causing the IVR, simulation of the IVR or a circuit including the IVR requires a nonlinear model of the IVR due to the power switches and control circuits inside the IVR. Such simulations are time consuming and / or require a large amount of computing resources. In addition, according to other approaches, there is no available method to perform an AC analysis that takes into account parasitic effects from the input network of the voltage regulator through the closed-loop voltage regulator to the output network. Therefore, it is difficult to obtain information to understand the weaknesses of the closed-loop voltage regulator or the system including the voltage regulator in the frequency spectrum.

[0168] In some embodiments, a voltage regulator circuit is replaced with a macro model to enable AC analysis or co-simulation of the entire power delivery system including the closed-loop voltage regulator and at least one of the input network or the output network, while reducing the co-simulation time from days in other methods to minutes.

[0169] In some embodiments, given design specifications such as maximum current load, maximum allowed voltage swing, closed-loop bandwidth, etc., the voltage regulator macromodeling approximates the electrical characteristics of the voltage regulator circuit from the perspective of time domain and frequency domain.

[0170] In at least one embodiment, a linear VR model is used to represent the electrical characteristics of a closed-loop multi-phase voltage regulator, which avoids the use of nonlinear models or nonlinear circuit components for simulation, thereby significantly reducing simulation time.

[0171] In one or more embodiments, a linear VR model of a closed-loop voltage regulator can be incorporated into a netlist or MNA along with a network model including passive elements that model or represent parasitic effects from an input network of the closed-loop voltage regulator through the closed-loop voltage regulator to an output network of the closed-loop voltage regulator. As a result, in one or more embodiments, an AC analysis of the entire power delivery system powered by a closed-loop VR becomes feasible.

[0172] In one or more embodiments, an existing netlist or MNA matrix that already contains a VR model for an open-loop voltage regulator may be simply converted to a netlist or MNA matrix that contains a VR model for a closed-loop voltage regulator by adding compensation network information to the existing netlist or MNA matrix.

[0173] In some embodiments, a standard interface is provided in power integrity (PI) analysis so that system designers do not need circuit details. In an example, the interface is configured to receive design specifications from a system designer, or to receive design specifications upon request from a system designer. A computer system or processor is connected to the interface to receive the design specifications and is configured to automatically determine parameters of a voltage regulator to be designed, generate a linear VR model for the voltage regulator, and perform one or more simulations using the linear VR model. In at least one embodiment, the computer system or processor is configured to provide an evaluation or assessment of whether the voltage regulator and / or the entire power delivery system meets predetermined specifications and / or requirements. In at least one embodiment, the computer system or processor is configured to automatically adjust the configuration of the voltage regulator and / or the power delivery system in response to an evaluation that the currently configured voltage regulator and / or the entire power delivery system does not meet one or more predetermined specifications and / or requirements. In at least one embodiment, the computer system or processor is configured to automatically perform the process from receiving the design specifications to outputting a final evaluation and / or outputting an acceptable configuration of the voltage regulator and / or the power delivery system without the input of the system designer, while at the same time eliminating the need for circuit details for the system designer.

[0174] Fig. 7A 700A is a flow chart of a process 700A according to some embodiments. In some embodiments, the process 700A is performed at least in part by a computer system or processor, as described herein. The process 700A includes operations 702, 704, 706.

[0175] At operation 702, voltage regulator parameters are determined based on a design specification of the voltage regulator. For example, as described with respect to operations 420, 430 of process 400, various parameters in the voltage regulator are determined based on the design specification of the voltage regulator provided at operation 410. Figure 3A , example voltage regulator parameters include but are not limited to the output inductor L OThe inductance value L, output capacitor C O One or more of the capacitance values ​​C, one or more capacitance values ​​of one or more capacitors in the compensation network 372, one or more resistance values ​​of one or more resistors in the compensation network 372, etc.

[0176] At operation 704, model parameters of a voltage regulator (VR) model are determined based on the parameters of the voltage regulator, wherein the VR model does not contain nonlinear circuit components. For example, as described in operation 440 of process 400, model parameters of the VR model are determined, for example, Figure 5B The equivalent model 575 does not contain nonlinear circuit components, that is, it does not contain transistors, switches, and circuits containing transistors and / or switches, such as power switches, drivers, control circuits, comparators, etc. The equivalent model 575 includes linear circuit components, such as resistors, capacitors, inductors, and voltage sources. Figure 5B In the example configuration in, the model parameters to be determined for the equivalent model 575 include but are not limited to the resistance value of the resistor 572, the inductance value of the inductor 573, the resistance value of the resistor Rx and the capacitance value of the capacitor C, the resistance value of the resistor ESR and the inductance value of the inductor ESL, one or more capacitance values ​​of one or more capacitors in the compensation network 372, one or more resistance values ​​of one or more resistors in the compensation network 372, etc.

[0177] At operation 706, the voltage regulator is simulated using the model parameters of the VR model. For example, as described with respect to operation 460 of process 400, one or more simulations and / or verifications are performed using the equivalent model 575, the model parameters of which are obtained at operation 440. In some embodiments, the model parameters of the equivalent model 575 are included in the FIG. 5C to FIG. 5D In one or more MNA matrices as shown, or in a netlist as described herein. In at least one embodiment, one or more advantages described herein can be achieved by process 700A, for example, reducing simulation time and / or computing resources in one or more embodiments.

[0178] Figure 7B 724 , 726 .

[0179] At operation 724, model parameters of a voltage regulator (VR) model are determined based on the design specification of the voltage regulator. The VR model includes: a voltage-dependent voltage source connected between an input and an output, and a compensation network of a capacitor and a resistor connected between the output and the first node. For example, as described with respect to Figure 5BAs described, the VR model, i.e., the equivalent model 575, includes a voltage-dependent voltage source 571 connected between the input IN and the output OUT. The equivalent model 575 also includes a compensation network 372 of a capacitor and a resistor connected between the output OUT and the first node 324. For example, various model parameters of the equivalent model 575 are determined in a manner similar to that described with respect to one or more of operations 702, 704 of the process 700A. Example model parameters of the equivalent model 575 include, but are not limited to, the resistance value R f1 , R f3 , R c1 , Capacitance value C c1 , C c2 , C f3 One or more of , and the voltage value of the voltage-dependent voltage source 571 depends on the voltage value v(d).

[0180] At operation 726, a simulation of the voltage regulator is performed using the model parameters of the VR model, e.g., in a manner similar to that described with respect to operation 706 of process 700A. In at least one embodiment, one or more advantages described herein may be achieved by process 700B, e.g., reducing simulation time and / or computing resources in one or more embodiments.

[0181] Figure 7C 700C is a flow chart of a process 700C according to some embodiments. In some embodiments, the process 700C is performed at least in part by a computer system or processor, as described herein. The process 700C includes operations 742, 744, 746.

[0182] At operation 742 , model parameters of a voltage regulator (VR) model are determined based on the design specification of the voltage regulator, for example, in a manner similar to that described with respect to one or more of operations 702 , 704 of process 700A.

[0183] At operation 744, network model parameters of a network model of an input network connected to an input terminal of the voltage regulator are modified based on the duty cycle of the voltage regulator. Figure 5A , Figure 5B As shown, with the input network (such as Figure 5A The network model parameters related to the resistors 561, 564, capacitor 563, and inductor 562 of the network model 560 (as shown in FIG. 5 ) are modified based on the duty cycle D of the voltage regulator. Figure 5B As shown, the modified network model parameters of the modified network model 565 are obtained.

[0184] At operation 746, the voltage regulator and the input network are simulated using the model parameters of the VR model and the modified network model parameters of the network model. For example, as described with respect to operation 460 of process 400, the voltage regulator and the input network are simulated. Figure 5B The voltage regulator represented by the equivalent model 575 and Figure 5B The entire power delivery system 500 of at least the input network represented by the modified network model 565 in the example embodiment is co-simulated. The co-simulation uses the model parameters of the equivalent model 575 and the modified model parameters of the modified network model 565. In some embodiments, the model parameters of the equivalent model 575 and the modified network model parameters of the modified network model 565 are included in the example embodiment. FIG. 5C to FIG. 5D In one or more MNA matrices, or in a netlist as described herein. In at least one embodiment, one or more advantages described herein can be achieved by process 700C, for example, reducing simulation time and / or computing resources in one or more embodiments.

[0185] The method includes example operations, but does not necessarily need to be performed in the order shown. According to the spirit and scope of the embodiments of the present disclosure, operations can be appropriately added, replaced, changed in order and / or eliminated. Embodiments combining different components and / or different embodiments are within the scope of the present disclosure, and will be apparent to those of ordinary skill in the art after reading the present disclosure.

[0186] In some embodiments, at least one of the above methods is performed in whole or in part by at least one EDA system. In some embodiments, the EDA system can be used as part of a design room of an IC manufacturing system discussed below.

[0187] Figure 8 is a block diagram of an electronic design automation (EDA) system 800 according to some embodiments.

[0188] In some embodiments, the EDA system 800 includes an APR system. According to one or more embodiments, the method of designing a floorplan described herein represents a wiring arrangement, for example, according to some embodiments, can be implemented using the EDA system 800 .

[0189] In some embodiments, the EDA system 800 is a general-purpose computing device that includes a hardware processor 802 and a non-transitory computer-readable storage medium 804. The storage medium 804 is encoded with, among other things, a computer program code 806, i.e., a set of executable instructions. The execution of the instructions 806 by the hardware processor 802 represents (at least in part) an EDA tool that implements part or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0190] The processor 802 is electrically connected to a computer-readable storage medium 804 via a bus 808. The processor 802 is also electrically connected to an I / O interface 810 via the bus 808. A network interface 812 is also electrically connected to the processor 802 via the bus 808. The network interface 812 is connected to a network 814 so that the processor 802 and the computer-readable storage medium 804 can be connected to external elements via the network 814. The processor 802 is configured to execute a computer program code 806 encoded in the computer-readable storage medium 804 so that the system 800 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 802 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0191] In one or more embodiments, the computer-readable storage medium 804 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 804 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 804 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0192] In one or more embodiments, the storage medium 804 stores computer program code 806 configured to enable the system 800 (where such execution represents (at least in part) an EDA tool) to perform some or all of the described processes and / or methods. In one or more embodiments, the storage medium 804 also stores information that facilitates the performance of some or all of the described processes and / or methods. In one or more embodiments, the storage medium 804 stores a standard cell library 807 that includes the standard cells disclosed herein.

[0193] The EDA system 800 includes an I / O interface 810. The I / O interface 810 is connected to an external circuit. In one or more embodiments, the I / O interface 810 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 802.

[0194] The EDA system 800 also includes a network interface 812 connected to the processor 802. The network interface 812 allows the system 800 to communicate with a network 814 to which one or more other computer systems are connected. The network interface 812 includes a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 800.

[0195] The system 800 is configured to receive information through the I / O interface 810. The information received through the I / O interface 810 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 802. The information is transmitted to the processor 802 via the bus 808. The EDA system 800 is configured to receive information related to the UI through the I / O interface 810. The information is stored in the computer-readable medium 804 as a user interface (UI) 842.

[0196] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an add-on software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EDA system 800. In some embodiments, the system is implemented using a software application such as that available from CADENCE DESIGN SYSTEMS, INC. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0197] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable storage medium. Examples of non-transitory computer-readable storage media include, but are not limited to, external / removable and / or internal / built-in storage or storage units, such as one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM), a RAM, a memory card, etc.

[0198] Fig. 91 is a block diagram of an integrated circuit (IC) manufacturing system 900 according to some embodiments, and an IC manufacturing process associated therewith. In some embodiments, based on the layout diagram, the manufacturing system 900 is used to manufacture at least one of (a) one or more semiconductor masks or (b) at least one component in a semiconductor integrated circuit layer.

[0199] exist Fig. 9 In the present invention, the IC manufacturing system 900 includes entities that interact in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 960, such as a design room 920, a mask room 930, and an IC manufacturer / fab ("fab") 950. The entities in the system 900 are connected by a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or fewer other entities. In some embodiments, two or more of the design room 920, the mask room 930, and the IC wafer factory 950 are owned by a single larger company. In some embodiments, two or more of the design room 920, the mask room 930, and the IC wafer factory 950 coexist in a common facility and use common resources.

[0200] The design office (or design team) 920 generates an IC design layout 922. The IC design layout 922 includes various geometric patterns designed for the IC device 960. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various components that constitute the IC device 960 to be manufactured. The layers are combined to form various IC features. For example, a portion of the IC design layout 922 includes various IC components, such as active areas, gate electrodes, source and drain electrodes, metal lines or through holes for interlayer interconnection, and openings for pads, which will be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 920 implements appropriate design procedures to form the IC design layout 922. The design process includes one or more of a logic design, a physical design, or a layout and routing operation. The IC design layout 922 is presented in the form of one or more data files with geometric pattern information. For example, the IC design layout 922 can be represented in a GDSII file format or a DFII file format.

[0201] The mask chamber 930 includes data preparation 932 and mask manufacturing 944. The mask chamber 930 uses the IC design layout drawing 922 to manufacture one or more masks 945 for manufacturing various layers of the IC device 960 according to the IC design layout drawing 922. The mask chamber 930 performs mask data preparation 932, wherein the IC design layout drawing 922 is converted into a representative data file ("RDF"). The mask data preparation 932 provides the RDF to the mask manufacturing 944. The mask manufacturing 944 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 945 or a semiconductor wafer 953. The design layout drawing 922 is manipulated by the mask data preparation 932 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer factory 950. In Fig. 9 , mask data preparation 932 and mask manufacturing 944 are shown as separate elements. In some embodiments, mask data preparation 932 and mask manufacturing 944 may be collectively referred to as mask data preparation.

[0202] In some embodiments, mask data preparation 932 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 922. In some embodiments, mask data preparation 932 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary components, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, an inverse lithography technique (ILT) is also used, which treats OPC as an inverse imaging problem.

[0203] In some embodiments, mask data preparation 932 includes a mask rule checker (MRC) that checks the IC design layout 922 that has been processed by OPC using a set of mask creation rules that contain certain geometric and / or connection constraints to ensure that there are sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 922 to compensate for the constraints during mask fabrication 944, which may undo some of the modifications performed by OPC to satisfy the mask creation rules.

[0204] In some embodiments, mask data preparation 932 includes a lithography process check (LPC), which simulates a process to be performed by the IC fab 950 to manufacture an IC device 960. The LPC simulates the process based on the IC design layout 922 to create a simulated manufactured device, such as the IC device 960. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, etc. or combinations thereof. In some embodiments, after the LPC creates the simulated manufactured device, if the shape of the simulated device is not close enough to meet the design rules, the OPC and / or MRC are repeated to further refine the IC design layout 922.

[0205] It should be understood that the above description of mask data preparation 932 has been simplified for the sake of clarity. In some embodiments, data preparation 932 includes additional components, such as modifying the logic operations (LOPs) of IC design layout 922 according to manufacturing rules. In addition, the processes applied to IC design layout 922 during data preparation 932 can be performed in a variety of different orders.

[0206] After mask data preparation 932 and during mask manufacturing 944, a mask 945 or a set of masks 945 are manufactured based on the modified IC design layout 922. In some embodiments, mask manufacturing 944 includes performing one or more photolithography exposures based on the IC design layout 922. In some embodiments, based on the modified IC design layout 922, a pattern is formed on a mask (photomask or reticle) 945 using an electron beam (e-beam) or a plurality of electron beams. Mask 945 can be formed using various techniques. In some embodiments, mask 945 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of mask 945 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque area of ​​the binary mask. In another example, a mask 945 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 945, various components in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 944 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 953, the mask is used in an etching process to form various etched regions in the semiconductor wafer 959, and / or used in other suitable processes.

[0207] IC fab 950 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 950 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, while a second manufacturing facility can provide back-end manufacturing (back-end process (BEOL) production) for interconnection and packaging of IC products, and a third manufacturing facility can provide other services for the foundry business.

[0208] IC fab 950 includes fabrication tools 952 configured to perform various fabrication operations on semiconductor wafer 953 to fabricate IC devices 960 based on masks (e.g., mask 945). In various embodiments, fabrication tools 952 include one or more of a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or a LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes described herein.

[0209] IC fab 950 uses mask 945 manufactured by mask chamber 930 to manufacture IC device 960. Therefore, IC fab 950 at least indirectly uses IC design layout 922 to manufacture IC device 960. In some embodiments, semiconductor wafer 953 is manufactured by IC fab 950 using mask 945 to form IC device 960. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on IC design layout 922. Semiconductor wafer 953 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 953 also includes one or more of various doped regions, dielectric components, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0210] In some embodiments, a method is performed at least in part by a processor and includes determining voltage regulator parameters based on a design specification of the voltage regulator. The method also includes determining model parameters of a voltage regulator (VR) model based on the parameters of the voltage regulator. The VR model does not contain nonlinear circuit components. The method also includes simulating the voltage regulator using the model parameters of the VR model.

[0211] In some embodiments, the voltage regulator model includes: a voltage source connected between an input terminal and an output terminal, and a compensation network of a capacitor and a resistor, the compensation network being connected between the output terminal and a first node, and model parameters of the voltage regulator model include: a resistance value of the resistor in the compensation network, a capacitance value of the capacitor in the compensation network, and a voltage value of the voltage source corresponding to the voltage value at the first node.

[0212] In some embodiments, the method further comprises: modifying the conductance matrix by adding a plurality of nodes in the compensation network and conductance values ​​associated with the plurality of nodes to a conductance matrix of a modified nodal analysis (MNA), the plurality of nodes including the first node, the conductance values ​​associated with the plurality of nodes corresponding to the resistance values ​​of the resistors in the compensation network; and modifying the capacitance matrix by adding the capacitance values ​​of the plurality of nodes and the capacitors in the compensation network to the capacitance matrix of the modified nodal analysis, wherein the simulation comprises using the modified conductance matrix and the modified nodal analysis of the capacitance matrix.

[0213] In some embodiments, the method further includes: adding compensation network information corresponding to the following in a netlist: a plurality of nodes in the compensation network, the plurality of nodes including the first node, conductance values ​​associated with the plurality of nodes, the conductance values ​​corresponding to the resistance values ​​of the resistors in the compensation network, and the capacitance values ​​of the capacitors in the compensation network, wherein the simulation includes using the netlist including the compensation network information.

[0214] In some embodiments, the first node corresponds to an output terminal of an error amplifier in a compensation circuit of the voltage regulator.

[0215] In some embodiments, the voltage regulator is a multi-phase voltage regulator having multiple phases, and determining the model parameters includes determining model parameters in the model parameters based on: corresponding parameters in the parameters of the voltage regulator, and the number of phases of the voltage regulator.

[0216] In some embodiments, the simulation includes simulation of the voltage regulator and at least one of: an input network connected to an input of the voltage regulator, and an output network connected to an output of the voltage regulator.

[0217] In some embodiments, the method further comprises: modifying network model parameters of the network model of the input network based on a duty cycle of the voltage regulator, wherein the simulating comprises using the modified network model parameters of the network model.

[0218] In some embodiments, the simulation includes an alternating current (AC) simulation of the voltage regulator and at least one of: an input network connected to an input of the voltage regulator, and an output network connected to an output of the voltage regulator.

[0219] In some embodiments, the method further comprises: modifying a configuration of the voltage regulator based on a result of the simulation.

[0220] In some embodiments, a system includes a processor configured to determine model parameters of a voltage regulator (VR) model based on a design specification of the voltage regulator, and simulate the voltage regulator using the parameters of the VR model. The VR model includes a voltage-dependent voltage source connected between an input and an output and a compensation network of a capacitor and a resistor. The compensation network is connected between the output terminal and a first node. The model parameters of the VR model include a resistance value of a resistor in the compensation network, a capacitance value of a capacitor in the compensation network, and a voltage value of a voltage-dependent voltage source that depends on a voltage value at a first node.

[0221] In some embodiments, the first node corresponds to an output terminal of an error amplifier in a compensation circuit of the voltage regulator.

[0222] In some embodiments, the processor is configured to determine parameters of the voltage regulator based on the design specification of the voltage regulator, and determine the model parameters of the voltage regulator model based on the parameters of the voltage regulator.

[0223] In some embodiments, the voltage regulator is a multi-phase voltage regulator having multiple phases, and the processor is configured to determine the model parameters in the model parameters based on: corresponding parameters in the parameters of the voltage regulator, and the number of phases of the voltage regulator.

[0224] In some embodiments, the processor is configured to perform a simulation of the voltage regulator together with at least one of: an input network connected to an input of the voltage regulator, and an output network connected to an output of the voltage regulator.

[0225] In some embodiments, the processor is configured to modify network model parameters of a network model of the input network based on a duty cycle of the voltage regulator, and perform a simulation of the voltage regulator together with at least the input network using the modified network model parameters of the network model.

[0226] In some embodiments, the processor is further configured to: modify a configuration of the voltage regulator based on a result of the simulation.

[0227] In some embodiments, a computer program product includes a non-transitory computer-readable storage medium containing instructions. When executed by a processor, the instructions cause the processor to determine model parameters of a voltage regulator (VR) model based on a design specification of the voltage regulator. When executed, the instructions also cause the processor to modify network model parameters of a network model of an input network connected to an input of the voltage regulator based on a duty cycle of the voltage regulator. When executed, the instructions also cause the processor to perform a simulation of the voltage regulator together with the input network using the model parameters of the VR model and the modified network model parameters of the network model.

[0228] In some embodiments, the voltage regulator model includes: a voltage-dependent voltage source, a first resistor and a first inductor, connected in series between the input and output terminals of the voltage regulator, and a compensation network of capacitors and resistors, the compensation network being connected between the output terminal and a first node, and model parameters of the voltage regulator model include: a first inductance value of the first inductor, a first resistance value of the first resistor, a resistance value of the resistor in the compensation network, a capacitance value of the capacitor in the compensation network, and a voltage value of the voltage-dependent voltage source that depends on the voltage value at the first node.

[0229] In some embodiments, the network model includes: a second resistor and a second inductor, connected in series between the input terminal and the second node, and a third resistor and a first capacitor, connected in series between the input terminal and the second node, the network model parameters include: a second resistance value of the second resistor, a second inductance value of the second inductor, a third resistance value of the third resistor, a first capacitance value of the first capacitor, and the modified network model parameters include: the second resistance value multiplied by the square of the duty cycle, the second inductance value multiplied by the square of the duty cycle, the third resistance value multiplied by the square of the duty cycle, and the first capacitance value divided by the square of the duty cycle.

[0230] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method for integrated circuit design, the method being at least partially performed by a processor and comprising: Determining parameters of the voltage regulator based on a design specification of the voltage regulator; determining model parameters of a voltage regulator (VR) model based on the parameters of the voltage regulator, wherein the voltage regulator model does not contain nonlinear circuit components; as well as A simulation of the voltage regulator is performed using the model parameters of the voltage regulator model.

2. The method according to claim 1, wherein: The voltage regulator model includes: A voltage source, connected between the input and output terminals, and a compensation network of capacitors and resistors connected between the output terminal and the first node, and The model parameters of the voltage regulator model include: the resistance value of the resistor in the compensation network, the capacitance value of the capacitor in the compensation network, and The voltage value of the voltage source corresponds to the voltage value at the first node.

3. The method according to claim 2, further comprising: modifying the conductance matrix by adding a plurality of nodes in the compensation network and conductance values ​​associated with the plurality of nodes to a conductance matrix of a modified nodal analysis (MNA), the plurality of nodes including the first node, the conductance values ​​associated with the plurality of nodes corresponding to the resistance value of the resistor in the compensation network; as well as modifying the capacitance matrix by adding the capacitance values ​​of the plurality of nodes and the capacitors in the compensation network to the capacitance matrix of the modified node analysis, wherein the simulation includes the modified nodal analysis using the modified conductance matrix and the capacitance matrix.

4. The method according to claim 2, further comprising: Add compensation network information corresponding to the following in the netlist: a plurality of nodes in the compensation network, the plurality of nodes including the first node, conductance values ​​associated with the plurality of nodes, the conductance values ​​corresponding to the resistance values ​​of the resistors in the compensation network, and the capacitance value of the capacitor in the compensation network, Wherein, the simulating includes using the netlist including the compensation network information.

5. An integrated circuit design system, comprising a processor, wherein the processor is configured to: determining model parameters of a voltage regulator (VR) model of the voltage regulator based on a design specification of the voltage regulator, and The voltage regulator is simulated using the model parameters of the voltage regulator model, wherein The voltage regulator model includes: A voltage-dependent voltage source, connected between the input and output terminals, and a compensation network of capacitors and resistors connected between the output terminal and the first node, and The model parameters of the voltage regulator model include: the resistance value of the resistor in the compensation network, the capacitance value of the capacitor in the compensation network, and The voltage that depends on the voltage value at the first node is a voltage value of a voltage dependence voltage source.

6. The system according to claim 5, wherein: The first node corresponds to an output terminal of an error amplifier in a compensation circuit of the voltage regulator.

7. The system according to claim 5, wherein: The processor is configured to: determining parameters of the voltage regulator based on the design specification of the voltage regulator, and The model parameters of the voltage regulator model are determined based on the parameters of the voltage regulator.

8. The system according to claim 7, wherein: The voltage regulator is a multiphase voltage regulator having multiple phases, and The processor is configured to determine a model parameter among the model parameters based on: corresponding ones of the parameters of the voltage regulator, and The number of phases of the voltage regulator.

9. A computer program product comprising a non-transitory computer-readable storage medium containing instructions which, when executed by a processor, cause the processor to: determining model parameters of a voltage regulator (VR) model of the voltage regulator based on a design specification of the voltage regulator, modifying network model parameters of a network model of an input network connected to an input terminal of the voltage regulator based on a duty cycle of the voltage regulator, and The voltage regulator and the input network were simulated using: model parameters of the voltage regulator model, and The modified network model parameters of the network model.

10. The computer program product according to claim 9, wherein: The voltage regulator model includes: a voltage-dependent voltage source, a first resistor and a first inductor connected in series between the input terminal and the output terminal of the voltage regulator, and a compensation network of capacitors and resistors connected between the output terminal and the first node, and The model parameters of the voltage regulator model include: a first inductance value of the first inductor, a first resistance value of the first resistor, the resistance value of the resistor in the compensation network, the capacitance value of the capacitor in the compensation network, and The voltage that depends on the voltage value at the first node is a voltage value of a voltage dependence voltage source.

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