Quantum circuit construction method for predicting optimal state of system and related device

Through the quantum circuit construction method, the Hadamar Gate and the variable component quantum logic gate are used to solve the accuracy problem of the system's long-term optimal state prediction, and more efficient system state estimation is achieved.

CN119990349APending Publication Date: 2025-05-13ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
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Patent Information

Application Number
CN202510064192.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-01-15
Publication Date
2025-05-13

AI Technical Summary

Technical Problem

The prior art is difficult to accurately predict the long-term optimal state of the system, mainly due to problems such as inaccurate system state, evolution error of mathematical model, and discrete errors in the calculation process.

Method used

A quantum circuit construction method is designed to achieve the evolution of system state and the update of weights by acting in sequence with Hadamar Gate and variable component quantum logic gate, and determine the optimal state of the system based on the observation probability of quantum states.

Benefits of technology

This method can more accurately estimate the optimal state of the system, reduce model errors and discrete errors, and improve the accuracy of long-term predictions.

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Abstract

The embodiment of the invention discloses a quantum circuit construction method for predicting the optimal state of a system and a related device, and the method comprises the steps: enabling a Hadamard gate to act on a first register, enabling a first group of variable component sub-logic gates virtually controlled by the first register to act on a second register, a third register and a fourth register, and enabling a second group of variable component sub-logic gates to act on a fourth register; enabling a second group of variable component sub logic gates actually controlled by the first register to act on a second register, a third register and a fourth register, enabling a NOT gate actually controlled by the first register and the third register to act on the fourth register, and enabling a Hadamard gate to act on the first register to obtain a target quantum circuit; the target quantum circuit is used for determining the optimal state of the system at the current moment according to the observation probability of the quantum state of the first register, the embodiment of the invention discloses a specific quantum circuit for predicting the optimal state of the system, and estimation of the optimal state of the system is facilitated.
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Description

Technical Field

[0001] The present invention relates to the field of quantum computing technology, and in particular to a quantum circuit construction method and related devices for predicting the optimal state of a system. Background Art

[0002] System optimal state prediction refers to the process of estimating the system state through mathematical models using the input and output data of the system. It is widely used in many important fields such as control systems, weather forecasts, and machine learning. In actual situations, it is often difficult to predict a system for a long time. There are several main reasons: First, the state of the system is often not very accurate, especially for actual multidimensional systems; second, the mathematical model is more often an evolutionary model rather than an accurate evolutionary law, and there are model errors when using it for prediction; third, various types of errors such as discrete errors and machine errors are inevitably introduced during the calculation process. The above reasons together make it difficult to predict the evolution of a system for a long time. For example, it is much more difficult to predict the weather one month later than to predict the weather one hour later.

[0003] The development of quantum computing has brought hope for solving the above problems. However, quantum computers are still in a period of rapid development, and the specific structure of quantum circuits used to predict the optimal state of the system still needs further research. Summary of the invention

[0004] The embodiments of the present application provide a quantum circuit construction method and related devices for predicting the optimal state of a system, and disclose a specific quantum circuit for predicting the optimal state of a system, which is conducive to realizing the estimation of the optimal state of the system.

[0005] A first aspect of an embodiment of the present application provides a quantum circuit construction method for predicting the optimal state of a system, comprising:

[0006] Sequentially apply the Hadamard gate to the first register, apply the first group of variational quantum logic gates virtually controlled by the first register to the second register, the third register and the fourth register, apply the second group of variational quantum logic gates actually controlled by the first register to the second register, the third register and the fourth register, apply the NOT gate actually controlled by the first register and the third register to the fourth register, apply the Hadamard gate to the first register, and obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at the current moment according to the observation probability of the quantum state of the first register; the first group of variational quantum logic gates is used to evolve the initial state from the quantum state representing the system state at the past moment to the quantum state representing the system state at the current moment; the second group of variational quantum logic gates is used to evolve the initial state from the quantum state representing the weight of each system state at the past moment to the quantum state representing the weight of each system state at the current moment.

[0007] Optionally, the first group of variational quantum logic gates and the second group of variational quantum logic gates both include a first quantum logic gate for data encoding and a second quantum logic gate for constructing a proposed circuit, the first quantum logic gate in the first group of variational quantum logic gates is used to encode the system state at the past moment into the quantum state of the second register, and the first quantum logic gate in the second group of variational quantum logic gates is used to encode the weights of each system state at the past moment into the quantum state of the second register.

[0008] Optionally, the parameters of the second quantum logic gate are determined according to loss function training, and the value of the loss function is obtained by observing a quantum circuit.

[0009] Optionally, the weights of each system state at the current moment are updated according to the product of the weights of each system state at the past moment and a likelihood probability, and the likelihood probability is used to characterize the probability of the system state at the current moment when the system state at the current moment is an observed state.

[0010] Optionally, the weight of each system state at the current moment is proportional to the product of the weight of each system state at the past moment and the likelihood probability, and the proportional coefficient is determined based on the observation circuit, which is composed of a Hadamard gate acting on the fifth register in sequence, a Hadamard gate acting on the sixth register and being virtually controlled by the fifth register, the second group of variational quantum logic gates acting on the sixth, seventh and eighth registers and being actually controlled by the fifth register, and a Hadamard gate acting on the fifth register.

[0011] Optionally, the observation probability that the quantum state of the first register is the ground state is Q 0 , the observation probability that the quantum state of the first register is an excited state is Q 1 ; The observation probability that the quantum state of the fifth register is the ground state is P 0 , the observation probability that the quantum state of the fifth register is an excited state is P 1 The optimal state at the current moment is based on (Q 0 -Q 1 ) / (P 0 -P 1 )Sure.

[0012] Optionally, the likelihood probability is a polynomial about the system state at the current moment, the second quantum logic gate in the second group of variational quantum logic gates includes the second quantum logic gate in the first group of variational quantum logic gates and a third quantum logic gate for constructing a proposed circuit, the second quantum logic gate in the first group of variational quantum logic gates is also used to encode the likelihood probability into the quantum state of the second register, and the third quantum logic gate is used to obtain the quantum state of each system state weight at the current moment based on the quantum state training corresponding to the system state weights at the past moments and the likelihood probability.

[0013] A second aspect of an embodiment of the present application provides a quantum circuit construction device for predicting the optimal state of a system, comprising:

[0014] A circuit construction unit is used to sequentially apply a Hadamard gate to a first register, apply a first set of variational quantum logic gates virtually controlled by the first register to a second register, a third register, and a fourth register, apply a second set of variational quantum logic gates actually controlled by the first register to the second register, the third register, and the fourth register, apply a NOT gate actually controlled by the first register and the third register to the fourth register, and apply a Hadamard gate to the first register to obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at a current moment according to the observation probability of the quantum state of the first register; the first set of variational quantum logic gates is used to evolve an initial state from a quantum state representing a system state at a past moment to a quantum state representing a system state at a current moment; and the second set of variational quantum logic gates is used to evolve an initial state from a quantum state representing a weight of each system state at a past moment to a quantum state representing a weight of each system state at a current moment.

[0015] A third aspect of the embodiments of the present application provides an electronic device, including: a processor and a memory;

[0016] The processor is connected to the memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method in the first aspect of the embodiment of the present application.

[0017] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. The computer program includes program instructions. When the program instructions are executed by a processor, the method in the first aspect of the embodiment of the present application is executed.

[0018] In the embodiment of the present application, the Hadamard gate is applied to the first register in sequence, the first group of variational quantum logic gates virtually controlled by the first register is applied to the second register, the third register and the fourth register, the second group of variational quantum logic gates actually controlled by the first register is applied to the second register, the third register and the fourth register, the NOT gate actually controlled by the first register and the third register is applied to the fourth register, and the Hadamard gate is applied to the first register to obtain the target quantum circuit, which is used to determine the optimal state of the system at the current moment according to the observation probability of the quantum state of the first register; the first group of variational quantum logic gates is used to evolve the initial state from the quantum state representing the system state at the past moment to the quantum state representing the system state at the current moment; the second group of variational quantum logic gates is used to evolve the initial state from the quantum state representing the weight of each system state at the past moment to the quantum state representing the weight of each system state at the current moment. It can be seen that the embodiment of the present application discloses a specific quantum circuit for predicting the optimal state of the system, which is conducive to the estimation of the optimal state of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 An example system block diagram for predicting the optimal state of a system provided by an embodiment of the present application is shown;

[0021] Figure 2 A schematic flow chart of a quantum circuit construction method for predicting the optimal state of a system provided by an embodiment of the present application is shown;

[0022] Figure 3 A schematic diagram of the structure of a quantum circuit for predicting the optimal state of a system provided by one embodiment of the present application is shown;

[0023] Figure 4 A schematic diagram showing the structure of a quantum circuit for observing a proportional coefficient provided by an embodiment of the present application

[0024] Figure 5 A schematic diagram of the structure of a quantum circuit construction device for predicting the optimal state of a system provided by one embodiment of the present application is shown;

[0025] Figure 6 A schematic diagram of the structure of a computer device provided in one embodiment of the present application is shown. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0027] Classical computers use transistors to encode information in binary data, such as bits, where each bit can represent a value of 1 or 0. These 1s and 0s act as switches that drive the functions of a classical computer. If there are n bits of data, there are 2n possible classical states, and one state is represented at a time.

[0028] Quantum computers use quantum processors that operate on data represented by quantum bits, also known as qubits. A qubit can represent the classical binary state "0", "1", or a superposition of "0" and "1". Because it can represent a superposition of "0" and "1", a qubit can represent both the "0" and "1" states at the same time. For example, if there are n bits of data, then 2 n Quantum states can be represented simultaneously. Further, qubits in superposition can be related to each other, known as entanglement, where the state of one qubit (whether it is 1 or 0 or both) can depend on the state of another qubit, and more information can be encoded within the two entangled qubits. Based on the principles of superposition and entanglement, qubits can enable quantum computers to perform functions that may be relatively complex and time-consuming for classical computers.

[0029] Please refer to Figure 1 , which shows an example system block diagram for predicting the optimal state of a system provided by an embodiment of the present application. System 100 may be a hybrid computing system including a combination of one or more quantum computers, quantum systems and / or classical computers. Figure 1 In the example shown, system 100 may include a quantum system 110 and a classical computer 120. In one embodiment, quantum system 110 and classical computer 120 may be configured to communicate via one or more of a wired connection and / or a wireless connection (e.g., a wireless network). Quantum system 110 may include a quantum chipset consisting of one or more quantum chips, which includes various hardware components for processing data encoded in quantum bits. The quantum chipset may be a quantum computing core surrounded by infrastructure to protect the quantum chip from electromagnetic noise sources, mechanical vibration sources, heat sources, and other noise sources that may degrade the performance of the quantum chip. Classical computer 120 may be electronically integrated with quantum system 110 via any suitable wired and / or wireless electronic connection.

[0030] exist Figure 1 In the example shown, quantum system 110 can be any suitable set of components capable of performing quantum operations on a physical system. Quantum operations, such as quantum gate operations, manipulate the quantum states of quantum bits to evolve and / or entangle. Figure 1 In the example embodiment shown, the quantum system 110 may include a measurement and control integrated machine 111, an interface 112, and a quantum chip 113. In some embodiments, all or part of each of the measurement and control integrated machine 111, the interface 112, and the quantum chip 113 may be located in a cryogenic environment to help perform quantum operations. The quantum chip 113 may be any hardware capable of processing information using quantum states. The hardware may include a plurality of qubits and a device for coupling or entanglement of the qubits so as to process information using quantum states. Qubits may include, but are not limited to, charge qubits, flux qubits, phase qubits, spin qubits, and ion qubits. The quantum chip may include a set of quantum logic gates configured to perform quantum logic operations on qubits stored in a quantum register. The quantum gate may include one or more single-qubit gates, dual-qubit gates, and / or other multi-qubit gates.

[0031] The measurement and control integrated machine 111 can be any combination of digital computing devices capable of performing quantum computing (e.g., executing quantum circuits) in combination with the interface 112. The digital computing device may include a digital processor and memory for storing and executing quantum instructions using the interface 112. The digital computing device may also include a communication protocol device for receiving instructions and sending the results of the quantum computing performed to a classical computer. In addition, the digital computing device may also include a communication interface with an interface 112. In one embodiment, the measurement and control integrated machine 111 may be configured to receive classical instructions (e.g., from a classical computer 120) and convert the classical instructions into measurement and control instructions for the interface 112. The measurement and control instructions provided to the interface 112 by the measurement and control integrated machine 111 may be, for example, digital signals indicating which quantum gates in the quantum gate need to act on the quantum bit to perform a specific function. The interface 112 may be configured to convert these digital signals into analog signals (e.g., analog pulses of microwave pulses), which may be used to apply quantum gates on the quantum bit to manipulate the interaction between the quantum bits.

[0032] The interface 112 may be a classical-quantum interface, including a device combination capable of receiving instructions from the measurement and control integrated machine 111 and converting the instructions into a device for implementing quantum operations. In one embodiment, the interface 112 may convert instructions from the measurement and control integrated machine 111 into a drive signal that can drive or manipulate a quantum bit, and / or act on a quantum gate on the quantum bit. In addition, the interface 112 may be configured to convert a signal received from the quantum chip 113 into a digital signal that can be processed and transmitted by the measurement and control integrated machine 111. The devices included in the interface 112 may include, but are not limited to, a digital-to-analog converter, an analog-to-digital converter, a waveform generator, an attenuator, an amplifier, an optical fiber, a laser, and a filter. The interface 112 may further include a circuit component configured to measure a plurality of quantum bits after the quantum gate acts, wherein the measurement may produce a result represented by a classical bit. Each measurement performed by the interface 112 may be read out to a device connected to the quantum system 110, such as a classical computer 120. The plurality of measurement results provided by the interface 112 may represent a probabilistic result.

[0033] The classical computer 120 can include hardware components such as a processor and a storage device (e.g., including a memory device and a classical register) for processing data encoded in classical bits. In one embodiment, the classical computer 120 can be configured to provide various control signals, instructions, and data encoded in classical bits to the quantum system 110. Further, the quantum state measured by the quantum system 110 can be read out by the classical computer 120, and the classical computer 120 can store the measured quantum state as a classical bit in a classical register. In one embodiment, the classical computer 120 can be any suitable combination of computer executable hardware and / or computer executable software capable of executing a preparation module 121 to perform quantum computing using data stored in a data storage module 122 as part of the construction and calculation. The data storage module 122 can be a repository for data to be analyzed using a quantum computing algorithm and the results of the analysis. The preparation module 121 can be a program or module capable of preparing classical data from the data storage module 122 as part of a quantum circuit implementation. The preparation module 121 can be instantiated as part of a larger algorithm, such as a function call of an application programming interface (API), or by parsing hybrid classical-quantum computing into aspects of quantum and classical computing. For example, the preparation module 121 can generate instructions for creating a quantum circuit using quantum gates. In an embodiment, such instructions can be stored by the measurement and control integrated machine 111, and components of the interface 112 can be instantiated to execute, so that the quantum operation of the quantum gate can be performed on the quantum chip 113.

[0034] The classical computer 120 may be a laptop computer, a desktop computer, a vehicle integrated computer, a smart mobile device, a tablet device, and / or any other suitable classical computing device. Additionally or alternatively, the classical computer 120 may also be operated as part of a cloud computing service model, such as software as a service (SaaS), platform as a service (PaaS), or infrastructure as a service (IaaS). The classical computer 120 may also be located in a cloud computing deployment model, such as a private cloud, a community cloud, a public cloud, or a hybrid cloud.

[0035] Please refer to Figure 2 , which shows a flow chart of a quantum circuit construction method for predicting the optimal state of a system provided by an embodiment of the present application. The method can be applied to a computer device, which refers to an electronic device with data calculation and processing capabilities. The method may include the following steps:

[0036] Step 201: sequentially apply a Hadamard gate to a first register, apply a first set of variational quantum logic gates virtually controlled by the first register to a second register, a third register, and a fourth register, apply a second set of variational quantum logic gates actually controlled by the first register to the second register, the third register, and the fourth register, apply a NOT gate actually controlled by the first register and the third register to the fourth register, and apply a Hadamard gate to the first register to obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at a current moment according to the observation probability of the quantum state of the first register; the first set of variational quantum logic gates is used to evolve a quantum state representing a system state at a past moment to a quantum state representing a system state at a current moment; and the second set of variational quantum logic gates is used to evolve a quantum state representing a weight of each system state at a past moment to a quantum state of a weight of each system state at a current moment.

[0037] Among them, the first group of variational quantum logic gates and the second group of variational quantum logic gates both include a first quantum logic gate for data encoding and a second quantum logic gate for constructing a proposed circuit, the first quantum logic gate in the first group of variational quantum logic gates is used to encode the system state at the past moment into the quantum state of the second register, and the first quantum logic gate in the second group of variational quantum logic gates is used to encode the weights of each system state at the past moment into the quantum state of the second register.

[0038] For example, the system state at the past moment is x, which includes multiple possibilities, each possible state is x i , where ω i is each x i The weight or probability of + , x iThe corresponding evolution state is in Every weight or probability.

[0039] The first quantum logic gate U in the first set of variational quantum logic gates x Acting on the initial state |000>, the system state x at the past moment is encoded into the quantum state of the second register, that is:

[0040]

[0041] in, is the normalization coefficient, and N is the total number of system states sampled in the past.

[0042] Then, through the second quantum logic gate U in the first set of variational quantum logic gates θ Will Evolved into

[0043] Similarly, the first quantum logic gate U in the second set of variational quantum logic gates z Acting on the initial state |000>, the weight w of each system state at the past moment is encoded into the quantum state of the second register, that is:

[0044]

[0045] Then, through the second quantum logic gate U in the second set of variational quantum logic gates θ Will Evolved into

[0046] Wherein, whether it is the first set of variational quantum logic gates or the second set of variational quantum logic gates, the parameters of the second quantum logic gate are determined according to the loss function training, the value of the loss function is obtained by observing the quantum circuit, and the loss function can be determined according to the difference between the actual value and the predicted value. θ The proposed routes can be the same or different. Even if they are the same, their loss functions are different, so the parameters θ obtained through training will basically be different.

[0047] like Figure 3 As shown, it shows a schematic diagram of the structure of a quantum circuit for predicting the optimal state of a system provided by an embodiment of the present application. Among them, the initial states of the first register, the second register, the third register and the fourth register are the ground state, represented by |0>. For simplicity, the first set of variational quantum logic gates are represented by U m The second set of variational quantum logic gates is represented by U n express.

[0048] After the first H gate, the quantum state is

[0049]

[0050] After the second U m The gate, quantum state is

[0051]

[0052] in, for The corresponding normalization coefficient, v i are quantum states that we don't care about.

[0053] After the third U n The gate, quantum state is

[0054]

[0055] same, for The corresponding normalization coefficient, w i is a quantum state that we do not care about. After the NOT gate controlled by the first and third registers, the quantum state is

[0056]

[0057] After passing through the H gate, the quantum state is

[0058]

[0059] Observe the first bit, the probability of the result being 0 and 1 is

[0060]

[0061] Therefore, there is

[0062]

[0063] According to the Monte Carlo sampling principle and particle filtering method, assume that N samples x are drawn from the distribution with probability density p(x|y) i ,have

[0064]

[0065] In the above formula, E is the expectation and g(x) is an arbitrary function of x. Based on Monte Carlo sampling, formula (10) can be written as

[0066]

[0067] where x i It is the "particle" in particle filtering. δ is the δ function.

[0068]

[0069] is the particle weight, satisfying Based on formula (13), the weight expectation of state x can be obtained as

[0070]

[0071] Therefore, based on equations (9) and (14), we can get

[0072]

[0073] Finally, we get the optimal estimate

[0074]

[0075] In summary, it can be seen that the embodiment of the present application discloses a specific quantum circuit for predicting the optimal state of the system, and the estimation of the optimal state of the system can be achieved through the specific quantum circuit. Secondly, in the embodiment of the present application, the system state is obtained by Monte Carlo sampling, so the final estimation result is related to the number of samples. The more samples are taken, the more accurate the estimation result is. Using a classical computer, the complexity is positively correlated with the number of samples, which leads to the need to balance the estimation accuracy and computing resources when performing the above method on a classical computer. In the embodiment of the present application, quantum acceleration is introduced to alleviate the computational difficulties of classical computers when using large samples.

[0076] In one embodiment provided in the present application, the weights of the system states at the current moment are According to the weight ω of each system state at the past moment i and the likelihood The likelihood probability is used to characterize that the system state at the current moment is the observed state y + The probability of the system state at the current moment is Right now

[0077]

[0078] It can be seen that the actual operation uses an iterative update method, and each new observation y + After being obtained, directly based on the previous ω i Update weights. The update method is to directly use ω i and Multiply them, and then normalize the result to ensure that the sum of the new weight coefficients is 1. The embodiment of the present application provides a method for updating the weights of each system state.

[0079] Further, in the embodiment of the present application, there are

[0080]

[0081] Among them, p i is the likelihood probability The corresponding amplitude, For p i The corresponding normalization coefficient. Figure 3 The proof in the embodiment only needs to substitute formula (18). The result is given directly here without repeating the derivation. Formula (9) becomes:

[0082]

[0083] Furthermore, the weight of each system state at the current moment and the weights ω of each system state at the past moment i and the likelihood The proportional coefficient L is determined according to the observation circuit, that is,

[0084]

[0085] Among them, the observation circuit is composed of a Hadamard gate acting on the fifth register in sequence, a Hadamard gate acting on the sixth register and being virtually controlled by the fifth register, the second group of variational quantum logic gates acting on the sixth register, the seventh register and the eighth register and being actually controlled by the fifth register, and a Hadamard gate acting on the fifth register.

[0086] It should be noted that the first to fourth registers may be the same as or different from the fifth to eighth registers, which is not limited here. For example, the first to fourth registers may be reused to reduce the number of required registers, thereby saving hardware resources.

[0087] Among them, the observation probability that the quantum state of the first register is the ground state is Q 0 , the observation probability that the quantum state of the first register is an excited state is Q 1 ; The observation probability that the quantum state of the fifth register is the ground state is P 0 , the observation probability that the quantum state of the fifth register is an excited state is P 1 ; The optimal state at the current moment is based on (Q 0 -Q 1 ) / (P 0 -P 1 )Sure.

[0088] Here, proof of the conclusion of the above embodiment is given.

[0089] like Figure 4As shown, it shows a schematic diagram of the structure of a quantum circuit for observing a proportional coefficient provided by an embodiment of the present application.

[0090] After the first H gate, the quantum state is

[0091]

[0092] After the controlled H gate layer, the quantum state becomes

[0093]

[0094] Through the controlled U n The gate, the quantum state becomes

[0095]

[0096] After the H gate, the quantum state becomes

[0097]

[0098] When observing the first bit, the probabilities of the results being 0 and 1 are

[0099]

[0100] Therefore, there is

[0101]

[0102] Combining formula (20), we have

[0103]

[0104] Combining equation (19) with equation (26), we have

[0105]

[0106] Finally, we get the optimal estimate

[0107]

[0108] In one embodiment provided in the present application, the likelihood probability is a polynomial about the system state at the current moment, the second quantum logic gate in the second set of variational quantum logic gates includes the second quantum logic gate in the first set of variational quantum logic gates and a third quantum logic gate for constructing a proposed circuit, the second quantum logic gate in the first set of variational quantum logic gates is also used to encode the likelihood probability into the quantum state of the second register, and the third quantum logic gate is used to obtain the quantum state of each system state weight at the current moment according to the quantum state training corresponding to the system state weight at the past moment and the likelihood probability.

[0109] The analytical form of the likelihood density is sometimes difficult to obtain, so it is necessary to expand it into a polynomial form about the current system state for solution. The polynomial about the current system state can first be prepared through the first set of variational quantum logic gates to represent the quantum state of the system at the current moment |x + >, and then through the proposed circuit, the quantum state |x + >evolves into the quantum state corresponding to its polynomial form. The quantum state representing the current state of the system is prepared by the first set of variational quantum logic gates |x + >, we must first pass through the first quantum logic gate U in the first set of variational quantum logic gates. x Acting on the initial state |000>, the system state x at the past moment is encoded into the quantum state of the second register, that is, first through the first quantum logic gate U in the first set of variational quantum logic gates x Prepare the system state x at the past moment, and then pass through two assumed circuits to realize the preparation of the polynomial form of the system state at the current moment.

[0110] For example, suppose the density function is the variance Gaussian distribution, observation result y + = 0, then the likelihood density function can be written as

[0111]

[0112] Formula (29) is not a polynomial function, but it can be approximated by using Taylor expansion and truncating high-order terms to express it as

[0113]

[0114] In this way, you can Written about ω i and and + The multivariate polynomial form is as follows

[0115]

[0116] So The preparation of is already obvious. First, based on the line U m Preparation of quantum state |x + >, then use the variational method to prepare |p>, and finally use the variational algorithm to prepare |ω + >. Specific implementation details are given later.

[0117] The first step is to notice that p is x + The polynomial function can therefore be based on the line U m , using the variational quantum algorithm to construct and train the proposed route Up . Assume line U p The prepared quantum state is

[0118]

[0119] Specifying the loss function

[0120]

[0121] When the loss function C = 0, the proposed route U can be obtained. p satisfy

[0122]

[0123] At this point, we have completed |p i >Preparation.

[0124] The second step is to determine the proposed route U n , determine the loss function

[0125]

[0126] Obviously, when C = 0, z i =ω i p i We already have input U ω and U p preparation

[0127]

[0128] Therefore, we can continue to use the variational quantum algorithm to train the circuit U n , so that

[0129]

[0130] Figure 5 The schematic diagram of the structure of a quantum circuit construction device for predicting the optimal state of a system provided by an embodiment of the present application is shown. The device includes:

[0131] The circuit construction unit 501 is used to sequentially apply a Hadamard gate to a first register, apply a first set of variational quantum logic gates virtually controlled by the first register to a second register, a third register, and a fourth register, apply a second set of variational quantum logic gates actually controlled by the first register to the second register, the third register, and the fourth register, apply a NOT gate actually controlled by the first register and the third register to the fourth register, and apply a Hadamard gate to the first register to obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at a current moment according to the observation probability of the quantum state of the first register; the first set of variational quantum logic gates is used to evolve an initial state from a quantum state representing a system state at a past moment to a quantum state representing a system state at a current moment; and the second set of variational quantum logic gates is used to evolve an initial state from a quantum state representing a weight of each system state at a past moment to a quantum state representing a weight of each system state at a current moment.

[0132] Figure 6 A schematic diagram of the structure of a computer device provided by an embodiment of the present application is shown, including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the functions of the computer system of the quantum circuit construction method for predicting the optimal state of the system in any of the above-mentioned embodiments are implemented.

[0133] The embodiments of the present application also provide a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a computer, the computer executes the functions of the computer system of the quantum circuit construction method for predicting the optimal state of the system in any of the above embodiments.

[0134] The embodiments of the present application also provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to execute the functions of the computer system of the quantum circuit construction method for predicting the optimal state of a system in any of the above embodiments.

[0135] It should be understood that the specific examples in this application are only intended to help those skilled in the art to better understand the implementation methods of this application, rather than to limit the scope of the present invention.

[0136] It can be understood that in the various implementations of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation methods of the present application.

[0137] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0138] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0139] It can be understood that the processor of the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0140] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0141] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0142] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0143] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0145] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0146] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of each implementation method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0147] The above are only specific embodiments of the present application, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for constructing a quantum circuit for predicting the optimal state of a system, characterized in that: include: Sequentially apply the Hadamard gate to the first register, apply the first group of variational quantum logic gates virtually controlled by the first register to the second register, the third register and the fourth register, apply the second group of variational quantum logic gates actually controlled by the first register to the second register, the third register and the fourth register, apply the NOT gate actually controlled by the first register and the third register to the fourth register, apply the Hadamard gate to the first register, and obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at the current moment according to the observation probability of the quantum state of the first register; the first group of variational quantum logic gates is used to evolve the initial state to the quantum state representing the system state at the current moment through the quantum state representing the system state at the past moment; The second set of variational quantum logic gates is used to evolve the initial state through a quantum state representing the weights of each system state at a past moment to a quantum state representing the weights of each system state at a current moment.

2. The method according to claim 1, characterized in that The first group of variational quantum logic gates and the second group of variational quantum logic gates both include a first quantum logic gate for data encoding and a second quantum logic gate for constructing a proposed circuit. The first quantum logic gate in the first group of variational quantum logic gates is used to encode the system state at the past moment into the quantum state of the second register, and the first quantum logic gate in the second group of variational quantum logic gates is used to encode the weights of each system state at the past moment into the quantum state of the second register.

3. The method according to claim 2, characterized in that The parameters of the second quantum logic gate are determined according to loss function training, and the value of the loss function is obtained by observing the quantum circuit.

4. The method according to claim 3, characterized in that: The weights of the system states at the current moment are updated according to the product of the weights of the system states at the past moments and the likelihood probability, and the likelihood probability is used to characterize the probability of the system state at the current moment when the system state at the current moment is the observed state.

5. The method according to claim 4, characterized in that The weight of each system state at the current moment is proportional to the product of the weight of each system state at the past moment and the likelihood probability, and the proportional coefficient is determined according to the observation circuit, which is composed of a Hadamard gate acting on the fifth register in sequence, a Hadamard gate acting on the sixth register and being virtually controlled by the fifth register, the second group of variational quantum logic gates acting on the sixth register, the seventh register and the eighth register and being actually controlled by the fifth register, and a Hadamard gate acting on the fifth register.

6. The method according to claim 5, characterized in that The observation probability that the quantum state of the first register is the ground state is Q0, and the observation probability that the quantum state of the first register is the excited state is Q1; the observation probability that the quantum state of the fifth register is the ground state is P0, and the observation probability that the quantum state of the fifth register is the excited state is P1; the optimal state at the current moment is determined according to (Q0-Q1) / (P0-P1).

7. The method according to any one of claims 4 to 6, characterized in that: The likelihood probability is a polynomial about the system state at the current moment, the second quantum logic gate in the second group of variational quantum logic gates includes the second quantum logic gate in the first group of variational quantum logic gates and a third quantum logic gate for constructing a proposed circuit, the second quantum logic gate in the first group of variational quantum logic gates is also used to encode the likelihood probability into the quantum state of the second register, and the third quantum logic gate is used to obtain the quantum state of each system state weight at the current moment according to the quantum state training corresponding to the system state weight at the past moment and the likelihood probability.

8. A quantum circuit construction device for predicting the optimal state of a system, characterized in that: include: A circuit construction unit is used to sequentially apply a Hadamard gate to a first register, apply a first set of variational quantum logic gates virtually controlled by the first register to a second register, a third register, and a fourth register, apply a second set of variational quantum logic gates actually controlled by the first register to the second register, the third register, and the fourth register, apply a NOT gate actually controlled by the first register and the third register to the fourth register, and apply a Hadamard gate to the first register to obtain a target quantum circuit, wherein the target quantum circuit is used to determine the optimal state of the system at the current moment according to the observation probability of the quantum state of the first register; the first set of variational quantum logic gates is used to evolve the initial state to the quantum state representing the system state at the current moment through the quantum state representing the system state at the past moment; The second set of variational quantum logic gates is used to evolve the initial state through a quantum state representing the weights of each system state at a past moment to a quantum state representing the weights of each system state at a current moment.

9. An electronic device, characterized in that: include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to call the computer program to execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 7 is executed.