A Method for Measuring the Coplanarity of Chip BGA, an Electronic Device, and a Medium

Abstract

The present invention discloses a method for measuring the coplanarity of a chip BGA, an electronic device, and a medium. The method includes: obtaining chip BGA package height map data and segmenting the chip BGA in the height map; segmenting the solder balls in the obtained chip BGA; performing coplanarity measurement on the segmented solder ball data through a dynamic plane fitting algorithm to obtain a measurement result, where the measurement result includes a coplanarity deviation value, a warpage degree, and the overall package height. By dynamically adjusting morphological parameters, introducing principal component analysis noise evaluation, and optimizing the plane fitting algorithm, the present invention improves the accuracy, efficiency, and adaptability of chip BGA coplanarity measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of chip detection, and particularly relates to a method for measuring the coplanarity of chip BGA, an electronic device, and a medium. Background Art

[0002] With the rapid development of electronic manufacturing technology, Ball Grid Array (BGA) packaging has been widely used in the field of integrated circuits due to its high density and high performance characteristics. However, the quality of BGA packaging directly affects the reliability and performance of electronic devices, and coplanarity and warpage are key measurement indicators. Traditional measurement methods usually rely on manual visual inspection or simple image processing techniques, which have problems such as low efficiency and insufficient accuracy, and are difficult to meet the requirements of modern high-precision manufacturing.

[0003] In recent years, automatic measurement technology based on height maps has gradually become the mainstream. By collecting height map data of BGA packaging and combining image processing and machine learning algorithms, efficient and accurate measurement of coplanarity and warpage can be achieved.

[0004] For example, in a Chinese patent document with the publication number CN113052797A and the application number 2021102495776, a three-dimensional detection method for BGA solder balls based on depth image processing is disclosed. Using machine vision technology, after converting the collected chip point cloud into a depth map using point cloud and image processing techniques, the detection and analysis of chip solder balls are carried out. However, this method analyzes and processes the acquired images through a fixed image processing process, and still has deficiencies in dealing with complex noise and dynamically adjusting parameters, and cannot be adjusted according to the specific chip situation, resulting in poor stability and adaptability of the measurement results. Summary of the Invention

[0005] Technical Objective: Aiming at the deficiencies in the existing chip BGA coplanarity detection, the present invention discloses a method for measuring the coplanarity of chip BGA, an electronic device, and a medium based on height maps and dynamic plane fitting, which can adapt to different noise levels and scenarios and perform efficient detection and processing on chips.

[0006] Technical Solution: To achieve the above technical objective, the present invention adopts the following technical solution:

[0007] A method for measuring the coplanarity of chip BGA, characterized by comprising the steps of:

[0008] Step A, obtaining a height map of the chip BGA package;

[0009] Step B, segmenting the chip BGA in the package height map;

[0010] Step C, then segmenting the solder balls in the obtained chip BGA;

[0011] Step D: For the segmented solder ball data, perform coplanarity measurement through the dynamic plane fitting algorithm. Determine the reference plane for coplanarity measurement based on the vertex positions of the solder balls in the segmented solder ball data, and perform coplanarity analysis by calculating the distance from the solder balls to the plane to obtain the measurement results. The measurement results include coplanarity deviation values, warpage, and the overall package height.

[0012] Preferably, in step D of the present invention, the process of determining the reference plane for coplanarity measurement includes:

[0013] Traverse all solder ball combinations in the solder ball set arranged in descending order of height. Start from the solder ball with the highest height and take three solder balls as a group. Perform collinearity judgment on the solder balls in the same group, select non-collinear solder balls for plane equation calculation and centroid inclusion verification; for multiple groups of qualified solder balls, use the plane determined by the group of solder balls with the worst coplanarity as the mounting plane; for the case where there is no mounting plane, obtain the regression plane through weighted least squares regression plane fitting and use the regression plane as the reference plane.

[0014] Preferably, in the present invention, the process of performing collinearity judgment on the solder balls in the same group includes: According to the coordinates of the solder balls, calculate the projection vectors of the solder balls on the XY plane and perform collinearity judgment through vector cross product.

[0015] Preferably, the weighted least squares regression plane fitting process of the present invention includes: Assign weights to each solder ball. The weight value is positively correlated with the height, and construct a weighted point cloud matrix: , , where is the weight value of the th solder ball, which is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of the weight change with height; is the vertical height at the top of the th solder ball; is the lowest value of the heights of all solder balls; is the three-dimensional coordinate of the th solder ball, that is, =( , , ); is the mean vector of the coordinates of all solder balls, that is, , n is the number of solder balls; Calculate the main direction through singular value decomposition (SVD), and take the vector corresponding to the smallest singular value as the normal vector a; Translate the plane to make it pass through the solder ball with the highest height among all solder balls , that is, , and use this plane as the regression plane.

[0016] Preferably, in step B of the present invention, the pixel values of the height map data are first converted into a true height value matrix , , is the encapsulated height map data, is the depth of the encapsulated height map, is the conversion parameter of the line laser measuring instrument for collecting the encapsulated height map;

[0017] Then, the true height value matrix is subjected to PCA dimensionality reduction, the first two principal components are extracted, the image is reconstructed and the residual variance is calculated, and the morphological parameters are dynamically adjusted according to the residual variance;

[0018] The chip BGA of the encapsulated height map is segmented by an adaptive noise suppression chip region segmentation method.

[0019] Preferably, the process of dimensionality reduction and adjustment of morphological parameters of the true height value matrix in the present invention includes:

[0020] Step B1: Center the true height value matrix to obtain the matrix , where is the mean vector of all solder ball coordinates; perform singular value decomposition on to obtain the principal component direction; extract the first two principal components and reconstruct the reduced-dimensional height map matrix ; then calculate the residual variance; , where N is the total number of pixels in the encapsulated height map;

[0021] Set a noise threshold to divide the noise scene, and each divided noise scene corresponds to corresponding morphological parameters. Step B2: Compare the calculated residual variance with a preset threshold, judge the noise scene, and select the corresponding morphological parameters according to the corresponding noise scene; the morphological parameters include the size of the morphological kernel and the number of iterations;

[0022] Step B3: Then calculate the median value of the true height value matrix , and generate a binary mask according to and the tolerance : ;

[0023] The tolerance takes of the maximum height of the true height value matrix, that is ;

[0024] Step B4: Finally, perform morphological closing and opening operations on the binary mask using the morphological parameters determined in step B2 to eliminate noise and retain the complete chip region, and obtain the height map of the segmented chip region.

[0025] Preferably, in step C of the present invention, the process of dividing the solder balls in the chip BGA includes:

[0026] Step C1: Perform bilateral filtering on the height map of the chip area formed after division to remove noise;

[0027] Step C2: Generate binary solder balls according to the height threshold : ;

[0028] where is the height of the corresponding pixel in the true height value matrix , where is , and are the mean and standard deviation of the true height value matrix respectively;

[0029] Step C3: Perform morphological closing and opening operations on , with a kernel size of 3×3 to fill the internal holes of the solder balls, remove small noise points and smooth the contour, and retain the complete solder ball area; extract the solder ball contour through connected component analysis and screen valid solder balls based on area and roundness:

[0030] ;

[0031] Only retain the areas with a roundness greater than the roundness threshold and an area greater than the area threshold as valid solder balls.

[0032] The present invention discloses an electronic device, including: a memory for storing a computer program; a processor for executing the computer program so that the device executes the above-mentioned chip BGA coplanarity measurement method.

[0033] The present invention discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is run, the device running the computer program implements the above-mentioned chip BGA coplanarity measurement method.

[0034] Advantageous effects: The chip BGA coplanarity measurement method, electronic device and medium disclosed by the present invention have the following advantageous effects:

[0035] 1. When dividing the package height map, the present invention dynamically adjusts the morphological parameters according to the noise scenario, and uses dynamic plane fitting, which can adapt to different noise levels and scenario requirements and ensure the stability of the measurement results.

[0036] 2. Through the method of dynamic plane fitting, the present invention can determine the corresponding coplanarity measurement plane according to different encapsulation height map situations, thereby effectively ensuring the measurement accuracy of the coplanarity and warpage of BGA chips. Brief Description of the Drawings

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art.

[0038] Figure 1 It is a flowchart of the coplanarity measurement method of the present invention;

[0039] Figure 2 It is the encapsulation height map of the chip BGA collected;

[0040] Figure 3 It is a schematic diagram of the result of segmenting the chip BGA;

[0041] Figure 4 It is a schematic diagram of a segmented chip BGA;

[0042] Figure 5 It is a schematic diagram of the solder ball segmentation result on a chip BGA;

[0043] Figure 6 It is a schematic diagram of the installation plane of the chip BGA

[0044] Figure 7 It is a schematic diagram of the regression fitting plane of the chip BGA

[0045] Figure 8 It is a schematic diagram of the correlation between the installation plane and the regression fitting plane of the chip BGA. Detailed Embodiments

[0046] Now, reference will be made in detail to the embodiments of the present disclosure, one or more examples of which are set forth below. Each embodiment and example is provided by way of explanation of the apparatus, composition, and materials of the present disclosure, and not by way of limitation. On the contrary, the following description provides a convenient illustration for implementing the exemplary embodiments of the present disclosure. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made within the teachings of the present disclosure without departing from the scope or spirit of the present disclosure.

[0047] As Figure 1 shown, the present invention discloses a method for measuring the coplanarity of a chip BGA, which is characterized by including the steps of:

[0048] Step A, obtaining the encapsulation height map of the chip BGA;

[0049] The present invention uses a line laser measuring instrument to obtain the encapsulation height map data of the chip BGA, Figure 1The figure in the middle is an example of the collected height map of the chip BGA package. The size of the chip BGA package height map is 3200×12000, and its depth is 16 bits, that is, the pixel values range from [0, 32767].

[0050] Step B: Segment the chip BGA in the package height map; when segmenting the chip BGA, first convert the pixel values of the height map data into a real height value matrix , , is the data of the package height map, is the depth of the package height map, is the conversion parameter of the line laser measuring instrument for collecting the package height map. In this embodiment, it is taken as 1.6, and the height unit of the real height value matrix H is mm;

[0051] Then perform PCA dimensionality reduction on the real height value matrix H, extract the first two principal components, reconstruct the image and calculate the residual variance, and dynamically adjust the morphological parameters according to the residual variance;

[0052] Adopt an adaptive noise suppression chip area segmentation method to segment the chip PGA of the package height map. When segmenting, consider the influence of the noise scenario on the segmentation result, so that it can automatically adjust according to the set segmentation process.

[0053] The process of the present invention for dimensionality reduction and adjustment of morphological parameters of the real height value matrix includes:

[0054] Step B1: Centralize the real height value matrix to obtain the matrix , where is the mean vector of the coordinates of all solder balls; perform singular value decomposition on to obtain the principal component direction; extract the first two principal components and reconstruct the height map matrix after dimensionality reduction ; then calculate the residual variance; , where N is the total number of pixels in the package height image, and N is numerically the product of the number of pixels in the height and width directions of the package height map;

[0055] Set a noise threshold to divide the noise scenario. Each divided noise scenario corresponds to corresponding morphological parameters. Step B2: Compare the calculated residual variance with a preset threshold, judge the noise scenario, and select corresponding morphological parameters according to the corresponding noise scenario; the morphological parameters include the size of the morphological kernel and the number of iterations;

[0056] Specifically, the noise threshold can be obtained and set based on experimental data, and the number of divisions can be adjusted according to the measurement accuracy. In the embodiments of the present invention, two sets of thresholds are set to perform a three-level allocation of low, medium, and high for the noise scenario, where threshold 1 = 0.001 and threshold 2 = 0.01; if , it is determined as a low-noise scenario, and the morphological kernel size is set to 3×3, and the number of iterations is 2; if , it is determined as a medium-noise scenario, and the morphological kernel size is set to 5×5, and the number of iterations is 3; if , it is determined as a high-noise scenario, and the morphological kernel size is set to 7×7, and the number of iterations is 4.

[0057] Step B3: Calculate the median value of the true height value matrix , and generate a binary mask according to and the tolerance : ; ;

[0058] The tolerance takes of the maximum height of the true height value matrix, that is , and in the present invention, the tolerance .

[0059] Step B4: Finally, perform morphological closing and opening operations on the binary mask using the morphological parameters determined in Step B2 to eliminate noise and retain the complete chip area, and obtain the height map of the segmented chip area, forming the segmentation result as shown in Figure 3 .

[0060] Step C: Then segment the solder balls in the obtained chip BGA;

[0061] The process of segmenting the solder balls in the chip BGA includes:

[0062] Step C1: Perform bilateral filtering on the height map of the segmented chip area to remove noise;

[0063] Step C2: Generate a binary solder ball according to the height threshold : ;

[0064] Where is the height of the corresponding pixel in the true height value matrix , where is , and are the mean and standard deviation of the true height value matrix respectively;

[0065] Step C3: For Perform morphological closing and opening operations with a kernel size of 3×3 to fill the internal voids of the solder balls, remove small noise, and smooth the contours, retaining the complete solder ball area; extract the solder ball contours through connected component analysis, and filter valid solder balls based on area and roundness:

[0066] ;

[0067] Only retain the regions where the roundness is greater than the roundness threshold and the area is greater than the area threshold as valid solder balls. The roundness threshold and area threshold are set according to requirements. In this embodiment, the roundness threshold is set to 0.7, and the area threshold is 70% of the nominal solder ball size.

[0068] Step D: For the segmented solder ball data, perform coplanarity measurement through the dynamic plane fitting algorithm. Determine the reference plane for coplanarity measurement based on the vertex positions of the solder balls in the segmented solder ball data, and perform coplanarity analysis by calculating the distance from the solder balls to the plane to obtain the measurement results. The measurement results include the coplanarity deviation value, warpage, and the overall package height.

[0069] In step D of the present invention, the process of determining the reference plane for coplanarity measurement includes:

[0070] Traverse all combinations of solder balls in the solder ball set arranged in descending order of height. Start with the solder ball with the highest height and take three solder balls as a group. Perform collinearity judgment on the solder balls in the same group, select non-collinear solder balls for plane equation calculation and centroid inclusion verification. The purpose of the centroid inclusion verification is to ensure that the plane formed by the vertices of the selected three solder balls can simulate the stable placement state of the chip on an ideal plane, that is, the projection of the triangle formed by these three points on the XY plane must contain the projection of the overall centroid of the chip. The conventional verification method is: calculate the XY coordinate projection of the chip centroid and the XY coordinate projection of the selected three solder ball vertices, and then use the judgment algorithm for a point inside a triangle, such as the cross product method, to determine whether the centroid projection falls inside the triangle formed by the three-point projection (excluding the boundary); for multiple groups of solder balls that meet the conditions, use the plane determined by the group of solder balls with the worst coplanarity as the mounting plane. Figure 6 Figure showing the plane obtained by the mounting plane method.

[0071] The process of performing collinearity judgment on the solder balls in the same group includes: According to the coordinates of the solder balls, calculate the projection vectors of the solder balls on the XY plane, and perform collinearity judgment through vector cross product. Assume that the coordinates of three solder balls in the height map coordinate system are respectively ( , , ), ( , , ), ( , , ); Calculate the projection vectors of three points on the XY plane and ; Determine collinearity by the absolute value of the cross product. If , that is is collinear with , then skip this combination, where is a minimum value; Select the solder balls that meet the requirements in this way to determine the installation plane.

[0072] For the case where there is no installation plane, weighted least squares regression plane fitting is used to obtain the regression plane, and the regression plane is used as the reference plane; The weighted least squares regression plane fitting process of the present invention includes: Assign weights to each solder ball, and the weight value is positively correlated with the height, and construct a weighted point cloud matrix: , , where is the weight value of the th solder ball, which is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of the weight change with height; is the vertical height at the top of the th solder ball; is the lowest value of the heights of all solder balls; is the three-dimensional coordinate of the th solder ball, that is = ([[]] , , ); is the mean vector of the coordinates of all solder balls, that is , and n is the number of solder balls; Calculate the main direction by singular value decomposition (SVD), and take the vector corresponding to the smallest singular value as the normal vector a; Translate to get a plane passing through the solder ball with the highest height among all solder balls, that is , and take this plane as the regression plane, Figure 7 is the schematic diagram of the plane obtained by the regression plane method. As Figure 8 shown, it is the correlation between the two planes obtained by simultaneously confirming the installation plane and the regression plane for the same chip BGA height map. It can be seen from the figure that the coplanarity calculated using the installation plane and the regression plane method is statistically consistent and interchangeable. Therefore, when the chip BGA height map does not have an installation plane, the regression plane can be used instead of the installation plane for coplanarity measurement and analysis.

[0073] After obtaining the corresponding reference plane, calculate the vertical distance from the solder ball to the corresponding reference plane for all solder balls on the chip height map, the total number of solder balls on the chip BGA. Assume the reference plane expression is , solder balls The vertical distance to the reference plane is: ;

[0074] The coplanarity is defined as the difference between the maximum and minimum vertical distances, i.e.: ;

[0075] Thus, coplanarity analysis can be performed based on the calculation results.

[0076] When calculating the warpage of the chip BGA, the sampling ratio is dynamically determined according to the total number of solder balls: ;

[0077] where n is the total number of solder balls on the chip BGA. Select the top and the bottom solder balls in descending order of height, and calculate the warpage through the following formula: .

[0078] The overall package height of the chip BGA is the height of the solder ball with the maximum vertical distance to the substrate among all solder balls.

[0079] The present invention also discloses an electronic device, including: a memory for storing a computer program; a processor for executing the computer program so that the device performs the above-mentioned chip BGA coplanarity measurement method.

[0080] The present invention also discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is run, the device running the computer program implements the above-mentioned chip BGA coplanarity measurement method.

[0081] From the description of the above embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solution of the present application can be embodied in the form of a software product, and the computer software product can be stored in a storage medium. The memory can be various types of memories, such as random access memory, read-only memory, flash memory, etc., such as read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or some parts of the embodiments of the present application.

[0082] The above are only the preferred embodiments of the present invention. It should be noted that: for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A chip BGA coplanarity measurement method, characterized in that: Includes steps: Step A, obtaining a chip BGA package height map; Step B, segmenting the chip BGA in the package height diagram; Step C, then dividing the solder balls in the obtained chip BGA; Step D, performing coplanarity measurement on the segmented solder ball data by a dynamic plane fitting algorithm, determining a reference plane for coplanarity measurement according to the position of the solder ball vertices in the segmented solder ball data, and performing coplanarity analysis by calculating the distance from the solder ball to the plane to obtain a measurement result, wherein the measurement result includes a coplanarity deviation value, a warpage, and an overall height of the package; In step D, the process of determining the reference plane for coplanarity measurement includes: Traverse all solder ball combinations in the solder ball set arranged in descending order of height, prioritize the solder ball with the highest height and group three solder balls together, make collinearity judgment for the solder balls in the same group, and select non-collinear solder balls for plane equation calculation and centroid inclusion verification; for multiple groups of solder balls that meet the conditions, take the plane determined by the group of solder balls with the worst coplanarity as the installation plane; if there is no installation plane, obtain the regression plane through weighted least squares regression plane fitting, and take the regression plane as the reference plane; The weighted least squares regression plane fitting process includes: assigning a weight to each solder ball, the weight value is positively correlated with the height, and constructing a weighted point cloud matrix: , ,in, For the The weight value of each solder ball is used for weighted regression plane fitting; k is the weight adjustment coefficient, which controls the sensitivity of weight changes with height; For the The vertical height of the top of the solder ball; It is the minimum value of all solder ball heights; For the The three-dimensional coordinates of the solder ball are =( , , ); is the mean vector of all solder ball coordinates, that is , n is the number of solder balls; calculate the main direction through singular value decomposition SVD, take the vector corresponding to the minimum singular value as the normal vector a; translate the plane to make it pass through the solder ball with the highest height among all solder balls ,Right now , and use this plane as the regression plane.

2. A chip BGA coplanarity measurement method according to claim 1, characterized in that: The process of judging the collinearity of the solder balls in the same group includes: calculating the projection vector of the solder balls on the XY plane according to the coordinates of the solder balls, and judging the collinearity by the vector cross product.

3. A chip BGA coplanarity measurement method according to claim 1, characterized in that: In step B, the height map data pixel values ​​are first converted into a real height value matrix , , To encapsulate height map data, is the package height map depth, Conversion parameters for line laser measuring instruments that collect package height maps; Then the real height value matrix Perform PCA dimensionality reduction, extract the first two principal components, reconstruct the image and calculate the residual variance, and dynamically adjust the morphological parameters according to the residual variance; The chip BGA of the package height map is segmented using a chip area segmentation method with adaptive noise suppression.

4. A chip BGA coplanarity measurement method according to claim 3, characterized in that: The process of reducing the dimension of the true height value matrix and adjusting the morphological parameters includes: Step B1: Matrix the real height value Centralize and get the matrix ,in is the mean vector of all solder ball coordinates; Perform singular value decomposition to obtain the principal component direction; extract the first two principal components and reconstruct the height map matrix after dimensionality reduction ; Then calculate the residual variance; , where N is the total number of pixels in the packed height map; The noise threshold is set to divide the noise scene, and each divided noise scene corresponds to the corresponding morphological parameters. Step B2: Compare the calculated residual variance with a preset threshold value to determine the noise scene, and select corresponding morphological parameters according to the corresponding noise scene; the morphological parameters include morphological kernel size and number of iterations; Step B3, then calculate the true height value matrix The median value ,according to With Tolerance Generate a binary mask: ; Tolerance Get the maximum value of the real height value matrix height ,Right now ; Step B4: Finally, the binary mask is subjected to morphological closing and opening operations using the morphological parameters determined in step B2 to eliminate noise and retain the complete chip area, thereby obtaining a height map of the segmented chip area.

5. A chip BGA coplanarity measurement method according to claim 1, characterized in that: In step C, the process of segmenting the solder balls in the chip BGA includes: Step C1, performing bilateral filtering on the chip area height map formed after segmentation to remove noise; Step C2: According to the height threshold Generate binary solder balls: ; in is the real height value matrix The height of the corresponding pixel in for , and The real height value matrix The mean and standard deviation of Step C3: Perform morphological closing and opening operations with a kernel size of 3×3 to fill the internal voids of the solder balls, remove small noise points, smooth the contours, and retain the complete solder ball area; extract the solder ball contours through connected domain analysis, and select valid solder balls based on area and roundness: ； Only regions with a roundness greater than the roundness threshold and an area greater than the area threshold are retained as valid solder balls.

6. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program so that the device executes the chip BGA coplanarity measurement method described in any one of claims 1-5.

7. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program. When the computer program is executed, a device executing the computer program implements a chip BGA coplanarity measurement method as described in any one of claims 1 to 5.

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