Fingerprint sensor and display device including same

Abstract

The invention discloses a fingerprint sensor and a display device including the same. The fingerprint sensor includes: a readout line disposed on the substrate and extending in a first direction; a first sensor transistor controlling a sensing current based on a voltage of the sensor node; a second sensor transistor supplying a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first sensor transistor with the readout line based on a gate signal; and a fourth sensor transistor including a gate electrode connected to the bias voltage line, a first electrode connected to the bias voltage line, and a second electrode connected to the sensor node.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0155574 filed in the Korean Intellectual Property Office on November 10, 2023, and all benefits obtained therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a fingerprint sensor and a display device including the fingerprint sensor. Background Art

[0004] As information-oriented society progresses, there is an increasing demand for display devices for displaying images. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs. In the display device, since each of the pixels of the display panel includes a light-emitting element capable of self-luminescence, it is possible to display an image without a backlight unit that provides light to the display panel.

[0005] The display device may include a display panel that displays an image, an optical sensor that detects light, and a fingerprint sensor that detects a person's fingerprint, etc. As electronic devices using display devices are diversified, it is necessary to provide display devices in various designs. For example, the display device can expand the display area for displaying an image by removing a sensor device such as a separate optical sensor or fingerprint sensor. Summary of the invention

[0006] Aspects of the present disclosure provide a fingerprint sensor capable of minimizing leakage current flowing in a fingerprint sensor and improving sensitivity of a fingerprint sensor even in a high-resolution structure having a fingerprint sensor and dense pixels, and a display device including the fingerprint sensor.

[0007] However, aspects of the present disclosure are not limited to the one aspect set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to an embodiment, a fingerprint sensor includes: a readout line disposed on a substrate and extending in a first direction; a first sensor transistor that controls a sensing current based on a voltage of a sensor node; a second sensor transistor that supplies a reset voltage to the sensor node based on a reset signal; a third sensor transistor that electrically connects a first electrode of the first sensor transistor to the readout line based on a gate signal; and a fourth sensor transistor including a gate electrode connected to a bias voltage line, a first electrode connected to the bias voltage line, and a second electrode connected to the sensor node.

[0009] The second sensor transistor may supply a reset voltage to the sensor node during a first period. The fourth sensor transistor may supply a leakage current to the sensor node during a second period after the first period. The third sensor transistor may be turned on during a third period after the second period.

[0010] The fingerprint sensor may include: a first active layer, which is arranged on a substrate and includes a semiconductor region of each of a first sensor transistor, a third sensor transistor and a fourth sensor transistor; a first gate layer, which is arranged on the first active layer; a second gate layer, which is arranged on the first gate layer; a second active layer, which is arranged on the second gate layer and includes a semiconductor region of a second sensor transistor; a third gate layer, which is arranged on the second active layer; a first source metal layer, which is arranged on the third gate layer; and a second source metal layer, which is arranged on the first source metal layer.

[0011] The fingerprint sensor may further include: a shielding electrode disposed on the second source metal layer to overlap the second sensor transistor but not to overlap the fourth sensor transistor.

[0012] The fingerprint sensor may further include: a hole transport layer disposed on the shielding electrode to overlap the first to fourth sensor transistors; an electron transport layer disposed on the hole transport layer to overlap the first to fourth sensor transistors; and a common electrode disposed on the electron transport layer to overlap the first to fourth sensor transistors.

[0013] The gate electrode of the fourth sensor transistor may include a hole exposing a portion of the semiconductor region of the fourth sensor transistor to the reflected light.

[0014] According to an embodiment, a fingerprint sensor includes: a readout line disposed on a substrate and extending in a first direction; a first sensor transistor controlling a sensing current based on a voltage of a sensor node; a second sensor transistor supplying a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first sensor transistor to the readout line based on a gate signal; and a fourth sensor transistor including a gate electrode connected to a leakage voltage line to receive a leakage voltage, a first electrode connected to a bias voltage line to receive a bias voltage smaller than the leakage voltage, and a second electrode connected to the sensor node.

[0015] The second sensor transistor may supply a reset voltage to the sensor node during a first period. The fourth sensor transistor may supply a leakage current to the sensor node during a second period after the first period. The third sensor transistor may be turned on during a third period after the second period.

[0016] The fingerprint sensor may include: a first active layer, which is arranged on a substrate and includes a semiconductor region of each of a first sensor transistor, a third sensor transistor and a fourth sensor transistor; a first gate layer, which is arranged on the first active layer; a second gate layer, which is arranged on the first gate layer; a second active layer, which is arranged on the second gate layer and includes a semiconductor region of a second sensor transistor; a third gate layer, which is arranged on the second active layer; a first source metal layer, which is arranged on the third gate layer; and a second source metal layer, which is arranged on the first source metal layer.

[0017] The fingerprint sensor may further include: a shielding electrode disposed on the second source metal layer to overlap the second sensor transistor but not to overlap the fourth sensor transistor.

[0018] The fingerprint sensor may further include: a hole transport layer disposed on the shielding electrode to overlap the first to fourth sensor transistors; an electron transport layer disposed on the hole transport layer to overlap the first to fourth sensor transistors; and a common electrode disposed on the electron transport layer to overlap the first to fourth sensor transistors.

[0019] The gate electrode of the fourth sensor transistor may include a hole exposing a portion of the semiconductor region of the fourth sensor transistor to the reflected light.

[0020] According to an embodiment, a display device includes: a pixel disposed in an emission region and including a light emitting element; and a fingerprint sensor disposed in a sensor region. The fingerprint sensor includes: a readout line disposed on a substrate and extending in a first direction; a first sensor transistor controlling a sensing current based on a voltage of a sensor node; a second sensor transistor supplying a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting a first electrode of the first sensor transistor to the readout line based on a first gate signal; and a fourth sensor transistor including a gate electrode connected to a leakage voltage line to receive a leakage voltage, a first electrode connected to a bias voltage line to receive a bias voltage smaller than the leakage voltage, and a second electrode connected to the sensor node.

[0021] The pixel may include: a first transistor that controls a driving current flowing through a light-emitting element; a second transistor that supplies a data voltage to a first electrode of the first transistor based on a first gate signal; a third transistor that electrically connects the second electrode of the first transistor to the gate electrode of the first transistor based on a second gate signal; and a fourth transistor that discharges the gate electrode of the first transistor to a first initialization voltage based on the third gate signal.

[0022] A semiconductor region of each of the first transistor and the second transistor may include a silicon-based material, and a semiconductor region of each of the third transistor and the fourth transistor may include an oxide-based material.

[0023] The pixel may further include: a fifth transistor, which supplies a driving voltage to the first electrode of the first transistor based on the emission signal; a sixth transistor, which electrically connects the second electrode of the first transistor to the light-emitting element based on the emission signal; and a seventh transistor, which discharges the first electrode of the light-emitting element to a second initialization voltage based on the fourth gate signal.

[0024] The display device may include: a first active layer, which is arranged on a substrate and includes a semiconductor region of each of a first sensor transistor, a third sensor transistor, and a fourth sensor transistor; a first gate layer, which is arranged on the first active layer; a second gate layer, which is arranged on the first gate layer; a second active layer, which is arranged on the second gate layer and includes a semiconductor region of a second sensor transistor; a third gate layer, which is arranged on the second active layer; a first source metal layer, which is arranged on the third gate layer; and a second source metal layer, which is arranged on the first source metal layer.

[0025] The light-emitting element may include: a pixel electrode, which is arranged on the second source metal layer; a hole transport layer, which is arranged on the pixel electrode and is implemented as a common layer of the emission region and the sensor region; a light-emitting layer, which is arranged on the hole transport layer; an electron transport layer, which is arranged on the light-emitting layer and is implemented as a common layer of the emission region and the sensor region; and a common electrode, which is arranged on the electron transport layer.

[0026] The fingerprint sensor may further include: a shielding electrode disposed at the same layer as the pixel electrode to overlap the second sensor transistor but not to overlap the fourth sensor transistor.

[0027] The gate electrode of the fourth sensor transistor may include a hole exposing a portion of the semiconductor region of the fourth sensor transistor to the reflected light.

[0028] A fingerprint sensor and a display device including the fingerprint sensor according to an embodiment may include a phototransistor having a gate-source voltage greater than zero, thereby minimizing leakage current flowing in the fingerprint sensor and improving sensitivity of the fingerprint sensor even in a high-resolution structure having the fingerprint sensor and dense pixels.

[0029] However, the effects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other effects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 is a perspective view showing a display device according to an embodiment;

[0032] Figure 2 is a cross-sectional view illustrating a display device according to an embodiment;

[0033] Figure 3 is a plan view illustrating a display unit of a display device according to an embodiment;

[0034] Figure 4 is a block diagram illustrating a display unit and a display driver according to one embodiment;

[0035] Figure 5 is a plan view illustrating a display area of ​​a display device according to an embodiment;

[0036] Figure 6 is a circuit diagram illustrating a pixel of a display device according to an embodiment;

[0037] Figure 7 is a cross-sectional view illustrating a pixel of a display device according to an embodiment;

[0038] Figure 8 is a circuit diagram illustrating a fingerprint sensor of a display device according to one embodiment;

[0039] Fig. 9 is supplied to Figure 8 A waveform diagram of a signal of the fingerprint sensor shown in FIG.

[0040] Fig.10 The fingerprint sensor is shown in the figure Fig. 9 a circuit diagram of operation during a first period of time;

[0041] Fig.11 The fingerprint sensor is shown in the figure Fig. 9 a circuit diagram of operation during a second period of time;

[0042] Fig.12 The fingerprint sensor is shown in the figure Fig. 9 a circuit diagram of operation during a third period of time;

[0043] Fig.13 It is shown in Figure 8 a graph showing a magnitude of a leakage current flowing in a fourth sensor transistor;

[0044] Fig.14 is a circuit diagram illustrating a fingerprint sensor of a display device according to another embodiment;

[0045] Fig.15 is a cross-sectional view illustrating a portion of a fingerprint sensor in a display device according to an embodiment;

[0046] Fig.16is a plan view illustrating one example of a fourth sensor transistor of a fingerprint sensor in a display device according to one embodiment;

[0047] Fig.17 is along Fig.16 A cross-sectional view taken along line II';

[0048] Fig.18 is a plan view illustrating another example of a fourth sensor transistor of a fingerprint sensor in a display device according to one embodiment; and

[0049] Fig.19 is along Fig.18 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0050] In the following description, for the purpose of explanation, many details are set forth to provide a thorough understanding of various embodiments or implementations of the present disclosure. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of devices or methods that adopt one or more concepts in the concepts disclosed herein. However, it is apparent that various embodiments can be practiced without these specific details or one or more equivalent arrangements can be used. In other cases, structures and devices are shown in block diagram form to avoid unnecessary ambiguity of various embodiments. Further, various embodiments can be different, but do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration and characteristics of the embodiment can be used or implemented in other embodiments without departing from the present disclosure.

[0051] Unless otherwise specified, the illustrated embodiments should be understood as providing features of different details of some ways in which the present disclosure can be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter referred to as "elements" individually or collectively) of the various embodiments can be combined, separated, interchanged and / or rearranged in other ways without departing from the present disclosure.

[0052] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, neither the presence or absence of cross-hatching or shading conveys or indicates any preference or requirement for specific materials, material properties, dimensions, proportions, commonalities between illustrated elements, and / or any other features, attributes, properties, etc. of elements.

[0053] Further, in the accompanying drawings, the size and relative size of the elements may be exaggerated for clarity and / or descriptive purposes. When the embodiments can be implemented differently, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals refer to the same elements.

[0054] When an element, such as a layer, is referred to as being "on," "connected to," or "coupled to" another element or layer, it may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements.

[0055] Further, the X-axis direction, the Y-axis direction, and the Z-axis direction are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and therefore, the X-axis direction, the Y-axis direction, and the Z-axis direction may be interpreted in a broader sense. For example, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0056] For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, for example, XYZ, XY, YZ, or XZ, etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0057] Although the terms "first" and "second" etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0058] For descriptive purposes, spatially relative terms such as "below," "below," "under," "down," "above," "on," "above," and "side" (e.g., as in "sidewall") may be used herein and thereby describe the relationship of one element to another element(s) as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, an element described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Thus, the term "below" can encompass both above and below orientations. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0059] The term used herein is for the purpose of describing a particular embodiment, and is not intended to be limiting. As used herein, the singular "one" and "the (described)" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when used in this specification, the term "includes", "comprising" and / or its variations indicate that there are narrated features, integral bodies, steps, operations, elements, parts and / or their groups, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. It should also be noted that, as used herein, the term "substantially", "about" and other similar terms are used as approximate terms, and are not used as terms of degree, and are therefore used to explain the inherent deviation of the measured value, calculated value and / or the value provided that a person of ordinary skill in the art will recognize.

[0060] Various embodiments are described herein with reference to cross-sectional illustrations and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. As such, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the particular shapes of the illustrated zones, but should include deviations in shapes due to, for example, manufacturing. In this manner, the zones illustrated in the drawings may be schematic in nature, and the shapes of these zones may not reflect the actual shapes of the zones of the device, and are therefore not necessarily intended to be limiting.

[0061] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units, parts and / or modules. It will be appreciated by those skilled in the art that these blocks, units, parts and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units, parts and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit, part and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware that performs certain functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, the various blocks, units, parts and / or modules of some embodiments can be physically separated into two or more interacting and discrete blocks, units, parts and / or modules without departing from the scope of this disclosure. Further, the blocks, units, parts and / or modules of some embodiments may be physically combined into more complex blocks, units, parts and / or modules without departing from the scope of the present disclosure.

[0062] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and should not be interpreted in an ideal or overly formal sense unless explicitly so defined herein.

[0063] Detailed embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings.

[0064] Figure 1 is a perspective view showing a display device according to one embodiment.

[0065] refer to Figure 1 , the display device 10 may be applied to portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation systems, or ultra mobile PCs (UMPCs). For example, the display device 10 may be used as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) device. As another example, the display device 10 may be applied to wearable devices such as smart watches, watch phones, glasses-type displays, or head-mounted displays (HMDs).

[0066] The display device 10 may have a planar shape similar to a quadrilateral shape. Figure 1 In the embodiment of the present invention, the display device 10 may have a shape similar to a quadrilateral shape in a plan view, which has a short side in the X-axis direction and a long side in the Y-axis direction. The corner at which the short side in the X-axis direction and the long side in the Y-axis direction intersect may be rounded to have a predetermined curvature, or may be a right angle. The planar shape of the display device 10 is not limited to a quadrilateral shape, and may be formed in a shape similar to other polygonal shapes, a circular shape, or an elliptical shape.

[0067] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , a touch driver 400 , and a power supply unit 500 .

[0068] The display panel 100 may include a main area MA and a sub-area SBA.

[0069] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of opening areas. For example, the display panel 100 may include a pixel circuit including a switching element, a pixel defining layer defining an emission area or an opening area, and a self-luminous element.

[0070] For example, the self-luminous element may include one of an organic light emitting diode (LED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED, but is not limited thereto.

[0071] The non-display area NDA may be an area outside the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies a gate signal to a gate line and a fan-out line (not shown) that connects the display driver 200 to the display area DA.

[0072] The sub-area SBA may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a display driver 200 and a pad portion connected to the circuit board 300. Alternatively, the sub-area SBA may be omitted, and the display driver 200 and the pad portion may be arranged in the non-display area NDA.

[0073] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power supply voltage to a power supply line, and may supply a gate control signal to a gate driver. The display driver 200 may receive a sensing signal through a readout line. The display driver 200 may be formed as an integrated circuit (IC) and may be mounted on the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in a sub-area SBA, and may overlap with the main area MA in a thickness direction (Z-axis direction) by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0074] The circuit board 300 may be attached to the pad portion of the display panel 100 by using an anisotropic conductive film (ACF). Leads of the circuit board 300 may be electrically connected to the pad portion of the display panel 100. The circuit board 300 may be a flexible printed circuit board, a rigid printed circuit board, or a flexible film such as a chip on film.

[0075] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to the touch sensing unit of the display panel 100. The touch driver 400 may supply a touch drive signal to a plurality of touch electrodes of the touch sensing unit, and may sense the amount of change in capacitance between the plurality of contact electrodes. For example, the touch drive signal may be a pulse signal having a predetermined frequency. The touch driver 400 may calculate whether an input is made and the input coordinates based on the amount of change in capacitance between the plurality of touch electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0076] The power supply unit 500 may be provided on the circuit board 300 to supply the power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a driving voltage to supply it to a driving voltage line, and may generate a common voltage to supply it to a common electrode shared by the light-emitting elements of a plurality of pixels. For example, the driving voltage may be a high potential voltage for driving the light-emitting element, and the common voltage may be a low potential voltage for driving the light-emitting element. The power supply unit 500 may generate an initialization voltage to supply it to an initialization voltage line, generate a reference voltage to supply it to a reference voltage line, generate a bias voltage to supply it to a bias voltage line, and generate a reset voltage to supply it to a reset voltage line.

[0077] Figure 2 is a cross-sectional view illustrating a display device according to an embodiment.

[0078] refer to Figure 2The display panel 100 may include a display unit DU, a touch sensing unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a transistor layer TFTL, a light emitting element layer EDL, and an encapsulation layer TFEL.

[0079] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0080] The transistor layer TFTL may be disposed on the substrate SUB. The transistor layer TFTL may include a plurality of transistors constituting pixels and fingerprint sensors. The transistor layer TFTL may further include a gate line, a data line, a power line, a readout line, a gate control line, a fan-out line connecting the display driver 200 to the data line, and a lead connecting the display driver 200 to the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when a gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0081] The transistor layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, power lines, and readout lines of the transistor layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the transistor layer TFTL may be disposed in the non-display area NDA. The lead lines of the transistor layer TFTL may be disposed in the sub-area SBA.

[0082] The light emitting element layer EDL may be disposed on the transistor layer TFTL. The light emitting element layer EDL may include a light emitting element of a pixel and a pixel defining layer defining a pixel and a fingerprint sensor. The light emitting element may be formed by sequentially stacking a pixel electrode, a light emitting layer, and a common electrode to emit light.

[0083] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through the transistor of the transistor layer TFTL and the common electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transport layer, electrons may move to the organic light-emitting layer through the electron transport layer, and holes and electrons may recombine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode, and the common electrode may be a cathode electrode, but the present disclosure is not limited thereto.

[0084] For example, the plurality of light emitting elements may include a quantum dot light emitting diode including a quantum dot light emitting layer, an inorganic light emitting diode including an inorganic semiconductor, or a micro light emitting diode.

[0085] The encapsulation layer TFEL may cover the top surface and the side surface of the light emitting element layer EDL and may protect the light emitting element layer EDL. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EDL.

[0086] The touch sensing unit TSU may be disposed on the encapsulation layer TFEL. The touch sensing unit TSU may include a plurality of touch electrodes for sensing a user touch in a capacitive manner and a touch line connecting the plurality of touch electrodes to the touch driver 400. The plurality of touch electrodes of the touch sensing unit TSU may be disposed in a touch sensor region overlapping the display area DA. The touch line of the touch sensing unit TSU may be disposed in a touch peripheral region overlapping the non-display area NDA. For example, the touch sensing unit TSU may sense a user touch by using a mutual capacitance method or a self-capacitance method.

[0087] As another example, the touch sensing unit TSU may be provided on a separate substrate provided on the display unit DU. In this case, the substrate supporting the touch sensing unit TSU may be a base member that packages the display unit DU.

[0088] The color filter layer CFL may be disposed on the touch sensing unit TSU. The color filter layer CFL may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and may block or absorb light of a different wavelength. The color filter layer CFL may absorb a portion of light coming from outside the display device 10 to reduce reflection of external light. Accordingly, the color filter layer CFL may prevent color distortion caused by reflection of external light.

[0089] Since the color filter layer CFL is directly disposed on the touch sensing unit TSU, the display device 10 may not require a separate substrate for the color filter layer CFL. Therefore, the thickness of the display device 10 may be reduced.

[0090] The sub-area SBA of the display panel 100 may extend from one side of the main area MA. The sub-area SBA may include a flexible material that can be bent, folded, or curled. For example, when the sub-area SBA is bent, the sub-area SBA may overlap the main area MA in the thickness direction (Z-axis direction). The sub-area SBA may include a display driver 200 and a pad portion electrically connected to the circuit board 300.

[0091] Figure 3 is a plan view illustrating a display unit of a display device according to an embodiment. Figure 4 is a block diagram illustrating a display unit and a display driver according to one embodiment.

[0092] refer to Figure 3 and Figure 4 The display unit DU may include a display area DA and a non-display area NDA. The display area DA may include pixels SP, a fingerprint sensor OPD, power lines VL, data lines DL, readout lines ROL, gate lines GL, and emission control lines EML.

[0093] Each of the plurality of pixels SP may be connected to a gate line GL, an emission control line EML, a data line DL, and a power line VL. Each of the pixels SP may include a light emitting element, a capacitor, and a plurality of transistors.

[0094] Each of the plurality of fingerprint sensors OPD may be connected to a gate line GL, a power line VL, and a readout line ROL. Each of the plurality of fingerprint sensors OPD may include a plurality of transistors.

[0095] The gate lines GL may extend in an X-axis direction and may be spaced apart from each other in a Y-axis direction crossing the X-axis direction. The gate lines GL may sequentially supply gate signals to the pixels SP and the fingerprint sensor OPD.

[0096] The emission control lines EML may extend in the X-axis direction and may be spaced apart from each other in the Y-axis direction. The emission control lines EML may sequentially supply emission signals to the pixels SP.

[0097] The data lines DL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The data lines DL may supply a data voltage to the pixels SP. The data voltage may determine the brightness of each of the pixels SP.

[0098] The power lines VL may extend in the Y-axis direction and may be spaced apart from each other in the X-axis direction. The power lines VL may supply a power voltage to the pixels SP and the fingerprint sensor OPD. Here, the power voltage may be a driving voltage, a common voltage, an initialization voltage, a reference voltage, a bias voltage, or a reset voltage. The driving voltage may be a high potential voltage for driving the pixels SP, and the common voltage may be a low potential voltage for driving the pixels SP and the fingerprint sensor OPD.

[0099] The non-display area NDA may surround the display area DA. The non-display area NDA may include a gate driver 610, an emission control driver 620, a fan-out line FL, a first gate control line GSL1, and a second gate control line GSL2.

[0100] like Figure 3As shown in , the fan-out line FL may extend from the display driver 200 to the display area DA. The fan-out line FL may supply a data voltage received from the display driver 200 to the data line DL, may supply a power supply voltage received from the display driver 200 to the power line VL, and may supply a sensing signal received from the readout line ROL to the display driver 200. Accordingly, the display driver 200 may drive the pixel SP and the fingerprint sensor OPD.

[0101] The first gate control line GSL1 may extend from the display driver 200 to the gate driver 610. The first gate control line GSL1 may supply the gate control signal GCS received from the display driver 200 to the gate driver 610.

[0102] The second gate control line GSL2 may extend from the display driver 200 to the emission control driver 620. The second gate control line GSL2 may supply the emission control signal ECS received from the display driver 200 to the emission control driver 620.

[0103] The sub-area SBA may extend from one side of the non-display area NDA. The sub-area SBA may include a display driver 200 and a pad portion DP. The pad portion DP may be disposed closer to one edge of the sub-area SBA than the display driver 200. The pad portion DP may be electrically connected to the circuit board 300 through an anisotropic conductive film.

[0104] Figure 4 It is depicted that the display driver 200 may include a timing controller 210 and a data driver 220 .

[0105] The timing controller 210 may receive the digital video data DATA and the timing signal from the circuit board 300. The timing controller 210 may generate the data control signal DCS based on the timing signal, and supply the digital video data DATA and the data control signal DCS to the data driver 220 to control the operation timing of the data driver 220. The timing controller 210 may supply the gate control signal GCS to the gate driver 610, and control the operation timing of the gate driver 610. The timing controller 210 may supply the emission control signal ECS to the emission control driver 620, and control the operation timing of the emission control driver 620.

[0106] The data driver 220 may convert the digital video data DATA into an analog data voltage and supply it to the data line DL through the fan-out line FL. The gate signal of the gate driver 610 may select the pixel SP to be supplied with the data voltage, and the selected pixel SP may receive the data voltage through the data line DL. The data driver 220 may supply the sensing signal received through the readout line ROL to the display driver 200.

[0107] The power supply unit 500 may be provided on the circuit board 300 to supply a power supply voltage to the display driver 200 and the display panel 100. The power supply unit 500 may generate a power supply voltage to supply it to the power supply line VL, and generate a common voltage to supply it to a common electrode shared by the pixel SP and the fingerprint sensor OPD. The power supply unit 500 may generate an initialization voltage to supply it to an initialization voltage line, generate a reference voltage to supply it to a reference voltage line, generate a bias voltage to supply it to a bias voltage line, and generate a reset voltage to supply it to a reset voltage line.

[0108] The gate driver 610 may be disposed on one side outside the display area DA or on one side of the non-display area NDA. The emission control driver 620 may be disposed on the other side outside the display area DA or on the other side of the non-display area NDA. However, the present disclosure is not limited thereto. As another example, the gate driver 610 and the emission control driver 620 may be disposed on either one side or the other side of the non-display area NDA.

[0109] The gate driver 610 may include a plurality of transistors for generating gate signals based on the gate control signal GCS. The emission control driver 620 may include a plurality of transistors for generating emission signals based on the emission control signal ECS. For example, the transistors of the gate driver 610 and the transistors of the emission control driver 620 may be formed in the same layer as the transistors of each pixel SP. The gate driver 610 may supply the gate signal to the gate line GL, and the emission control driver 620 may supply the emission signal to the emission control line EML.

[0110] Figure 5 is a plan view illustrating a display area of ​​a display device according to an embodiment.

[0111] refer to Figure 5 , the display area DA may include an emission area EA and a non-emission area NEA. The emission area EA may emit light of a light emitting element, and the light emitting element may not be disposed in the non-emission area NEA. The non-emission area NEA may include sensor areas PDA spaced apart from each other with at least one emission area EA therebetween. The emission area EA may include first to third emission areas EA1, EA2, and EA3. For example, the first emission area EA1 may emit light of a first color or red light, the second emission area EA2 may emit light of a second color or green light, and the third emission area EA3 may emit light of a third color or blue light, but is not limited thereto.

[0112] Figure 5A unit pixel UP is depicted, which can express a white grayscale by including one first emission area EA1, two second emission areas EA2, and one third emission area EA3, but the configuration of the unit pixel UP is not limited thereto. The white grayscale can be expressed by a combination of light emitted from one first emission area EA1, light emitted from two second emission areas EA2, and light emitted from one third emission area EA3.

[0113] The first to third emission areas EA1, EA2, and EA3 may be different in size from each other. For example, the size of the third emission area EA3 may be larger than the size of the first emission area EA1, and the size of the first emission area EA1 may be larger than the size of the second emission area EA2. However, the present disclosure is not limited thereto. As another example, the sizes of the first to third emission areas EA1, EA2, and EA3 may be the same.

[0114] The sensor area PDA may be surrounded by the first to third emission areas EA1, EA2, and EA3. The sensor area PDA may be adjacent to the first emission area EA1 or the third emission area EA3 in the X-axis direction, and may be adjacent to the second emission area EA2 in the Y-axis direction. The sensor areas PDA may be spaced apart from each other with at least one emission area EA therebetween. The sensor area PDA may receive light reflected by a fingerprint.

[0115] Figure 6 is a circuit diagram illustrating a pixel of a display device according to an embodiment.

[0116] refer to Figure 6 , the pixel SP may be connected to a first gate line GWL, a second gate line GCL, a third gate line GIL, a fourth gate line GBL, an emission control line EML, a data line DL, a driving voltage line VDDL, a first initialization voltage line VIL1, a second initialization voltage line VIL2, and a bias voltage line VBL.

[0117] The pixel SP may include a light emitting element ED and a pixel circuit for driving the light emitting element ED. The pixel circuit may include first to seventh transistors ST1, ST2, ST3, ST4, ST5, ST6, and ST7 and a capacitor CST.

[0118] The first transistor ST1 may control a driving current supplied to the light emitting element ED. The first transistor ST1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor ST1 may be connected to the third node N3, the first electrode of the first transistor ST1 may be connected to the first node N1, and the second electrode of the first transistor ST1 may be connected to the second node N2. For example, the first electrode of the first transistor ST1 may be a source electrode, and the second electrode of the first transistor ST1 may be a drain electrode, but the present disclosure is not limited thereto.

[0119] The first transistor ST1 may control a source-drain current Isd (hereinafter referred to as a "driving current") according to a data voltage applied to a gate electrode. The driving current Isd flowing through the channel of the first transistor ST1 may be proportional to the square of a difference between a threshold voltage Vth of the first transistor ST1 and a voltage Vsg between a source electrode and a gate electrode (Isd=k×(Vsg-Vth) 2 ). Here, k is a proportionality coefficient determined by the structure and physical characteristics of the first transistor ST1, Vsg is a source-gate voltage of the first transistor ST1, and Vth is a threshold voltage of the first transistor ST1.

[0120] The light emitting element ED may emit light by receiving a driving current Isd. The emission amount or emission brightness of the light emitting element ED may be proportional to the size of the driving current Isd. The light emitting element ED may include a first electrode, a second electrode, and a light emitting layer disposed between the first electrode and the second electrode. The first electrode of the light emitting element ED may be connected to a fourth node N4. The first electrode of the light emitting element ED may be connected to a second electrode of the sixth transistor ST6 and a first electrode of the seventh transistor ST7 through the fourth node N4. The second electrode of the light emitting element ED may be electrically connected to a bias voltage line VBL. The second electrode of the light emitting element ED may receive a bias voltage or a low potential voltage from the bias voltage line VBL. For example, the first electrode of the light emitting element ED may be an anode electrode or a pixel electrode, and the second electrode of the light emitting element ED may be a cathode electrode or a common electrode, but the present disclosure is not limited thereto.

[0121] The second transistor ST2 may be turned on by the first gate signal of the first gate line GWL to electrically connect the data line DL to the first node N1 which is the first electrode of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal to supply the data voltage to the first node N1. The gate electrode of the second transistor ST2 may be connected to the first gate line GWL, the first electrode of the second transistor ST2 may be connected to the data line DL, and the second electrode of the second transistor ST2 may be connected to the first node N1. The second electrode of the second transistor ST2 may be connected to the first electrode of the first transistor ST1 and the second electrode of the fifth transistor ST5 through the first node N1. For example, the first electrode of the second transistor ST2 may be a source electrode, and the second electrode of the second transistor ST2 may be a drain electrode, but the present disclosure is not limited thereto.

[0122] The third transistor ST3 may be turned on by the second gate signal of the second gate line GCL to electrically connect the second node N2 of the second electrode of the first transistor ST1 to the third node N3 which is the gate electrode of the first transistor ST1. The gate electrode of the third transistor ST3 may be connected to the second gate line GCL, the first electrode of the third transistor ST3 may be connected to the second node N2, and the second electrode of the third transistor ST3 may be connected to the third node N3. The first electrode of the third transistor ST3 may be connected to the second electrode of the first transistor ST1 and the first electrode of the sixth transistor ST6. The second electrode of the third transistor ST3 may be connected to the gate electrode of the first transistor ST1, the first electrode of the fourth transistor ST4, and the first capacitor electrode of the capacitor CST through the third node N3. For example, the first electrode of the third transistor ST3 may be a drain electrode, and the second electrode of the third transistor ST3 may be a source electrode, but the present disclosure is not limited thereto.

[0123] The fourth transistor ST4 may be turned on by the third gate signal of the third gate line GIL to electrically connect the third node N3 of the gate electrode of the first transistor ST1 to the first initialization voltage line VIL1. The fourth transistor ST4 may be turned on based on the third gate signal so that the gate electrode of the first transistor ST1 is discharged to the first initialization voltage. The gate electrode of the fourth transistor ST4 may be connected to the third gate line GIL, the first electrode of the fourth transistor ST4 may be connected to the third node N3, and the second electrode of the fourth transistor ST4 may be connected to the first initialization voltage line VIL1. The first electrode of the fourth transistor ST4 may be connected to the gate electrode of the first transistor ST1, the second electrode of the third transistor ST3, and the first capacitor electrode of the capacitor CST. For example, the first electrode of the fourth transistor ST4 may be a drain electrode, and the second electrode of the fourth transistor ST4 may be a source electrode, but the present disclosure is not limited thereto.

[0124] The fifth transistor ST5 may be turned on by an emission signal of an emission control line EML to electrically connect the driving voltage line VDDL to a first node N1 which is a first electrode of the first transistor ST1. A gate electrode of the fifth transistor ST5 may be connected to the emission control line EML, a first electrode of the fifth transistor ST5 may be connected to the driving voltage line VDDL, and a second electrode of the fifth transistor ST5 may be connected to the first node N1. A second electrode of the fifth transistor ST5 may be electrically connected to a first electrode of the first transistor ST1 and a second electrode of the second transistor ST2 through a first node N1. For example, the first electrode of the fifth transistor ST5 may be a source electrode, and the second electrode of the fifth transistor ST5 may be a drain electrode, but the present disclosure is not limited thereto.

[0125] The sixth transistor ST6 may be turned on by the emission signal of the emission control line EML to electrically connect the second node N2 of the second electrode of the first transistor ST1 to the fourth node N4 which is the first electrode of the light emitting element ED. The gate electrode of the sixth transistor ST6 may be connected to the emission control line EML, the first electrode of the sixth transistor ST6 may be connected to the second node N2, and the second electrode of the sixth transistor ST6 may be connected to the fourth node N4. The first electrode of the sixth transistor ST6 may be connected to the second electrode of the first transistor ST1 and the first electrode of the third transistor ST3 through the second node N2. The second electrode of the sixth transistor ST6 may be connected to the first electrode of the light emitting element ED and the first electrode of the seventh transistor ST7 through the fourth node N4. For example, the first electrode of the sixth transistor ST6 may be a source electrode, and the second electrode of the sixth transistor ST6 may be a drain electrode, but the present disclosure is not limited thereto.

[0126] When all of the fifth transistor ST5 , the first transistor ST1 , and the sixth transistor ST6 are turned on, the driving current Isd may be supplied to the light emitting element ED.

[0127] The seventh transistor ST7 may be turned on by the fourth gate signal of the fourth gate line GBL to electrically connect the second initialization voltage line VIL2 to the fourth node N4 which is the first electrode of the light emitting element ED. By turning on the seventh transistor ST7 based on the fourth gate signal, the first electrode of the light emitting element ED may be discharged to the second initialization voltage. The gate electrode of the seventh transistor ST7 may be connected to the fourth gate line GBL, the first electrode of the seventh transistor ST7 may be connected to the fourth node N4, and the second electrode of the seventh transistor ST7 may be connected to the second initialization voltage line VIL2. The first electrode of the seventh transistor ST7 may be connected to the first electrode of the light emitting element ED and the second electrode of the sixth transistor ST6 through the fourth node N4. For example, the first electrode of the seventh transistor ST7 may be a source electrode, and the second electrode of the seventh transistor ST7 may be a drain electrode, but the present disclosure is not limited thereto.

[0128] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include a silicon-based semiconductor region. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may include a semiconductor region made of low-temperature polysilicon (LTPS). The semiconductor region made of low-temperature polysilicon may have high electron mobility and excellent conduction characteristics. That is, since the display device 10 includes the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 having excellent conduction characteristics, a plurality of pixels SP may be driven in a stable and effective manner.

[0129] Each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may correspond to a p-type transistor. For example, each of the first transistor ST1, the second transistor ST2, the fifth transistor ST5, the sixth transistor ST6, and the seventh transistor ST7 may output a current flowing into its first electrode to its second electrode based on a gate low voltage applied to its gate electrode.

[0130] Each of the third transistor ST3 and the fourth transistor ST4 may include an oxide-based semiconductor region. For example, each of the third transistor ST3 and the fourth transistor ST4 may have a coplanar structure in which a gate electrode is disposed on the oxide-based semiconductor region. Transistors having a coplanar structure may have excellent leakage current characteristics and may perform low-frequency driving, thereby reducing power consumption. Accordingly, the display device 10 may include a third transistor ST3 and a fourth transistor ST4 having excellent leakage current characteristics, thereby preventing leakage current from flowing in the pixel SP and stably maintaining the voltage in the pixel SP.

[0131] Each of the third transistor ST3 and the fourth transistor ST4 may correspond to an n-type transistor. For example, each of the third transistor ST3 and the fourth transistor ST4 may output a current flowing through its first electrode to its second electrode based on a gate high voltage applied to its gate electrode.

[0132] The capacitor CST may be connected between the third node N3, which is the gate electrode of the first transistor ST1, and the driving voltage line VDDL. For example, a first capacitor electrode of the capacitor CST may be connected to the third node N3, and a second capacitor electrode of the capacitor CST may be connected to the driving voltage line VDDL, thereby maintaining a potential difference between the driving voltage line VDDL and the gate electrode of the first transistor ST1.

[0133] Figure 7 is a cross-sectional view illustrating a pixel of a display device according to an embodiment.

[0134] refer to Figure 7 The display unit DU may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a second gate layer GTL2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first through-hole layer VIA1, a second source metal layer SDL2, a second through-hole layer VIA2, a pixel defining layer PDL, a light emitting element ED, and an encapsulation layer TFEL.

[0135] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded, or rolled. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0136] The buffer layer BF may be disposed on the substrate SUB. For example, the buffer layer BF may include an inorganic layer capable of preventing air or moisture from penetrating. For example, the buffer layer BF may include a plurality of inorganic layers alternately stacked.

[0137] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include a silicon-based material. For example, the first active layer ACTL1 may be formed of low temperature polycrystalline silicon (LTPS). The first active layer ACTL1 may include a semiconductor region ACT1, a first electrode SE1, and a second electrode DE1 of the first transistor ST1 and a semiconductor region ACT2, a first electrode SE2, and a second electrode DE2 of the second transistor ST2.

[0138] The first gate insulating layer GI1 may be disposed on the first active layer ACTL1. The first gate insulating layer GI1 may insulate the first active layer ACTL1 from the first gate layer GTL1.

[0139] The first gate layer GTL1 may be disposed on the first gate insulating layer GI1. The first gate layer GTL1 may include a gate electrode GE1 of the first transistor ST1, a gate electrode GE2 of the second transistor ST2, and a first capacitor electrode CPE1. The gate electrode GE1 of the first transistor ST1 may be a portion of the first capacitor electrode CPE1, and the gate electrode GE2 of the second transistor ST2 may be a portion of the first gate line GWL.

[0140] The second gate insulating layer GI2 may be disposed on the first gate layer GTL1. The second gate insulating layer GI2 may insulate the first gate layer GTL1 from the second gate layer GTL2.

[0141] The second gate layer GTL2 may be disposed on the second gate insulating layer GI2. The second gate layer GTL2 may include a second capacitor electrode CPE2. The second capacitor electrode CPE2 may overlap the first capacitor electrode CPE1.

[0142] The first interlayer insulating layer ILD1 may be disposed on the second gate layer GTL2. The first interlayer insulating layer ILD1 may insulate the second gate layer GTL2 from the second active layer ACTL2.

[0143] The second active layer ACTL2 may be disposed on the first interlayer insulating layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include a third semiconductor region ACT3 of the third transistor ST3, a first electrode DE3, and a second electrode SE3.

[0144] The third gate insulating layer GI3 may be disposed on the second active layer ACTL2. The third gate insulating layer GI3 may insulate the second active layer ACTL2 from the third gate layer GTL3.

[0145] The third gate layer GTL3 may be disposed on the third gate insulating layer GI3. The third gate layer GTL3 may include a gate electrode GE3 of the third transistor ST3. The gate electrode GE3 of the third transistor ST3 is a portion of the second gate line GCL.

[0146] The second interlayer insulating layer ILD2 may be disposed on the third gate layer GTL3 . The second interlayer insulating layer ILD2 may insulate the third gate layer GTL3 from the first source metal layer SDL1 .

[0147] The first source metal layer SDL1 may be disposed on the second interlayer insulating layer ILD2. The first source metal layer SDL1 may include first to third connection electrodes CE1, CE2, and CE3. The first connection electrode CE1 may electrically connect the data line DL with the first electrode SE2 of the second transistor ST2. The second connection electrode CE2 may electrically connect the first capacitor electrode CPE1 with the second electrode SE3 of the third transistor ST3. The third connection electrode CE3 may electrically connect the first electrode DE3 of the third transistor ST3 with the second electrode DE1 of the first transistor ST1.

[0148] The first via layer VIA1 may be disposed on the first source metal layer SDL1. The first via layer VIA1 may insulate the first source metal layer SDL1 from the second source metal layer SDL2. A top surface of the first via layer VIA1 may be flat. The first via layer VIA1 may include an organic insulating material such as polyimide (PI).

[0149] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include the data line DL.

[0150] The second via layer VIA2 may be disposed on the second source metal layer SDL2. The second via layer VIA2 may insulate the second source metal layer SDL2 from the pixel electrode AE. The top surface of the second via layer VIA2 may be flat. The second via layer VIA2 may include an organic insulating material such as polyimide (PI).

[0151] The pixel defining layer PDL may be disposed on the second via layer VIA2. The pixel defining layer PDL may define a plurality of emission areas EA. The pixel defining layer PDL may include an organic insulating material such as polyimide (PI).

[0152] The light emitting element ED may include a pixel electrode AE, a hole transport layer HTL, a light emitting layer EL, an electron transport layer ETL, and a common electrode CAT. The pixel electrode AE ​​may be disposed on the second through hole layer VIA2. The pixel electrode AE ​​may overlap a corresponding one of a plurality of emission areas EA defined by the pixel defining layer PDL. The pixel electrode AE ​​may receive a driving current from a pixel circuit of the pixel SP.

[0153] The hole transport layer HTL may be disposed on the pixel electrode AE ​​in the emission area EA and may be disposed on the pixel defining layer PDL in the non-emission area NEA. The hole transport layer HTL may not be divided for each pixel SP but may be implemented as a common layer for the fingerprint sensor OPD and a plurality of pixels SP.

[0154] The light emitting layer EL may be disposed on the hole transport layer HTL in the emission area EA. For example, the light emitting layer EL may be an organic light emitting layer made of an organic material, but is not limited thereto.

[0155] The electron transport layer ETL may be disposed on the light emitting layer EL in the emission area EA, and may be disposed on the hole transport layer HTL in the non-emission area NEA. The electron transport layer ETL may not be divided for each pixel SP, but may be implemented as a common layer for all pixels SP and the fingerprint sensor OPD.

[0156] The common electrode CAT may be disposed on the electron transport layer ETL. For example, the common electrode CAT may be implemented in the form of an electrode shared by all pixels SP rather than being separated for each of the plurality of pixels SP. The common electrode CAT may be a transparent electrode and may transmit light. The common electrode CAT may be electrically connected to a bias voltage line VBL and may receive a bias voltage, a low potential voltage, a common voltage, or a cathode voltage.

[0157] When an organic light-emitting layer is used as the light-emitting layer EL, the pixel circuit of the pixel SP applies a predetermined voltage to the pixel electrode AE, and if the common electrode CAT receives a common voltage or a cathode voltage, holes and electrons can move to the light-emitting layer EL through the hole transport layer HTL and the electron transport layer ETL, respectively, and recombine to generate light emitted by the light-emitting layer EL.

[0158] The encapsulation layer TFEL may be disposed on the common electrode CAT to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one organic layer to protect the plurality of light emitting elements ED from foreign matter such as dust.

[0159] Figure 8 is a circuit diagram illustrating a fingerprint sensor of a display device according to one embodiment, and Fig. 9 is supplied to Figure 8 Graph showing the waveform of the signal of the fingerprint sensor shown in FIG. Fig.10 The fingerprint sensor is shown in the figure Fig. 9 A circuit diagram of the operation during the first period of time, Fig.11 The fingerprint sensor is shown in the figure Fig. 9 A circuit diagram of the operation during the second period, and Fig.12 The fingerprint sensor is shown in the figure Fig. 9 A circuit diagram of the operation during the third period of time. Fig.13 It is shown in Figure 8 A graph showing the magnitude of the leakage current flowing in the fourth sensor transistor.

[0160] refer to Figures 8 to 13 , the fingerprint sensor OPD may be connected to the first gate line GWL, the reset voltage line VRL, the second initialization voltage line VIL2, the bias voltage line VBL, and the readout line ROL.

[0161] The fingerprint sensor OPD may include first to fourth sensor transistors PT1 , PT2 , PT3 , and PT4 .

[0162] The first sensor transistor PT1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first sensor transistor PT1 may be connected to the sensor node NS, the first electrode of the first sensor transistor PT1 may be connected to the third sensor transistor PT3, and the second electrode of the first sensor transistor PT1 may be connected to the second initialization voltage line VIL2. The first sensor transistor PT1 may control a source-drain current Isd (hereinafter referred to as “sensing current”) according to the voltage of the sensor node NS. The sensing current Isd flowing through the channel of the first sensor transistor PT1 may be proportional to the square of the difference between the threshold voltage Vth of the first sensor transistor PT1 and the voltage Vsg between the source electrode and the gate electrode (Isd=k'×(Vsg–Vth) 2 ), where k' represents a proportionality coefficient determined by the structure and physical characteristics of the first sensor transistor PT1, Vsg represents a source-gate voltage of the first sensor transistor PT1, and Vth represents a threshold voltage of the first sensor transistor PT1. The first electrode of the first sensor transistor PT1 may be a source electrode, and the second electrode of the first sensor transistor PT1 may be a drain electrode, but the present disclosure is not limited thereto.

[0163] The second sensor transistor PT2 may be turned on by the reset signal GR of the reset signal line GRL to electrically connect the sensor node NS to the reset voltage line VRL. The gate electrode of the second sensor transistor PT2 may be connected to the reset signal line GRL, the first electrode of the second sensor transistor PT2 may be connected to the sensor node NS, and the second electrode of the second sensor transistor PT2 may be connected to the reset voltage line VRL. The second sensor transistor PT2 may receive the reset voltage VR from the reset voltage line VRL. The first electrode of the second sensor transistor PT2 may be connected to the second electrode of the fourth sensor transistor PT4 and the gate electrode of the first sensor transistor PT1 through the sensor node NS. The first electrode of the second sensor transistor PT2 may be a drain electrode, and the second electrode of the second sensor transistor PT2 may be a source electrode, but the present disclosure is not limited thereto.

[0164] The third sensor transistor PT3 may be turned on by the first gate signal GW of the first gate line GWL to electrically connect the first electrode of the first sensor transistor PT1 to the readout line ROL. The gate electrode of the third sensor transistor PT3 may be connected to the first gate line GWL, the first electrode of the third sensor transistor PT3 may be connected to the readout line ROL, and the second electrode of the third sensor transistor PT3 may be connected to the first electrode of the first sensor transistor PT1. The first electrode of the third sensor transistor PT3 may be a source electrode, and the second electrode of the third sensor transistor PT3 may be a drain electrode, but the present disclosure is not limited thereto.

[0165] The fourth sensor transistor PT4 may be connected between a bias voltage line VBL and a sensor node NS. A gate electrode and a first electrode of the fourth sensor transistor PT4 may be connected to the bias voltage line VBL, and a second electrode of the fourth sensor transistor PT4 may be connected to the sensor node NS. The first electrode of the fourth sensor transistor PT4 may be a source electrode, and the second electrode of the fourth sensor transistor PT4 may be a drain electrode, but the present disclosure is not limited thereto. Since the gate electrode and the first electrode of the fourth sensor transistor PT4 receive a bias voltage from the bias voltage line VBL, a gate-source voltage Vgs of the fourth sensor transistor PT4 may be zero. If the fourth sensor transistor PT4 does not receive light, the fourth sensor transistor PT4 may be turned off. Fig.13 In the embodiment, when the fourth sensor transistor PT4 is turned off, a small amount of leakage current may flow, but it will not affect the operation of the fingerprint sensor OPD.

[0166] The fourth sensor transistor PT4 may be a phototransistor. The fourth sensor transistor PT4 may identify the pattern of the user's fingerprint based on the light reflected from the user's fingerprint. When the user's fingerprint touches the display panel 100, the fourth sensor transistor PT4 may receive light reflected by the ridge or valley of the fingerprint. The light output from the light emitting element ED may be reflected by the ridge or valley of the fingerprint, and the reflected light may reach the fourth sensor transistor PT4. The fourth sensor transistor PT4 may convert light energy into an electrical signal (current or voltage) formed between its first electrode and the second electrode, and the converted electrical signal is a reverse bias current that may flow from the bias voltage line VBL to the sensor node NS. For example, when the fourth sensor transistor PT4 receives light and an electric field is formed between the first electrode and the second electrode of the fourth sensor transistor PT4, a current may flow through the fourth sensor transistor PT4 in proportion to the amount of light, and the voltage of the sensor node NS may increase. Accordingly, when the fourth sensor transistor PT4 receives light, the voltage of the sensor node NS may increase, and the magnitude of the sensing current (or source-drain current) of the first sensor transistor PT1 may decrease. The sensing current of the first sensor transistor PT1 may be applied to the display driver 200 as a sensing signal through the third sensor transistor PT3 and the readout line ROL.

[0167] Each of the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 may include a silicon-based semiconductor region. The semiconductor region of each of the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 may be disposed at Figure 7In the first active layer ACTL1. For example, each of the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 may include a semiconductor region formed of low-temperature polycrystalline silicon (LTPS). The semiconductor region made of low-temperature polycrystalline silicon may have high electron mobility and excellent conduction characteristics. Accordingly, since the display device 10 includes the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 having excellent conduction characteristics, multiple fingerprint sensors OPD can operate stably and effectively.

[0168] Each of the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 may correspond to a p-type transistor. For example, each of the first sensor transistor PT1, the third sensor transistor PT3, and the fourth sensor transistor PT4 may output a current flowing through its first electrode to its second electrode based on a gate low voltage applied to its gate electrode.

[0169] The second sensor transistor PT2 may include an oxide-based semiconductor region. For example, the second sensor transistor PT2 may have a coplanar structure in which a gate electrode is disposed on the oxide-based semiconductor region. A transistor having a coplanar structure may have excellent leakage current characteristics and may perform low-frequency driving, thereby reducing power consumption. Accordingly, the display device 10 may include a second sensor transistor PT2 having excellent leakage current characteristics, thereby preventing leakage current from flowing in the fingerprint sensor OPD and stably maintaining the voltage of the sensor node NS.

[0170] The second sensor transistor PT2 may correspond to an n-type transistor. For example, the second sensor transistor PT2 may output a current flowing through its first electrode to its second electrode based on a gate high voltage applied to its gate electrode.

[0171] refer to Fig. 9 Combined with Figures 10 to 12 , the fingerprint sensor OPD may be driven at a predetermined frequency, and one frame period may include first to third periods t1 to t3.

[0172] exist Fig.10 In the embodiment of the present invention, the second sensor transistor PT2 may receive a high-level reset signal GR during the first period t1. The second sensor transistor PT2 may be turned on based on the high-level reset signal GR and may discharge the sensor node NS to the reset voltage VR. The reset voltage VR of the reset voltage line VRL may be smaller than the bias voltage of the bias voltage line VBL.

[0173] exist Fig.11In the embodiment, the fourth sensor transistor PT4 may receive the reflected light during the second period t2 and supply the leakage current to the sensor node NS. As the intensity of the reflected light becomes stronger, the magnitude of the leakage current may increase. Fig.13 In the embodiment, the fourth sensor transistor PT4 may receive light reflected from the valley of the fingerprint and supply a relatively large leakage current to the sensor node NS. The fourth sensor transistor PT4 may receive light reflected from the ridge of the fingerprint and supply a relatively small leakage current to the sensor node NS.

[0174] exist Fig.12 In the third period t3, the third sensor transistor PT3 may receive the first gate signal GW of the low level during the third period t3. The third sensor transistor PT3 may be turned on based on the first gate signal GW of the low level, and the sensing current of the first sensor transistor PT1 may be applied to the display driver 200 through the third sensor transistor PT3 and the readout line ROL. Accordingly, the voltage of the sensor node NS may change depending on the magnitude of the leakage current, and sensing signals of different magnitudes corresponding to the valleys and ridges of the fingerprint may be applied to the display driver 200.

[0175] Since the gate electrode and the first electrode of the fourth sensor transistor PT4 are connected to the bias voltage line VBL, the fourth sensor transistor PT4 may be turned off when the fourth sensor transistor PT4 does not receive reflected light, and the fourth sensor transistor PT4 may supply leakage current to the sensor node NS when the fourth sensor transistor PT4 receives reflected light. Accordingly, the fourth sensor transistor PT4 may minimize the flowing leakage current to easily distinguish the voltage of the sensor node NS and improve the sensitivity of the fingerprint sensor OPD.

[0176] Fig.14 is a circuit diagram illustrating a fingerprint sensor of a display device according to another embodiment. Fig.14 Fingerprint sensor with Figure 8 The difference of the fingerprint sensor is the configuration of the fourth sensor transistor PT4. Fig.14 The parts of the circuit diagram that are the same as the configuration described above.

[0177] refer to Fig.14 , the fingerprint sensor OPD may be connected to a first gate line GWL, a reset signal line GRL, a reset voltage line VRL, a second initialization voltage line VIL2, a bias voltage line VBL, a leakage voltage line VKL, and a readout line ROL.

[0178] The fingerprint sensor OPD may include first to fourth sensor transistors PT1 , PT2 , PT3 , and PT4 .

[0179] A gate electrode of the first sensor transistor PT1 may be connected to the sensor node NS, a first electrode of the first sensor transistor PT1 may be connected to the third sensor transistor PT3, and a second electrode of the first sensor transistor PT1 may be connected to the second initialization voltage line VIL2. The first sensor transistor PT1 may control a source-drain current Isd (hereinafter referred to as a "sensing current") based on a voltage of the sensor node NS.

[0180] The second sensor transistor PT2 may be turned on by a reset signal of the reset signal line GRL to electrically connect the sensor node NS to the reset voltage line VRL. A gate electrode of the second sensor transistor PT2 may be connected to the reset signal line GRL, a first electrode of the second sensor transistor PT2 may be connected to the sensor node NS, and a second electrode of the second sensor transistor PT2 may be connected to the reset voltage line VRL.

[0181] The third sensor transistor PT3 may be turned on by the first gate signal of the first gate line GWL to electrically connect the first electrode of the first sensor transistor PT1 with the readout line ROL. A gate electrode of the third sensor transistor PT3 may be connected to the first gate line GWL, a first electrode of the third sensor transistor PT3 may be connected to the readout line ROL, and a second electrode of the third sensor transistor PT3 may be connected to the first electrode of the first sensor transistor PT1.

[0182] The fourth sensor transistor PT4 may be connected between the bias voltage line VBL and the sensor node NS. A gate electrode of the fourth sensor transistor PT4 may be connected to the leakage voltage line VKL, a first electrode of the fourth sensor transistor PT4 may be connected to the bias voltage line VBL, and a second electrode of the fourth sensor transistor PT4 may be connected to the sensor node NS. The first electrode of the fourth sensor transistor PT4 may be a source electrode, and the second electrode of the fourth sensor transistor PT4 may be a drain electrode, but the present disclosure is not limited thereto.

[0183] The magnitude of the leakage voltage of the leakage voltage line VKL may be greater than the magnitude of the bias voltage of the bias voltage line VBL, and the gate-source voltage Vgs of the fourth sensor transistor PT4 may be greater than zero. Fig.13 , Fig.14 The gate-source voltage Vgs of the fourth sensor transistor PT4 may be greater than Figure 8 The gate-source voltage Vgs of the fourth sensor transistor PT4 is . Fig.14 The fingerprint sensor OPD can have a large difference in leakage current corresponding to the valleys and ridges of the fingerprint, and can easily distinguish the voltage of the sensor node NS to improve the sensitivity of the fingerprint sensor OPD.

[0184] Fig.15 : is a cross-sectional view illustrating a portion of a fingerprint sensor in a display device according to an embodiment. The same configuration as that described above will be briefly described, or the description thereof will be omitted.

[0185] refer to Fig.15 The display unit DU may include a substrate SUB, a buffer layer BF, a first active layer ACTL1, a first gate insulating layer GI1, a first gate layer GTL1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a second active layer ACTL2, a third gate insulating layer GI3, a third gate layer GTL3, a second interlayer insulating layer ILD2, a first source metal layer SDL1, a first through-hole layer VIA1, a second source metal layer SDL2, a second through-hole layer VIA2, a pixel defining layer PDL, a shielding electrode SHD, and an encapsulation layer TFEL.

[0186] The first active layer ACTL1 may be disposed on the buffer layer BF. The first active layer ACTL1 may include a silicon-based material. For example, the first active layer ACTL1 may be made of low temperature polysilicon (LTPS). The first active layer ACTL1 may include a semiconductor region PACT4 of the fourth sensor transistor PT4, a first electrode PSE4, and a second electrode PDE4.

[0187] The first gate layer GTL1 may be disposed on the first gate insulating layer GI1. The first gate layer GTL1 may include a gate electrode PGE4 of the fourth sensor transistor PT4.

[0188] The second active layer ACTL2 may be disposed on the first interlayer insulating layer ILD1. The second active layer ACTL2 may include an oxide-based material. The second active layer ACTL2 may include a semiconductor region PACT2 of the second sensor transistor PT2, a first electrode PDE2, and a second electrode PSE2.

[0189] The third gate layer GTL3 may be disposed on the third gate insulating layer GI3. The third gate layer GTL3 may include a gate electrode PGE2 of the second sensor transistor PT2. The gate electrode PGE2 of the second sensor transistor PT2 may be a portion of the reset signal line GRL.

[0190] The first source metal layer SDL1 may be disposed on the second interlayer insulating layer ILD2. The first source metal layer SDL1 may include first to third sensor connection electrodes PCE1, PCE2, and PCE3. The first sensor connection electrode PCE1 may electrically connect the reset voltage line VRL with the first electrode PDE2 of the second sensor transistor PT2. The second sensor connection electrode PCE2 may electrically connect the second electrode PSE2 of the second sensor transistor PT2 with the second electrode PDE4 of the fourth sensor transistor PT4. The third sensor connection electrode PCE3 may electrically connect the gate electrode PGE4 and the first electrode PSE4 of the fourth sensor transistor PT4 with the bias voltage line VBL.

[0191] The second source metal layer SDL2 may be disposed on the first via layer VIA1. The second source metal layer SDL2 may include a reset voltage line VRL and a bias voltage line VBL.

[0192] The shielding electrode SHD may be disposed on the second through hole layer VIA2 and be located at the same layer as the pixel electrode AE ​​of the light emitting element ED. The shielding electrode SHD may overlap the first to third sensor transistors PT1, PT2, and PT3, and may not overlap the fourth sensor transistor PT4. In some embodiments, the shielding electrode SHD may cover a portion of the substrate SUB except for a portion overlapping the fourth sensor transistor PT4.

[0193] The hole transport layer HTL may be disposed on the shielding electrode SHD. The hole transport layer HTL may not be divided for each pixel SP but may be implemented as a common layer for all pixels SP and the fingerprint sensor OPD.

[0194] The electron transport layer ETL may be disposed on the hole transport layer HTL. The electron transport layer ETL may not be divided for each pixel SP but may be implemented as a common layer for all pixels SP and the fingerprint sensor OPD.

[0195] The common electrode CAT may be disposed on the electron transport layer ETL. For example, the common electrode CAT may not be divided for each of the plurality of pixels SP, but may be implemented in the form of an electrode shared by all pixels SP. The common electrode CAT may be a transparent electrode and may transmit light.

[0196] The fingerprint sensor OPD may include a hole transport layer HTL and an electron transport layer ETL, each of which is implemented as a common layer of all pixels SP and the fingerprint sensor OPD, but may include a fourth sensor transistor PT4 which is a phototransistor instead of a separate light receiving element arranged on the same layer, thereby minimizing the leakage current flowing through the fingerprint sensor OPD and improving the sensitivity of the fingerprint sensor OPD even in a high-resolution structure having the fingerprint sensor OPD and dense pixels SP.

[0197] Fig.16 is a plan view illustrating one example of a fourth sensor transistor of a fingerprint sensor in a display device according to one embodiment, and Fig.17 is along Fig.16 The same configuration as that described above will be briefly described, or the description thereof will be omitted.

[0198] refer to Fig.16 and Fig.17 , the fourth sensor transistor PT4 may be a phototransistor. The fourth sensor transistor PT4 may identify the pattern of the user's fingerprint based on the light RFL (also referred to as reflected light) reflected from the user's fingerprint. When the user's fingerprint touches the display panel 100, the fourth sensor transistor PT4 may receive the light RFL reflected by the ridges or valleys of the fingerprint. The light output from the light emitting element ED may be reflected by the ridges or valleys of the fingerprint, and the reflected light RFL may reach the fourth sensor transistor PT4. The fourth sensor transistor PT4 may convert light energy into an electrical signal (current or voltage) formed between its first electrode PSE4 and the second electrode PDE4, and the converted electrical signal is a reverse bias current that may flow from the bias voltage line VBL to the sensor node NS. For example, when the fourth sensor transistor PT4 receives light and an electric field is formed between the first electrode PSE4 and the second electrode PDE4 of the fourth sensor transistor PT4, a current may flow through the fourth sensor transistor PT4 in proportion to the amount of light, and the voltage of the sensor node NS may increase. Accordingly, when the fourth sensor transistor PT4 receives light, the voltage of the sensor node NS may increase, and the magnitude of the sensing current (or source-drain current) of the first sensor transistor PT1 may decrease. The sensing current of the first sensor transistor PT1 may be applied to the display driver 200 as a sensing signal through the third sensor transistor PT3 and the readout line ROL.

[0199] Fig.18 is a plan view illustrating another example of a fourth sensor transistor of a fingerprint sensor in a display device according to one embodiment, and Fig.19 is along Fig.18 A cross-sectional view taken along line II-II'.

[0200] refer to Fig.18 and Fig.19 ,and Fig.16 and Fig.17 Unlike the embodiment of the present invention, the gate electrode PGE4 of the fourth sensor transistor PT4 may include a hole. A portion of the semiconductor region PACT4 of the fourth sensor transistor PT4 may not overlap with the gate electrode PGE4. The gate electrode PGE4 of the fourth sensor transistor PT4 may expose a portion of the semiconductor region PACT4 to the reflected light RFL. Fig.18 and Fig.19 The semiconductor region PACT4 of the fourth sensor transistor PT4 can be Fig.16 and Fig.17 The semiconductor region PACT4 of the fourth sensor transistor PT4 receives more reflected light RFL. Accordingly, Fig.18 and Fig.19 The amount of leakage current of the fourth sensor transistor PT4 may increase, and the difference in leakage current corresponding to the valley and ridge of the fingerprint may be large. The fingerprint sensor OPD may easily distinguish the voltage of the sensor node NS to improve the sensitivity of the fingerprint sensor OPD.

[0201] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A fingerprint sensor, comprising: a readout line disposed on the substrate and extending in a first direction; a first sensor transistor that controls a sense current based on a voltage at a sensor node; a second sensor transistor that supplies a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting the first electrode of the first sensor transistor to the readout line based on a gate signal; as well as A fourth sensor transistor includes a gate electrode connected to a bias voltage line, a first electrode connected to the bias voltage line, and a second electrode connected to the sensor node.

2. The fingerprint sensor according to claim 1, in, the second sensor transistor supplies the reset voltage to the sensor node during a first period, wherein the fourth sensor transistor supplies a leakage current to the sensor node during a second period after the first period, and The third sensor transistor is turned on during a third period after the second period.

3. The fingerprint sensor according to claim 1, comprising: a first active layer disposed on the substrate and including a semiconductor region of each of the first sensor transistor, the third sensor transistor, and the fourth sensor transistor; a first gate layer, disposed on the first active layer; a second gate layer, disposed on the first gate layer; a second active layer disposed on the second gate layer and including a semiconductor region of the second sensor transistor; a third gate layer, disposed on the second active layer; A first source metal layer, disposed on the third gate layer; as well as The second source metal layer is disposed on the first source metal layer.

4. The fingerprint sensor according to claim 3, further comprising: A shielding electrode is disposed on the second source metal layer to overlap with the second sensor transistor but not to overlap with the fourth sensor transistor.

5. The fingerprint sensor according to claim 4, further comprising: a hole transport layer disposed on the shielding electrode to overlap the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor; an electron transport layer disposed on the hole transport layer to overlap with the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor; as well as A common electrode is disposed on the electron transport layer to overlap with the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor.

6. The fingerprint sensor according to claim 1 or 2, wherein: The gate electrode of the fourth sensor transistor includes a hole exposing a portion of a semiconductor region of the fourth sensor transistor to reflected light.

7. A fingerprint sensor comprising: a readout line disposed on the substrate and extending in a first direction; a first sensor transistor that controls a sense current based on a voltage at a sensor node; a second sensor transistor that supplies a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting the first electrode of the first sensor transistor to the readout line based on a gate signal; as well as The fourth sensor transistor includes a gate electrode connected to the leakage voltage line to receive the leakage voltage, a first electrode connected to the bias voltage line to receive a bias voltage smaller than the leakage voltage, and a second electrode connected to the sensor node.

8. The fingerprint sensor according to claim 7, in, the second sensor transistor supplies the reset voltage to the sensor node during a first period, wherein the fourth sensor transistor supplies a leakage current to the sensor node during a second period after the first period, and The third sensor transistor is turned on during a third period after the second period.

9. The fingerprint sensor according to claim 7, comprising: a first active layer disposed on the substrate and including a semiconductor region of each of the first sensor transistor, the third sensor transistor, and the fourth sensor transistor; a first gate layer, disposed on the first active layer; a second gate layer, disposed on the first gate layer; a second active layer disposed on the second gate layer and including a semiconductor region of the second sensor transistor; a third gate layer, disposed on the second active layer; A first source metal layer, disposed on the third gate layer; as well as The second source metal layer is disposed on the first source metal layer.

10. The fingerprint sensor according to claim 9, further comprising: A shielding electrode is disposed on the second source metal layer to overlap with the second sensor transistor but not to overlap with the fourth sensor transistor.

11. The fingerprint sensor according to claim 10, further comprising: a hole transport layer disposed on the shielding electrode to overlap the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor; an electron transport layer disposed on the hole transport layer to overlap with the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor; as well as A common electrode is disposed on the electron transport layer to overlap with the first sensor transistor, the second sensor transistor, the third sensor transistor, and the fourth sensor transistor.

12. The fingerprint sensor according to claim 7 or 8, wherein: The gate electrode of the fourth sensor transistor includes a hole exposing a portion of a semiconductor region of the fourth sensor transistor to reflected light.

13. A display device, comprising: a pixel disposed in the emission region and comprising a light emitting element; as well as A fingerprint sensor, disposed in the sensor area, Wherein, the fingerprint sensor comprises: a readout line disposed on the substrate and extending in a first direction; a first sensor transistor that controls a sense current based on a voltage at a sensor node; a second sensor transistor that supplies a reset voltage to the sensor node based on a reset signal; a third sensor transistor electrically connecting the first electrode of the first sensor transistor to the readout line based on a first gate signal; and The fourth sensor transistor includes a gate electrode connected to the leakage voltage line to receive the leakage voltage, a first electrode connected to the bias voltage line to receive a bias voltage smaller than the leakage voltage, and a second electrode connected to the sensor node.

14. The display device according to claim 13, wherein: The pixels include: a first transistor, controlling a driving current flowing through the light emitting element; a second transistor supplying a data voltage to a first electrode of the first transistor based on the first gate signal; a third transistor electrically connecting the second electrode of the first transistor to the gate electrode of the first transistor based on a second gate signal; and The fourth transistor discharges the gate electrode of the first transistor to a first initialization voltage based on a third gate signal.

15. The display device according to claim 14, wherein: A semiconductor region of each of the first transistor and the second transistor includes a silicon-based material, and a semiconductor region of each of the third transistor and the fourth transistor includes an oxide-based material.

16. The display device according to claim 14, wherein: The pixel further comprises: a fifth transistor that supplies a driving voltage to the first electrode of the first transistor based on an emission signal; a sixth transistor electrically connecting the second electrode of the first transistor to the light emitting element based on the emission signal; and The seventh transistor discharges the first electrode of the light emitting element to a second initialization voltage based on the fourth gate signal.

17. The display device according to claim 13, comprising: a first active layer disposed on the substrate and including a semiconductor region of each of the first sensor transistor, the third sensor transistor, and the fourth sensor transistor; a first gate layer, disposed on the first active layer; a second gate layer, disposed on the first gate layer; a second active layer disposed on the second gate layer and including a semiconductor region of the second sensor transistor; a third gate layer, disposed on the second active layer; A first source metal layer, disposed on the third gate layer; as well as The second source metal layer is disposed on the first source metal layer.

18. The display device according to claim 17, wherein: The light emitting element comprises: A pixel electrode, disposed on the second source metal layer; a hole transport layer, disposed on the pixel electrode and implemented as a common layer of the emission region and the sensor region; A light-emitting layer, disposed on the hole transport layer; an electron transport layer disposed on the light emitting layer and implemented as a common layer of the emission region and the sensor region; and The common electrode is arranged on the electron transport layer.

19. The display device according to claim 18, wherein: The fingerprint sensor further comprises: A shielding electrode is disposed at the same layer as the pixel electrode to overlap with the second sensor transistor but not overlap with the fourth sensor transistor.

20. The display device according to any one of claims 13 to 16, wherein: The gate electrode of the fourth sensor transistor includes a hole exposing a portion of a semiconductor region of the fourth sensor transistor to reflected light.

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