Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a pixel circuit and a light emitting device. The pixel circuit comprises a first sub-circuit and a second sub-circuit, and the input end of a first data write-in module of the first sub-circuit is electrically connected with a first data line. The second end of the light-emitting device is electrically connected with the first signal line. The display panel further comprises a test module, and the test module comprises a first test module and a second test module. The first end of the first test module is electrically connected with the first data line. The first end of the second test module is electrically connected with the first test signal line. Wherein the second end of the first test module is electrically connected with the second end of the light-emitting device, and the second end of the second test module is electrically connected with the first end of the light-emitting device; or, the second end of the first test module is electrically connected with the first end of the light-emitting device, and the second end of the second test module is electrically connected with the first end of the light-emitting device. The circuit condition of the first data line can be detected on the premise that a light-emitting device is not arranged.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous advancement of display technology, integrated circuits in display panels are gradually developing towards precision and miniaturization. However, during the production process, some structures in the integrated circuits are often easily damaged, which in turn affects the display effect of the display panel. For example, during production, it is easy to cause some data signal lines electrically connected to the pixel circuit to be broken, thereby interfering with the driving effect of the pixel circuit on the light-emitting device and causing display abnormality.

[0003] In order to detect the damage of some data signal lines, the existing technology usually selects the signal line to be detected and the light-emitting device to form a loop, and judges the damage of the signal line to be detected based on the light emission of the light-emitting device. However, this detection method can only be performed when there is a light-emitting device (or after the light-emitting device is bonded), and the corresponding detection scenario is limited. Summary of the invention

[0004] In view of this, the present application provides a display panel and a display device to solve the above-mentioned problem of limited detection scenes.

[0005] In a first aspect, the present application provides a display panel, comprising a pixel circuit and a light-emitting device. The pixel circuit comprises a first subcircuit and a second subcircuit, wherein the output end of the first subcircuit is electrically connected to the control end of the control module of the second subcircuit; the first subcircuit comprises a first data writing module, wherein the input end of the first data writing module is electrically connected to the first data line. The first end of the light-emitting device is electrically connected to the output end of the second subcircuit, and the second end of the light-emitting device is electrically connected to the first signal line.

[0006] The display panel also includes a test module, and the test module includes a first test module and a second test module. The first end of the first test module is electrically connected to the first data line, and the control end of the first test module is electrically connected to the first control signal line. The first end of the second test module is electrically connected to the first test signal line, and the control end of the second test module is electrically connected to the second control signal line.

[0007] Wherein, the second end of the first test module is electrically connected to the second end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device; Alternatively, the second end of the first test module is electrically connected to the first end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device.

[0008] In a second aspect, the present application provides a display device, comprising the display panel provided in the first aspect.

[0009] The configuration of the present application helps to detect the line condition of the first data line without relying on the light-emitting device, and helps to enrich the applicable scenarios of the above detection method. Specifically, it is helpful to detect some data signal lines before the display panel is bonded with the light-emitting device, and helps to complete the repair of the faulty line before setting the light-emitting device, thereby increasing the probability of finished products and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 is an equivalent schematic diagram of a pixel circuit related to the present application; Figure 2 An equivalent circuit diagram of a pixel circuit provided in this application; Figure 3 An equivalent circuit diagram of a pixel circuit provided in this application; Figure 4 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Figure 5 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Figure 6 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Figure 7 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Figure 8 Statistical illustration of voltages transmitted by some signal lines in the first detection stage and the second detection stage respectively; Fig. 9 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Fig.10 An equivalent circuit diagram of a pixel circuit provided in this application; Fig.11 An equivalent circuit diagram of a pixel circuit provided in this application; Fig.12 An equivalent circuit diagram of a pixel circuit provided in this application; Fig.13 An equivalent circuit diagram of a pixel circuit provided in this application; Fig.14 A schematic top view of a partial structure of a display panel provided in the present application; Fig.15 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Fig.16 A schematic diagram of the magnitude relationship of voltages transmitted by some signal lines in a pixel circuit during a detection phase; Fig.17 A schematic diagram of a display device provided in the present application. DETAILED DESCRIPTION

[0012] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0014] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0015] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0016] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] Figure 1 is an equivalent schematic diagram of a pixel circuit related to the present application.

[0018] In the prior art, Figure 1As shown, the pixel circuit 01 can receive the data signal transmitted by the first data line L1, and the above data signal can participate in the process of the pixel circuit 01 generating the light-emitting driving current. In order to detect the line condition of the first data line L1, the prior art chooses to connect the first data line L1 to the first end of the light-emitting device 02 through the test transistor T0, so that when the test transistor T0 is turned on, the first data line L1, the light-emitting device 02 and the first signal line L0 form an electrically conductive loop. Among them, the second end of the light-emitting device 02 is electrically connected to the first signal line L0, and the first end of the light-emitting device 02 is electrically connected to the second end of the output module 120 of the pixel circuit 01. The corresponding detection method includes: when the output module 120 of the pixel circuit 01 is turned off, the first data line L1 is controlled to transmit the first type of voltage, the first signal line L0 is controlled to transmit the second type of voltage, and the test transistor T0 is turned on by adjusting the voltage signal transmitted by the control signal line S0. Among them, the above-mentioned first type voltage is different from the above-mentioned second type voltage in size, for example, the first type voltage is greater than the second type voltage or the first type voltage is less than the second type voltage; the voltage difference between the above-mentioned first type voltage and the above-mentioned second type voltage can drive the light-emitting device 02 to emit light.

[0019] If the light emitting device 02 does not emit light after the test transistor T0 is turned on, it means that there is a risk of a circuit breaker in the first data line L1.

[0020] However, the above-mentioned existing detection method is limited to the situation where the pixel circuit 01 is electrically connected to the light-emitting device 02. The above-mentioned existing detection method is not applicable when the display panel has not yet been bonded to the light-emitting device 02. This leads to limitations of the existing detection method in terms of detection scenarios.

[0021] The existing pixel circuit 01 includes a first driving transistor T11, a first voltage writing transistor T12, a first data writing transistor T13, a first regulating transistor T14, a first reset transistor T15, a first transmission transistor T16, a second reset transistor T17, a second regulating transistor T18, a first capacitor C1 and a second capacitor C2; in addition, the existing pixel circuit 01 also includes a second driving transistor T21, a second voltage writing transistor T22, a second data writing transistor T23, a third regulating transistor T24, a third reset transistor T25, a second transmission transistor T26, a fourth regulating transistor T27, a fifth regulating transistor T28, a first control transistor T29, a first output transistor T30 and a third capacitor C3. The existing pixel circuit 01 can also be electrically connected to a first data line L1, a second data line L2, a first voltage line X1, a second voltage line X2, a third voltage line X3, a first scan line S1, a second scan line S2, a third scan line S3, a first reset line F1, a fourth scan line S4, a second reset line F2, and a fifth scan line S5. Please refer to the connection method between the above transistors, capacitors and signal lines. Figure 1 To avoid redundant description, no further details will be given here.

[0022] Figure 2 An equivalent circuit diagram of a pixel circuit provided in this application, Figure 3 An equivalent circuit diagram of a pixel circuit provided in this application.

[0023] In view of the above problems, the present application provides a display panel, including a pixel circuit 01 and a light emitting device 02. Figure 2 and Figure 3 , the pixel circuit 01 includes a first subcircuit 011 and a second subcircuit 012, the first subcircuit 011 may be a pulse width modulation subcircuit, and the second subcircuit 012 may be an amplitude modulation subcircuit. The pixel circuit 01 may generate a light-emitting driving current with the participation of the first subcircuit 011 and the second subcircuit 012, the first subcircuit 011 may be used to adjust the pulse width of the current applied to the light-emitting device 02, and the second subcircuit 012 may be used to control the amplitude of the light-emitting driving current.

[0024] The output end of the first sub-circuit 011 is electrically connected to the control end of the control module 121 of the second sub-circuit 012, and the electrical signal output by the first sub-circuit 011 can be used to control the switching state of the control module 121, that is, the first sub-circuit 011 can be used to control the switching state of the first control transistor T29, thereby realizing the function of the first sub-circuit 011 to adjust the pulse width of the light-emitting drive current.

[0025] The first sub-circuit 011 includes a first data writing module 122, and the first data writing module 122 may include a first data writing transistor T13. The input end of the first data writing module 122 is electrically connected to the first data line L1. When the first data writing module 122 is turned on, the data voltage signal transmitted by the first data line L1 can be transmitted to the input end of the first driving transistor T11 through the first data writing transistor T13. After receiving the data voltage signal, the first driving transistor T11 can generate a control signal for controlling the switch of the control module 121.

[0026] The first end of the light emitting device 02 is electrically connected to the output end of the second sub-circuit 012 , and the second end of the light emitting device 02 is electrically connected to the first signal line L0 . The first signal line L0 can transmit a power supply voltage signal to the second end of the light emitting device 02 .

[0027] The display panel also includes a test module 03, combined with Figure 2 and Figure 3The test module 03 includes a first test module 031 and a second test module 032. The first end of the first test module 031 is electrically connected to the first data line L1, and the control end of the first test module 031 is electrically connected to the first control signal line K1. The first test module 031 may include a first test transistor T31, the first end of the first test transistor T31 is electrically connected to the first data line L1, and the control end of the first test transistor T31 is electrically connected to the first control signal line K1.

[0028] The first end of the second test module 032 is electrically connected to the first test signal line L3, and the control end of the second test module 032 is electrically connected to the second control signal line K2. The second test module 032 may include a second test transistor T32, a first end of the second test transistor T32 is electrically connected to the first test signal line L3, and a control end of the second test transistor T32 is electrically connected to the second control signal line K2.

[0029] Among them, Figure 2 As shown, the second end of the first test module 031 is electrically connected to the second end of the light emitting device 02, and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02; that is, the second end of the first test transistor T31 is electrically connected to the second end of the light emitting device 02, and the second end of the second test transistor T32 is electrically connected to the first end of the light emitting device 02. At this time, in the case where there is no light emitting device 02 (or the light emitting device 02 has not yet been bonded in the display panel), the first test module 031 can be controlled to turn on, and different voltages can be transmitted to the first data line L1 and the first signal line L0 respectively, and then a detection device (such as a multimeter) can be used to detect whether there is current in the first data line L1 and the first signal line L0, and then the line condition of the first data line L1 can be determined. For example, if there is no current in the first data line L1, there is a risk of a circuit breaker in the first data line L1.

[0030] Or, if Figure 3As shown, the second end of the first test module 031 is electrically connected to the first end of the light emitting device 02, and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02; that is, the second end of the first test transistor T31 is electrically connected to the first end of the light emitting device 02, and the second end of the second test transistor T32 is electrically connected to the first end of the light emitting device 02. At this time, in the case where there is no light emitting device 02 (or the light emitting device 02 has not been bonded in the display panel), the first test module 031 and the second test module 032 can be controlled to be turned on, and different voltages are transmitted to the first data line L1 and the first test signal line L3 respectively, and then a detection device (such as a multimeter) can be used to detect whether there is current in the first data line L1 and the first test signal line L3, and then the line conditions of the first data line L1 and the first test signal line L3 are determined. For example, if there is no current in the first data line L1 and the first test signal line L3, there is a risk of a circuit breaker in the first data line L1 and / or a risk of a circuit breaker in the first test signal line L3.

[0031] The configuration of the embodiment of the present application is helpful to detect the line condition of the first data line L1 without relying on the light-emitting device 02, and helps to enrich the applicable scenarios of the above detection method. Specifically, relying on the configuration of the embodiment, it is helpful to detect some data signal lines before the display panel is bonded with the light-emitting device 02, and it is helpful to complete the repair of the faulty line before setting the light-emitting device 02, thereby improving the probability of finished products and reducing the manufacturing cost.

[0032] Combination Figure 2 and Figure 3 , the connection relationship of each circuit structure in the first sub-circuit 011 is as follows: The input end of the first voltage writing transistor T12 is electrically connected to the first voltage line X1, the output end of the first voltage writing transistor T12 is electrically connected to the input end of the first driving transistor T11, and the control end of the first voltage writing transistor T12 is electrically connected to the third scanning line S3. The first voltage line X1 can transmit the first power supply voltage to the first sub-circuit 011. The input end of the first data writing transistor T13 is electrically connected to the first data line L1, the output end of the first data writing transistor T13 is electrically connected to the input end of the first driving transistor T11, and the control end of the first data writing transistor T13 is electrically connected to the second scanning line S2. The input end of the first regulating transistor T14 is electrically connected to the output end of the first driving transistor T11, the output end of the first regulating transistor T14 is electrically connected to the control end of the first driving transistor T11, and the control end of the first regulating transistor T14 is electrically connected to the second scanning line S2. The input end and the control end of the first reset transistor T15 are both electrically connected to the first reset line F1, and the output end of the first reset transistor T15 is electrically connected to the control end of the first driving transistor T11. The first plate of the first capacitor C1 is electrically connected to the control end of the first driving transistor T11, and the second plate of the first capacitor C1 is electrically connected to the fourth scan line S4. The input end of the first transmission transistor T16 is electrically connected to the output end of the first driving transistor T11, the output end of the first transmission transistor T16 is electrically connected to the control end of the first control transistor T29, and the control end of the first transmission transistor T16 is electrically connected to the third scan line S3. The input end of the second reset transistor T17 is electrically connected to the second reset line F2, the output end of the second reset transistor T17 is electrically connected to the control end of the first control transistor T29, and the control end of the second reset transistor T17 is electrically connected to the fifth scan line S5. The first plate of the second capacitor C2 is electrically connected to the second reset line F2, and the second plate of the second capacitor C2 is electrically connected to the control end of the first control transistor T29. The input end of the second regulating transistor T18 is electrically connected to the third voltage line X3, the output end of the second regulating transistor T18 is electrically connected to the second plate of the first capacitor C1, and the control end of the second regulating transistor T18 is electrically connected to the second scan line S3.

[0033] Combination Figure 2 and Figure 3 , the connection relationship of each circuit structure in the second sub-circuit 012 is as follows: The input end of the second voltage writing transistor T22 is electrically connected to the second voltage line X2, the output end of the second voltage writing transistor T22 is electrically connected to the input end of the second driving transistor T21, and the control end of the second voltage writing transistor T22 is electrically connected to the third scanning line S3. The second voltage line X2 can transmit the second power supply voltage to the second sub-circuit 012. The input end of the second data writing transistor T23 is electrically connected to the second data line L2, the output end of the second data writing transistor T23 is electrically connected to the input end of the second driving transistor T21, and the control end of the second data writing transistor T23 is electrically connected to the second scanning line S2. The input end of the third regulating transistor T24 is electrically connected to the output end of the second driving transistor T21, the output end of the third regulating transistor T24 is electrically connected to the control end of the second driving transistor T21, and the control end of the third regulating transistor T24 is electrically connected to the second scanning line S2. The input end of the third reset transistor T25 is electrically connected to the first reset line F1, and the output end and control end of the third reset transistor T25 are both electrically connected to the control end of the second driving transistor T21. The input end of the fourth regulating transistor T27 and the input end of the fifth regulating transistor T28 are both electrically connected to the second voltage line X2, the output end of the fourth regulating transistor T27 and the output end of the fifth regulating transistor T28 are both electrically connected to the input end of the second transmission transistor T26, the control end of the fourth regulating transistor T27 is electrically connected to the second scan line S2, and the control end of the fifth regulating transistor T28 is electrically connected to the first reset line F1. The output end of the second transmission transistor T26 is electrically connected to the input end of the second driving transistor T21, and the control end of the second transmission transistor T26 is electrically connected to the third scan line S3. The input end of the first control transistor T29 is electrically connected to the output end of the second driving transistor T21, and the output end of the first control transistor T29 is electrically connected to the input end of the first output transistor T30. The output end of the first output transistor T30 is electrically connected to the first end of the light emitting device 02, and the control end of the first output transistor T30 is electrically connected to the first scan line S1.

[0034] The transistors in the pixel circuit 01 can be P-type transistors or N-type transistors, which are not limited here. For the convenience of description, the transistors in the equivalent circuit diagrams given in this specification are all P-type transistors.

[0035] Figure 4 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Figure 4 , the magnitude relationship between the voltages transmitted by the first data line, the first signal line and the first control signal line in the first detection phase is shown, and the ordinate V in the figure represents the magnitude of the voltage, and the abscissa T represents the time.

[0036] In one embodiment of the present application, Figure 2As shown, the second end of the first test module 031 is electrically connected to the second end of the light emitting device 02 , and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02 .

[0037] Combination Figure 2 and Figure 4 , in the first detection stage t1, the first test module 031 is turned on, the first data line L1 transmits the first voltage V1, the first signal line L0 transmits the second voltage V2, V1≠V2. The second voltage V2 may be a power supply voltage. The first test transistor T31 in the first test module 031 may be a P-type transistor, then in the first detection stage t1, the first control signal line K1 may transmit a low-level signal, at which time, the voltage Vc1 transmitted by the first control signal line K1 may be less than the first voltage V1 and the second voltage V2.

[0038] In the embodiment of the present application, in the first detection stage t1, the first data line L1 and the first signal line L0 can be electrically connected in theory. When V1≠V2, the first data line L1 and the first signal line L0 can be detected using a detection tool (such as a multimeter). If no current is detected in the first data line L1 and the first signal line L0, it proves that there is a circuit breakage fault in the loop formed by the first data line L1 and the first signal line L0. At this time, there is a risk of circuit breakage on the first data line L1. Therefore, the setting method of this embodiment helps to detect the line condition of the first data line L1 without setting the light-emitting device 02 (or the light-emitting device 02 is not bonded in the display panel).

[0039] In one embodiment of the present application, Figure 4 As shown, V1>V2. In this embodiment, when V1>V2, if there is no circuit breakage fault, there may be current transmitted from the first data line L1 to the first signal line L0. When there is a circuit breakage fault, a detection tool may be used to detect the potential of a certain point on the first data line L1. If the potential of the point is equal to V2, it is proved that there is no circuit breakage on the portion of the first data line L1 between the point and the first signal line L0.

[0040] Figure 5 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Figure 5 , the magnitude relationship between the voltages transmitted by the first data line, the first signal line and the first control signal line in the first detection phase is shown, and the ordinate V in the figure represents the magnitude of the voltage, and the abscissa T represents the time.

[0041] In one embodiment of the present application, Figure 5As shown, V1<V2, at this time, the voltage Vc1 transmitted by the first control signal line K1 can be less than the first voltage V1 and the second voltage V2. In this embodiment, when V1<V2, if there is no circuit breakage fault, there can be a current transmitted from the first signal line L0 to the first data line L1. When there is a circuit breakage fault, a detection tool can be used to detect the potential of a certain point on the first data line L1. If the potential of the point is equal to V1, it proves that the circuit breakage position is located on the part of the first data line L1 between the point and the first signal line L0 or on the first signal line L0.

[0042] In one embodiment of the present application, Figure 2 As shown, the second sub-circuit 012 also includes an output module 120, the output end of the output module 120 is electrically connected to the first end of the light-emitting device 02, the control end of the output module 120 is electrically connected to the output control signal line K0, and the output module 120 may include the above-mentioned first output transistor T30, wherein the output control signal line K0 and the first scan line S1 may be the same signal line.

[0043] Figure 6 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Figure 6 , the magnitude relationship between the voltages transmitted by the first data line, the first signal line and the output control signal line in the first detection phase is shown, and the ordinate V in the figure represents the magnitude of the voltage, and the abscissa T represents the time.

[0044] Among them, combined Figure 2 and Figure 6 In the first detection stage t1, the output control signal line K0 transmits a third voltage V3, V3>V1.

[0045] In the embodiment of the present application, V3>V1 can be understood as the output control signal line K0 transmitting a high-level voltage signal in the first detection stage t1. Since the first output transistor T30 can be a P-type transistor, the output module 120 can be in a turned-off state in the first detection stage t1. In addition, considering that V1>V2, the third voltage V3 is larger than the first voltage V1 and the second voltage V2, which helps to increase the degree of turn-off of the output module 120 and prevent the output module 120 from outputting an electrical signal and interfering with the detection process.

[0046] Figure 7 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Figure 7 2 shows the magnitude relationship between the voltages transmitted by the first data line, the first signal line and the first test signal line respectively.

[0047] In one embodiment of the present application, Figure 2 and Figure 7 , in the second detection stage t2, the first test module 031 and the second test module 032 are both turned on. The first test transistor T31 and the second test transistor T32 can both be P-type transistors, and in the second detection stage t2, the first control signal line K1 and the second control signal line K2 can both transmit low-level voltage signals. The second detection stage t2 can occur after the first detection stage t1.

[0048] The first signal line L0 transmits a second voltage V2, the first data line L1 transmits a fourth voltage V4, the first test signal line L3 transmits a fifth voltage V5, V2≠V5 and V4≠V5.

[0049] In the embodiment of the present application, the line condition of the first data line L1 can be detected in the first detection stage t1, and the line condition of the first test signal line L3 can be detected in the second detection stage t2. When the light-emitting device 02 is present, in the second detection stage t2, since V2≠V5, if the light-emitting device 02 does not emit light, there is a risk of a short circuit on the first test signal line L3. When the light-emitting device 02 is not present, in the second detection stage t2, since V4≠V5, if a current is detected in the first test signal line L3, it is proved that there is a risk of a short circuit between the first test signal line L3 and the first data line L1.

[0050] In one possible implementation, Figure 7 As shown, in the first test stage t1, the voltage transmitted by the first test signal line L3 is the same as the voltage transmitted by the first data line L1.

[0051] In one embodiment of the present application, Figure 7 As shown, V5>V2 and V5>V4.

[0052] In the embodiment of the present application, in the presence of the light-emitting device 02, if the light-emitting device 02 emits light in the second test phase t2, it proves that there is no short circuit between the first test signal line L3, the light-emitting device 02 and the first signal line L0. Since V5>V2, a current can be transmitted from the first test signal line L3 to the first signal line L0.

[0053] If the light emitting device 02 does not emit light in the second test stage t2, it proves that there is a circuit breaker fault. At this time, the potential of the first end of the light emitting device 02 can be detected by a detection tool. Since V2 and V4 are both smaller than V5, if the potential of the first end of the light emitting device 02 is smaller than V5, it proves that the circuit breaker is located on the first test signal line L3.

[0054] In a possible implementation, V5>V2 and V5<V4 (the voltage magnitude relationship diagram corresponding to this situation is not provided in the specification). If the light emitting device 02 does not emit light in the second test stage t2, and it is detected that the potential of the second end of the light emitting device 02 is equal to V5, it is proved that the disconnection position is not on the first test signal line L3.

[0055] In a possible implementation, V5<V2 and V5>V4 (the voltage magnitude relationship diagram corresponding to this situation is not provided in the specification). If the light emitting device 02 does not emit light in the second test stage t2, and it is detected that the potential of the second end of the light emitting device 02 is equal to V5, it is proved that the disconnection position is not on the first test signal line L3.

[0056] In a possible implementation, V5<V2 and V5<V4 (the voltage magnitude relationship diagram corresponding to this situation is not provided in the specification). If the light emitting device 02 does not emit light in the second test stage t2, and it is detected that the potential of the second end of the light emitting device 02 is greater than V2 and V4, it is proved that the disconnection position is not on the first test signal line L3.

[0057] In one embodiment of the present application, Figure 7 As shown, V2=V4.

[0058] In the embodiment of the present application, since the first detection stage t1 can be a stage for detecting the line condition of the first data line L1, considering that the second detection stage t2 can be performed after the first detection stage t1 is completed, the second detection stage t2 can be regarded as a stage for detecting the line condition of the first test signal line L3. Therefore, in order to avoid interfering with the detection process of the first test signal line L3, V2=V4 can be set to prevent current from appearing between the first data line L1 and the first signal line L0.

[0059] In one embodiment of the present application, Figure 7 As shown, V5=V1.

[0060] In the embodiment of the present application, in order to meet the requirement of V5>V2 in the second detection stage t2, considering that V1>V2 in the first detection stage t1, the first voltage V1 can be directly transmitted to the first test signal line L3 in the second detection stage t2, thereby reducing the difficulty of power supply required in the detection stage.

[0061] Figure 8 Statistical illustration of voltages transmitted by some signal lines in the first detection stage and the second detection stage respectively.

[0062] Combination Figure 2 and Figure 8, the first test signal line L3 can transmit the first voltage V1 in both the first detection stage t1 and the second detection stage t2; the first data line L1 can transmit the first voltage V1 in the first detection stage t1 and can transmit the second voltage V2 in the second detection stage t2; the first signal line L0 can transmit the second voltage V2 in both the first detection stage t1 and the second detection stage t2; the output control signal line K0 can transmit the third voltage V3 in both the first detection stage t1 and the second detection stage t2. Among them, it can be satisfied that: V2=V4<V1=V5<V3.

[0063] In one embodiment of the present application, Figure 3 As shown, the second end of the first test module 031 is electrically connected to the first end of the light emitting device 02 , and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02 .

[0064] Fig. 9 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Fig. 9 The relationship between the voltages transmitted by the first data line and the first test signal line is shown in FIG.

[0065] Combination Figure 3 and Fig. 9 In the third detection stage t3, the first test module 031 and the second test module 032 are both turned on, the first data line L1 transmits the first voltage V1, and the first test signal line L3 transmits the sixth voltage V6, V1≠V6.

[0066] In the embodiment of the present application, when the first test module 031 and the second test module 032 are both turned on, the first data line L1 and the first test signal line L3 can theoretically form a connection loop. Considering that V1≠V6, in principle, current can be detected on the first data line L1 and the first test signal line L3. If it is found after detection that there is no current on the first data line L1 and the first test signal line L3, it proves that there is a circuit break fault between the first data line L1 and the first test signal line L3.

[0067] In one embodiment of the present application, Fig. 9As shown, V1>V6. If there is a circuit break fault between the first data line L1 and the first test signal line L3, a detection can be performed at a certain point (herein referred to as point A) on the first data line L1. If the potential of the point A is detected to be equal to V6, it is proved that the circuit break position is on the first data line L1 and is not located between the point A and the first test signal line L3. Similarly, a detection can be performed at a certain point (herein referred to as point B) on the first test signal line L3. If the potential of the point B is detected to be equal to V1, it is proved that the circuit break position is on the first test signal line L3 and is not located between the point B and the first data line L1.

[0068] In one embodiment of the present application, V1<V6 may also be satisfied (in order to avoid cluttering the drawings, the corresponding voltage magnitude diagram is not provided for this case). If there is a circuit break fault between the first data line L1 and the first test signal line L3, a detection may be performed at a certain point (herein referred to as point A) on the first data line L1. If the potential magnitude of the point A is detected to be equal to V6, it is proved that the circuit break position is on the first data line L1 and is not located between the point A and the first test signal line L3. Similarly, a detection may be performed at a certain point (herein referred to as point B) on the first test signal line L3. If the potential magnitude of the point B is detected to be equal to V1, it is proved that the circuit break position is on the first test signal line L3 and is not located between the point B and the first data line L1.

[0069] Fig.10 An equivalent circuit diagram of a pixel circuit provided in this application, Fig.11 An equivalent circuit diagram of a pixel circuit provided in this application.

[0070] In one embodiment of the present application, Fig.10 and Fig.11 The second sub-circuit 012 includes a second data writing module 123, and the second data writing module 123 may include a second data writing transistor T23. The input end of the second data writing module 123 is electrically connected to the first test signal line L3, that is, the first test signal line L3 and the second data line L2 may be the same signal line.

[0071] In the manufacturing process of the display panel, the number of data signal lines (first data line L1 and second data line L2) is relatively large compared to other signal lines, and the display panel has high requirements on the signal transmission quality of the data signal lines when working, so it is more important to detect the line conditions corresponding to the data signal lines. Therefore, this embodiment helps to detect the line conditions of the first data line L1 and the second data line L2 respectively by setting the first test signal line L3 and the second data line L2 as the same signal line, thereby reducing line faults in the finished display panel and improving the finished product yield of the display panel.

[0072] Fig.12 An equivalent circuit diagram of a pixel circuit provided in this application, Fig.13 An equivalent circuit diagram of a pixel circuit provided in this application.

[0073] In one embodiment of the present application, Fig.12 and Fig.13 , the first control signal line K1 and the second control signal line K2 are the same signal line.

[0074] In the embodiment of the present application, the same electrical signal can be transmitted in the first control signal line K1 and the second control signal line K2. This setting method helps to realize the simultaneous opening or closing of the first test module 031 and the second test module 032, which is beneficial to the detection step.

[0075] In one embodiment of the present application, in the first detection stage t1 , the voltage transmitted by the first control signal line K1 and the voltage transmitted by the second control signal line K2 are both lower than the voltage transmitted by the first signal line L0 .

[0076] In the embodiment of the present application, the first test transistor T31 and the second test transistor T32 can both be P-type transistors, and the condition for both the first test transistor T31 and the second test transistor T32 to be turned on can be that the first control signal line K1 and the second control signal line K2 both transmit low-level voltage signals. In addition, the smaller the voltage transmitted by the first control signal line K1 and the second control signal line K2, the higher the corresponding turn-on degree of the first test transistor T31 and the second test transistor T32. Therefore, the setting method of this embodiment helps to maximize the corresponding turn-on degree of the first test transistor T31 and the second test transistor T32, and avoid the phenomenon that the transistor is not fully turned on and affects the line detection.

[0077] In one embodiment of the present application, Figure 2 and Figure 3 , the first control signal line K1 and the second control signal line K2 are different signal lines.

[0078] In the embodiment of the present application, during the process of detecting the line conditions of some signal lines, the first control signal line K1 and the second control signal line K2 can transmit different electrical signals respectively. Figure 2 In the second detection stage t2, when there is a light-emitting device 02, the first control signal line K1 can be controlled to transmit a high-level electrical signal, and the second control signal line K2 can be controlled to transmit a low-level electrical signal. At this time, the first test module 031 is turned off and the second test module 032 is turned on. In this case, the line condition of the first test signal line L3 can be specifically determined according to the light-emitting condition of the light-emitting device 02, and the voltage signal transmitted by the first data line L1 can be prevented from affecting the detection process.

[0079] In one embodiment of the present application, Figure 2 As shown, the second end of the first test module 031 is electrically connected to the second end of the light emitting device 02 , and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02 .

[0080] After the output terminal of the pixel circuit 01 outputs the light-emitting driving current, a reset voltage may be transmitted to the first terminal of the light-emitting device 02 to reset the first terminal of the light-emitting device 02 and prepare for the next writing of the light-emitting driving current. The above process of transmitting the reset voltage to the first terminal of the light-emitting device 02 may be referred to as a reset stage.

[0081] In the reset phase, the first test signal line L3 transmits a reset voltage to the first end of the light emitting device 02 , that is, the voltage transmitted by the first test signal line L3 can be used as the reset voltage.

[0082] Fig.14 A schematic top view of a partial structure of a display panel provided in the present application.

[0083] Combination Figure 2 and Fig.14 The display panel 10 may include a pixel circuit 01 arranged in an array, a plurality of first data lines L1, and a plurality of first test signal lines L3. The plurality of first data lines L1 extend along a first direction X and are arranged along a second direction Y, and the plurality of first test signal lines L3 extend along the second direction Y and are arranged along the first direction X, and the first direction X and the second direction Y intersect.

[0084] In the above detection process, the electric signal can be transmitted to the first test signal line L3 in sequence along the first direction X to realize "row-by-row scanning"; combined with the arrangement of the first data line L1 along the second direction Y, it is helpful to determine the line fault position and further increase the number of finished products of the display panel 10. For example, in the second detection stage t2, the fourth voltage V4 can be transmitted to all the first data lines L1, and the fifth voltage V5 can be transmitted to the first test signal line L3 row by row along the first direction X. In the case that the detection modules (the first detection module 031 and the second detection module 032) corresponding to all pixel circuits 01 are turned on and there is no light-emitting device 02, since V5≠V4, if it is confirmed after the detection that there is current in the first data line L1 and the first test signal line L3 (the two signal lines are collectively referred to as the line to be confirmed) corresponding to a certain pixel circuit 01 (herein referred to as the circuit to be tested N), it is proved that the part of the line to be confirmed that is located near the circuit to be tested N has a short circuit risk.

[0085] Fig.15 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Fig.15 The relationship between the voltages transmitted by the first data line and the first test signal line is shown in FIG.

[0086] In one embodiment of the present application, Figure 2 and Fig.15 In the fourth detection stage t4, the first test module 031 and the second test module 032 are both turned on, the first data line L1 transmits the first voltage V1, the first test signal line L3 transmits the seventh voltage V7, and V1>V7.

[0087] In the embodiment of the present application, if the light emitting device 02 does not emit light in the fourth test stage t4, it is proved that there is a circuit breaker fault. At this time, the potential of the first end of the light emitting device 02 can be detected by a detection tool. Since V1 is greater than V7, if the potential of the first end of the light emitting device 02 is equal to V7, it is proved that the circuit breaker position is located on the first test signal line L3.

[0088] In a possible implementation, V1<V7 (the voltage magnitude relationship diagram corresponding to this situation is not provided in the specification). If the light-emitting device 02 does not emit light in the fourth test stage t4, it is proved that there is a circuit breaker fault. At this time, the potential of the second end of the light-emitting device 02 can be detected by a detection tool. Since V1 is greater than V7, if the potential of the second end of the light-emitting device 02 is equal to V7, it is proved that the circuit breaker position is located on the first data line L1.

[0089] Fig.16 Schematic diagram of the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection phase. For the convenience of description, Fig.16 2 shows the magnitude relationship between the voltages transmitted by the first signal line, the first control signal line and the second control signal line respectively.

[0090] In one embodiment of the present application, Figure 2 and Fig.16 In the fourth detection stage t4, the first signal line L0 transmits the second voltage V2, the first control signal line K1 transmits the eighth voltage V8, and the second control signal line K2 transmits the ninth voltage V9, V8<V2 and V9<V2.

[0091] In the embodiment of the present application, the condition for both the first test transistor T31 and the second test transistor T32 to be turned on can be that both the first control signal line K1 and the second control signal line K2 transmit low-level voltage signals. In addition, the smaller the voltage transmitted by the first control signal line K1 and the second control signal line K2, the higher the corresponding turn-on degree of the first test transistor T31 and the second test transistor T32. Therefore, the configuration of the present embodiment helps to maximize the corresponding turn-on degree of the first test transistor T31 and the second test transistor T32, and avoids the phenomenon that the transistor is not fully turned on and affects the line detection.

[0092] In one possible implementation, Fig.16 As shown, V8=V9, that is, in the fourth stage t4, the same electrical signal can be transmitted to the first control signal line K1 and the second control signal line K2 respectively, which helps to reduce the complexity of power supply.

[0093] Fig.17 A schematic diagram of a display device provided in the present application.

[0094] The present application provides a display device 20, such as Fig.17 As shown, the display device 20 includes the display panel provided in the above embodiment. The display device 20 can be a mobile phone, in addition, the display device 20 can also be an electronic device such as a computer, a television, etc.

[0095] In the display device 20 provided in the embodiment of the present application, the process of detecting some signal lines in the pixel circuit 01 can be performed without providing the light-emitting device 02 (or without bonding the light-emitting device 02), and the detection scenarios are greatly enriched.

[0096] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A display panel, characterized in that: include: A pixel circuit, the pixel circuit comprising a first sub-circuit and a second sub-circuit, the output end of the first sub-circuit is electrically connected to the control end of the control module of the second sub-circuit; the first sub-circuit comprises a first data writing module, the input end of the first data writing module is electrically connected to the first data line; a light emitting device, wherein a first end of the light emitting device is electrically connected to the output end of the second sub-circuit, and a second end of the light emitting device is electrically connected to the first signal line; The test module comprises a first test module and a second test module; the first end of the first test module is electrically connected to the first data line, and the control end of the first test module is electrically connected to the first control signal line; the first end of the second test module is electrically connected to the first test signal line, and the control end of the second test module is electrically connected to the second control signal line; wherein, The second end of the first test module is electrically connected to the second end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device; or, The second end of the first test module is electrically connected to the first end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device.

2. The display panel according to claim 1, characterized in that: The second end of the first test module is electrically connected to the second end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device; In the first detection phase, the first test module is turned on, the first data line transmits a first voltage V1, and the first signal line transmits a second voltage V2, where V1≠V2.

3. The display panel according to claim 2, characterized in that: V1>V2.

4. The display panel according to claim 3, characterized in that: The second sub-circuit further comprises an output module, an output end of the output module is electrically connected to the first end of the light emitting device, and a control end of the output module is electrically connected to an output control signal line; In the first detection phase, the output control signal line transmits a third voltage V3, where V3>V1.

5. The display panel according to claim 2, characterized in that: In the second detection phase, the first test module and the second test module are both turned on, the first signal line transmits the second voltage V2, the first data line transmits the fourth voltage V4, the first test signal line transmits the fifth voltage V5, V2≠V5 and V4≠V5.

6. The display panel according to claim 5, characterized in that: V5>V2 and V5>V4.

7. The display panel according to claim 5, characterized in that: V2=V4.

8. The display panel according to claim 5, characterized in that: V5=V1.

9. The display panel according to claim 1, characterized in that: The second end of the first test module is electrically connected to the first end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device; In the third detection phase, the first test module and the second test module are both turned on, the first data line transmits a first voltage V1, and the first test signal line transmits a sixth voltage V6, where V1≠V6.

10. The display panel according to claim 9, characterized in that: V1>V6.

11. The display panel according to claim 1, characterized in that: The second sub-circuit includes a second data writing module, and an input end of the second data writing module is electrically connected to the first test signal line.

12. The display panel according to claim 1, characterized in that: The first control signal line and the second control signal line are the same signal line.

13. The display panel according to claim 12, characterized in that: In the first detection phase, a voltage transmitted by the first control signal line and a voltage transmitted by the second control signal line are both smaller than a voltage transmitted by the first signal line.

14. The display panel according to claim 1, characterized in that: The first control signal line and the second control signal line are different signal lines.

15. The display panel according to claim 14, characterized in that: The second end of the first test module is electrically connected to the second end of the light emitting device, and the second end of the second test module is electrically connected to the first end of the light emitting device; In the reset phase, the first test signal line transmits a reset voltage to the first end of the light emitting device.

16. The display panel according to claim 15, characterized in that: In the fourth detection stage, the first test module and the second test module are both turned on, the first data line transmits a first voltage V1, and the first test signal line transmits a seventh voltage V7, where V1>V7.

17. The display panel according to claim 15, characterized in that: In the fourth detection phase, the first signal line transmits a second voltage V2, the first control signal line transmits an eighth voltage V8, and the second control signal line transmits a ninth voltage V9, where V8<V2 and V9<V2.

18. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-17.

Images