Display panel and display device

Abstract

The application provides a display panel and a display device. The display panel comprises a pixel circuit and a light-emitting device. The pixel circuit comprises a first sub-circuit and a second sub-circuit. An input end of a first data writing module of the first sub-circuit is electrically connected with a first data line. A second end of the light-emitting device is electrically connected with a first signal line. The display panel further comprises a test module, which comprises a first test module and a second test module. A first end of the first test module is electrically connected with the first data line. A first end of the second test module is electrically connected with a first test signal line. Wherein, a second end of the first test module is electrically connected with the second end of the light-emitting device, and a second end of the second test module is electrically connected with the first end of the light-emitting device; or, the second end of the first test module is electrically connected with the first end of the light-emitting device, and the second end of the second test module is electrically connected with the first end of the light-emitting device. The application can detect the line condition of the first data line without setting the light-emitting device.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] With the continuous advancement of display technology, integrated circuits in display panels are becoming increasingly precise and miniaturized. However, during the manufacturing process, some structures within these integrated circuits are prone to damage, which can affect the display panel's performance. For example, during production, some data signal lines connecting the pixel circuits can become broken, interfering with the pixel circuits' driving effect on the light-emitting devices and causing display abnormalities.

[0003] To detect damage to certain data signal lines, existing technologies typically involve forming a circuit between the signal line under test and a light-emitting device, and then judging the damage level of the signal line based on the light emission of the device. However, this detection method can only be performed when a light-emitting device is present (or after the light-emitting device has been bonded), thus limiting its applicable detection scenarios. Summary of the Invention

[0004] In view of this, this application provides a display panel and display device to help solve the problem of limited detection scenarios.

[0005] In a first aspect, this application provides a display panel, including a pixel circuit and a light-emitting device. The pixel circuit includes a first sub-circuit and a second sub-circuit, the output terminal of the first sub-circuit being electrically connected to the control terminal of the control module of the second sub-circuit; the first sub-circuit includes a first data writing module, the input terminal of the first data writing module being electrically connected to a first data line. A first terminal of the light-emitting device is electrically connected to the output terminal of the second sub-circuit, and a second terminal of the light-emitting device is electrically connected to a first signal line.

[0006] The display panel also includes a testing module, which comprises a first testing module and a second testing module. A first terminal of the first testing module is electrically connected to a first data line, and a control terminal of the first testing module is electrically connected to a first control signal line. A first terminal of the second testing module is electrically connected to the first test signal line, and a control terminal of the second testing module is electrically connected to a second control signal line.

[0007] The second end of the first test module is electrically connected to the second end of the light-emitting device, and the second end of the second test module is electrically connected to the first end of the light-emitting device.

[0008] Alternatively, the second end of the first test module is electrically connected to the first end of the light-emitting device, and the second end of the second test module is electrically connected to the first end of the light-emitting device.

[0009] Secondly, this application provides a display device, including a display panel as provided in the first aspect.

[0010] The configuration method of this application facilitates the detection of the circuit condition of the first data line without relying on the light-emitting device, thus enriching the applicable scenarios of the aforementioned detection method. Specifically, it is beneficial to detect some data signal lines before bonding the light-emitting device to the display panel, and to complete the repair of faulty lines between the setting of the light-emitting device, thereby increasing the success rate of the finished product and reducing manufacturing costs. Attached Figure Description

[0011] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is an equivalent schematic diagram of a pixel circuit related to this application;

[0013] Figure 2 An equivalent circuit diagram of a pixel circuit provided in this application;

[0014] Figure 3 An equivalent circuit diagram of a pixel circuit provided in this application;

[0015] Figure 4 This is a schematic diagram showing the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection stage.

[0016] Figure 5 This is a schematic diagram showing the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection stage.

[0017] Figure 6 This is a schematic diagram showing the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection stage.

[0018] Figure 7 This is a schematic diagram showing the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection stage.

[0019] Figure 8 This is a statistical illustration of the voltage transmitted by some signal lines in the first and second detection stages, respectively.

[0020] Figure 9 This is a schematic diagram showing the magnitude relationship of the voltages transmitted by some signal lines in the pixel circuit during the detection stage.

[0021] Figure 10 An equivalent circuit diagram of a pixel circuit provided in this application;

[0022] Figure 11 An equivalent circuit diagram of a pixel circuit provided in the present application is shown in FIG. 1.

[0023] Figure 12 An equivalent circuit diagram of a pixel circuit provided in the present application is shown in FIG. 1.

[0024] Figure 13 An equivalent circuit diagram of a pixel circuit provided in the present application is shown in FIG. 1.

[0025] Figure 14 A top view schematic diagram of a partial structure of a display panel provided in the present application is shown in FIG. 2.

[0026] Figure 15 A schematic diagram of the size relationship of the voltages respectively transmitted by the partial signal lines in the pixel circuit in the detection stage is shown in FIG. 3.

[0027] Figure 16 A schematic diagram of the size relationship of the voltages respectively transmitted by the partial signal lines in the pixel circuit in the detection stage is shown in FIG. 3.

[0028] Figure 17 A schematic diagram of a display device provided in the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0029] In order to better understand the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] It should be clear that the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0031] The terms used in the embodiments of the present application are only for the purpose of describing the specific embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0032] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.

[0033] Various modifications and changes can be made to the application without departing from the spirit thereof, and it is intended to include all such modifications and changes and so to cover the application as broadly as the prior art permits. Accordingly, the application is intended to encompass all alternatives, modifications and equivalents thereof. It is to be understood that the application as provided by the embodiments herein can be combined with each other, if not contradictory.

[0034] Figure 1 An equivalent schematic diagram of a pixel circuit related to the present application.

[0035] In the prior art, as shown in Figure 1 The pixel circuit 01 can receive a data signal transmitted by the first data line L1, and the data signal can participate in the process of generating the light-emitting driving current by the pixel circuit 01. In order to detect the line condition of the first data line L1, the prior art selects to connect the first data line L1 to the first end of the light-emitting device 02 through the test transistor T0, so that when the test transistor T0 is turned on, the first data line L1, the light-emitting device 02 and the first signal line L0 form a conductive loop. The second end of the light-emitting device 02 is electrically connected with the first signal line L0, and the first end of the light-emitting device 02 is electrically connected with the second end of the output module 120 of the pixel circuit 01. The corresponding detection method includes: when the output module 120 of the pixel circuit 01 is turned off, controlling the first data line L1 to transmit a first type of voltage, controlling the first signal line L0 to transmit a second type of voltage, and turning on the test transistor T0 by adjusting the voltage signal transmitted by the control signal line S0. The first type of voltage and the second type of voltage are different in size, for example, the first type of voltage is greater than the second type of voltage or the first type of voltage is less than the second type of voltage; the voltage difference between the first type of voltage and the second type of voltage can drive the light-emitting device 02 to emit light.

[0036] If the light-emitting device 02 does not emit light after the test transistor T0 is turned on, it indicates that there is a risk of open circuit of the first data line L1.

[0037] However, the above-mentioned prior detection method is limited to the case of electrical connection between the pixel circuit 01 and the light-emitting device 02, and the above-mentioned prior detection method is not applicable during the display panel has not yet bonded the light-emitting device 02, which leads to the limitation of the prior detection method in the detection scene.

[0038] The existing pixel circuit 01 includes a first drive transistor T11, a first voltage writing transistor T12, a first data writing transistor T13, a first adjusting transistor T14, a first reset transistor T15, a first transfer transistor T16, a second reset transistor T17, a second adjusting transistor T18, a first capacitor C1 and a second capacitor C2. In addition, the existing pixel circuit 01 further includes a second drive transistor T21, a second voltage writing transistor T22, a second data writing transistor T23, a third adjusting transistor T24, a third reset transistor T25, a second transfer transistor T26, a fourth adjusting transistor T27, a fifth adjusting transistor T28, a first control transistor T29, a first output transistor T30 and a third capacitor C3. The existing pixel circuit 01 can also be electrically connected to a first data line L1, a second data line L2, a first voltage line X1, a second voltage line X2, a third voltage line X3, a first scan line S1, a second scan line S2, a third scan line S3, a first reset line F1, a fourth scan line S4, a second reset line F2 and a fifth scan line S5. The connection mode between the above-mentioned transistors, capacitors and signal lines can be referred to Figure 1 For the sake of brevity, the details are not repeated here.

[0039] Figure 2 An equivalent circuit diagram of a pixel circuit provided by the present application is as follows, Figure 3 An equivalent circuit diagram of a pixel circuit provided by the present application is as follows.

[0040] In view of the above problems, the present application provides a display panel, which includes a pixel circuit 01 and a light emitting device 02. In combination with Figure 2 and Figure 3 The pixel circuit 01 includes a first sub-circuit 011 and a second sub-circuit 012. The first sub-circuit 011 can be a pulse width modulation sub-circuit, and the second sub-circuit 012 can be an amplitude modulation sub-circuit. The pixel circuit 01 can generate a light emitting driving current under the participation of the first sub-circuit 011 and the second sub-circuit 012. The first sub-circuit 011 can be used to adjust the pulse width of the current applied to the light emitting device 02, and the second sub-circuit 012 can be used to control the amplitude of the light emitting driving current.

[0041] The output end of the first sub-circuit 011 is electrically connected to the control end of the control module 121 of the second sub-circuit 012. Therefore, the electrical signal output by the first sub-circuit 011 can be used to control the switching state of the control module 121, that is, the first sub-circuit 011 can be used to control the switching state of the first control transistor T29, thereby realizing the function of adjusting the pulse width of the light emitting driving current by the first sub-circuit 011.

[0042] The first sub-circuit 011 comprises a first data writing module 122, which can comprise a first data writing transistor T13. The input end of the first data writing module 122 is electrically connected with the first data line L1. When the first data writing module 122 is turned on, the data voltage signal transmitted by the first data line L1 can be transmitted to the input end of the first driving transistor T11 through the first data writing transistor T13. After the first driving transistor T11 receives the data voltage signal, the first driving transistor T11 can generate a control signal for controlling the switch of the control module 121.

[0043] The first end of the light emitting device 02 is electrically connected with the output end of the second sub-circuit 012, and the second end of the light emitting device 02 is electrically connected with the first signal line L0. The first signal line L0 can transmit a power voltage signal to the second end of the light emitting device 02.

[0044] The display panel further comprises a test module 03, which is electrically connected with the first sub-circuit 011 and the second sub-circuit 012. Figure 2 and Figure 3 The test module 03 comprises a first test module 031 and a second test module 032. The first end of the first test module 031 is electrically connected with the first data line L1, and the control end of the first test module 031 is electrically connected with the first control signal line K1. The first test module 031 can comprise a first test transistor T31. The first end of the first test transistor T31 is electrically connected with the first data line L1, and the control end of the first test transistor T31 is electrically connected with the first control signal line K1.

[0045] The first end of the second test module 032 is electrically connected with the first test signal line L3, and the control end of the second test module 032 is electrically connected with the second control signal line K2. The second test module 032 can comprise a second test transistor T32. The first end of the second test transistor T32 is electrically connected with the first test signal line L3, and the control end of the second test transistor T32 is electrically connected with the second control signal line K2.

[0046] In the display panel, the first test module 031 and the second test module 032 can be used to test the first data line L1 and the first signal line L0. Figure 2As shown, the second terminal of the first test module 031 is electrically connected to the second terminal of the light-emitting device 02, and the second terminal of the second test module 032 is electrically connected to the first terminal of the light-emitting device 02; that is, the second terminal of the first test transistor T31 is electrically connected to the second terminal of the light-emitting device 02, and the second terminal of the second test transistor T32 is electrically connected to the first terminal of the light-emitting device 02. In the absence of the light-emitting device 02 (or when the light-emitting device 02 has not yet been bonded to the display panel), the first test module 031 can be turned on and different voltages can be transmitted to the first data line L1 and the first signal line L0 respectively. Then, a detection device (e.g., a multimeter) can be used to detect whether there is current in the first data line L1 and the first signal line L0, thereby determining the circuit condition of the first data line L1. For example, if there is no current in the first data line L1, there is a risk of an open circuit in the first data line L1.

[0047] Or, such as Figure 3 As shown, the second terminal of the first test module 031 is electrically connected to the first terminal of the light-emitting device 02, and the second terminal of the second test module 032 is electrically connected to the first terminal of the light-emitting device 02; that is, the second terminal of the first test transistor T31 is electrically connected to the first terminal of the light-emitting device 02, and the second terminal of the second test transistor T32 is electrically connected to the first terminal of the light-emitting device 02. In the absence of the light-emitting device 02 (or when the light-emitting device 02 has not yet been bonded to the display panel), both the first test module 031 and the second test module 032 can be turned on, transmitting different voltages to the first data line L1 and the first test signal line L3 respectively. Then, a detection device (e.g., a multimeter) can be used to detect whether there is current in the first data line L1 and the first test signal line L3, thereby determining the circuit condition of the first data line L1 and the first test signal line L3. For example, if there is no current in the first data line L1 and the first test signal line L3, there is a risk of an open circuit in the first data line L1 and / or the first test signal line L3.

[0048] The configuration method of this application embodiment helps to detect the circuit condition of the first data line L1 without relying on the light-emitting device 02, and helps to enrich the applicable scenarios of the above detection method. Specifically, relying on the configuration method of this embodiment, it is beneficial to detect some data signal lines before bonding the light-emitting device 02 to the display panel, and it is helpful to complete the repair of faulty lines before setting the light-emitting device 02, thereby increasing the success rate of finished products and reducing manufacturing costs.

[0049] Combination Figure 2 and Figure 3 The connection relationships of each circuit structure in the first sub-circuit 011 are as follows:

[0050] The input end of the first voltage writing transistor T12 is electrically connected with the first voltage line X1, the output end of the first voltage writing transistor T12 is electrically connected with the input end of the first driving transistor T11, and the control end of the first voltage writing transistor T12 is electrically connected with the third scan line S3. The first voltage line X1 can transmit the first power voltage to the first sub-circuit 011. The input end of the first data writing transistor T13 is electrically connected with the first data line L1, the output end of the first data writing transistor T13 is electrically connected with the input end of the first driving transistor T11, and the control end of the first data writing transistor T13 is electrically connected with the second scan line S2. The input end of the first adjusting transistor T14 is electrically connected with the output end of the first driving transistor T11, the output end of the first adjusting transistor T14 is electrically connected with the control end of the first driving transistor T11, and the control end of the first adjusting transistor T14 is electrically connected with the second scan line S2. The input end and the control end of the first reset transistor T15 are electrically connected with the first reset line F1, and the output end of the first reset transistor T15 is electrically connected with the control end of the first driving transistor T11. The first plate of the first capacitor C1 is electrically connected with the control end of the first driving transistor T11, and the second plate of the first capacitor C1 is electrically connected with the fourth scan line S4. The input end of the first transmission transistor T16 is electrically connected with the output end of the first driving transistor T11, the output end of the first transmission transistor T16 is electrically connected with the control end of the first control transistor T29, and the control end of the first transmission transistor T16 is electrically connected with the third scan line S3. The input end of the second reset transistor T17 is electrically connected with the second reset line F2, the output end of the second reset transistor T17 is electrically connected with the control end of the first control transistor T29, and the control end of the second reset transistor T17 is electrically connected with the fifth scan line S5. The first plate of the second capacitor C2 is electrically connected with the second reset line F2, and the second plate of the second capacitor C2 is electrically connected with the control end of the first control transistor T29. The input end of the second adjusting transistor T18 is electrically connected with the third voltage line X3, the output end of the second adjusting transistor T18 is electrically connected with the second plate of the first capacitor C1, and the control end of the second adjusting transistor T18 is electrically connected with the second scan line S3.

[0051] In combination Figure 2 and Figure 3 , the connection relationship of the circuit structures in the second sub-circuit 012 is as follows:

[0052] The input end of the second voltage writing transistor T22 is electrically connected with the second voltage line X2, the output end of the second voltage writing transistor T22 is electrically connected with the input end of the second driving transistor T21, and the control end of the second voltage writing transistor T22 is electrically connected with the third scan line S3. The second voltage line X2 can transmit the second power voltage to the second sub-circuit 012. The input end of the second data writing transistor T23 is electrically connected with the second data line L2, the output end of the second data writing transistor T23 is electrically connected with the input end of the second driving transistor T21, and the control end of the second data writing transistor T23 is electrically connected with the second scan line S2. The input end of the third adjusting transistor T24 is electrically connected with the output end of the second driving transistor T21, the output end of the third adjusting transistor T24 is electrically connected with the control end of the second driving transistor T21, and the control end of the third adjusting transistor T24 is electrically connected with the second scan line S2. The input end of the third reset transistor T25 is electrically connected with the first reset line F1, and the output end and the control end of the third reset transistor T25 are both electrically connected with the control end of the second driving transistor T21. The input end of the fourth adjusting transistor T27 and the input end of the fifth adjusting transistor T28 are both electrically connected with the second voltage line X2, the output end of the fourth adjusting transistor T27 and the output end of the fifth adjusting transistor T28 are both electrically connected with the input end of the second transmission transistor T26, the control end of the fourth adjusting transistor T27 is electrically connected with the second scan line S2, and the control end of the fifth adjusting transistor T28 is electrically connected with the first reset line F1. The output end of the second transmission transistor T26 is electrically connected with the input end of the second driving transistor T21, and the control end of the second transmission transistor T26 is electrically connected with the third scan line S3. The input end of the first control transistor T29 is electrically connected with the output end of the second driving transistor T21, and the output end of the first control transistor T29 is electrically connected with the input end of the first output transistor T30. The output end of the first output transistor T30 is electrically connected with the first end of the light emitting device 02, and the control end of the first output transistor T30 is electrically connected with the first scan line S1.

[0053] The transistors in the pixel circuit 01 can be P-type transistors or N-type transistors, which are not limited herein. For convenience of description, the transistors in the equivalent circuit diagram shown in the specification are P-type transistors.

[0054] Figure 4 The size relationship between the voltages respectively transmitted by the first data line, the first signal line and the first control signal line in the first detection stage is shown in the figure. For convenience of description, Figure 4 The size relationship between the voltages respectively transmitted by the first data line, the first signal line and the first control signal line in the first detection stage is shown in the figure. For convenience of description,

[0055] In an embodiment of the present application, as Figure 2As shown, the second end of the first test module 031 is electrically connected with the second end of the light emitting device 02, and the second end of the second test module 032 is electrically connected with the first end of the light emitting device 02.

[0056] In combination Figure 2 And Figure 4 In the first detection stage t1, the first test module 031 is turned on, the first data line L1 transmits the first voltage V1, the first signal line L0 transmits the second voltage V2, and V1≠V2. The second voltage V2 can be a power supply voltage. The first test transistor T31 in the first test module 031 can be a P-type transistor, and in the first detection stage t1, the first control signal line K1 can transmit a low-level signal, at which time the voltage Vc1 transmitted by the first control signal line K1 can be less than the first voltage V1 and the second voltage V2.

[0057] In the embodiment of the present application, in the first detection stage t1, the first data line L1 and the first signal line L0 can theoretically be electrically connected, and when V1≠V2, the first data line L1 and the first signal line L0 can be detected by using a detection tool (for example, a multimeter). If no current is detected in the first data line L1 and the first signal line L0, it proves that there is an open circuit fault in the loop formed by the first data line L1 and the first signal line L0, at which time there is an open circuit risk on the first data line L1. Therefore, the setting mode of the embodiment is helpful to realize the detection of the line condition of the first data line L1 without setting the light emitting device 02 (or without bonding the light emitting device 02 in the display panel).

[0058] In one embodiment of the present application, as Figure 4 shown, V1>V2. In the embodiment, when V1>V2, if there is no open circuit fault, there can be a current transmitted from the first data line L1 to the first signal line L0. When there is an open circuit fault, the potential size of a certain point on the first data line L1 can be detected by using a detection tool, and if the potential size of the point is equal to V2, it proves that the part of the first data line L1 between the point and the first signal line L0 does not have an open circuit.

[0059] Figure 5 A schematic diagram of the size relationship of the voltages respectively transmitted by the first data line, the first signal line and the first control signal line in the detection stage is shown. For convenience of description, Figure 5 the size relationship between the voltages respectively transmitted by the first data line, the first signal line and the first control signal line in the first detection stage is shown, and the vertical coordinate V in the figure represents the size of the voltage, and the horizontal coordinate T represents time.

[0060] In one embodiment of the present application, as Figure 5As shown, V1 < V2, at this time, the voltage Vc1 transmitted by the first control signal line K1 can be less than the first voltage V1 and the second voltage V2. In this embodiment, when V1 < V2, if there is no open circuit fault, there can be a current transmitted from the first signal line L0 to the first data line L1. When there is an open circuit fault, the potential at a certain site on the first data line L1 can be detected by a detection tool, and if the potential at the site is equal to V1, it is proved that the open circuit position is on the first data line L1 between the site and the first signal line L0 or on the first signal line L0.

[0061] In an embodiment of the present application, as shown in Figure 2 The second sub-circuit 012 further includes an output module 120, an output end of the output module 120 is electrically connected with the first end of the light emitting device 02, and a control end of the output module 120 is electrically connected with the output control signal line K0. The output module 120 can include the first output transistor T30 described above, and the output control signal line K0 and the first scan line S1 can be the same signal line.

[0062] Figure 6 Figures showing the size relationship of the voltages respectively transmitted by the partial signal lines in the pixel circuit in the detection stage. For convenience of description, Figure 6 Figures showing the size relationship of the voltages respectively transmitted by the first data line, the first signal line and the output control signal line in the first detection stage, and the vertical coordinate V in the figure represents the size of the voltage, and the horizontal coordinate T represents time.

[0063] In the first detection stage t1, the output control signal line K0 transmits the third voltage V3, and V3 > V1. Figure 2 Figure 6 In the first detection stage t1, the output control signal line K0 transmits the third voltage V3, and V3 > V1.

[0064] In the embodiment of the present application, V3 > V1 can be understood as that the output control signal line K0 transmits a high-level voltage signal in the first detection stage t1, and since the first output transistor T30 can be a P-type transistor, the output module 120 can be in an off state in the first detection stage t1. In addition, considering that V1 > V2, the third voltage V3 is larger than the first voltage V1 and the second voltage V2, which helps to improve the off degree of the output module 120 and prevent the output module 120 from outputting an electrical signal to interfere with the detection process.

[0065] Figure 7 Figures showing the size relationship of the voltages respectively transmitted by the partial signal lines in the pixel circuit in the detection stage. For convenience of description, Figure 7 Figures showing the size relationship of the voltages respectively transmitted by the first data line, the first signal line and the first test signal line.

[0066] ​In an embodiment of the present application, in combination Figure 2 and Figure 7 In the second detection stage t2, the first test module 031 and the second test module 032 are both turned on. The first test transistor T31 and the second test transistor T32 can be P-type transistors. In the second detection stage t2, the first control signal line K1 and the second control signal line K2 can transmit low voltage signals. The second detection stage t2 can occur after the first detection stage t1.

[0067] The first signal line L0 transmits the second voltage V2, the first data line L1 transmits the fourth voltage V4, and the first test signal line L3 transmits the fifth voltage V5. V2≠V5 and V4≠V5.

[0068] In an embodiment of the present application, the first detection stage t1 can be used to detect the line condition of the first data line L1, and the second detection stage t2 can be used to detect the line condition of the first test signal line L3. When the light emitting device 02 exists, in the second detection stage t2, because V2≠V5, if the light emitting device 02 does not emit light, there is a risk of open circuit on the first test signal line L3. When the light emitting device 02 does not exist, in the second detection stage t2, because V4≠V5, if a current is detected in the first test signal line L3, it proves that there is a risk of short circuit between the first test signal line L3 and the first data line L1.

[0069] In a possible implementation manner, as shown in Figure 7 In the first test stage t1, the voltage transmitted by the first test signal line L3 is the same as the voltage transmitted by the first data line L1.

[0070] In an embodiment of the present application, as shown in Figure 7 V5>V2 and V5>V4.

[0071] In an embodiment of the present application, when the light emitting device 02 exists, if the light emitting device 02 emits light in the second test stage t2, it proves that there is no open circuit between the first test signal line L3, the light emitting device 02 and the first signal line L0. Because V5>V2, a current transmitted from the first test signal line L3 to the first signal line L0 can occur.

[0072] If the light emitting device 02 does not emit light in the second test stage t2, it proves that there is an open circuit fault. At this time, the potential of the first end of the light emitting device 02 can be detected by a detection tool. Because V2 and V4 are both less than V5, if the potential of the first end of the light emitting device 02 is less than V5, it proves that the open circuit position is on the first test signal line L3.

[0073] In one possible implementation, V5>V2 and V5

[0074] In one possible implementation, V5

[0075] In one possible implementation, V5

[0076] In one embodiment of the present application, as shown in Figure 7 V2=V4.

[0077] In one embodiment of the present application, since the first detection stage t1 can be a stage for detecting the line condition of the first data line L1, and the second detection stage t2 can be considered as a stage for detecting the line condition of the first test signal line L3 after the first detection stage t1, V2=V4 can be set to avoid interfering with the detection process of the first test signal line L3, so as to prevent the current between the first data line L1 and the first signal line L0.

[0078] In one embodiment of the present application, as shown in Figure 7 V5=V1.

[0079] In one embodiment of the present application, in order to meet the requirement of V5>V2 in the second detection stage t2, and considering that V1>V2 in the first detection stage t1, the first voltage V1 can be directly transmitted to the first test signal line L3 in the second detection stage t2, so as to reduce the difficulty of power supply required in the detection stage.

[0080] Figure 8 Statistics of the voltages transmitted by the signal lines in the first detection stage and the second detection stage.

[0081] In combination with Figure 2 and Figure 8In the first detection stage t1 and the second detection stage t2, the first test signal line L3 can transmit the first voltage V1; the first data line L1 can transmit the first voltage V1 in the first detection stage t1 and can transmit the second voltage V2 in the second detection stage t2; the first signal line L0 can transmit the second voltage V2 in the first detection stage t1 and the second detection stage t2; and the output control signal line K0 can transmit the third voltage V3 in the first detection stage t1 and the second detection stage t2. Wherein, V2=V4

[0082] In an embodiment of the present application, as shown in Figure 3 The second end of the first test module 031 is electrically connected with the first end of the light emitting device 02, and the second end of the second test module 032 is electrically connected with the first end of the light emitting device 02.

[0083] Figure 9 The size relationship between the voltages respectively transmitted by the first data line and the first test signal line in the detection stage is shown in the figure. For the convenience of description, Figure 9 The size relationship between the voltages respectively transmitted by the first data line and the first test signal line in the detection stage is shown in the figure. For the convenience of description,

[0084] In combination with Figure 3 and Figure 9 In the third detection stage t3, the first test module 031 and the second test module 032 are both turned on, the first data line L1 transmits the first voltage V1, the first test signal line L3 transmits the sixth voltage V6, and V1≠V6.

[0085] In the embodiment of the present application, when the first test module 031 and the second test module 032 are both turned on, the first data line L1 and the first test signal line L3 can theoretically form a connection loop. Considering that V1≠V6, in principle, a current can be detected on the first data line L1 and the first test signal line L3. If it is found after detection that there is no current on the first data line L1 and the first test signal line L3, it proves that there is an open circuit fault between the first data line L1 and the first test signal line L3.

[0086] In an embodiment of the present application, as shown in Figure 9As shown, V1>V6. If there is an open circuit fault between the first data line L1 and the first test signal line L3, detection can be performed at a certain bit point (hereinafter referred to as bit point A) on the first data line L1. If the potential of the bit point A is equal to V6, it is proved that the open circuit position is on the first data line L1 and not between the bit point A and the first test signal line L3. Similarly, detection can also be performed at a certain bit point (hereinafter referred to as bit point B) on the first test signal line L3. If the potential of the bit point B is equal to V1, it is proved that the open circuit position is on the first test signal line L3 and not between the bit point B and the first data line L1.

[0087] In an embodiment of the present application, V1V6 (for the sake of avoiding redundancy of the drawings, the corresponding voltage size diagram is not given). If there is an open circuit fault between the first data line L1 and the first test signal line L3, detection can be performed at a certain bit point (hereinafter referred to as bit point A) on the first data line L1. If the potential of the bit point A is equal to V6, it is proved that the open circuit position is on the first data line L1 and not between the bit point A and the first test signal line L3. Similarly, detection can also be performed at a certain bit point (hereinafter referred to as bit point B) on the first test signal line L3. If the potential of the bit point B is equal to V1, it is proved that the open circuit position is on the first test signal line L3 and not between the bit point B and the first data line L1.

[0088] Figure 10 An equivalent circuit diagram of a pixel circuit provided by the present application is shown in FIG. 6. Figure 11 An equivalent circuit diagram of a pixel circuit provided by the present application is shown in FIG. 6.

[0089] In an embodiment of the present application, in combination with Figure 10 and Figure 11 The second sub-circuit 012 includes a second data writing module 123, which can include a second data writing transistor T23. The input end of the second data writing module 123 is electrically connected with the first test signal line L3, i.e., the first test signal line L3 and the second data line L2 can be the same signal line.

[0090] In the preparation process of the display panel, the number of data signal lines (the first data line L1 and the second data line L2) is larger than that of other signal lines, and the display panel has a higher requirement for the signal transmission quality of the data signal line during work, so the detection of the line condition corresponding to the data signal line is more important. Therefore, by setting the first test signal line L3 and the second data line L2 as the same signal line, the line conditions of the first data line L1 and the second data line L2 are detected respectively, and the line fault of the display panel product is reduced, and the yield of the display panel product is improved.

[0091] Figure 12 An equivalent circuit diagram of a pixel circuit provided in the present application is provided, Figure 13 An equivalent circuit diagram of a pixel circuit provided in the present application is provided.

[0092] In an embodiment of the present application, in combination with Figure 12 and Figure 13 The first control signal line K1 and the second control signal line K2 are the same signal line.

[0093] In the embodiment of the present application, the same electrical signal can be transmitted in the first control signal line K1 and the second control signal line K2, and the setting mode is helpful to realize the simultaneous opening or simultaneous closing of the first test module 031 and the second test module 032, which is conducive to the detection step.

[0094] In an embodiment of the present application, in the first detection stage t1, the voltage transmitted by the first control signal line K1 and the voltage transmitted by the second control signal line K2 are both smaller than the voltage transmitted by the first signal line L0.

[0095] In the embodiment of the present application, the first test transistor T31 and the second test transistor T32 can both be P-type transistors, and the condition for the first test transistor T31 and the second test transistor T32 to be both opened can be that the first control signal line K1 and the second control signal line K2 both transmit low voltage signals. In addition, the smaller the voltage transmitted by the first control signal line K1 and the second control signal line K2, the higher the opening degree of the first test transistor T31 and the second test transistor T32 respectively corresponding. Therefore, the setting mode of the present embodiment is helpful to improve the opening degree of the first test transistor T31 and the second test transistor T32 respectively corresponding as much as possible, and avoid the phenomenon that the incomplete opening of the transistor affects the line detection.

[0096] In an embodiment of the present application, in combination with Figure 2 and Figure 3 The first control signal line K1 and the second control signal line K2 are different signal lines.

[0097] In the embodiment of the present application, during the detection of the line condition of the partial signal line, the first control signal line K1 and the second control signal line K2 can respectively transmit different electrical signals. For example, please refer to Figure 2 In the second detection stage t2, when the light emitting device 02 exists, the first control signal line K1 can be controlled to transmit a high-level electrical signal, and the second control signal line K2 can be controlled to transmit a low-level electrical signal. At this time, the first test module 031 is turned off and the second test module 032 is turned on. In this case, the line condition of the first test signal line L3 can be judged according to the light emitting condition of the light emitting device 02, and the influence of the voltage signal transmitted by the first data line L1 on the detection process can be avoided.

[0098] In an embodiment of the present application, as shown in Figure 2 The second end of the first test module 031 is electrically connected to the second end of the light emitting device 02, and the second end of the second test module 032 is electrically connected to the first end of the light emitting device 02.

[0099] After the output end of the pixel circuit 01 outputs the light emitting driving current, a reset voltage can be transmitted to the first end of the light emitting device 02 to reset the first end of the light emitting device 02, so as to prepare for the next writing of the light emitting driving current. The process of transmitting the reset voltage to the first end of the light emitting device 02 can be referred to as a reset stage.

[0100] In the reset stage, the first test signal line L3 transmits the reset voltage to the first end of the light emitting device 02, that is, the voltage transmitted by the first test signal line L3 can be used as the reset voltage.

[0101] Figure 14 A top view schematic diagram of a partial structure of a display panel provided by the present application is shown.

[0102] In combination with Figure 2 and Figure 14 , the display panel 10 can include pixel circuits 01 arranged in an array, a plurality of first data lines L1 and a plurality of first test signal lines L3. The plurality of first data lines L1 extend along a first direction X and are arranged along a second direction Y, the plurality of first test signal lines L3 extend along the second direction Y and are arranged along the first direction X, and the first direction X and the second direction Y intersect.

[0103] In the detection process, the electrical signal can be transmitted to the first test signal line L3 in sequence along the first direction X to realize "line-by-line scanning"; in combination with the arrangement of the first data line L1 along the second direction Y, the determination of the line fault position is facilitated, and the number of finished products of the display panel 10 is further improved. For example, in the second detection stage t2, the fourth voltage V4 can be transmitted to all the first data lines L1, and the fifth voltage V5 can be transmitted to the first test signal line L3 in sequence along the first direction X. In the case where all the detection modules (the first detection module 031 and the second detection module 032) corresponding to all the pixel circuits 01 are turned on and there is no light emitting device 02, since V5≠V4, if it is confirmed after detection that there is a current in the first data line L1 and the first test signal line L3 (the two signal lines are collectively referred to as a to-be-confirmed line) corresponding to a certain pixel circuit 01 (hereinafter referred to as a to-be-tested circuit N) exists, it is proved that the part of the to-be-confirmed line near the to-be-tested circuit N exists a short circuit risk.

[0104] Figure 15 The size relationship between the voltages respectively transmitted by the first data line and the first test signal line is shown in the following figure. Figure 15 The size relationship between the voltages respectively transmitted by the first data line and the first test signal line is shown in the following figure.

[0105] In an embodiment of the present application, in combination with Figure 2 and Figure 15 In the fourth detection stage t4, the first test module 031 and the second test module 032 are turned on, the first data line L1 transmits the first voltage V1, and the first test signal line L3 transmits the seventh voltage V7, and V1>V7.

[0106] In the embodiment of the present application, if the light emitting device 02 does not emit light in the fourth test stage t4, it is proved that there is a disconnection fault. At this time, the potential of the first end of the light emitting device 02 can be detected by the detection tool. Since V1 is greater than V7, if the potential of the first end of the light emitting device 02 is equal to V7, it is proved that the disconnection position is located on the first test signal line L3.

[0107] In a possible implementation, V1

[0108] Figure 16 The size relationship between the voltages respectively transmitted by the first data line and the first test signal line is shown in the following figure.Figure 16 The size relationship between the voltages transmitted by the first signal line, the first control signal line and the second control signal line is shown in the first stage t1.

[0109] In an embodiment of the present application, the first signal line, the first control signal line and the second control signal line transmit voltages in the following manner. Figure 2 and Figure 16 In the fourth detection stage t4, the first signal line L0 transmits the second voltage V2, the first control signal line K1 transmits the eighth voltage V8, the second control signal line K2 transmits the ninth voltage V9, V8 < V2 and V9 < V2.

[0110] In the embodiment of the present application, the condition under which the first test transistor T31 and the second test transistor T32 are both turned on can be that the first control signal line K1 and the second control signal line K2 both transmit low voltage signals. In addition, the smaller the voltages transmitted by the first control signal line K1 and the second control signal line K2, the higher the degree of turning on of the first test transistor T31 and the second test transistor T32. Therefore, the setting manner of the embodiment helps to improve the degree of turning on of the first test transistor T31 and the second test transistor T32 as much as possible, avoiding the phenomenon that the incomplete turning on of the transistors affects the line detection.

[0111] In a possible implementation manner, as shown in Figure 16 V8 = V9, that is, the same electrical signal can be transmitted to the first control signal line K1 and the second control signal line K2 in the fourth stage t4, which helps to reduce the complexity of power supply.

[0112] Figure 17 A schematic diagram of a display device provided by the present application is shown.

[0113] The present application provides a display device 20, as shown in Figure 17 The display device 20 includes the display panel provided by the above-mentioned embodiments. The display device 20 can be a mobile phone, and in addition, the display device 20 can also be a computer, a television or other electronic equipment.

[0114] In the display device 20 provided by the embodiment of the present application, the process of detecting part of the signal lines in the pixel circuit 01 can be carried out without setting the light emitting device 02 (or not bonding the light emitting device 02), and the detection scene is greatly enriched.

[0115] The same and similar parts among the various embodiments in the present specification can be referred to each other. Especially, for the device embodiments and the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the related parts can be referred to the description in the method embodiments.

Claims

1. A display panel, characterized by, Comprising: A pixel circuit, the pixel circuit comprising a first sub-circuit and a second sub-circuit, an output end of the first sub-circuit being electrically connected with a control end of a control module of the second sub-circuit; the first sub-circuit comprising a first data writing module, an input end of the first data writing module being electrically connected with a first data line; A light emitting device, a first end of the light emitting device being electrically connected with an output end of the second sub-circuit, a second end of the light emitting device being electrically connected with a first signal line; A test module, the test module comprising a first test module and a second test module; a first end of the first test module being electrically connected with the first data line, a control end of the first test module being electrically connected with a first control signal line; a first end of the second test module being electrically connected with a first test signal line, a control end of the second test module being electrically connected with a second control signal line; wherein, a second end of the first test module is electrically connected with the second end of the light emitting device, and a second end of the second test module is electrically connected with the first end of the light emitting device; or, a second end of the first test module is electrically connected with the first end of the light emitting device, and a second end of the second test module is electrically connected with the first end of the light emitting device.

2. The display panel of claim 1, wherein, a second end of the first test module is electrically connected with the second end of the light emitting device, and a second end of the second test module is electrically connected with the first end of the light emitting device; In a first detection stage, the first test module is turned on, the first data line transmits a first voltage V1, the first signal line transmits a second voltage V2, and V1≠V2.

3. The display panel of claim 2, wherein, V1>V2.

4. The display panel of claim 3, wherein, The second sub-circuit further comprises an output module, an output end of the output module being electrically connected with the first end of the light emitting device, and a control end of the output module being electrically connected with an output control signal line; In the first detection stage, the output control signal line transmits a third voltage V3, and V3>V1.

5. The display panel of claim 2, wherein, In a second detection stage, the first test module and the second test module are both turned on, the first signal line transmits the second voltage V2, the first data line transmits a fourth voltage V4, the first test signal line transmits a fifth voltage V5, V2≠V5 and V4≠V5.

6. The display panel of claim 5, wherein, V5>V2 and V5>V4.

7. The display panel of claim 5, wherein, V2=V4.

8. The display panel of claim 5, wherein, V5=V1.

9. The display panel of claim 1, wherein, a second end of the first test module is electrically connected with the first end of the light emitting device, and a second end of the second test module is electrically connected with the first end of the light emitting device. In a third detection stage, the first test module and the second test module are both turned on, the first data line transmits a first voltage V1, and the first test signal line transmits a sixth voltage V6, V1≠V6.

10. The display panel of claim 9, wherein, V1>V6.

11. The display panel of claim 1, wherein, The second sub-circuit comprises a second data writing module, an input end of the second data writing module being electrically connected with the first test signal line.

12. The display panel of claim 1, wherein, The first control signal line and the second control signal line are the same signal line.

13. The display panel of claim 12, wherein, In the first detection stage, the voltage transmitted by the first control signal line and the voltage transmitted by the second control signal line are both smaller than the voltage transmitted by the first signal line.

14. The display panel of claim 1, wherein, The first control signal line and the second control signal line are different signal lines.

15. The display panel of claim 14, wherein, The second end of the first test module is electrically connected with the second end of the light emitting device, and the second end of the second test module is electrically connected with the first end of the light emitting device. In the reset stage, the first test signal line transmits a reset voltage to the first end of the light emitting device.

16. The display panel of claim 15, wherein, In the fourth detection stage, the first test module and the second test module are both turned on, the first data line transmits a first voltage V1, the first test signal line transmits a seventh voltage V7, and V1>V7.

17. The display panel of claim 15, wherein, In the fourth detection stage, the first signal line transmits a second voltage V2, the first control signal line transmits an eighth voltage V8, the second control signal line transmits a ninth voltage V9, V8 18. A display device comprising: A display panel comprising any one of claims 1-17.

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