Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and aims at solving the problems that due to the fact that the layout space is limited and too many data lines are designed, crosstalk occurs between the data lines close to each other, and crosstalk type display is poor. Each driving circuit column in the display panel corresponds to two data lines, the odd-numbered sub-pixel driving circuits in the driving circuit columns are coupled with the first data line, and the even-numbered sub-pixel driving circuits in the driving circuit columns are coupled with the second data line; at least part of the data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are alternately arranged, and each data line group comprises two adjacent data lines; the distance between the two data lines in the first data line group is smaller than the distance between the two data lines in the second data line group; the two data lines in the same first data line group are both first data lines or both second data lines.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, the cost demand on the market side is reduced, and correspondingly on the display device side, there is a trend of reducing the functions of the driver chip (Source IC) and reducing the size of the driver chip; therefore, the Dual Data Line (DDL) design is introduced in the display device design to optimize the problem of insufficient data writing caused by the reduction of the Source IC. However, due to limited layout space, designing too many data lines will cause crosstalk between data lines that are close to each other, resulting in crosstalk-related display defects. Summary of the invention

[0003] The object of the present invention is to provide a display panel and a display device for solving the problem that due to limited layout space, designing too many data lines may cause crosstalk between data lines that are close to each other, resulting in crosstalk-related display defects.

[0004] In order to achieve the above object, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of driving circuit columns; the display panel further comprises:

[0006] A plurality of data lines, each driving circuit column corresponds to two of the data lines, an odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to a first data line of the two data lines, and an even-numbered sub-pixel driving circuit in the driving circuit column is coupled to a second data line of the two data lines;

[0007] At least part of the data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are alternately arranged, each data line group includes two adjacent data lines, and between an orthographic projection of a first data line group on the substrate and an orthographic projection of an adjacent second data line group on the substrate, there is an orthographic projection of a gate of a driving transistor included in a column of driving circuits on the substrate; a distance between two data lines in the first data line group is smaller than a distance between two data lines in the second data line group;

[0008] Two data lines in the same group of the first data line group are both the first data lines, or are both the second data lines.

[0009] Optionally, the plurality of drive circuit columns are divided into a plurality of drive circuit groups, each drive circuit group comprising two adjacent drive circuit columns;

[0010] The orthographic projections of the gates of the two columns of driving transistors in the driving circuit group on the substrate are arranged alternately with the orthographic projections of the first data line group on the substrate, and the orthographic projections of the second data line group on the substrate are located between the orthographic projections of the gates of the two columns of driving transistors in the corresponding driving circuit group on the substrate;

[0011] In two adjacent groups of driving circuit groups, among the data lines coupled to one group of driving circuit groups, the first data line is located on the first side of the corresponding driving circuit column, and the second data line is located on the second side of the corresponding driving circuit column; among the data lines coupled to the other group of driving circuit groups, the first data line is located on the second side of the corresponding driving circuit column, and the second data line is located on the first side of the corresponding driving circuit column; the first side and the second side are opposite to each other along a first direction.

[0012] Optionally, the display panel further includes a plurality of gating units, the gating units including a first gating sub-unit, a second gating sub-unit, a third gating sub-unit and a fourth gating sub-unit; the display panel further includes a first gating control line, a second gating control line, a third gating control line and a fourth gating control line;

[0013] The first gating subunit is respectively coupled to the first gating control line, the corresponding data signal input terminal, and the first data line corresponding to the first column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the first gating control line;

[0014] The second gating subunit is respectively coupled to the second gating control line, the corresponding data signal input terminal, and the first data line corresponding to the second column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the second gating control line;

[0015] The third gating subunit is respectively coupled to the third gating control line, the corresponding data signal input terminal, and the second data line corresponding to the first column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the third gating control line;

[0016] The fourth selection subunit is respectively coupled to the fourth selection control line, the corresponding data signal input terminal, and the second data line corresponding to the second column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the fourth selection control line.

[0017] Optionally, the sub-pixel driving circuit further includes a data writing transistor, a first reset transistor, a first conductive connecting portion, and a second conductive connecting portion;

[0018] The first electrode of the data writing transistor is coupled to the corresponding data line through the first conductive connection portion, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; the second electrode of the first reset transistor is coupled to the gate of the driving transistor through the second conductive connection portion;

[0019] In at least part of the sub-pixels, the orthographic projection of the second conductive connection portion on the substrate is located between the orthographic projection of the active layer of the data write transistor on the substrate and the orthographic projection of the data line coupled to the data write transistor on the substrate; in at least part of the sub-pixels, the first conductive connection portion includes a first connection portion and a second connection portion coupled to each other, an extension direction of the first connection portion intersects with an extension direction of the second connection portion, the first connection portion is coupled to the corresponding data line, and the second connection portion is coupled to the first electrode of the data write transistor.

[0020] Optionally, the display panel further includes a power line, and an orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps with an orthographic projection of the power line on the base substrate.

[0021] Optionally, the plurality of sub-pixels include a red sub-pixel, a green sub-pixel and a blue sub-pixel;

[0022] In the driving circuit group, the first driving circuit column includes sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels arranged alternately, and the second driving circuit column includes sub-pixel driving circuits for a plurality of green sub-pixels arranged sequentially.

[0023] Optionally, in two adjacent groups of driving circuit groups, the first column of driving circuits in one group of driving circuit groups includes sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels that are alternately arranged, and the first column of driving circuits in the other group of driving circuit groups includes sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels that are alternately arranged.

[0024] Optionally, the two data lines in the same group of the second data line group include one first data line and one second data line.

[0025] Optionally, the display panel further includes a plurality of first signal lines, and there is one first signal line between two data lines in the second data line group.

[0026] Optionally, the display panel further includes a plurality of power lines, and an orthographic projection of the power lines corresponding to the drive circuit column on the base substrate is located between orthographic projections of two data lines corresponding to the drive circuit column on the base substrate.

[0027] Optionally, the plurality of sub-pixels are divided into a plurality of drive circuit rows, and in the same drive circuit row, sub-pixel drive circuits included in two adjacent sub-pixels are mirror-symmetrical.

[0028] Optionally, the display panel includes a hole area, an isolation area and a pixel area, and the isolation area is located between the hole area and the pixel area; the plurality of data lines include a plurality of data lines crossing the hole area, and the plurality of data lines crossing the hole area include a plurality of first-type data lines and a plurality of second-type data lines;

[0029] The first type of data line comprises a first data portion, a first type of cross-region data portion and a second data portion coupled in sequence, the first data portion and the second data portion are located at two opposite sides of the hole area, and the first data portion, the first type of cross-region data portion and the second data portion are all located in the pixel area;

[0030] The second type of data line includes a third data portion, a second type of cross-region data portion and a fourth data portion coupled in sequence, the third data portion and the fourth data portion are located on opposite sides of the hole area, the third data portion and the fourth data portion are both located in the pixel area, and the second type of cross-region data portion is located in the isolation area.

[0031] Optionally, the plurality of second-category data lines are divided into a first portion of second-category data lines and a second portion of second-category data lines, and the plurality of first-category data lines are located between the first portion of second-category data lines and the second portion of second-category data lines.

[0032] Optionally, the first data portion included in the first-category data line and the third data portion included in the second-category data line are arranged alternately; the second data portion included in the first-category data line and the fourth data portion included in the second-category data line are arranged alternately.

[0033] Optionally, the first type of data lines are coupled to corresponding green sub-pixels, and the second type of data lines are coupled to corresponding red sub-pixels and / or blue sub-pixels.

[0034] Based on the technical solution of the above display panel, a second aspect of the present invention provides a display device including the above display panel.

[0035] In the technical solution provided by the present invention, each column of driving circuits is set to correspond to two data lines, the odd-numbered sub-pixel driving circuits in the driving circuit column are coupled to the first data line of the two data lines, and the even-numbered sub-pixel driving circuits in the driving circuit column are coupled to the second data line of the two data lines; this setting method enables the odd-numbered sub-pixel driving circuits and the even-numbered sub-pixel driving circuits in a column of driving circuits to be provided with data signals by different data lines, respectively, prolongs the time for the data lines to write data signals to the corresponding sub-pixel driving circuits, ensures that each sub-pixel driving circuit can be fully written with data signals, and avoids poor display problems caused by insufficient writing of data signals.

[0036] In the technical solution provided by the present invention, the distance between two data lines in the first data line group is set to be smaller than the distance between two data lines in the second data line group, and the two data lines in the same group of the first data line group are both the first data lines, or are both the second data lines; so that when scanning a row of odd-numbered sub-pixels or a row of even-numbered sub-pixels in the display panel, the two data lines in the first data line group that are closer can write data signals to the sub-pixel driving circuit located in the same odd-numbered row, or can write data signals to the sub-pixels located in the same even-numbered row; in this way, the two data lines in the first data line group that are closer can be controlled by the selection sub-unit, and the time of writing data signals is close, that is, the time of writing data signals to the sub-pixel driving circuit by the two data lines can be made the same, thereby shortening the time difference of writing data signals between the two data lines in the first data line group that are closer, and reducing the risk of one data line having completed the data writing work and being in a floating state and being interfered by another data line; therefore, the technical solution provided by the present invention effectively reduces the crosstalk problem between the data lines that are closer, and improves the problem of crosstalk-related display defects caused by the crosstalk between the data lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0038] Figure 1 A circuit schematic diagram of a sub-pixel driving circuit provided by an embodiment of the present invention;

[0039] Figure 2A schematic diagram of the layout of active layers in array-distributed sub-pixels provided in an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of the layout of the active layer and the first gate metal layer in the array-distributed sub-pixels provided in an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of the layout of the second gate metal layer in the array-distributed sub-pixels provided in an embodiment of the present invention;

[0042] Figure 5 For Figure 3 A schematic diagram of a layout of adding a second gate metal layer on the basis of FIG.

[0043] Figure 6 A schematic diagram of the layout of via holes in the interlayer insulating layer of sub-pixels distributed in an array provided by an embodiment of the present invention;

[0044] Figure 7 For Figure 5 On the basis of the above, a schematic diagram of the layout of the via holes in the interlayer insulation layer is added;

[0045] Figure 8 A schematic diagram of the layout of the first source-drain metal layer in the array-distributed sub-pixels provided in an embodiment of the present invention;

[0046] Fig. 9 For Figure 7 A schematic diagram of a layout of adding a first source-drain metal layer on the basis of FIG.

[0047] Fig.10 For Fig. 9 Add the layout diagram of the passivation layer vias on the basis of

[0048] Fig.11 A schematic diagram of the layout of planar layer vias in an array-distributed sub-pixel provided in an embodiment of the present invention;

[0049] Fig.12 For Fig.10 Add a layout diagram of the flat layer vias on the basis of

[0050] Fig.13 A schematic diagram of the layout of the second source-drain metal layer in the array-distributed sub-pixels provided in an embodiment of the present invention;

[0051] Fig.14 For Fig.12 A schematic diagram of a layout of adding a second source / drain metal layer on the basis of FIG.

[0052] Fig.15 A schematic diagram of the connection between a data line and a gating unit in a display panel provided by an embodiment of the present invention;

[0053] Fig.16 A timing diagram of a gate control line provided by an embodiment of the present invention;

[0054] Fig.17 A schematic diagram of the layout of a gating unit provided in an embodiment of the present invention;

[0055] Fig.18 A first schematic layout diagram near a hole area provided in an embodiment of the present invention;

[0056] Fig.19 A second schematic layout diagram near the hole area provided by an embodiment of the present invention;

[0057] Fig. 20 For Fig.18 The corresponding wiring diagram;

[0058] Fig.21 A schematic diagram of a mirror layout of a sub-pixel driving circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to further illustrate the display panel and the display device provided by the embodiments of the present invention, a detailed description is given below in conjunction with the accompanying drawings.

[0060] See also Figures 1 to 14 The embodiment of the present invention provides a display panel, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of driving circuit columns; the display panel further comprises:

[0061] A plurality of data lines, each driving circuit column corresponds to two of the data lines, an odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to a first data line DA1 of the two data lines, and an even-numbered sub-pixel driving circuit in the driving circuit column is coupled to a second data line DA2 of the two data lines;

[0062] At least part of the data lines are divided into a plurality of first data line groups Z11 and a plurality of second data line groups Z12, the first data line groups Z11 and the second data line groups Z12 are alternately arranged, each data line group includes two adjacent data lines, between an orthographic projection of the first data line group Z11 on the substrate and an orthographic projection of the adjacent second data line group Z12 on the substrate, there is an orthographic projection of the gates of the driving transistors included in a column of driving circuits on the substrate; the distance between the two data lines in the first data line group Z11 is smaller than the distance between the two data lines in the second data line group Z12;

[0063] The two data lines in the same first data line group Z11 are both the first data line DA1 , or are both the second data line DA2 .

[0064] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixels include a plurality of sub-pixel driving circuits distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of driving circuits and a plurality of columns of driving circuits. The plurality of rows of driving circuits are arranged along a second direction, and each row of driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of driving circuits are arranged along a first direction, and each column of driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0065] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0066] Exemplarily, the specific structure of the sub-pixel driving circuit is varied, for example: 7T1C (including 7 transistors and 1 capacitor) circuit structure, 8T1C (including 8 transistors and 1 capacitor) circuit structure, etc., but not limited to these.

[0067] Taking the sub-pixel driving circuit adopting the 7T1C circuit structure as an example, the connection relationship of the sub-pixel driving circuits belonging to the n-th row of driving circuits is described in detail below.

[0068] The sub-pixel driving circuit includes a driving transistor T3, a first reset transistor T1, a second reset transistor T7, a compensation transistor T2, a data writing transistor T4, a power control transistor T5, a light emission control transistor T6 and a storage capacitor Cst.

[0069] The gate of the first reset transistor T1 is coupled to the corresponding first scan line GA1, the first electrode of the first reset transistor T1 is coupled to the corresponding first initialization signal line Vinit1, and the second electrode of the first reset transistor T1 is coupled to the gate T3-g (ie, the first node N1) of the driving transistor T3.

[0070] The gate of the compensation transistor T2 is coupled to the corresponding second scan line GA2, the first electrode of the compensation transistor T2 is coupled to the second electrode (ie, the third node N3) of the driving transistor T3, and the second electrode of the compensation transistor T2 is coupled to the gate T3-g of the driving transistor T3.

[0071] The gate of the data writing transistor T4 is coupled to the corresponding second scanning line GA2, the first electrode of the data writing transistor T4 is coupled to the corresponding data line DA, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3 (ie, the second node N2).

[0072] The gate of the power control transistor T5 is coupled to the corresponding light emitting control signal line EM, the first electrode of the power control transistor T5 is coupled to the corresponding power line VDD, and the second electrode of the power control transistor T5 is coupled to the first electrode of the driving transistor T3.

[0073] The gate of the light emitting control transistor T6 is coupled to the corresponding light emitting control signal line EM, the first electrode of the light emitting control transistor T6 is coupled to the second electrode of the driving transistor T3, and the second electrode of the light emitting control transistor T6 is coupled to the anode of the corresponding light emitting element (i.e., the fourth node N4). The cathode of the light emitting element receives the negative power supply signal VSS.

[0074] The gate of the second reset transistor T7 is coupled to the first scan line GA1' corresponding to the next adjacent row of driving circuits, the first electrode of the second reset transistor T7 is coupled to the corresponding second initialization signal line Vinit2, and the second electrode of the second reset transistor T7 is coupled to the anode of the corresponding light emitting element.

[0075] The first plate Cst1 of the storage capacitor Cst is multiplexed as the gate of the driving transistor T3 , and the second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD.

[0076] Exemplarily, the display panel further comprises a plurality of data lines, the plurality of data lines are arranged along the first direction, and each data line comprises at least a portion extending along the second direction. Each driving circuit column corresponds to two of the data lines, and the orthographic projection of the gate of the driving transistor included in the driving circuit column on the substrate is located between the orthographic projections of the corresponding two data lines on the substrate.

[0077] Exemplarily, the plurality of data lines include a starting data line, an ending data line, and a plurality of intermediate data lines located between the starting data line and the ending data line; the plurality of intermediate data lines are divided into a plurality of first data line groups Z11 and a plurality of second data line groups Z12, the first data line groups Z11 and the second data line groups Z12 are alternately arranged along the first direction. The first data line group Z11 and the second data line group Z12 each include two adjacent data lines.

[0078] Exemplarily, the minimum distance between two data lines in the first data line group Z11 is smaller than the minimum distance between two data lines in the second data line group Z12. The minimum distance between adjacent first data line group Z11 and second data line group Z12 is greater than the minimum distance between two data lines in the second data line group Z12.

[0079] Exemplarily, two data lines in the same group of the first data line group Z11 are both the first data line DA1, that is, the two data lines in the same group of the first data line group Z11 are both coupled to odd-numbered sub-pixels; or, two data lines in the same group of the first data line group Z11 are both the second data line DA2, that is, the two data lines in the same group of the first data line group Z11 are both coupled to even-numbered sub-pixels.

[0080] According to the specific structure of the above-mentioned display panel, in the display panel provided by the embodiment of the present invention, each column of driving circuits is set to correspond to two data lines, the odd-numbered sub-pixel driving circuits in the driving circuit column are coupled to the first data line DA1 of the two data lines, and the even-numbered sub-pixel driving circuits in the driving circuit column are coupled to the second data line DA2 of the two data lines; this setting method enables the odd-numbered sub-pixel driving circuits and the even-numbered sub-pixel driving circuits in a column of driving circuits to be provided with data signals by different data lines, respectively, prolongs the time for the data line to write data signals to the corresponding sub-pixel driving circuits, ensures that each sub-pixel driving circuit can be fully written with data signals, and avoids poor display problems caused by insufficient writing of data signals.

[0081] In the display panel provided by the embodiment of the present invention, the distance between two data lines in the first data line group Z11 is set to be smaller than the distance between two data lines in the second data line group Z12, and the two data lines in the same group of the first data line group Z11 are both the first data line DA1, or are both the second data line DA2; so that when scanning a row of odd-numbered sub-pixels or a row of even-numbered sub-pixels in the display panel, the two data lines in the first data line group Z11 that are closer to each other can write data signals to the sub-pixel driving circuit located in the same odd-numbered row, or can write data signals to the sub-pixels located in the same even-numbered row; In this way, two data lines that are relatively close to each other in the first data line group Z11 can be controlled by the selection sub-unit, and the time for writing data signals can be close, that is, the time for the two data lines to write data signals to the sub-pixel driving circuit can be the same, thereby shortening the time difference for writing data signals between the two data lines that are relatively close to each other in the first data line group Z11, and reducing the risk of one data line having completed the data writing work and being in a floating state and being interfered by another data line; therefore, the display panel provided by the embodiment of the present invention effectively reduces the crosstalk problem between data lines that are relatively close to each other, and improves the problem of crosstalk-related display defects caused by crosstalk between data lines.

[0082] like Figures 2 to 14 As shown, in some embodiments, the plurality of drive circuit columns are divided into a plurality of drive circuit groups Z2, each drive circuit group Z2 includes two adjacent drive circuit columns;

[0083] The orthographic projections of the gates of the two columns of driving transistors in the driving circuit group Z2 on the substrate are arranged alternately with the orthographic projections of the first data line group Z11 on the substrate, and the orthographic projections of the second data line group Z12 on the substrate are located between the orthographic projections of the gates of the two columns of driving transistors in the corresponding driving circuit group Z2 on the substrate;

[0084] In two adjacent groups of driving circuit groups Z2, among the data lines coupled to one group of driving circuit groups Z2, the first data line DA1 is located on the first side of the corresponding driving circuit column, and the second data line DA2 is located on the second side of the corresponding driving circuit column; among the data lines coupled to the other group of driving circuit groups Z2, the first data line DA1 is located on the second side of the corresponding driving circuit column, and the second data line DA2 is located on the first side of the corresponding driving circuit column; the first side and the second side are opposite to each other along a first direction.

[0085] Exemplarily, the plurality of drive circuit columns are divided into a plurality of drive circuit groups Z2, and the plurality of drive circuit groups Z2 are arranged along the first direction. Two drive circuit columns in the drive circuit group Z2 include two columns of drive transistors.

[0086] The above configuration can achieve that two data lines in the same first data line group are both the first data line DA1 , or both are the second data line DA2 .

[0087] like Figures 13 to 17 As shown, in some embodiments, the display panel further includes a plurality of gating units, the gating unit including a first gating sub-unit (including a first gating transistor T8), a second gating sub-unit (including a second gating transistor T9), a third gating sub-unit (including a third gating transistor T10) and a fourth gating sub-unit (including a fourth gating transistor T11); the display panel further includes a first gating control line MUX1, a second gating control line MUX2, a third gating control line MUX3 and a fourth gating control line MUX4;

[0088] The first gating subunit is respectively coupled to the first gating control line MUX1, the corresponding data signal input terminal (such as: A1, A2, A3, A4), and the first data line DA1 corresponding to the first column of driving circuits in the corresponding driving circuit group Z2, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal A1 and the first data line DA1 under the control of the first gating control line MUX1;

[0089] The second gating subunit is respectively coupled to the second gating control line MUX2, the corresponding data signal input terminal, and the first data line DA1 corresponding to the second column of driving circuits in the corresponding driving circuit group Z2, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line DA1 under the control of the second gating control line MUX2;

[0090] The third gating subunit is respectively coupled to the third gating control line MUX3, the corresponding data signal input terminal, and the second data line DA2 corresponding to the first column of driving circuits in the corresponding driving circuit group Z2, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line DA2 under the control of the third gating control line MUX3;

[0091] The fourth selection subunit is respectively coupled to the fourth selection control line MUX4, the corresponding data signal input terminal, and the second data line DA2 corresponding to the second column of driving circuits in the corresponding driving circuit group Z2, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line DA2 under the control of the fourth selection control line MUX4.

[0092] Exemplarily, the first selection subunit includes a first selection transistor T8, the gate of the first selection transistor T8 is coupled to the first selection control line MUX1, the first electrode of the first selection transistor T8 is coupled to the corresponding data signal input terminal, and the second electrode of the first selection transistor T8 is coupled to the first data line DA1 corresponding to the first column of driving circuits in the corresponding driving circuit group Z2.

[0093] Exemplarily, the second selection subunit includes a second selection transistor T9, a gate of the second selection transistor T9 is coupled to the second selection control line MUX2, a first electrode of the second selection transistor T9 is coupled to the corresponding data signal input terminal, and a second electrode of the second selection transistor T9 is coupled to the first data line DA1 corresponding to the second column of the driving circuit column in the corresponding driving circuit group Z2.

[0094] Exemplarily, the third selection subunit includes a third selection transistor T10, the gate of the third selection transistor T10 is coupled to the third selection control line MUX3, the first electrode of the third selection transistor T10 is coupled to the corresponding data signal input terminal, and the second electrode of the third selection transistor T10 is coupled to the second data line DA2 corresponding to the first column of driving circuits in the corresponding driving circuit group Z2.

[0095] Exemplarily, the fourth selection subunit includes a fourth selection transistor T11, the gate of the fourth selection transistor T11 is coupled to the fourth selection control line MUX4, the first electrode of the fourth selection transistor T11 is coupled to the corresponding data signal input terminal, and the second electrode of the fourth selection transistor T11 is coupled to the second data line DA2 corresponding to the second column of the driving circuit column in the corresponding driving circuit group Z2.

[0096] Exemplarily, the first selection transistor T8, the second selection transistor T9, the third selection transistor T10 and the fourth selection transistor T11 are all P-type transistors, but are not limited thereto.

[0097] In more detail, the above embodiment is based on MUX1:4 (i.e. one data signal input terminal corresponds to four data lines), i.e. column MUX1:2 (i.e. one column of driving circuit corresponds to two data lines) + row MUX1:2 (i.e. odd-numbered row driving circuit corresponds to the first data line, even-numbered row driving circuit corresponds to the second data line) combined with the shift register unit odd and even row driving, which can increase the sub-pixel threshold voltage compensation time and improve display uniformity. However, since MUX1:4 doubles the number of data lines that need to be set, the distance between adjacent data lines will inevitably decrease in spatial arrangement, i.e. the parasitic capacitance between adjacent data lines will increase. At the same time, the crosstalk between the data lines will increase, which is prone to crosstalk-related display defects.

[0098] like Fig.15 As shown, the MUX1:4 timing corresponding to the DDL scheme is illustrated, the first selection signal transmitted by the first selection control line MUX1, the second selection signal transmitted by the second selection control line MUX2, the third selection signal transmitted by the third selection control line MUX3 and the fourth selection signal transmitted by the fourth selection control line MUX4 are successively in the effective level (such as low level), when the selection signal is at the effective level, the corresponding selection transistor is controlled to be turned on, and the data signal provided by the data signal input terminal is written into the corresponding data line.

[0099] like Fig.15 The time period outlined by the dotted line in the figure corresponds to the low potential of the scanning signal GateP[2n-1]. At this time, the data writing transistor T4 in the 2n-1 row sub-pixel is turned on, and the data line controlled by the first selection control line MUX1 and the second selection control line MUX2 writes a data signal to the gate of the driving transistor T3 through the data writing transistor T4 and the compensation transistor T2 (the data signal on this data line is pre-stored or written in the current period), that is, the data line controlled by the first selection control line MUX1 and the second selection control line MUX2 writes a data signal to the N1 node. During this time period, the data line corresponding to the 2n row sub-pixel is controlled by the third selection control line MUX3 and the fourth selection control line MUX4 to write a data signal to the data line and store it in the data line. When the scanning signal GateP[2n] is at a low level, writing into the corresponding sub-pixel driving circuit is realized; if the parasitic capacitance between the data lines controlled by the third selection control line MUX3 and the fourth selection control line MUX4 and the data lines controlled by the first selection control line MUX1 and the second selection control line MUX2 is large, then when the data voltage of the data lines controlled by the third selection control line MUX3 and the fourth selection control line MUX4 jumps, the data voltage of the data lines controlled by the first selection control line MUX1 and the second selection control line MUX2 will be directly pulled. Since the scanning signal GateP[2n-1] is at a low potential at this time, the pulled data voltage will be directly written into the corresponding sub-pixel driving circuit, resulting in abnormal signal writing in the sub-pixel driving circuit, which manifests as poor crosstalk.

[0100] In the display panel provided by the above embodiment, DDL combined with MUX1:4 driving design is adopted, and the two data lines with larger parasitic capacitance belonging to the same group of first data line groups are adjusted to data lines corresponding to sub-pixels in the same row through MUX transformation. In this way, in the entire display panel, the two data lines that are closer to each other will only be the second data line DA2 controlled by MUX3 and MUX4, or the first data line DA1 controlled by MUX1 and MUX2, which greatly reduces the crosstalk problem between data lines in the same group of first data line groups.

[0101] like Figures 2 to 14 As shown, in some embodiments, the sub-pixel driving circuit further includes a data writing transistor T4, a first reset transistor T1, a first conductive connecting portion 31 and a second conductive connecting portion 32;

[0102] In at least some sub-pixels, the first electrode of the data writing transistor T4 is coupled to the corresponding data line through the first conductive connection portion 31, and the second electrode of the data writing transistor T4 is coupled to the first electrode of the driving transistor T3; the second electrode of the first reset transistor T1 is coupled to the gate of the driving transistor through the second conductive connection portion 32;

[0103] In at least part of the sub-pixels, the orthographic projection of the second conductive connection portion 32 on the substrate is located between the orthographic projection of the active layer of the data writing transistor T4 on the substrate and the orthographic projection of the data line coupled to the data writing transistor T4 on the substrate; in at least part of the sub-pixels, the first conductive connection portion 31 includes a first connection portion 311 and a second connection portion 312 coupled to each other, the extension direction of the first connection portion 311 intersects with the extension direction of the second connection portion 312, the first connection portion 311 is coupled to the corresponding data line, and the second connection portion 312 is coupled to the first electrode of the data writing transistor T4.

[0104] Exemplarily, the first conductive connection portion 31 and the second conductive connection portion 32 are provided in the same layer and with the same material, but the present invention is not limited thereto.

[0105] Exemplarily, in at least some sub-pixels, the data writing transistor T4 included in the sub-pixel is close to one side of the sub-pixel driving circuit included in the sub-pixel, and the data line coupled to the data writing transistor T4 included in the sub-pixel is close to the other side of the sub-pixel driving circuit, that is, the data writing transistor T4 included in the sub-pixel and the data line coupled to the data writing transistor T4 are located on opposite sides of the sub-pixel driving circuit.

[0106] Exemplarily, the first conductive connection portion 31 includes a first connection portion 311 and a second connection portion 312 coupled to each other, and the first connection portion 311 and the second connection portion 312 are formed into an integral structure.

[0107] The above configuration enables the data writing transistor T4 and the data line coupled thereto, which are far apart in at least part of the sub-pixels, to be connected via the first conductive connection portion 31 .

[0108] like Figure 8 , Fig.13 and Fig.14As shown, in some embodiments, the display panel further includes a power line VDD, and an orthographic projection of the first conductive connection portion 31 on the base substrate at least partially overlaps with an orthographic projection of the power line VDD on the base substrate.

[0109] The above configuration enables the power line VDD to shield the interference of peripheral signals on the signal transmitted by the first conductive connection part 31 , thereby ensuring the stability of the signal transmitted by the first conductive connection part 31 .

[0110] In some embodiments, the multiple sub-pixels include red sub-pixels, green sub-pixels and blue sub-pixels; in the driving circuit group Z2, the first column of driving circuits includes sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels arranged alternately, and the second column of driving circuits includes sub-pixel driving circuits for multiple green sub-pixels arranged in sequence.

[0111] Exemplarily, the first column of driving circuits includes subpixel driving circuits for red subpixels and subpixel driving circuits for blue subpixels arranged alternately along the second direction, and the second column of driving circuits includes subpixel driving circuits for multiple green subpixels arranged sequentially along the second direction.

[0112] Exemplarily, in two adjacent groups of drive circuit groups Z2, the first column of drive circuits in one group of drive circuit groups Z2 includes sub-pixel drive circuits for red sub-pixels and sub-pixel drive circuits for blue sub-pixels that are alternately arranged, and the first column of drive circuits in the other group of drive circuit groups Z2 includes sub-pixel drive circuits for blue sub-pixels and sub-pixel drive circuits for red sub-pixels that are alternately arranged.

[0113] By arranging the sub-pixels in the above manner, it is possible to achieve that each data line is coupled to sub-pixels of only one color, that is, the range of data signal transitions on each data line is small, so that even if a data line in the first data line group Z11 undergoes a data signal transition, the crosstalk to another data line is small; similarly, if a data line in the second data line group Z12 undergoes a data signal transition, the crosstalk to another data line is also small.

[0114] like Fig.13 As shown, in some embodiments, the display panel further includes a plurality of power lines VDD, and the orthographic projection of the power line VDD corresponding to the driving circuit column on the substrate is located between the orthographic projections of the two data lines corresponding to the driving circuit column on the substrate.

[0115] Exemplarily, the power line VDD is used to transmit a power signal with a stable potential.

[0116] Exemplarily, the orthographic projection of the power line VDD corresponding to the driving circuit column on the substrate is located between the orthographic projection of the first data line DA1 and the orthographic projection of the second data line DA2 corresponding to the driving circuit column on the substrate.

[0117] Exemplarily, the power line VDD corresponding to the driving circuit column is located between a red data line for transmitting a data signal corresponding to a red sub-pixel and a blue data line for transmitting a data signal corresponding to a blue sub-pixel; or, the power line VDD corresponding to the driving circuit column is located between a green data line for transmitting a data signal corresponding to a green sub-pixel and a green data line for transmitting a data signal corresponding to a green sub-pixel.

[0118] The above configuration enables the power line VDD to effectively shield the crosstalk between the two data lines corresponding to the drive circuit column.

[0119] In some embodiments, the display panel further includes a shielding line, wherein an orthographic projection of the shielding line on the base substrate is located between orthographic projections of two data lines in the first data line group on the base substrate.

[0120] Exemplarily, the shielding line is used to transmit an initialization signal, that is, the shielding line is multiplexed as an initialization signal line; or, the shielding line is used to transmit a power signal, that is, the shielding line is multiplexed as a power line VDD.

[0121] It should be noted that the shielding line can be provided when the product PPI is small, that is, the pixel size is large and there is sufficient layout space.

[0122] The above configuration enables the shielding line to effectively shield the crosstalk between the two data lines in the first data line group.

[0123] like Fig.13 As shown, in some embodiments, two data lines in the same group of the second data line group Z12 include one first data line DA1 and one second data line DA2.

[0124] Exemplarily, the display panel further includes a plurality of first signal lines 40 , and there is one first signal line 40 between two data lines in the second data line group Z12 .

[0125] Exemplarily, the first signal line 40 includes a FIP lead, but is not limited thereto. It should be noted that in order to meet the requirement of narrowing the bottom frame of the display panel, the display panel can be set to adopt a FIP design, that is, the data lines of the left frame and the right frame of the display panel are connected to the FIP lead, and the lead is extended to the middle area of ​​the display panel, and then extended from the middle area to the bottom frame area, thereby narrowing the bottom frame width of the display panel.

[0126] Exemplarily, the first signal line 40 includes a power line VDD or an initialization signal line, but is not limited thereto.

[0127] The above configuration has one first signal line 40 between two data lines in the second data line group Z12, so that the first signal line 40 can effectively shield the crosstalk between the two data lines in the second data line group Z12.

[0128] like Fig.21 As shown, in some embodiments, the plurality of sub-pixels are divided into a plurality of drive circuit rows, and in the same drive circuit row, the sub-pixel drive circuits included in two adjacent sub-pixels are mirror-symmetrical.

[0129] It should be noted that Fig.21 The F indicated in the figure represents a sub-pixel driving circuit, but the sub-pixel driving circuit is not laid out in an F shape. It can be seen that in the same row of driving circuits, the sub-pixel driving circuits included in the two adjacent sub-pixels are mirror-symmetrical, and in the same column of driving circuits, the sub-pixel driving circuits are laid out in the same manner without mirror processing.

[0130] Exemplarily, in the same row of driving circuits, adjacent odd-numbered sub-pixel driving circuits and even-numbered sub-pixel driving circuits are mirror-symmetrical.

[0131] Exemplarily, the sub-pixel driving circuits included in two adjacent sub-pixels are mirror-symmetrical, and the symmetry axis of the mirror-symmetrical symmetry is located between the sub-pixel driving circuits included in the two adjacent sub-pixels and extends along the second direction.

[0132] The above configuration is conducive to the display panel achieving a higher PPI. At the same time, the FIP horizontal and vertical wiring layouts are better, the symmetry is better, and the anode layer in the display panel has better flatness.

[0133] like Figures 18 to 20 As shown, in some embodiments, the display panel includes a hole area 50, an isolation area 51 and a pixel area 52, and the isolation area 51 is located between the hole area 50 and the pixel area 52; the plurality of data lines include a plurality of data lines crossing the hole area, and the plurality of data lines crossing the hole area include a plurality of first-type data lines and a plurality of second-type data lines;

[0134] The first type of data line includes a first data portion 61, a first type of cross-region data portion 62 and a second data portion 63 coupled in sequence, the first data portion 61 and the second data portion 63 are located at two opposite sides of the hole area 50, and the first data portion 61, the first type of cross-region data portion 62 and the second data portion 63 are all located in the pixel area 52;

[0135] The second type of data line includes a third data portion 71, a second type of cross-region data portion 72 and a fourth data portion 73 coupled in sequence, the third data portion 71 and the fourth data portion 73 are located on opposite sides of the hole area 50, the third data portion 71 and the fourth data portion 73 are both located in the pixel area 52, and the second type of cross-region data portion 72 is located in the isolation area 51.

[0136] Exemplarily, the display panel includes a hole area 50 , an isolation area 51 and a pixel area 52 , wherein the isolation area 51 is located between the hole area 50 and the pixel area 52 , the isolation area 51 surrounds the hole area 50 , and the pixel area 52 surrounds the isolation area 51 .

[0137] Exemplarily, the multiple data lines include multiple data lines crossing the hole area, and the data lines crossing the hole area mean that if the data line is extended along the second direction, the data line will pass through the hole area 50, while in actual layout, the data line will bypass the hole area 50, that is, it will not pass through the hole area 50.

[0138] Exemplarily, the first type data line includes a first data portion 61, a first type cross-region data portion 62 and a second data portion 63 coupled in sequence, and the first data portion 61 and the second data portion 63 are located on opposite sides of the hole area 50 along the second direction.

[0139] Exemplarily, the first data portion 61 and the second data portion 63 both extend along the second direction, and the first type of cross-region data portion 62 includes a portion extending along the first direction and a portion extending along the second direction. When the first type of data line adopts the above structure, it is formed in a HIP winding manner.

[0140] Exemplarily, the second type data line includes a third data portion 71, a second type cross-region data portion 72 and a fourth data portion 73 coupled in sequence, and the third data portion 71 and the fourth data portion 73 are located on opposite sides of the hole area 50 along the second direction.

[0141] Exemplarily, the third data portion 71 and the fourth data portion 73 both extend along the second direction, and the second cross-region data portion 72 extends along the edge of the hole region 50. When the first type of data line adopts the above structure, it is formed in a Fanout winding manner.

[0142] For example, Fig.18 and Fig. 20 As shown, the plurality of second-category data lines are divided into a first part of second-category data lines and a second part of second-category data lines, and the plurality of first-category data lines (located in area B1) are located between the first part of second-category data lines (located in area B2) and the second part of second-category data lines (located in area B3).

[0143] For example, Fig.19 As shown, the first data part 61 (located in the C1 area) included in the first data line and the third data part 71 (located in the C2 area) included in the second data line are arranged alternately; the second data part 63 (located in the C3 area) included in the first data line and the fourth data part 73 (located in the C4 area) included in the second data line are arranged alternately. For example: the first data line is coupled to the corresponding green sub-pixel, and the second data line is coupled to the corresponding red sub-pixel and / or blue sub-pixel.

[0144] It is worth noting that by adopting a design in which each column of driving circuits corresponds to two data lines (i.e., a DDL design), the number of data lines in the display panel will be doubled, and thus the number of data lines that need to be wound in the hole area 50 will also be doubled. If only the Fanout winding method is adopted, then the doubling of the winding number in the hole area 50 will lead to an increase in the wiring space of the isolation area 51, which will directly lead to an increase in the border of the hole area 50.

[0145] The above configuration adopts a combination of HIP winding and Fanout winding, which can greatly narrow the border width of the hole area 50 under the DDL design. In more detail, the display panel provided by the embodiment of the present invention can reduce 152 Fanout windings and reduce the border width of the hole area 50 by about 190 microns.

[0146] It should be noted that if Figure 2 As shown, the third active layer 23 included in the driving transistor T3, the first active layer 21 included in the first reset transistor T1, the seventh active layer 27 included in the second reset transistor T7, the second active layer 22 included in the compensation transistor T2, the fourth active layer 24 included in the data writing transistor T4, the fifth active layer 25 included in the power control transistor T5, and the sixth active layer 26 included in the light emitting control transistor T6 are illustrated.

[0147] like Figures 3 to 14As shown, the first conductive connection portion 31 is coupled to the first electrode of the data writing transistor T4 through the sixth via hole Via6, and the first conductive connection portion 31 is coupled to the corresponding data line through the twelfth via hole Via12 and the seventeenth via hole Via17.

[0148] The second conductive connection portion 32 is coupled to the second electrode of the compensation transistor T2 and the second electrode of the first reset transistor T1 through the fifth via hole Via5 , and is coupled to the gate T3 - g of the driving transistor T3 through the seventh via hole Via7 .

[0149] The third conductive connection portion 33 is coupled to the first initialization signal line Vinit1 through the first via hole Via1 , and the third conductive connection portion 33 is coupled to the first electrode of the first reset transistor T1 through the second via hole Via2 .

[0150] The fourth conductive connection portion 34 is coupled to the first electrode of the data writing transistor T4 through the via Via0 , and the fourth conductive connection portion 34 is coupled to the corresponding data line through the thirteenth via Via13 and the twentieth via Via20 .

[0151] The fifth conductive connection portion 35 is coupled to the first electrode of the second reset transistor T7 through the third via hole Via3 , and is coupled to the second initialization signal line Vinit2 through the fourth via hole Via4 .

[0152] The sixth conductive connection part 36 is coupled to the second electrode of the light emitting control transistor T6 and the second electrode of the second reset transistor T7 through the ninth via hole Via9, and is coupled to the ninth conductive connection part 39 through the fifteenth via hole Via15 and the nineteenth via hole Via19. The ninth conductive connection part 39 is coupled to the corresponding anode layer.

[0153] The power compensation line 38 is coupled to the second plate Cst2 of the storage capacitor Cst through the eighth via Via8 and the eleventh via Via11, is coupled to the first electrode of the power control transistor T5 through the tenth via Via10, and is coupled to the power line VDD through the fourteenth via Via14 and the eighteenth via Via18.

[0154] The FIP transverse lead 37 is coupled to the corresponding FIP longitudinal lead through the sixteenth via Via16 .

[0155] An embodiment of the present invention further provides a display device, comprising the display panel provided by the above embodiment.

[0156] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane, etc.

[0157] In the display panel provided by the above embodiment, each column of driving circuits is set to correspond to two data lines, the odd-numbered sub-pixel driving circuits in the driving circuit column are coupled to the first data line DA1 of the two data lines, and the even-numbered sub-pixel driving circuits in the driving circuit column are coupled to the second data line DA2 of the two data lines; this setting method enables the odd-numbered sub-pixel driving circuits and the even-numbered sub-pixel driving circuits in a column of driving circuits to be provided with data signals by different data lines, respectively, prolongs the time for the data line to write data signals to the corresponding sub-pixel driving circuits, ensures that each sub-pixel driving circuit can be fully written with data signals, and avoids poor display problems caused by insufficient writing of data signals.

[0158] In the display panel provided by the above embodiment, the distance between two data lines in the first data line group Z11 is set to be smaller than the distance between two data lines in the second data line group Z12, and the two data lines in the same group of the first data line group Z11 are both the first data line DA1, or are both the second data line DA2; so that when scanning a row of odd-numbered sub-pixels or a row of even-numbered sub-pixels in the display panel, the two data lines in the first data line group Z11 that are closer to each other can write data signals to the sub-pixel driving circuit located in the same odd-numbered row, or can write data signals to the sub-pixels located in the same even-numbered row; In this way, two data lines that are relatively close to each other in the first data line group Z11 can be controlled by the selection sub-unit, and the time for writing data signals can be close, that is, the time for the two data lines to write data signals to the sub-pixel driving circuit can be the same, thereby shortening the time difference for writing data signals between the two data lines that are relatively close to each other in the first data line group Z11, and reducing the risk of one data line being disturbed by another data line when the data writing work has been completed and is in a floating state; therefore, the display panel provided by the above embodiment effectively reduces the crosstalk problem between data lines that are relatively close to each other, and improves the problem of crosstalk-related display defects caused by crosstalk between data lines.

[0159] The display device provided by the embodiment of the present invention also has the above-mentioned beneficial effects when it includes the above-mentioned display panel, which will not be described in detail here.

[0160] It should be noted that the signal line extends along a certain direction means that: the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along a certain direction, and the length of the main part extending along the certain direction is greater than the length of the secondary part extending along other directions.

[0161] It should be noted that the layout area of ​​the column unit is the layout area occupied by all sub-pixel driving circuits in the column unit. The layout area occupied by each sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0162] It should be noted that the "same layer" in the embodiment of the present invention may refer to a film layer on the same structural layer. Or, for example, a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0163] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the sequence of the steps. For ordinary technicians in this field, without paying creative work, changes to the sequence of the steps are also within the protection scope of the present invention.

[0164] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0165] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect", "couple" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0166] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0167] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0168] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A base substrate and a plurality of sub-pixels disposed on the base substrate, wherein the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of driving circuit columns; The display panel further includes: A plurality of data lines, each driving circuit column corresponds to two of the data lines, an odd-numbered sub-pixel driving circuit in the driving circuit column is coupled to a first data line of the two data lines, and an even-numbered sub-pixel driving circuit in the driving circuit column is coupled to a second data line of the two data lines; At least part of the data lines are divided into a plurality of first data line groups and a plurality of second data line groups, the first data line groups and the second data line groups are alternately arranged, each data line group includes two adjacent data lines, and between an orthographic projection of a first data line group on the substrate and an orthographic projection of an adjacent second data line group on the substrate, there is an orthographic projection of a gate of a driving transistor included in a column of driving circuits on the substrate; a distance between two data lines in the first data line group is smaller than a distance between two data lines in the second data line group; Two data lines in the same group of the first data line group are both the first data lines, or are both the second data lines.

2. The display panel according to claim 1, characterized in that: The plurality of drive circuit columns are divided into a plurality of drive circuit groups, each drive circuit group comprising two adjacent drive circuit columns; The orthographic projections of the gates of the two columns of driving transistors in the driving circuit group on the substrate are arranged alternately with the orthographic projections of the first data line group on the substrate, and the orthographic projections of the second data line group on the substrate are located between the orthographic projections of the gates of the two columns of driving transistors in the corresponding driving circuit group on the substrate; In two adjacent groups of driving circuit groups, among the data lines coupled to one group of driving circuit groups, the first data line is located on the first side of the corresponding driving circuit column, and the second data line is located on the second side of the corresponding driving circuit column; among the data lines coupled to the other group of driving circuit groups, the first data line is located on the second side of the corresponding driving circuit column, and the second data line is located on the first side of the corresponding driving circuit column; the first side and the second side are opposite to each other along a first direction.

3. The display panel according to claim 2, characterized in that: The display panel further includes a plurality of gating units, the gating units including a first gating sub-unit, a second gating sub-unit, a third gating sub-unit and a fourth gating sub-unit; the display panel further includes a first gating control line, a second gating control line, a third gating control line and a fourth gating control line; The first gating subunit is respectively coupled to the first gating control line, the corresponding data signal input terminal, and the first data line corresponding to the first column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the first gating control line; The second gating subunit is respectively coupled to the second gating control line, the corresponding data signal input terminal, and the first data line corresponding to the second column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the first data line under the control of the second gating control line; The third gating subunit is respectively coupled to the third gating control line, the corresponding data signal input terminal, and the second data line corresponding to the first column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the third gating control line; The fourth selection subunit is respectively coupled to the fourth selection control line, the corresponding data signal input terminal, and the second data line corresponding to the second column of driving circuits in the corresponding driving circuit group, and is used to control the conduction or disconnection of the electrical connection between the data signal input terminal and the second data line under the control of the fourth selection control line.

4. The display panel according to claim 2, characterized in that: The sub-pixel driving circuit further includes a data writing transistor, a first reset transistor, a first conductive connecting portion, and a second conductive connecting portion; In at least some sub-pixels, a first electrode of the data writing transistor is coupled to a corresponding data line through a first conductive connection portion, a second electrode of the data writing transistor is coupled to a first electrode of the driving transistor; and a second electrode of the first reset transistor is coupled to a gate of the driving transistor through the second conductive connection portion; In at least some sub-pixels, an orthographic projection of the second conductive connection portion on the substrate is located between an orthographic projection of an active layer of the data writing transistor on the substrate and an orthographic projection of a data line coupled to the data writing transistor on the substrate; In at least part of the sub-pixel, the first conductive connection portion includes a first connection portion and a second connection portion coupled to each other, an extension direction of the first connection portion intersects with an extension direction of the second connection portion, the first connection portion is coupled to the corresponding data line, and the second connection portion is coupled to the first electrode of the data writing transistor.

5. The display panel according to claim 4, characterized in that: The display panel further includes a power line, and an orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps with an orthographic projection of the power line on the base substrate.

6. The display panel according to claim 2, characterized in that: The plurality of sub-pixels include a red sub-pixel, a green sub-pixel and a blue sub-pixel; In the driving circuit group, the first driving circuit column includes sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels arranged alternately, and the second driving circuit column includes sub-pixel driving circuits for a plurality of green sub-pixels arranged sequentially.

7. The display panel according to claim 6, characterized in that: In two adjacent groups of driving circuit groups, the first column of driving circuits in one group of driving circuit groups includes sub-pixel driving circuits for red sub-pixels and sub-pixel driving circuits for blue sub-pixels arranged alternately, and the first column of driving circuits in the other group of driving circuit groups includes sub-pixel driving circuits for blue sub-pixels and sub-pixel driving circuits for red sub-pixels arranged alternately.

8. The display panel according to claim 1, characterized in that: The two data lines in the same group of the second data line group include one first data line and one second data line.

9. The display panel according to claim 8, characterized in that: The display panel further includes a plurality of first signal lines, and one first signal line is provided between two data lines in the second data line group.

10. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of power lines, wherein the orthographic projections of the power lines corresponding to the drive circuit column on the base substrate are located between the orthographic projections of the two data lines corresponding to the drive circuit column on the base substrate.

11. The display panel according to any one of claims 1 to 10, characterized in that: The plurality of sub-pixels are divided into a plurality of drive circuit rows. In the same drive circuit row, the sub-pixel drive circuits included in two adjacent sub-pixels are mirror-symmetrical.

12. The display panel according to any one of claims 1 to 10, characterized in that: The display panel comprises a hole area, an isolation area and a pixel area, wherein the isolation area is located between the hole area and the pixel area; the plurality of data lines comprises a plurality of data lines crossing the hole area, wherein the plurality of data lines crossing the hole area comprises a plurality of first-type data lines and a plurality of second-type data lines; The first type of data line comprises a first data portion, a first type of cross-region data portion and a second data portion coupled in sequence, the first data portion and the second data portion are located at two opposite sides of the hole area, and the first data portion, the first type of cross-region data portion and the second data portion are all located in the pixel area; The second type of data line includes a third data portion, a second type of cross-region data portion and a fourth data portion coupled in sequence, the third data portion and the fourth data portion are located on opposite sides of the hole area, the third data portion and the fourth data portion are both located in the pixel area, and the second type of cross-region data portion is located in the isolation area.

13. The display panel according to claim 12, characterized in that: The plurality of second-category data lines are divided into a first portion of second-category data lines and a second portion of second-category data lines, and the plurality of first-category data lines are located between the first portion of second-category data lines and the second portion of second-category data lines.

14. The display panel according to claim 12, characterized in that: The first data portion included in the first type of data lines and the third data portion included in the second type of data lines are arranged alternately; the second data portion included in the first type of data lines and the fourth data portion included in the second type of data lines are arranged alternately.

15. The display panel according to claim 14, characterized in that: The first type of data lines are coupled to corresponding green sub-pixels, and the second type of data lines are coupled to corresponding red sub-pixels and / or blue sub-pixels.

16. A display device, characterized in that: The invention comprises the display panel according to any one of claims 1 to 15.

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