Gate driving device and display panel

Abstract

The invention provides a gate driving device and a display panel, and belongs to the technical field of display driving, the gate driving device comprises a multi-stage gate driving circuit, and the gate driving circuit comprises a pull-up control unit and a pull-up unit. The pull-up control unit is used for generating a pull-up control signal according to a pre-stage scanning signal. The pull-up unit comprises at least two driving subunits. The driving subunits are respectively connected with different clock lines, and the driving subunits and the pull-up control unit are connected at a first node. And each driving subunit generates a driving signal according to the pull-up control signal and the clock signal output by the corresponding clock line, and outputs the scanning signal of the current stage based on the driving signal. Therefore, each driving subunit can be controlled to be closed through the driving signal after outputting the scanning signal of the level, at the moment, even if the clock line fluctuates due to the influence of coupling factors and the like, display abnormity caused by the fact that the clock line is output to the scanning line is avoided, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a gate driving device and a display panel. Background Art

[0002] With the rapid development of display technology, narrow border design has become one of the core trends of modern displays. Narrow border displays reduce the non-display area around the screen, making the screen look lighter and reducing visual fatigue, providing users with a more comfortable, immersive and efficient visual experience. The GOA (Gate Driver on Array) circuit integration solution is usually adopted to directly integrate the gate drive circuit into the display panel array to reduce the space occupied by the peripheral circuit on the border.

[0003] At present, in order to further save the occupied border space, the related technology usually uses a single-stage GOA circuit to output multiple scanning signals, so that each scanning signal shares the driving signal of the same control node, and then combines different clock signals through the same driving signal, thereby achieving the effect of a single-stage GOA circuit generating multiple different scanning signals.

[0004] However, since multiple scanning signals share the same control node, the generation of each scanning signal is prone to cause writing errors due to factors such as clock signal coupling, thereby causing display abnormalities. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present application provides a gate driving device and a display panel.

[0006] In a first aspect, the present application provides a gate driving device, comprising a multi-stage gate driving circuit, wherein the gate driving circuit comprises:

[0007] A pull-up control unit, used for generating a pull-up control signal according to a previous scanning signal;

[0008] The pull-up unit includes at least two driving sub-units; each of the driving sub-units is connected to a different clock line, and is connected to the pull-up control unit at a first node; each of the driving sub-units generates a driving signal according to the pull-up control signal and a clock signal output by the corresponding clock line, and outputs a scanning signal of this level based on the driving signal.

[0009] Optionally, the pull-up unit includes a first driving subunit and a second driving subunit;

[0010] The first driving subunit is connected to the first node, the first clock line and the n-th level scan line, generates a first driving signal according to the pull-up control signal and a first clock signal output by the first clock line, and outputs an n-th level scan signal based on the first driving signal;

[0011] The second driving subunit is connected to the first node, the second clock line and the n+1th level scan line, generates a second driving signal according to the pull-up control signal and a second clock signal output by the second clock line, and outputs the n+1th level scan signal based on the second driving signal;

[0012] The n is associated with the number of stages of the gate driving circuit in the gate driving device.

[0013] Optionally, the first driving subunit includes a first transistor and a second transistor;

[0014] The first transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to the first clock line;

[0015] The second transistor includes a first electrode connected to the first clock line, a second electrode connected to the n-th level scan line, and a control electrode connected to the second node.

[0016] Optionally, the second driving subunit includes a third transistor and a fourth transistor;

[0017] The third transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a control electrode connected to the second clock line;

[0018] The fourth transistor includes a first electrode connected to the second clock line, a second electrode connected to the n+1th stage scan line, and a control electrode connected to the third node.

[0019] Optionally, it further includes a pull-down unit, wherein the pull-down unit includes a plurality of pull-down sub-units corresponding to the driving sub-unit;

[0020] Each pull-down subunit is connected to a power line and a corresponding one of the driving subunits, and is used to pull down the driving signal and the current-stage scanning signal.

[0021] Optionally, the pull-down unit includes a first pull-down sub-unit and a second pull-down sub-unit;

[0022] The first pull-down subunit and the first driving subunit are connected to the second node, and are connected to the n-th level scanning line and the power line, and are used to pull down the first driving signal and the n-th level scanning signal;

[0023] The second pull-down subunit and the second driving subunit are connected to the third node and are connected to the n+1th level scanning line and the power line, and are used to pull down the second driving signal and the n+1th level scanning signal.

[0024] Optionally, the power cord includes a first power cord and a second power cord;

[0025] The first pull-down subunit includes a fifth transistor and a sixth transistor;

[0026] The fifth transistor comprises a first electrode connected to the second node, a second electrode connected to the first power line, and a control electrode for connecting to the n+ath level scanning signal;

[0027] The sixth transistor comprises a first electrode connected to the n-th level scan line, a second electrode connected to the second power line, and a control electrode for connecting to the n+a-th level scan signal;

[0028] The second pull-down subunit includes a seventh transistor and an eighth transistor;

[0029] The seventh transistor comprises a first electrode connected to the third node, a second electrode connected to the first power line, and a control electrode for connecting to the n+a+1th level scanning signal;

[0030] The eighth transistor includes a first electrode connected to the n+1th level scan line, a second electrode connected to the second power line, and a control electrode for accessing the n+a+1th level scan signal connection.

[0031] Optionally, it also includes a stage transmission unit connected to each of the clock lines and the first node, and is used to output the stage transmission signal of the current stage according to the pull-up control signal and each of the clock signals, and transmit it to the subsequent stage circuit of the gate drive circuit.

[0032] Optionally, the stage transmission unit includes a ninth transistor;

[0033] The ninth transistor includes a first electrode connected to the first clock line, a second electrode for outputting the stage transfer signal of the current stage, and a control electrode connected to the first node.

[0034] In a second aspect, in one embodiment, the present application provides a display panel, including: a gate driving device as described above.

[0035] In summary, in the present application, firstly, by connecting a plurality of driver sub-units to the pull-up control unit through the first node, all driver sub-units share the same pull-up control signal, and only one pull-up control unit is required to drive a plurality of sub-units, which is helpful to realize the design of the narrow frame of the display panel. Secondly, each driver sub-unit is independently connected to different clock lines to receive different clock signals, so that each driver sub-unit can independently generate a drive signal according to the clock signal connected to each other under the premise of sharing the same pull-up control signal, so that the generation of the scan signal is not only controlled by the clock signal, but also by the drive signal, so as to realize that the current level scan signal output by each driver sub-unit can be independently controlled. In this way, each driver sub-unit can control its closure through the drive signal after outputting the current level scan signal. At this time, even if the clock line fluctuates due to the influence of coupling factors, it will not be output to the scan line to cause display abnormality, thereby improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic diagram of a gate driving circuit in the related art;

[0038] Figure 2 This is a schematic diagram of an application scenario of a gate driving device in one embodiment of the present application;

[0039] Figure 3 A schematic diagram of a gate driving circuit in one embodiment of the present application;

[0040] Figure 4 This is a connection structure diagram of a gate driving circuit in one embodiment of the present application;

[0041] Figure 5 This is a connection structure diagram of a pull-down unit in one embodiment of the present application;

[0042] Figure 6 This is a connection structure diagram of a pull-down maintaining unit in one embodiment of the present application;

[0043] Figure 7 1 is a timing waveform diagram of a gate driving device in one embodiment of the present application.

[0044] Explanation of the accompanying drawings: 1. Pull-up control unit; 2. Pull-up unit; 21. First driving subunit; 22. Second driving subunit; 3. Pull-down unit; 31. First pull-down subunit; 32. Second pull-down subunit; 4. Stage transmission unit; 5. Pull-down maintaining unit; 51. First pull-down maintaining subunit; 52. Second pull-down maintaining subunit. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0046] In the description of the present application, it should be understood that the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can also be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0047] First, based on the content of the background technology of the present application, the background of the present application is further explained. Figure 1 , Figure 1It is a circuit connection diagram of a gate driving device in the related art. The gate driving device in the related art includes a pull-up control module, a pull-up module and a pull-down module. Among them, the pull-up control module receives a start signal and outputs a pull-up control signal Q(n) according to the start signal; the pull-up module is electrically connected to the pull-up control module, receives the pull-up control signal Q(n), the nth level clock signal CK(n), the n+1th level clock signal CK(n+1) and the n+2th level clock signal CK(n+2), specifically, the pull-up module includes a first driving transistor T22-1, a second driving transistor T22-2 and a third driving transistor T22-3, the first driving transistor T22-1 is output according to the pull-up control signal Q The first drive transistor T22-1 is configured to output the nth level scanning drive signal G(n) according to the pull-up control signal Q(n) and the nth level clock signal CK(n), the second drive transistor T22-2 is configured to output the n+1th level scanning drive signal G(n+1) according to the pull-up control signal Q(n) and the n+1th level clock signal CK(n+1), and the third drive transistor T22-3 is configured to output the n+2th level scanning drive signal G(n+2) according to the pull-up control signal Q(n) and the n+2th level clock signal CK(n+2), thereby sequentially selecting the pixel circuits corresponding to the nth level, the n+1th level and the n+2th level. Then, the pull-down module includes a pull-down transistor T41, which pulls down the pull-up control signal Q(n) according to the n+6th level scanning drive signal G(n+6) output by the subsequent circuit, and controls the first drive transistor T22-1, the second drive transistor T22-2 and the third drive transistor T22-3 to be turned off.

[0048] However, in the above scheme, since the on and off of the first drive transistor T22-1, the second drive transistor T22-2 and the third drive transistor T22-3 are all controlled by the pull-up control signal Q(n), that is, the first drive transistor T22-1, the second drive transistor T22-2 and the third drive transistor T22-3 will be turned on and off at the same time, so that in the process of generating the n-th level scan drive signal G(n), the n+1-th level scan drive signal G(n+1) and the n+2-th level scan drive signal G(n+2) according to the clock signals of each level, the first drive transistor T22-1, the second drive transistor T22-2 and the third drive transistor T22-3 are turned on at the same time, which may easily cause clock signal writing errors or adjacent clock signals to couple with each other, resulting in abnormal generated scan drive signals, thereby causing display abnormalities. Based on this, the present application is proposed.

[0049] The driving control method in the embodiment of the present application is applied to a display panel. The display panel can be applied to a terminal with a display function, such as a mobile phone, a tablet computer, a desktop computer, an e-reader, an electronic display screen, a notebook computer, a media player, a wearable device, a digital camera, a car navigation system, etc.

[0050] Reference Figure 2 As shown, Figure 2 Schematic diagram of a display panel in an embodiment of the present application. The display panel includes a timing controller 100 (Timing Controller, TCON), a source driver 200 (Source Driver) and a gate driver 300 (Gate Driver).

[0051] The display panel has a display area 400, and the display area 400 may include a plurality of scan lines G1 to Gn, a plurality of data lines D1 to Dm intersecting the plurality of scan lines G1 to Gn, and a plurality of pixel units respectively arranged in a plurality of regions defined by the intersection of the scan lines G1 to Gn and the data lines D1 to Dm. For example, the pixel unit may include a thin film transistor (TFT), which includes a gate and a source connected to the scan line and the data line corresponding thereto, respectively. When a scan line is selected from the plurality of scan lines G1 to Gn, the thin film transistor of the pixel unit connected to the selected scan line is turned on, and then the source driving device 200 may apply a voltage to the plurality of data lines D1 to Dm, thereby displaying an image.

[0052] Among them, the timing controller 100 receives image data and control signals, and performs format conversion, data sorting and other preprocessing on the image data to obtain a data signal. At the same time, the timing controller 100 also generates a control signal and a clock signal. Then, the data signal and the control signal are sent to the source driver 200 and the gate driver 300 respectively. The gate driver 300 includes a plurality of gate driver circuits cascaded in sequence, each of which receives a control signal and a clock signal from the timing controller 100 to generate a gate driver signal for scanning line by line, and the gate driver signal is used to sequentially open and close the thin film transistor switch in the display area 400 to control the gating of the scanning line. After receiving the data signal and the control signal from the timing controller 100, the source driver 200 stores the data signal in an internal register, and outputs it synchronously according to the scanning signal of the gate driver 300.

[0053] It should be noted that Figure 2 The application scenario of the gate driving device shown is only an example. The application scenario of the gate driving device described in the embodiment of the present application is to more clearly illustrate the technical solution of the embodiment of the present application, and does not constitute a limitation on the technical solution provided in the embodiment of the present application.

[0054] Based on the application scenarios of the above-mentioned gate driving device, the present application proposes an embodiment of the gate driving device.

[0055] First, as Figure 3As shown, in one embodiment, the gate driving device provided by the present application includes a multi-stage gate driving circuit, and the gate driving circuit includes a pull-up control unit 1 and a pull-up unit 2. Among them, the pull-up control unit 1 is used to generate a pull-up control signal according to a previous stage scanning signal. The pull-up unit 2 includes at least two driving sub-units. Each driving sub-unit is connected to a different clock line, and is connected to the pull-up control unit 1 at a first node Q. Each driving sub-unit generates a driving signal according to the pull-up control signal and the clock signal output by the corresponding clock line, and outputs a scanning signal of this stage based on the driving signal.

[0056] Since each driver unit needs to be connected to a different clock line, the number of driver units included in the pull-up unit 2 is less than or equal to the number of clock lines. For example, when the gate driving device requires twelve clock lines, the pull-up unit 2 includes at most twelve driver units.

[0057] In the above implementation, firstly, by connecting a plurality of driving sub-units to the pull-up control unit 1 through the first node Q, so that all driving sub-units share the same pull-up control signal, only one pull-up control unit 1 is needed to drive a plurality of sub-units, which is helpful to realize the design of narrow frame of display panel. Secondly, each driving sub-unit is independently connected to different clock lines to receive different clock signals, so that each driving sub-unit can independently generate driving signals according to the clock signals connected to each other under the premise of sharing the same pull-up control signal, so that the generation of scanning signal is not only controlled by the clock signal, but also controlled by the driving signal, so that the current scanning signal output by each driving sub-unit can be independently controlled. In this way, each driving sub-unit can control its closure through the driving signal after outputting the current scanning signal. At this time, even if the clock line fluctuates due to the influence of coupling factors, it will not be output to the scanning line to cause display abnormality, thereby improving the display effect of the display panel.

[0058] Reference Figure 4 As an implementation of the pull-up unit 2, the pull-up unit 2 includes a first driver unit 21 and a second driver unit 22. The first driver unit 21 is connected to the first node Q, the first clock line CK1, and the n-th level scan line, generates a first drive signal according to the pull-up control signal and the first clock signal output by the first clock line CK1, and outputs the n-th level scan signal based on the first drive signal. The second driver unit 22 is connected to the first node Q, the second clock line CK2, and the n+1-th level scan line, generates a second drive signal according to the pull-up control signal and the second clock signal output by the second clock line CK2, and outputs the n+1-th level scan signal based on the second drive signal.

[0059] Wherein, n is a positive integer, and n is associated with the number of gate drive circuits in the gate drive device. For example, if the number of gate drive circuits in the gate drive device is x, then n=x*m-1; wherein m is the number of driver units included in each pull-up unit 2. For example, when the pull-up unit 2 includes two driver units, namely, a first driver unit 21 and a second driver unit 22, each level of the gate drive circuit generates two scanning signals, and for the x-th level gate drive circuit, then n=2x-1, that is, the first level gate drive circuit outputs the first level scanning signal and the second level scanning signal, and the second level gate drive circuit outputs the third level scanning signal and the fourth level scanning signal, and so on.

[0060] In the above-mentioned embodiment, firstly, the first driver unit 21 and the second driver unit 22 share the same pull-up control unit 1, and are started by the pull-up control signal generated by the previous scan signal, and there is no need to configure the pull-up control unit 1 separately for each level of scan line. Secondly, the first driver unit 21 and the second driver unit 22 are independently connected to the first clock line CK1 and the second clock line CK2, respectively, so that the drive signal generated by the first driver unit 21 according to the first clock signal only acts on the nth level scan line, and the drive signal generated by the second driver unit 22 according to the second clock signal only acts on the n+1th level scan line, and the two are independent of each other, so that the first driver unit 21 and the second driver unit 22 can independently generate the nth level and the n+1th level scan signal, thereby improving the accuracy of the output of the adjacent two levels of scan signals while achieving a narrow frame.

[0061] Reference Figure 4 As an implementation of the first driving subunit 21, the first driving subunit 21 includes a first transistor T1 and a second transistor T2. The first transistor T1 includes a first electrode connected to the first node Q, a second electrode connected to the second node q1, and a control electrode connected to the first clock line CK1. The second transistor T2 includes a first electrode connected to the first clock line CK1, a second electrode connected to the n-th level scan line, and a control electrode connected to the second node q1.

[0062] As an example, the output of the n-level scanning signal to the n-level scanning line needs to satisfy the pull-up control signal and the first clock signal to be in the valid state at the same time. In this embodiment, the valid state can be a high level state, and the invalid state can be a low level state. For example, when the first transistor T1 and the second transistor T2 are NMOS tubes, the high level state of the pull-up control signal and the first clock signal is the valid state. If only the pull-up control signal is in the valid state and the first clock signal is in the invalid state, the first transistor T1 is turned off because the first clock signal cannot provide the conduction voltage to its control electrode, so that the pull-up control signal in the valid state cannot be transmitted to the second node q1, that is, the first drive signal in the valid state cannot be generated. At this time, the second transistor T2 remains turned off and the n-level scanning signal cannot be output. If only the first clock signal is in the valid state and the pull-up control signal is invalid, the first transistor T1 can be turned on under the control of the first clock signal, but the pull-up control signal in the valid state cannot be transmitted to the second node q1, so that the first drive signal in the valid state cannot be generated, and the second transistor T2 is still turned off, and the n-level scanning signal cannot be output. Therefore, only when the pull-up control signal and the first clock signal are both in a valid state, the first transistor T1 can be turned on and output the valid pull-up control signal to the second node q1 to obtain the valid first drive signal, thereby turning on the second transistor T2 to output the nth level scan signal.

[0063] Reference Figure 4 As an implementation of the second driving subunit 22, the second driving subunit 22 includes a third transistor T3 and a fourth transistor T4. The third transistor T3 includes a first electrode connected to the first node Q, a second electrode connected to the third node q2, and a control electrode connected to the second clock line CK2. The fourth transistor T4 includes a first electrode connected to the second clock line CK2, a second electrode connected to the n+1th level scan line, and a control electrode connected to the third node q2.

[0064] As an example, the output of the n+1 level scanning signal to the n+1 level scanning line needs to satisfy the pull-up control signal and the second clock signal are in the valid state at the same time. For example, when the third transistor T3 and the fourth transistor T4 are NMOS tubes, the high level state of the pull-up control signal and the second clock signal is the valid state. If only the pull-up control signal is in the valid state and the second clock signal is in the invalid state, the third transistor T3 is turned off because the second clock signal cannot provide the conduction voltage to its control electrode, so that the pull-up control signal in the valid state cannot be transmitted to the second node q1, and thus the second drive signal in the valid state cannot be generated, and the fourth transistor T4 remains turned off, and the n+1 level scanning signal cannot be output. If only the second clock signal is in the valid state and the pull-up control signal is invalid, the third transistor T3 can be turned on under the control of the second clock signal, but the pull-up control signal in the valid state cannot be transmitted to the third node q2, and thus the second drive signal in the valid state cannot be generated, and the fourth transistor T4 is still turned off, and the n+1 level scanning signal cannot be output. Therefore, only when the pull-up control signal and the second clock signal are both in a valid state, the third transistor T3 can be turned on and output the valid pull-up control signal to the third node q2 to obtain a valid second drive signal, thereby turning on the fourth transistor T4 to output the n+1th level scan signal.

[0065] In this way, the potential of the second node q1 is jointly controlled by the potential of the first node Q and the first clock signal, and the potential of the third node q2 is jointly controlled by the potential of the first node Q and the second clock signal, and the phases of the first clock signal and the second clock signal are different, so that the potential of the second node q1 and the potential of the third node q2 can be independently controlled based on the first clock signal and the second clock signal, thereby realizing independent output of the nth level scanning signal and the n+1th level scanning signal.

[0066] Reference Figure 5 As a further implementation of the gate driving circuit, the gate driving circuit further includes a pull-down unit 3, and the pull-down unit 3 includes a plurality of pull-down sub-units corresponding to the driving sub-units. Each pull-down sub-unit is connected to a power line and a corresponding driving sub-unit, and is used to pull down the driving signal and the current level scanning signal.

[0067] In the above implementation, by providing a corresponding pull-down subunit for each driving subunit, each driving subunit can be independently pulled down, so that the n-th level scanning signal and the (n+1)-th level scanning signal can be turned off independently.

[0068] Reference Figure 5As an implementation of the pull-down unit 3, the pull-down unit 3 includes a first pull-down subunit 31 and a second pull-down subunit 32. The first pull-down subunit 31 is connected to the first driver subunit 21 at the second node q1, and is connected to the n-th level scan line and the power line, and is used to pull down the first drive signal and the n-th level scan signal. The second pull-down subunit 32 is connected to the second driver subunit 22 at the third node q2, and is connected to the n+1-th level scan line and the power line, and is used to pull down the second drive signal and the n+1-th level scan signal.

[0069] As an example, the pull-down process of two adjacent scan signals can be completed independently through the pull-down unit 3. For example, when the first pull-down subunit 31 pulls down the n-th scan signal, the internal state of the first driving subunit 21 is only affected by the second node q1, while the state of the third node q2 and the n+1-th scan signal is completely independently controlled by the second pull-down subunit 32.

[0070] In the above embodiment, the first pull-down subunit 31 is directly connected to the second node q1 of the first driver unit 21 and the n-th level scan line, and the second pull-down subunit 32 is connected to the third node q2 of the second driver unit 22 and the n+1-th level scan line, so that the first pull-down subunit 31 can pull down the second node q1 and the n-th level scan signal to the potential of the power line, and the second pull-down subunit 32 can pull down the third node q2 and the n+1-th level scan signal to the potential of the power line. Since the second node q1 and the third node q2 are independent of each other, the pull-down operations of the first driver unit 21 and the second driver unit 22 are independent of each other.

[0071] Reference Figure 5 In some embodiments, the power line includes a first power line VSSQ and a second power line VSSG. The first pull-down subunit 31 includes a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 includes a first electrode connected to the second node q1, a second electrode connected to the first power line VSSQ, and a control electrode for accessing the n+a-th level scan signal. The sixth transistor T6 includes a first electrode connected to the n-th level scan line, a second electrode connected to the second power line VSSG, and a control electrode for accessing the n+a-th level scan signal. The second pull-down subunit 32 includes a seventh transistor T7 and an eighth transistor T8. The seventh transistor T7 includes a first electrode connected to the third node q2, a second electrode connected to the first power line VSSQ, and a control electrode for accessing the n+a+1-th level scan signal. The eighth transistor T8 includes a first electrode connected to the n+1-th level scan line, a second electrode connected to the second power line VSSG, and a control electrode for accessing the n+a+1-th level scan signal.

[0072] As an example, a and n are both positive integers, a is associated with the number of clock lines and the stage transmission architecture of the gate driving device, and a may be half of the number of clock lines. For example, when the number of clock lines b=12, a may be 6.

[0073] As an example, when the n+a-th level scan signal is in an effective state, the fifth transistor T5 and the sixth transistor T6 are turned on synchronously. After the fifth transistor T5 is turned on, the second node q1 is connected to the first power line VSSQ, which pulls the potential of the second node q1 down to the potential of the first power line VSSQ, so that the second transistor T2 is turned off, cutting off the physical connection between the first clock signal and the n-th level scan line, and stopping the output of the n-th level scan signal. After the sixth transistor T6 is turned on, the n-th level scan line is connected to the second power line VSSG, and the residual charge on the n-th level scan line is quickly released to the second power line VSSG, so that the n-th level scan signal is pulled down to the potential of the second power line VSSG, thereby improving the reset speed of the n-th level scan signal. Similarly, when the n+a+1-th level scan signal is in an effective state, the seventh transistor T7 and the eighth transistor T8 are turned on synchronously. After the seventh transistor T7 is turned on, the third node q2 is connected to the first power line VSSQ, so that the potential of the third node q2 is pulled down to the potential of the first power line VSSQ, so that the fourth transistor T4 is turned off, the physical connection between the second clock signal and the n+1th level scan line is cut off, and the output of the n+1th level scan signal is stopped. After the eighth transistor T8 is turned on, the n+1th level scan line is connected to the second power line VSSG, and the residual charge on the n+1th level scan line is quickly released to the second power line VSSG, so that the n+1th level scan signal is pulled down to the potential of the second power line VSSG, thereby improving the reset speed of the n+1th level scan signal.

[0074] The fifth transistor T5 and the sixth transistor T6 are turned on by the n+a-th level scan signal to pull down the second node q1, and the seventh transistor T7 and the eighth transistor T8 are turned on by the n+a+1-th level scan signal to pull down the third node q2, thereby realizing the independent pull-down of the second node q1 and the third node q2 without affecting the high level of the first node Q. In this way, the mutual independence between the first node Q, the second node q1 and the third node q2 is realized.

[0075] Reference Figure 5 and Figure 6 As shown, as an implementation of the pull-up control unit 1, the pull-up control unit 1 includes an eleventh transistor T11, the eleventh transistor T11 includes a control electrode for accessing a previous stage transmission signal, a first electrode for accessing a previous stage scanning signal, and a second electrode connected to the first node Q.

[0076] As an example, when the previous stage transfer signal and the previous stage scanning signal are both in the valid state, the eleventh transistor T11 is turned on and outputs the pull-up control signal in the valid state to the first node Q.

[0077] As a further implementation of the gate drive circuit, the gate drive circuit also includes a stage transmission unit 4, which is connected to each clock line and the first node Q, and is used to output the stage transmission signal of this stage according to the pull-up control signal and each clock signal, and transmit it to the subsequent stage circuit of the gate drive circuit.

[0078] The subsequent circuit is a subsequent stage or multiple subsequent stages of the gate driving circuit of the current stage, and outputs the current stage stage transmission signal to the pull-up control unit 1 of the subsequent circuit.

[0079] As an implementation of the stage transmission unit 4, the stage transmission unit 4 includes a ninth transistor T9, wherein the ninth transistor T9 includes a first electrode connected to the first clock line CK1, a second electrode for outputting the stage transmission signal of the current stage, and a control electrode connected to the first node Q.

[0080] In the above implementation, the ninth transistor T9 is turned on based on the pull-up control signal. When the first clock signal outputted by the first clock line CK1 is in a valid state, the ninth transistor T9 outputs the level transfer signal of this level so as to complete the output of multi-level scanning signals by each driving sub-unit.

[0081] Reference Figure 4 As a further implementation of the gate driving circuit, the gate driving circuit further includes a reset transistor T10, which includes a control electrode for accessing a reset control signal Reset, a first electrode connected to the first node Q, and a second electrode connected to the first power line VSSQ.

[0082] As an example, at the beginning of each frame, the first touch control reset transistor T10 may be turned on by controlling the reset control signal Reset, thereby achieving an effect of resetting the potential of the first node.

[0083] Reference Figure 6 The gate driving circuit further includes a pull-down maintaining unit 5 , and the pull-down maintaining unit 5 may include a first pull-down maintaining sub-unit 51 and a second pull-down maintaining sub-unit 52 .

[0084] As an example, the first pull-down maintaining subunit 51 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, and a twenty-first transistor T21. Among them, the first electrode and the control electrode of the twelfth transistor T12 are connected to the first low-frequency control line; the first electrode of the thirteenth transistor T13 is connected to the second electrode of the twelfth transistor T12, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the second electrode of the eleventh transistor T11; the first electrode of the fourteenth transistor T14 is connected to the second electrode of the twelfth transistor T12, the control electrode is used to access the pull-up control signal of the previous stage, and the second electrode is connected to the first power line VSSQ; the first electrode of the fifteenth transistor T15 is connected to the first low-frequency control line, the control electrode is connected to the second electrode of the twelfth transistor T12 The first electrode of the sixteenth transistor T16 is connected to the second electrode of the fifteenth transistor T15, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the control electrode of the thirteenth transistor T13; the first electrode of the seventeenth transistor T17 is connected to the second electrode of the fifteenth transistor T15, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the control electrode of the fourteenth transistor T14; the control electrode of the eighteenth transistor T18 is connected to the second electrode of the fifteenth transistor T15, the first electrode is connected to the second electrode of the eleventh transistor T11, and the second electrode is connected to the second power line VSSG. The control electrode of the nineteenth transistor T19 is connected to the second electrode of the fifteenth transistor T15, the first electrode is connected to the n+1th level scan line, and the second electrode is connected to the second power line VSSG; the control electrode of the twentieth transistor T20 is connected to the second electrode of the fifteenth transistor T15, the first electrode is connected to the nth level scan line, and the second electrode is connected to the first power line VSSQ; the control electrode of the twenty-first transistor T21 is connected to the second electrode of the fifteenth transistor T15, the first electrode is connected to the ninth transistor T9 and the tenth transistor T10, and the second electrode is connected to the first power line VSSQ.

[0085] Among them, by controlling the fourteenth transistor T14 and the seventeenth transistor T17 to be turned on, the potential of the second electrode of the twelfth transistor T12 is pulled to the potential of the first power line VSSQ, thereby turning on the fifteenth transistor T15, and generating a first pull-down maintenance signal at the second electrode of the fifteenth transistor T15, so that the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20 and the twenty-first transistor T21 are turned on according to the first pull-down maintenance signal, thereby realizing the pull-down maintenance of the first node Q, the n+1th level scan signal, the nth level scan signal and the level transfer signal of the current level.

[0086] As an example, the second pull-down maintaining subunit 52 includes a twenty-second transistor T22, a twenty-third transistor T23, a twenty-fourth transistor T24, a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, a twenty-eighth transistor T28, a twenty-ninth transistor T29, a thirtieth transistor T30, and a thirty-first transistor T31. Among them, the first electrode and the control electrode of the twenty-second transistor T22 are connected to the second low-frequency control line; the first electrode of the twenty-third transistor T23 is connected to the second electrode of the twenty-second transistor T22, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the second electrode of the eleventh transistor T11; the first electrode of the twenty-fourth transistor T24 is connected to the second electrode of the twenty-second transistor T22, the control electrode is used to access the pull-up control signal of the previous stage, and the second electrode is connected to the first power line VSSQ; the first electrode of the twenty-fifth transistor T25 is connected to the second low-frequency control line, the control electrode is connected to the second electrode of the twenty-second transistor T22 The first electrode of the twenty-sixth transistor T26 is connected to the second electrode of the twenty-fifth transistor T25, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the control electrode of the twenty-third transistor T23; the first electrode of the twenty-seventh transistor T27 is connected to the second electrode of the twenty-fifth transistor T25, the second electrode is connected to the first power line VSSQ, and the control electrode is connected to the control electrode of the twenty-fourth transistor T24; the control electrode of the twenty-eighth transistor T28 is connected to the second electrode of the twenty-fifth transistor T25, the first electrode is connected to the second electrode of the eleventh transistor T11, and the second electrode is connected to the second power line VSSG. The control electrode of the twenty-ninth transistor T29 is connected to the second electrode of the twenty-fifth transistor T25, the first electrode is connected to the n+1th level scan line, and the second electrode is connected to the second power line VSSG; the control electrode of the thirtieth transistor T30 is connected to the second electrode of the twenty-fifth transistor T25, the first electrode is connected to the nth level scan line, and the second electrode is connected to the first power line VSSQ; the control electrode of the thirty-first transistor T31 is connected to the second electrode of the twenty-fifth transistor T25, the first electrode is connected to the ninth transistor T9 and the tenth transistor T10, and the second electrode is connected to the first power line VSSQ.

[0087] Among them, by controlling the twenty-fourth transistor T24 and the twenty-seventh transistor T27 to be turned on, the potential of the second electrode of the twenty-second transistor T22 is pulled to the potential of the first power line VSSQ, thereby turning on the twenty-fifth transistor T25, and generating a first pull-down maintenance signal at the second electrode of the twenty-fifth transistor T25, so that the twenty-eighth transistor T28, the twenty-ninth transistor T29, the thirtieth transistor T30 and the thirty-first transistor T31 are turned on according to the first pull-down maintenance signal, thereby realizing the pull-down maintenance of the first node Q, the n+1th level scan signal, the nth level scan signal and the level transfer signal of the current level respectively.

[0088] The first low-frequency control line is used to transmit a first low-frequency control signal LC1, and the second low-frequency control line is used to transmit a second low-frequency control signal LC2. Figure 7 The first low frequency control signal LC1 and the second low frequency control signal LC2 have opposite phases. If the first low frequency control signal LC1 is high, the second low frequency control signal LC2 is low. Alternatively, if the first low frequency control signal LC1 is low, the second low frequency control signal LC2 is high.

[0089] As an example, taking the above-mentioned transistors as N-type transistors, when the second low-frequency control signal LC2 is at a high level, the second maintenance subunit works to pull down and maintain the first node Q, the n+1th level scan signal, the nth level scan signal, and the level transmission signal of the current level. When the first low-frequency control signal LC1 is at a high level, the first maintenance subunit works to pull down and maintain the first node Q, the n+1th level scan signal, the nth level scan signal, and the level transmission signal of the current level. By reversing the phase of the first low-frequency control signal LC1 and the second low-frequency control signal LC2, for example, the first low-frequency control signal LC1 and the second low-frequency control signal LC2 can be set to reverse once every 1.67 seconds, so that the first pull-down maintenance subunit 51 and the second pull-down maintenance subunit 52 work alternately, so as to jointly realize the pull-down maintenance of the first node Q, the n+1th level scan signal, the nth level scan signal, and the level transmission signal of the current level.

[0090] Reference Figure 7 , Figure 7It is a working timing diagram of the gate driving device. Taking the Nth frame image as an example, first, the first clock signal enters the effective state first, the first driving subunit 21 first outputs the nth level scanning signal, and then, the first driving subunit 21 is pulled down by the first pull-down subunit 31 to stop outputting the nth level scanning signal. When the second clock signal is in the effective state, the second driving subunit 22 outputs the n+1th level scanning signal, and then, the second driving subunit 21 is pulled down by the second pull-down subunit 32 to stop outputting the n+1th level scanning signal. By analogy, the clock lines CK3-CK12 respectively control the gate driving circuits of different levels in the gate driving device to output corresponding scanning signals in sequence until all pixel rows of the frame image are selected.

[0091] It should be noted that, in this embodiment, the first electrode may be one of the source electrode and the drain electrode, and the second electrode may be the other of the source electrode and the drain electrode. For example, when the first electrode is the source electrode, the second electrode is the drain electrode; or when the first electrode is the drain electrode, the second electrode is the source electrode.

[0092] In a second aspect, in one embodiment, the present application provides a display panel, including: a gate driving device as described above.

[0093] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0094] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0095] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A gate driving device, comprising a multi-stage gate driving circuit, characterized in that: The gate drive circuit comprises: A pull-up control unit, used for generating a pull-up control signal according to a previous scanning signal; The pull-up unit includes at least two driving sub-units; each of the driving sub-units is connected to a different clock line, and is connected to the pull-up control unit at a first node; each of the driving sub-units generates a driving signal according to the pull-up control signal and a clock signal output by the corresponding clock line, and outputs a scanning signal of this level based on the driving signal.

2. The gate driving device according to claim 1, characterized in that: The pull-up unit includes a first driving subunit and a second driving subunit; The first driving subunit is connected to the first node, the first clock line and the n-th level scan line, generates a first driving signal according to the pull-up control signal and a first clock signal output by the first clock line, and outputs an n-th level scan signal based on the first driving signal; The second driving subunit is connected to the first node, the second clock line and the n+1th level scan line, generates a second driving signal according to the pull-up control signal and a second clock signal output by the second clock line, and outputs the n+1th level scan signal based on the second driving signal; The n is associated with the number of stages of the gate driving circuit in the gate driving device.

3. The gate driving device according to claim 2, characterized in that: The first driving subunit includes a first transistor and a second transistor; The first transistor includes a first electrode connected to the first node, a second electrode connected to the second node, and a control electrode connected to the first clock line; The second transistor includes a first electrode connected to the first clock line, a second electrode connected to the n-th level scan line, and a control electrode connected to the second node.

4. The gate driving device according to claim 3, characterized in that: The second driving subunit includes a third transistor and a fourth transistor; The third transistor includes a first electrode connected to the first node, a second electrode connected to the third node, and a control electrode connected to the second clock line; The fourth transistor includes a first electrode connected to the second clock line, a second electrode connected to the n+1th stage scan line, and a control electrode connected to the third node.

5. The gate driving device according to claim 4, characterized in that: It also includes a pull-down unit, wherein the pull-down unit includes a plurality of pull-down sub-units corresponding to the driving sub-unit; Each pull-down subunit is connected to a power line and a corresponding one of the driving subunits, and is used to pull down the driving signal and the current-stage scanning signal.

6. The gate driving device according to claim 5, characterized in that: The pull-down unit includes a first pull-down sub-unit and a second pull-down sub-unit; The first pull-down subunit and the first driving subunit are connected to the second node, and are connected to the n-th level scanning line and the power line, and are used to pull down the first driving signal and the n-th level scanning signal; The second pull-down subunit and the second driving subunit are connected to the third node and are connected to the n+1th level scanning line and the power line, and are used to pull down the second driving signal and the n+1th level scanning signal.

7. The gate driving device according to claim 6, characterized in that: The power cord includes a first power cord and a second power cord; The first pull-down subunit includes a fifth transistor and a sixth transistor; The fifth transistor comprises a first electrode connected to the second node, a second electrode connected to the first power line, and a control electrode for connecting to the n+ath level scanning signal; The sixth transistor comprises a first electrode connected to the n-th level scan line, a second electrode connected to the second power line, and a control electrode for connecting to the n+a-th level scan signal; The second pull-down subunit includes a seventh transistor and an eighth transistor; The seventh transistor comprises a first electrode connected to the third node, a second electrode connected to the first power line, and a control electrode for connecting to the n+a+1th level scanning signal; The eighth transistor includes a first electrode connected to the n+1th level scan line, a second electrode connected to the second power line, and a control electrode for accessing the n+a+1th level scan signal connection.

8. The gate driving device according to claim 3, characterized in that: It also includes a stage transmission unit connected to each of the clock lines and the first node, and is used to output the stage transmission signal of the current stage according to the pull-up control signal and each of the clock signals, and transmit it to the subsequent stage circuit of the gate drive circuit.

9. The gate driving device according to claim 8, characterized in that: The stage transmission unit includes a ninth transistor; The ninth transistor includes a first electrode connected to the first clock line, a second electrode for outputting the stage transfer signal of the current stage, and a control electrode connected to the first node.

10. A display panel, characterized in that: Comprising the gate driving device as described in any one of claims 1 to 9.

Images