A display panel and display device

Abstract

This invention discloses a display panel and a display device. The display panel includes: a first driving circuit, which includes a multi-stage shift register; the shift register includes: a first shift control module electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node; a second shift control module electrically connected to the input terminal, the first clock terminal, the first node, the second power supply terminal, and a fourth node; a shift output module electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and the shift output terminal; and a potential control module electrically connected to the third node, the second clock terminal, and the second node. In this invention, adding a potential control module to the shift register helps ensure the effectiveness, accuracy, and stability of the shift register's output, thereby improving the display quality of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Display panels typically have multiple pixels. A driving circuit scans each pixel line by line, allowing data signals to be written into each pixel line by line. This enables each pixel to emit light based on the received data signals, thus presenting the corresponding display image.

[0003] Typically, a driver circuit contains cascaded multi-stage shift registers. By controlling the signals of the corresponding nodes in each stage of the shift register, the gate drive signals output by the shift register can be controlled.

[0004] However, some nodes in the shift register are currently experiencing leakage current, which affects the accuracy of the gate drive signal output by the shift register, and consequently affects the display quality of the display panel. Summary of the Invention

[0005] The present invention provides a display panel and a display device to improve the output stability of a shift register.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a first driving circuit, the first driving circuit including a multi-stage shift register;

[0007] The shift register includes:

[0008] The first shift control module is electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node, and is used to control the signals of the first node, the second node, and the third node.

[0009] The second shift control module is electrically connected to the input terminal, the first clock terminal, the first node, the second power supply terminal, and the fourth node, and is used to control the signal of the fourth node;

[0010] The shift output module is electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and the shift output terminal, and is used to control the shift output terminal to output a shift signal;

[0011] The potential control module is electrically connected to the third node, the second clock terminal, and the second node, and is used to control the signal of the second node.

[0012] According to another aspect of the present invention, a display device is provided, comprising: a display panel as described above.

[0013] In this invention, a potential control module is added to the shift register. This module receives a second clock signal from a second clock input, which has periodic high-to-low level transitions. The potential control module controls the signal of the second node based on the second clock signal and the signal of the third node, thereby enhancing the voltage holding capability of the second node. Especially when the shift register operates in low-frequency mode, the second node may operate at a low or high level for extended periods. The periodic high-to-low level transitions of the second clock signal can periodically couple the second node, enhancing its voltage holding capability and ensuring it remains at the required voltage level. This reduces leakage current and helps guarantee the effectiveness, accuracy, and stability of the shift register's output, ultimately improving the display quality of the display panel.

[0014] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 This is a schematic diagram of a first driving circuit provided in an embodiment of the present invention;

[0018] Figure 3 This is a schematic diagram of a shift register provided in an embodiment of the present invention;

[0019] Figure 4 This is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram of a shift register provided by a proportional method;

[0022] Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0023] Figure 8 yes Figure 7 The timing diagram of the shift register shown is shown below.

[0024] Figure 9 This is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0025] Figure 10 yes Figure 9 The timing diagram of the shift register shown is shown below.

[0026] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0027] Figure 12 yes Figure 11 The following is a timing diagram of the low-frequency operation of the shift register in the first display partition;

[0028] Figure 13 yes Figure 11 The second display partition shows the high-frequency operating timing diagram of the shift register;

[0029] Figure 14 This is a schematic diagram of the refresh output section in another shift register provided by an embodiment of the present invention;

[0030] Figure 15 yes Figure 14 The following is a timing diagram of the low-frequency operation of the shift register in the first display partition;

[0031] Figure 16 yes Figure 14 The second display partition shows the high-frequency operating timing diagram of the shift register;

[0032] Figure 17 This is a schematic diagram of the refresh output section in another shift register provided by an embodiment of the present invention;

[0033] Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a first driving circuit provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a shift register provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of another shift register provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figures 1 to 5 As shown, the display panel 10 includes: a first driving circuit 11, which includes a multi-stage shift register 12; the shift register 12 includes: a first shift control module 110, electrically connected to input terminal IN, first clock terminal CK, first power supply terminal VG1, first node N1, second node N2 and third node N3, for controlling the signals of the first node N1, the second node N2 and the third node N3; a second shift control module 120, electrically connected to input terminal IN, first clock terminal CK, first node N1, second power supply terminal VG2 and fourth node N4, for controlling the signal of the fourth node N4; a shift output module 130, electrically connected to the fourth node N4, second node N2, first power supply terminal VG1, second power supply terminal VG2 and shift output terminal NEXT, for controlling the shift output terminal NEXT to output a shift signal; and a potential control module 140, electrically connected to the third node N3, second clock terminal XCK and second node N2, for controlling the signal of the second node N2.

[0037] In this embodiment, the shift register 12 includes a first shift control module 110. The first shift control module 110 is electrically connected to the input terminal IN to receive the input signal provided by the input terminal IN; the first shift control module 110 is electrically connected to the first clock terminal CK to receive the first clock signal provided by the first clock terminal CK; the first shift control module 110 is electrically connected to the first power supply terminal VG1 to receive the first power supply signal provided by the first power supply terminal VG1. The first shift control module 110 is also electrically connected to a first node N1, a second node N2, and a third node N3. Based on the input signal provided by the input terminal IN, the first clock signal provided by the first clock terminal CK, and the first power supply signal provided by the first power supply terminal VG1, the first shift control module 110 controls the signals of the first node N1, the second node N2, and the third node N3, causing the signals of the first node N1, the second node N2, and the third node N3 to undergo high-low level transitions.

[0038] The shift register 12 includes a second shift control module 120. A second power supply terminal VG2 provides a second power signal, which differs from the first power supply terminal VG1. One of the second power signal and the first power signal is low, while the other is high. The second shift control module 120 controls the signal of the fourth node N4 based on the input signal provided by the input terminal IN, the first clock signal, the signal of the first node N1, and the second power signal, causing the signal of the fourth node N4 to transition between high and low levels.

[0039] The shift register 12 includes a potential control module 140. A second clock signal, XCK, is provided by the second clock terminal, which differs from the first clock signal provided by the first clock terminal CK. The second clock signal from XCK undergoes periodic high-low level transitions, while the first clock signal from CK undergoes periodic high-low level transitions. Optionally, the second clock signal and the first clock signal may have the same frequency but different phases. The potential control module 140 controls the signal of the second node N2 based on the signal from the third node N3 and the second clock signal from XCK, causing the signal of the second node N2 to undergo high-low level transitions.

[0040] The shift register 12 includes a shift output module 130. The shift output module 130 controls the shift output terminal NEXT to output a shift signal based on the signal of the fourth node N4, the signal of the second node N2, the first power supply signal of the first power supply terminal VG1, and the second power supply signal of the second power supply terminal VG2. The shift signal includes an active level and an inactive level, one of which is high and the other is low.

[0041] Optional, see reference Figures 1 to 2As shown, the display panel 10 may also include multiple signal lines 20 for providing signals to the first driving circuit 11. For example, the multiple signal lines 20 of the display panel 10 may include at least an input signal line STV, a first clock signal line CKL1, a second clock signal line CKL2, a first power signal line VL1, and a second power signal line VL2; the input signal line STV provides an input signal to the input terminal IN of at least one shift register 12; the first clock signal line CKL1 and the second clock signal line CKL2 respectively provide a first clock signal to the first clock terminal CK of the shift register 12 and a second clock signal to the second clock terminal XCK of the shift register 12; the first power signal line VL1 provides a first power signal to the first power terminal VG1 of the shift register 12; and the second power signal line VL2 provides a second power signal to the second power terminal VG2 of the shift register 12. The display panel 10 may also include multiple other types of signal lines 20, which will not be described in detail here.

[0042] refer to Figure 2 As shown, the shift output terminal NEXT of the i-th stage shift register 12 / Gi can be electrically connected to the input terminal IN of the (i+m)-th stage shift register 12, where m=1. Then, the shift output terminal NEXT of the i-th stage shift register 12 / Gi can be electrically connected to the input terminal IN of the (i+1)-th stage shift register 12 / G(i+1). In other embodiments, the shift output terminal of the i-th stage shift register can also be electrically connected to the input terminal IN of the (i+m)-th stage shift register, where m can be an integer greater than 1, such as m=2, m=3, m=4, or m equal to other positive integers, and is not limited to any particular type. Figure 2 The m=1 shown.

[0043] refer to Figure 4 and Figure 5As shown, the optional shift output module 130 includes: a first output submodule 131 and a second output submodule 132; the first output submodule 131 is electrically connected to the fourth node N4, the second power supply terminal VG2, and the shift output terminal NEXT, and is used to control the shift output terminal NEXT to output a shift signal; the second output submodule 132 is electrically connected to the second node N2, the first power supply terminal VG1, and the shift output terminal NEXT, and is used to control the shift output terminal NEXT to output a shift signal. The optional first output submodule 131 includes: an eleventh transistor M11 and a third capacitor Ca3; the gate of the eleventh transistor M11 is electrically connected to the fourth node N4, the first terminal of the eleventh transistor M11 is electrically connected to the second power supply terminal VG2, and the second terminal of the eleventh transistor M11 is electrically connected to the shift output terminal NEXT; the first plate of the third capacitor Ca3 is electrically connected to the fourth node N4, and the second plate of the third capacitor Ca3 is electrically connected to the second power supply terminal VG2. The optional second output submodule 132 includes: a twelfth transistor M12; the gate of the twelfth transistor M12 is electrically connected to the second node N2, the first terminal of the twelfth transistor M12 is electrically connected to the first power supply terminal VG1, and the second terminal of the twelfth transistor M12 is electrically connected to the shift output terminal NEXT. (See reference) Figure 5 As shown, the optional second output submodule 132 includes: a fourth capacitor Ca4; the first plate of the fourth capacitor Ca4 is electrically connected to the second node N2, and the second plate of the fourth capacitor Ca4 is electrically connected to the shift output terminal NEXT.

[0044] In this embodiment, the shift output module 130 includes a first output submodule 131. Optionally, the first output submodule 131 includes an eleventh transistor M11 and a third capacitor Ca3. The gate of the eleventh transistor M11 is electrically connected to a fourth node N4. When the signal from the fourth node N4 controls the eleventh transistor M11 to turn on, the second power signal provided by the second power supply terminal VG2 is written to the shift output terminal NEXT through the turned-on eleventh transistor M11. The shift output module 130 also includes a second output submodule 132. Optionally, the second output submodule 132 includes a twelfth transistor M12. The gate of the twelfth transistor M12 is electrically connected to a second node N2. When the signal from the second node N2 controls the twelfth transistor M12 to turn on, the first power signal provided by the first power supply terminal VG1 is written to the shift output terminal NEXT through the turned-on twelfth transistor M12.

[0045] The first output submodule 131 and the second output submodule 132 in the shift output module 130 are turned on in a time-sharing manner.

[0046] Optionally, both the eleventh transistor M11 and the twelfth transistor M12 can be PMOS, with the second power supply signal being high (vgh) and the first power supply signal being low (vgl). Based on this, when the signal at the second node N2 is high, and the signal at the fourth node N4 transitions from high to low, the eleventh transistor M11 turns on and the twelfth transistor M12 turns off. The high level (vgh) provided by the second power supply terminal VG2 is transmitted and written to the shift output terminal NEXT through the turned-on eleventh transistor M11. Alternatively, when the signal at the fourth node N4 is high, and the signal at the second node N2 transitions from high to low, the eleventh transistor M11 turns off and the twelfth transistor M12 turns on. The low level (vgl) provided by the first power supply terminal VG1 is transmitted and written to the shift output terminal NEXT through the turned-on twelfth transistor M12.

[0047] In other embodiments, at least one of the eleventh and twelfth transistors may be an NMOS transistor, and the high and low levels of the power signals provided by the first and second power supply terminals in the corresponding shift output module can be adaptively adjusted, and are not limited to... Figure 4 or Figure 5 As shown.

[0048] Figure 6 This is a schematic diagram of a shift register provided by a proportional method, and... Figure 5 compared to, Figure 6 The shift register 12a does not have a bit control module 140 set, and correspondingly, the shift register 12a does not have a third node set. Figure 6 In the shift register 12a, the valid level of the NEXT shift output is high (vgh) and the invalid level is low. When the shift register 12a outputs an invalid level (vgl), the low level of the NEXT shift output is coupled through the fourth capacitor Ca4, making the potential of the second node N2 sufficiently low, thereby ensuring that the shift register 12a can output a low level (vgl) normally.

[0049] Figure 6 In the shift register 12a, when operating in low-frequency mode, specifically during the data holding phase, the second node N2 is at a low level to ensure that the shift output NEXT remains at a low level (vgl) for an extended period. However, in practice, the low level of the second node N2 gradually increases due to leakage current, which may cause the low level of the shift output NEXT to rise, resulting in abnormal output of the shift register 12a. Even if the fourth capacitor Ca4 is increased to enhance the voltage holding capability of the second node N2, the leakage current of the second node N2 increases during the long data holding phase, causing the low level of the second node N2 to still rise, thus resulting in abnormal output of the shift register 12a.

[0050] In this embodiment, a potential control module 140 is added between the third node N3 and the second node N2. The potential control module 140 controls the signal of the second node N2 based on the signal of the third node N3 and the second clock signal provided by the second clock terminal XCK. This avoids the problem of abnormal output caused by leakage current in the second node N2.

[0051] refer to Figure 4 As shown, when shift register 12 is in the data holding phase and the second node N2 is low, the shift output terminal NEXT of shift register 12 outputs the first power supply signal vgl.

[0052] After the second clock signal provided by the second clock terminal XCK jumps from low level to high level, the control potential control module 140 is turned off. At this time, the turned-off potential control module 140 blocks the second clock terminal XCK and the second node N2. Therefore, the high level of the second clock signal will not affect the signal of the second node N2, and the second node N2 remains at a low level.

[0053] After the second clock signal provided by the second clock terminal XCK jumps from high level to low level, the control potential control module 140 is turned on. At this time, the turned-on potential control module 140 connects the second clock terminal XCK and the second node N2. Then, the low level of the second clock signal pulls the signal of the second node N2 low through coupling, so that the second node N2 is kept at a low level.

[0054] Therefore, in this embodiment, a potential control module 140 is provided so that the periodic high-low level transitions of the second clock signal can periodically couple the second node N2. During the data holding phase, the second node N2 can be kept at a low level, avoiding the problem that the low level of the second node N2 will gradually rise due to leakage. This ensures that the output of the shift output terminal NEXT is normal, especially when the shift register 12 is working in low-frequency mode. Setting the potential control module 140 can ensure that the output of the shift output terminal NEXT is normal.

[0055] Furthermore, Figure 5 Adding a fourth capacitor Ca4 can further enhance the voltage holding capability of the second node N2. It is understood that in this embodiment of the invention, the shift register 12 may or may not include the fourth capacitor Ca4.

[0056] Similarly, in other embodiments, assuming the twelfth transistor is an NMOS, by setting a potential control module, the periodic high and low level transitions of the second clock signal can periodically couple the second node. In this way, the second node can be kept at a high level during the data holding phase, avoiding the problem that the high level of the second node will gradually decrease due to leakage. This ensures that the output of the shift output terminal is normal.

[0057] In this invention, a potential control module is added to the shift register. This module receives a second clock signal from a second clock input, which has periodic high-to-low level transitions. The potential control module controls the signal of the second node based on the second clock signal and the signal of the third node, thereby enhancing the voltage holding capability of the second node. Especially when the shift register operates in low-frequency mode, the second node may operate at a low or high level for extended periods. The periodic high-to-low level transitions of the second clock signal can periodically couple the second node, enhancing its voltage holding capability and ensuring it remains at the required voltage level. This reduces leakage current and helps guarantee the effectiveness, accuracy, and stability of the shift register's output, ultimately improving the display quality of the display panel.

[0058] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0059] refer to Figures 3 to 5 As shown, in the display panel 10, the shift register 12 includes a first shift control module 110, a second shift control module 120, and a shift output module 130. These three modules constitute the shift output section of the shift register 12. The shift output section includes an input terminal IN and a shift output terminal NEXT, used to control the shift output terminal NEXT to output a shift signal. The shift signal includes valid and invalid levels. The structural configuration of the first shift control module 110, the second shift control module 120, and the shift output module 130 in the shift register 12 of the display panel 10 can be varied. For example, the structure of the first shift control module 110, the second shift control module 120, and the shift output module 130 can be "p*T+k*C", where "T" represents a transistor, "C" represents a storage capacitor, and p and k are constants. For example, if p is 9 and k is 2, then the structure of the first shift control module 110, the second shift control module 120, and the shift output module 130 includes 9 transistors and 2 capacitors, but p and k are not limited to these; for example, p is 7 and k is 2; and so on. In the various embodiments below, the structure of the first shift control module 110, the second shift control module 120, and the shift output module 130 is not specifically limited, and those skilled in the art can make adaptive adjustments to the shift output section according to their needs, and it is not limited to the following figures.

[0060] Figure 7This is a schematic diagram of another shift register provided in an embodiment of the present invention. An optional first shift control module 110 includes: a first shift control submodule 111 and a second shift control submodule 112. The first shift control submodule 111 is electrically connected to an input terminal IN, a first clock terminal CK, a first power supply terminal VG1, a first node N1, and a second node N2, and is used to control the signals of the first node N1 and the second node N2. The second shift control submodule 112 is electrically connected to an input terminal IN, a first clock terminal CK, a first power supply terminal VG1, and a third node N3, and is used to control the signals of the third node N3. The optional first shift control submodule 111 includes: a fourth transistor M4 and a fifth transistor M5. The gate of the fourth transistor M4 is electrically connected to the first clock terminal CK, the first terminal of the fourth transistor M4 is electrically connected to the input terminal IN, and the second terminal of the fourth transistor M4 is electrically connected to the first node N1. The gate of the fifth transistor M5 is electrically connected to the first power supply terminal VG1, the first terminal of the fifth transistor M5 is electrically connected to the first node N1, and the second terminal of the fifth transistor M5 is electrically connected to the second node N2. The second shift control submodule 112 includes: a sixth transistor M6 and a seventh transistor M7; the gate of the sixth transistor M6 is electrically connected to the first clock terminal CK, the first terminal of the sixth transistor M6 is electrically connected to the input terminal IN, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the seventh transistor M7; the gate of the seventh transistor M7 is electrically connected to the first power supply terminal VG1, and the second terminal of the seventh transistor M7 is electrically connected to the third node N3.

[0061] In this embodiment, the first clock signal provided by the first clock terminal CK controls the fourth transistor M4 and the sixth transistor M6 to be turned on or off simultaneously. When the first clock signal provided by the first clock terminal CK controls the fourth transistor M4 and the sixth transistor M6 to be turned on simultaneously, the input signal provided by the input terminal IN is written to the first node N1 through the turned-on fourth transistor M4, and the input signal provided by the input terminal IN is transmitted to the seventh transistor M7 through the turned-on sixth transistor M6.

[0062] The first power signal provided by the first power supply terminal VG1 controls both the fifth transistor M5 and the seventh transistor M7 to remain on. Then, the signal of the first node N1 is written to the second node N2 through the on fifth transistor M5, and the signal at the output terminal of the sixth transistor M6 is transmitted to the third node N3 through the seventh transistor M7.

[0063] The optional second shift control module 120 includes: a third shift control submodule 121 and a fourth shift control submodule 122; the third shift control submodule 121 is electrically connected to the input terminal IN, the second power supply terminal VG2, and the sixth node N6, and is used to control the signal of the sixth node N6; the fourth shift control submodule 122 is electrically connected to the sixth node N6, the first clock terminal CK, the second power supply terminal VG2, the first node N1, and the fourth node N4, and is used to control the signal of the fourth node N4. The optional third shift control submodule 121 includes: an eighth transistor M8; the gate of the eighth transistor M8 is electrically connected to the input terminal IN, the first terminal of the eighth transistor M8 is electrically connected to the second power supply terminal VG2, and the second terminal of the eighth transistor M8 is electrically connected to the sixth node N6. The optional fourth shift control submodule 122 includes: a ninth transistor M9 and a tenth transistor M10; the gate of the ninth transistor M9 is electrically connected to the sixth node N6, the first terminal of the ninth transistor M9 is electrically connected to the first clock terminal CK, and the second terminal of the ninth transistor M9 is electrically connected to the fourth node N4; the gate of the tenth transistor M10 is electrically connected to the first node N1, the first terminal of the tenth transistor M10 is electrically connected to the second power supply terminal VG2, and the second terminal of the tenth transistor M10 is electrically connected to the fourth node N4. The fourth shift control submodule 122 includes: a second capacitor Ca2; the first plate of the second capacitor Ca2 is electrically connected to the sixth node N6, and the second plate of the second capacitor Ca2 is electrically connected to the first clock terminal CK.

[0064] In this embodiment, the input signal provided by the input terminal IN controls the eighth transistor M8 to turn on or off. When the input signal provided by the input terminal IN controls the eighth transistor M8 to turn on, the second power supply signal provided by the second power supply terminal VG2 is transmitted to the sixth node N6 through the turned-on eighth transistor M8.

[0065] The signal from node N6 controls the ninth transistor M9 to turn on or off. When the signal from node N6 controls the ninth transistor M9 to turn on, the first clock signal provided by the first clock terminal CK is written to node N4. The signal from node N1 controls the tenth transistor M10 to turn on or off. When the signal from node N1 controls the tenth transistor M10 to turn on, the second power signal provided by the second power terminal VG2 is transmitted to node N4 through the turned-on tenth transistor M10.

[0066] The optional potential control module 140 includes: a first electrical control submodule 141 and a second electrical control submodule 142; the first electrical control submodule 141 is electrically connected to the second clock terminal XCK and the third node N3, and is used to control the signal of the third node N3; the second electrical control submodule 142 is electrically connected to the third node N3 and the second node N2, and is used to control the signal of the second node N2.

[0067] Optional first electronic control submodule 141 includes: a first electronic control unit 141a and a first coupling unit 141b; the first electronic control unit 141a is electrically connected to the second clock terminal XCK, the third node N3, and the fifth node N5, and is used to control the signal of the fifth node N5; the first terminal of the first coupling unit 141b is electrically connected to the fifth node N5, and the second terminal of the first coupling unit 141b is electrically connected to the third node N3. Optional first electronic control unit 141a includes: a first transistor M1; the gate of the first transistor M1 is electrically connected to the third node N3, the first terminal of the first transistor M1 is electrically connected to the second clock terminal XCK, and the second terminal of the first transistor M1 is electrically connected to the fifth node N5. First coupling unit 141b includes: a first capacitor Ca1; the first plate of the first capacitor Ca1 is electrically connected to the fifth node N5, and the second plate of the first capacitor Ca1 is electrically connected to the third node N3.

[0068] The optional second electronic control submodule 142 includes: a third transistor M3; the gate and the first terminal of the third transistor M3 are both electrically connected to the third node N3, and the second terminal of the third transistor M3 is electrically connected to the second node N2.

[0069] In this embodiment, the signal from the third node N3 controls the first transistor M1 to turn on or off. When the signal from the third node N3 controls the first transistor M1 to turn on, the second clock signal provided by the second clock terminal XCK is transmitted to the fifth node N5 through the turned-on first transistor M1, and the signal from the third node N3 can be coupled through the first capacitor Ca1.

[0070] The signal from the third node N3 also controls the third transistor M3 to turn on or off. When the signal from the third node N3 controls the third transistor M3 to turn on, the signal from the third node N3 is written to the second node N2 through the turned-on third transistor M3.

[0071] The first transistor M1 and the third transistor M3 can both be PMOS. The fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can all be PMOS. The eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 can all be PMOS. The eleventh transistor M11 and the twelfth transistor M12 can both be PMOS. Correspondingly, the first power supply signal provided by the first power supply terminal VG1 can be a low level vgl, and the second power supply signal provided by the second power supply terminal VG2 can be a high level vgh. However, this is not a limitation; relevant personnel can design the transistors and signal terminals in the circuit according to the product requirements.

[0072] In this embodiment, the phase of the first clock signal provided by the first clock terminal VG1 may be different from the phase of the second clock signal provided by the second clock terminal XCK. Alternatively, the period of the first clock signal and the period of the second clock signal may be the same. Alternatively, the phase difference between the first clock signal and the second clock signal may be 2 / H, where H is the period of the first clock signal.

[0073] The operation of the optional shift register includes: a first stage and a second stage; in the first stage, the transmission path between the first power supply terminal and the shift output terminal in the shift output module is connected, so that the first power signal provided by the first power supply terminal is transmitted to the shift output terminal; in the second stage, the transmission path between the second power supply terminal and the shift output terminal in the shift output module is connected, so that the second power signal provided by the second power supply terminal is transmitted to the shift output terminal.

[0074] The optional second clock signal provided by the second clock terminal transitions between the first level signal and the second level signal; in the first stage, when the second clock signal transitions to the first level signal, the control potential module is turned on, and when the second clock signal transitions to the second level signal, the control potential module is turned off. The polarity of the first level signal is the same as that of the signal of the second node, and the polarity of the second level signal is opposite to that of the signal of the second node; in the second stage, the control potential module is turned off.

[0075] In this embodiment, when the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT, the shift output terminal NEXT outputs an invalid shift signal; conversely, when the second power signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT, the shift output terminal NEXT outputs an active shift signal. Therefore, the first stage of the shift register 12 can be understood as the invalid level output stage of the shift signal, and similarly, the second stage of the shift register 12 can be understood as the active level output stage of the shift signal.

[0076] Taking the twelfth transistor M12 as a PMOS as an example, it can be seen that in the first stage, the second node N2 is at a low level. When the second clock signal jumps to a low level with the same polarity as the signal of the second node N2, the potential control module 140 is turned on. When the second clock signal jumps to a high level with the opposite polarity to the signal of the second node N2, the potential control module 140 is turned off. In the second stage, the second node N2 should be at a high level, and the potential control module 140 should be turned off.

[0077] In other embodiments, if the twelfth transistor is an NMOS, then in the first stage, the second node should be at a high level, and the potential control module should be turned on when the second clock signal jumps to a high level with the same signal polarity as the second node, and turned off when the second clock signal jumps to a low level with the opposite signal polarity to the second node; in the second stage, the second node is at a low level, and the potential control module is turned off.

[0078] Figure 8 yes Figure 7 The timing diagram of the shift register shown is for reference. Figure 7 and Figure 8 As shown, the operation of shift register 12 includes at least the following stages:

[0079] In stage t11, the first clock signal provided by the first clock terminal CK is high, the sixth transistor M6 and the fourth transistor M4 are both turned off, the fifth transistor M5 and the seventh transistor M7 remain on, and the first node N1, the second node N2 and the third node N3 remain at the low level of the previous stage; the eighth transistor M8 is turned off, the sixth node N6 remains at the high level of the previous stage, and the ninth transistor M9 is turned off; the tenth transistor M10 is turned on, the fourth node N4 is high, and the eleventh transistor M11 is turned off; the twelfth transistor M12 is turned on, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT. During this stage, the first transistor M1 is turned on. When the second clock signal provided by the second clock terminal XCK transitions from a high level to a low level, the low level of node N3b can be pulled down even lower through the coupling of the first capacitor Ca1. The low level of node N3b then controls the third transistor M3 to turn on, and the low level of node N3b is written to the second node N2, ensuring that the twelfth transistor M12 is turned on. That is, when the second clock signal transitions to a low level with the same polarity as the signal of the second node N2, the potential control module 140 is turned on. Sequentially, when the second clock signal provided by the second clock terminal XCK transitions from a low level to a high level, the level of node N3b (same as the third node N3) can be pulled high through the coupling of the first capacitor Ca1. The level of node N3b is higher than that of the second node N2, controlling the third transistor M3 to turn off. The level of node N3b does not affect the second node N2. The second node N2 remains at a low level and controls the twelfth transistor M12 to turn on. That is, when the second clock signal transitions to a high level with the opposite polarity to the signal of the second node N2, the potential control module 140 is turned off.

[0080] In stage t12, the first clock signal provided by the first clock terminal CK is low, so the sixth transistor M6 and the fourth transistor M4 are turned on simultaneously, while the fifth transistor M5 and the seventh transistor M7 remain on. The high-level signal provided by the input terminal IN is then written to the first node N1, the second node N2, and the third node N3, respectively. The first transistor M1, the third transistor M3, the eighth transistor M8, the tenth transistor M10, and the twelfth transistor M12 are all turned off. The first clock terminal CK pulls down the potential of the sixth node N6 through the second capacitor Ca2, and the ninth transistor M9 is turned on. The low level of the first clock signal is written to the fourth node N4, and the eleventh transistor M11 is turned on. The second power signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT. That is, in the second stage, the potential control module 140 is turned off.

[0081] In stage t13, the first clock signal provided by the first clock terminal CK is high, so the sixth transistor M6 and the fourth transistor M4 are simultaneously turned off, while the fifth transistor M5 and the seventh transistor M7 remain on. Therefore, the first node N1, the second node N2, and the third node N3 all remain high; the first transistor M1, the third transistor M3, the eighth transistor M8, the tenth transistor M10, and the twelfth transistor M12 are all turned off; the first clock terminal CK is coupled up to the potential of the sixth node N6 through the second capacitor Ca2, and the ninth transistor M9 is turned off; the fourth node N4 remains low, and the eleventh transistor M11 is turned on; the second power signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT. That is, in the second stage, the potential control module 140 is turned off.

[0082] During stage t14, the first clock signal provided by the first clock terminal CK undergoes a high-low level transition. The fifth transistor M5 and the seventh transistor M7 remain on. When the sixth transistor M6 and the fourth transistor M4 are on, the low-level signal provided by the input terminal IN is written to the first node N1, the second node N2, and the third node N3, respectively. The eighth transistor M8, the tenth transistor M10, and the twelfth transistor M12 are all on. The sixth node N6 and the fourth node N4 are both at a high level, and the ninth transistor M9 and the eleventh transistor M11 are both off. The first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT. During this stage, the first transistor M1 is turned on. When the second clock signal provided by the second clock terminal XCK transitions from a high level to a low level, the low level of node N3b (same as the third node N3) can be pulled down even lower through the coupling of the first capacitor Ca1. The low level of node N3b then controls the third transistor M3 to turn on, and the low level of node N3b is written to the second node N2, ensuring that the twelfth transistor M12 is turned on. That is, when the second clock signal transitions to a low level with the same polarity as the signal of the second node N2, the potential control module 140 is turned on. Sequentially, when the second clock signal provided by the second clock terminal XCK transitions from a low level to a high level, the level of node N3b can be pulled high through the coupling of the first capacitor Ca1. The level of node N3b is higher than that of the second node N2, controlling the third transistor M3 to turn off. The level of node N3b does not affect the second node N2. The second node N2 remains at a low level and controls the twelfth transistor M12 to turn on. That is, when the second clock signal transitions to a high level with the opposite polarity to the signal of the second node N2, the potential control module 140 is turned off.

[0083] Optional Figure 7 A fourth capacitor can also be added between the second node N2 and the shift output terminal NEXT (see reference). Figure 5 The fourth capacitor (Ca4) shown can enhance the voltage holding capability of the second node N2.

[0084] As described above, stages t12 to t13 represent the output stage of the shift signal of shift register 12 at an effective level, i.e., the second stage. Stages t14 to t11 of the next frame represent the output stage of the shift signal of shift register 12 at an invalid level, i.e., the first stage. Clearly, from stage t14 of the current frame to stage t11 of the next frame (the first stage), the second node N2 remains at a low level. When the second clock signal transitions to a low level, the potential control module 140 is turned on; when the second clock signal transitions to a high level, the potential control module 140 is turned off. This pulls down the potential of the second node N2, thereby continuously controlling the twelfth transistor M12 to be turned on, which facilitates the transmission of the first power signal vgl provided by the first power supply terminal VG1 to the shift output terminal NEXT. Especially when the shift register 12 is operating in low-frequency mode, by adding a potential control module 140 and using a periodic high-low level transition second clock signal to periodically couple the second node N2, the low-voltage holding capability of the second node N2 can be enhanced, the leakage current of the second node N2 can be reduced, which is conducive to ensuring the output effectiveness, accuracy and stability of the shift register 12, and thus conducive to improving the display quality of the display panel.

[0085] Figure 9 This is a schematic diagram of another shift register provided in an embodiment of the present invention, and... Figure 7 different, Figure 9 The optional first electronic control submodule 141 includes: a second electronic control unit 141c; the second electronic control unit 141c is electrically connected to the fourth node N4, the third power supply terminal VG3, and the fifth node N5, and is used to control the signal of the fifth node N5. The optional second electronic control unit 141c includes: a second transistor M2; the gate of the second transistor M2 is electrically connected to the fourth node N4, the first terminal of the second transistor M2 is electrically connected to the third power supply terminal VG3, and the second terminal of the second transistor M2 is electrically connected to the fifth node N5. The optional third power supply signal provided by the third power supply terminal VG3 is a fixed voltage signal. The optional second power supply signal provided by the second power supply terminal VG2 is the same as the third power supply signal.

[0086] In this embodiment, the first electronic control submodule 141 includes a first transistor M1, a second transistor M2, and a first capacitor Ca1. The gate of the second transistor M2 is electrically connected to a fourth node N4, the first terminal of the second transistor M2 is electrically connected to a third power supply terminal VG3, and the second terminal of the second transistor M2 is electrically connected to a fifth node N5. The signal from the fourth node N4 controls the second transistor M2 to turn on or off. When the signal from the fourth node N4 controls the second transistor M2 to turn on, the third power supply signal provided by the third power supply terminal VG3 is written to the fifth node N5.

[0087] Optionally, the third power signal provided by the third power supply terminal VG3 can be a fixed voltage signal. Optionally, the second power signal provided by the second power supply terminal VG2 can be the same as the third power signal. In this embodiment, the second power signal is a high level vgh, so the third power signal provided by the third power supply terminal VG3 can be a high level vgh.

[0088] The operation of shift register 12 includes a first stage and a second stage.

[0089] Figure 10 yes Figure 9 The timing diagram of the shift register shown is for reference. Figure 9 and Figure 10 As shown, the operation of shift register 12 includes at least the following stages:

[0090] In stage t21, the signals and transistor on / off states of multiple nodes are similar to those in stage t11 and will not be repeated; among them, the fourth node N4 is at a high level, controlling the second transistor M2 to turn off.

[0091] During stages t22 to t23, the signal and transistor on / off states of multiple nodes are similar to those in stages t12 to t13, and will not be repeated. Specifically, the fourth node N4 is at a low level, controlling the second transistor M2 to turn on. The third power signal vgh provided by the third power supply terminal VG3 is transmitted to the fifth node N5. The third power signal vgh is then coupled up to the potential of node N3b through the first capacitor Ca1 to ensure that node N3b is at a high level. That is, in the second stage, the potential control module 140 is turned off.

[0092] In stage t24, the signals and transistor on / off states of multiple nodes are similar to those in stage t14 and will not be repeated; among them, the fourth node N4 is at a high level, controlling the second transistor M2 to turn off.

[0093] Optional Figure 9 A fourth capacitor can also be added between the second node N2 and the shift output terminal NEXT (see reference). Figure 5 The fourth capacitor (Ca4) shown can enhance the voltage holding capability of the second node N2.

[0094] As described above, the t22 to t23 stage is the output stage of the effective level of the shift signal of the shift register 12. During this stage, the second transistor M2 is turned on, and the third power supply signal vgh provided by the third power supply terminal VG3 can be coupled to the potential of node N3b through the first capacitor Ca1, thereby ensuring that the third transistor M3 is turned off, preventing the high and low level transitions of the second clock signal from affecting the potential of node N3b, further enhancing the voltage holding capability of the second node N2, reducing the leakage current of the second node N2, which is conducive to ensuring the output effectiveness, accuracy and stability of the shift register 12, and thus improving the display quality of the display panel.

[0095] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of the present invention, to... Figure 7 The shift register 12 shown is the basis, as follows Figure 11 The optional shift register 12 shown also includes a refresh output section 150, which includes a scan output terminal OUT. The refresh output section 150 is also electrically connected to a first refresh signal line. In response to the first refresh control signal Ctrl1 provided by the first refresh signal line, the refresh output section 150 controls the scan output terminal OUT to output a gate drive signal Gout. The gate drive signal Gout includes an active level and an inactive level.

[0096] In this embodiment, the optional refresh output section 150 has a "5T3C" structure. For example, the refresh output section 150 includes a first transistor Mb1, a second transistor Mb2, a third transistor Mb3, a fourth transistor Mb4, and a fifth transistor Mb5. The refresh output section 150 also includes a first capacitor Cb1, a second capacitor Cb2, and a third capacitor Cb3. All transistors in the optional refresh output section 150 are PMOS.

[0097] The gate of transistor Mb1 is electrically connected to node Nb1, the first terminal of transistor Mb1 is electrically connected to the fourth node N4, and the second terminal is electrically connected to node Nb2.

[0098] The gate of transistor Mb2 is electrically connected to the second control terminal B. The second control terminal B can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3, and the node N3b. The first terminal of transistor Mb2 is electrically connected to the first refresh signal line to receive the first refresh control signal Ctrl1, and the second terminal is electrically connected to node Nb1.

[0099] The gate of transistor Mb3 is electrically connected to the first control terminal A. The first control terminal A can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3, and the node N3b. The first terminal of transistor Mb3 receives a high-level signal vgh and the second terminal is electrically connected to node Nb2.

[0100] The gate of transistor Mb4 is electrically connected to node Nb2. The first terminal of transistor Mb4 receives a high-level signal vgh and the second terminal is electrically connected to the scan output terminal OUT.

[0101] The gate of transistor Mb5 is electrically connected to the second node N2. The first terminal of transistor Mb5 receives a low-level signal vgl, and the second terminal is electrically connected to the scan output terminal OUT.

[0102] One plate of capacitor Cb1 receives a high-level signal vgh, and the other plate is electrically connected to node Nb2.

[0103] One plate of capacitor Cb2 receives a high-level signal vgh or a low-level signal vgl, and the other plate of capacitor Cb2 is electrically connected to node Nb1.

[0104] One plate of capacitor Cb3 is electrically connected to the second node N2, and the other plate is electrically connected to the scan output terminal OUT.

[0105] based on Figure 11 The shift register 12 shown enables the display panel to achieve partitioned refresh. Specifically, the display panel has a multi-frequency refresh mode; in the multi-frequency refresh mode, the display area of ​​the display panel includes at least a first display partition and a second display partition, the refresh frequency of the first display partition is a first refresh frequency, the refresh frequency of the second display partition is a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.

[0106] Optionally, in multi-frequency refresh mode, the frequency of the shift signal of the shift register in the first display partition is greater than the frequency of the gate drive signal; in multi-frequency refresh mode, the frequency of the gate drive signal of the shift register in the first display partition is less than the frequency of the gate drive signal of the shift register in the second display partition. Therefore, the first display partition operates at a low frequency, and the second display partition operates at a high frequency. Optionally, in multi-frequency refresh mode, the frequency of the shift signal of the shift register in the second display partition can be equal to the frequency of the gate drive signal, but is not limited to this.

[0107] For example, in multi-frequency refresh mode, the first refresh frequency of the first display partition is 30Hz, and the second refresh frequency of the second display partition is 120Hz. Taking a display panel refresh frequency of 120Hz as an example, in multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120Hz and the frequency of the gate drive signal is 30Hz; in the second display partition, the frequency of the shift signal of the shift register is 120Hz and the frequency of the gate drive signal is 120Hz.

[0108] For example, in multi-frequency refresh mode, the first refresh frequency of the first display partition is 30Hz, and the second refresh frequency of the second display partition is 60Hz. Taking a display panel refresh frequency of 120Hz as an example, then in multi-frequency refresh mode, in the first display partition, the frequency of the shift signal of the shift register is 120Hz and the frequency of the gate drive signal is 30Hz; in the second display partition, the frequency of the shift signal of the shift register is 120Hz and the frequency of the gate drive signal is 60Hz.

[0109] The operation of the optional shift register 12 includes a data writing stage and a data holding stage. During the data writing stage, the first refresh control signal Ctrl1 provided by the first refresh signal line to the shift register 12 is at an active level, making the shift signal of the shift register 12 active and the gate drive signal Gout active. During the data holding stage, the first refresh control signal Ctrl1 provided by the first refresh signal line to the shift register 12 is at an inactive level, making the shift signal of the shift register 12 active and the gate drive signal Gout inactive.

[0110] This embodiment uses the example of the first refresh control signal Ctrl1 having a low effective level (vgl) and a high ineffective level (vgh) to illustrate the working principle of the shift register 12. Optionally, the gate of transistor Mb2 is electrically connected to the shift output terminal NEXT, and the gate of transistor Mb3 is electrically connected to the second node N2. Here, a high level of the shift signal is the effective level and a low level is the ineffective level, and a high level of the gate drive signal Gout is the effective level and a low level is the ineffective level.

[0111] Figure 11 The second control terminal B can be selected as the shift output terminal NEXT, and the first control terminal A can be selected as the second node N2.

[0112] Figure 12 yes Figure 11 The diagram shown illustrates the low-frequency operating timing of the shift register in the first display partition. (Reference) Figure 11 and Figure 12 As shown, in the first display partition, the shift signal frequency of shift register 12 is greater than the gate drive signal frequency. Therefore, when the shift signal of shift register 12 is at an active level, there is a possibility that the gate drive signal of shift register 12 is at an inactive level, thus achieving low-frequency operation. Based on this, for... Figure 11 The operation of shift register 12 in the first display partition is shown. During the t32 to t33 stage, the first refresh control signal Ctrl1 is at a high level vgh, which is an invalid level, so that shift register 12 satisfies the condition that the shift signal is at an effective level and the gate drive signal is at an invalid level.

[0113] refer to Figure 11 and Figure 12 As shown, the low-frequency operation of shift register 12 includes:

[0114] In stage t31, the second node N2 is at a low level, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on and transistor Mb3 is turned on; node Nb1 is at a high level and transistor Mb1 is turned off; node Nb2 is at a high level and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0115] During the t32 to t33 phase, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; transistor Mb2 and transistor Mb3 are turned off; node Nb1 remains at a high level, and transistor Mb1 is turned off; node Nb2 remains at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned off, and the gate drive signal Gout output from the scan output terminal OUT remains at a low level. It can be seen that during this phase, the shift signal is at an active level, and the gate drive signal Gout is at an inactive level.

[0116] In stage t34 and thereafter, the second node N2 is low, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb3 is turned on; node Nb1 is high, and transistor Mb1 is turned off; node Nb2 is high, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is low.

[0117] As described above, when shift register 12 operates in low-frequency mode, the high-level signal provided by the first refresh signal line can keep node Nb1 at a high level (vgh) and keep the gate drive signal Gout of the scan output terminal OUT at a low level (vgl). This effectively enhances the circuit stability and effectiveness of shift register 12 in low-frequency mode.

[0118] Figure 13 yes Figure 11 The second display partition shows the high-frequency operating timing diagram of the shift register. (Reference) Figure 11 and Figure 13 As shown, in the optional second display partition, the shift signal frequency of shift register 12 is equal to the gate drive signal frequency. Therefore, when the shift signal of shift register 12 is at an active level, the gate drive signal of shift register 12 is also at an active level, thus achieving high-frequency operation. Based on this, for... Figure 11The operation of shift register 12 in the second display partition is shown. During the t42 to t43 stage, the first refresh control signal Ctrl1 is at a low level vgl, i.e., an effective level, so that shift register 12 satisfies the condition that the shift signal is at an effective level and the gate drive signal is at an effective level.

[0119] refer to Figure 11 and Figure 13 As shown, the high-frequency operation of shift register 12 includes:

[0120] During stage t41, the second node N2 is at a low level, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on and transistor Mb3 is turned on; node Nb1 is at a low level, and transistor Mb1 is turned on; node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0121] During the t42 to t43 phase, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; transistor Mb2 and transistor Mb3 are turned off; node Nb1 remains at a low level, and transistor Mb1 is turned on; node Nb2 is at a low level, and transistor Mb4 is turned on; transistor Mb5 is turned off, and the gate drive signal Gout output by the scan output terminal OUT is at a high level. It can be seen that during this phase, the shift signal and the gate drive signal Gout are both at an effective level.

[0122] During and after stage t44, the second node N2 is at a low level, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb3 is turned on; node Nb1 is at a low level, and transistor Mb1 is turned on; node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0123] As mentioned above, when shift register 12 operates in high-frequency mode, the circuit stability and effectiveness of shift register 12 in high-frequency mode are discussed.

[0124] Figure 14 This is a schematic diagram of the refresh output section in another shift register provided in an embodiment of the present invention, and... Figure 11 The difference is, such as Figure 14 The optional refresh output section 150 shown has a "6T4C" structure and includes two refresh signal lines. Figure 14 Only the refresh output section 150 of shift register 12 is shown in the figure. The other structures of shift register 12 can be found in [reference]. Figure 11 As shown, it will not be shown again here.

[0125] Specifically, the refresh output unit 150 includes transistors Mb1, Mb2, Mb4, and Mb5, capacitors Cb1, Cb2, and Cb3. The connection method of these four transistors and three capacitors is similar to... Figure 11 same.

[0126] and Figure 11 The difference lies in that the refresh output section 150 also includes transistors Mb31 and Mb6, and a fourth capacitor Cb4. The gate of transistor Mb6 is electrically connected to the second control terminal B, which can be any of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3, and node N3b. The first terminal of transistor Mb6 is electrically connected to the second refresh signal line to receive the second refresh control signal Ctrl2, and the second terminal of transistor Mb6 is electrically connected to the gate of transistor Mb31. The first plate of capacitor Cb4 is electrically connected to the gate of transistor Mb31, and the second plate of capacitor Cb4 can receive either a high-level signal vgh or a low-level signal vgl. The first terminal of transistor Mb31 receives the high-level signal vgh, and its second terminal is electrically connected to node Nb2.

[0127] Optionally, the control signal Ctrl2 provided by the second refresh signal line may differ from the control signal Ctrl1 provided by the first refresh signal line. Both the optional second refresh signal line control signal Ctrl2 and the first refresh signal line control signal Ctrl1 are high-to-low level transition signals, and they are in opposite phases.

[0128] Figure 14 The second control terminal B can be selected as the shift output terminal NEXT.

[0129] based on Figure 14 The shift register 12 shown allows the display panel to be refreshed in sections.

[0130] Figure 15 yes Figure 14 The diagram shown illustrates the low-frequency operating timing of the shift register in the first display partition. (Reference) Figure 14 and Figure 15 As shown, in the first display partition, the shift signal frequency of shift register 12 is greater than the gate drive signal frequency. Therefore, when the shift signal of shift register 12 is at an active level, there is a possibility that the gate drive signal of shift register 12 is at an inactive level, thus achieving low-frequency operation. Based on this, for... Figure 14The operation of shift register 12 in the first display partition is shown. During the t52 to t53 stage, the first refresh control signal Ctrl1 is high level vgh, which is an invalid level, and the second refresh control signal Ctrl2 is low level vgl, which is an effective level, so that shift register 12 satisfies the condition that the shift signal is an effective level and the gate drive signal is an invalid level.

[0131] refer to Figure 14 and Figure 15 As shown, the low-frequency operation of shift register 12 includes:

[0132] In stage t51, the second node N2 is low, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, the high level vgh of the first refresh control signal Ctrl1 is written to node Nb1, and transistor Mb1 is turned off; transistor Mb6 is turned on, the low level vgl of the second refresh control signal Ctrl2 is written to node Nb21, and transistor Mb31 is turned on; node Nb2 is high, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is low level vgl.

[0133] During stages t52 to t53, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; transistor Mb2 and transistor Mb6 are turned off; node Nb1 remains at a high level, and transistor Mb1 is turned off; node Nb21 remains at a low level, and transistor Mb31 is turned on; node Nb2 remains at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned off, and the gate drive signal Gout output from the scan output terminal OUT remains at a low level. It can be seen that during this stage, the shift signal is at an active level, and the gate drive signal Gout is at an inactive level.

[0134] During and after stage t54, the second node N2 is at a low level, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb6 is turned on; node Nb1 is at a high level, and transistor Mb1 is turned off; node Nb21 is at a low level, and transistor Mb31 is turned on; node Nb2 is at a high level, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level.

[0135] As described above, when shift register 12 operates in low-frequency mode, the high-level signal provided by the first refresh signal line keeps node Nb1 at a high level (vgh), and the low-level signal provided by the second refresh signal line keeps node Nb21 at a low level (vgl). Correspondingly, transistor Mb31 turns on, keeping node Nb2 at a high level, while transistor Mb4 remains off, keeping the gate drive signal Gout of the scan output terminal OUT at a low level (vgl). This effectively enhances the circuit stability and effectiveness of shift register 12 in low-frequency mode.

[0136] Figure 16 yes Figure 14 The second display partition shows the high-frequency operating timing diagram of the shift register. (Reference) Figure 14 and Figure 16 As shown, in the optional second display partition, the shift signal frequency of shift register 12 is equal to the gate drive signal frequency. Therefore, when the shift signal of shift register 12 is at an active level, the gate drive signal of shift register 12 is also at an active level, thus achieving high-frequency operation. Based on this, for... Figure 14 The operation of shift register 12 in the second display partition is shown. During the t62 to t63 stage, the first refresh control signal Ctrl1 is low level vgl (i.e., effective level), and the second refresh control signal Ctrl2 is high level vgh (i.e., ineffective level), so that shift register 12 satisfies the condition that the shift signal is effective level and the gate drive signal is effective level.

[0137] refer to Figure 14 and Figure 16 As shown, the high-frequency operation of shift register 12 includes:

[0138] In stage t61, the second node N2 is at a low level, and the first power supply signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and the low level vgl of the first refresh control signal Ctrl1 is written to node Nb1, transistor Mb1 is turned on, and the high level of the fourth node N4 is written to node Nb2; transistor Mb6 is turned on, and the high level vgh of the second refresh control signal Ctrl2 is written to node Nb21, transistor Mb31 is turned off; node Nb2 is at a high level, transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is at a low level vgl.

[0139] During stages t62 to t63, the second node N2 is at a high level, and the second power supply signal vgh provided by the second power supply terminal VG2 is transmitted to the shift output terminal NEXT; transistor Mb2 and transistor Mb6 are turned off; node Nb1 remains at a low level, and transistor Mb1 is turned on; node Nb21 remains at a high level, and transistor Mb31 is turned off; the low level of the fourth node N4 is written to node Nb2, and transistor Mb4 is turned on; transistor Mb5 is turned off, and the gate drive signal Gout output by the scan output terminal OUT is at a high level. It can be seen that during this stage, the shift signal and the gate drive signal Gout are both at an effective level.

[0140] In stage t64 and thereafter, the second node N2 is low, and the first power signal vgl provided by the first power supply terminal VG1 is transmitted to the shift output terminal NEXT; transistor Mb2 is turned on, and transistor Mb6 is turned on; node Nb1 is low, and transistor Mb1 is turned on; node Nb21 is high, and transistor Mb31 is turned off; the high level of the fourth node N4 is written to node Nb2, and transistor Mb4 is turned off; transistor Mb5 is turned on, and the gate drive signal Gout output by the scan output terminal OUT is low.

[0141] As mentioned above, when shift register 12 operates in high-frequency mode, the circuit stability and effectiveness of shift register 12 in high-frequency mode are discussed.

[0142] Figure 17 This is a schematic diagram of the refresh output section in another shift register provided in an embodiment of the present invention, and... Figure 14 The difference is, such as Figure 17 The optional refresh output section 150 shown is a "7T4C" structure. Figure 17 Only the refresh output section 150 of shift register 12 is shown in the figure. The other structures of shift register 12 can be found in [reference]. Figure 11 As shown, it will not be shown again here.

[0143] Specifically, the refresh output unit 150 includes transistors Mb1, Mb2, Mb31, Mb4, Mb5, and Mb6, and capacitors Cb1, Cb2, Cb3, and Cb4. The connection method of these six transistors and four capacitors is similar to... Figure 14 same.

[0144] and Figure 14 The difference is that a transistor Mb32 is added to the refresh output section 150. The gate of the transistor Mb32 is electrically connected to the first control terminal A. The first control terminal A can be any one of the shift output terminal NEXT, the first node N1, the second node N2, the third node N3, and the node N3b. The first terminal of the transistor Mb32 receives a high-level signal vgh and the second terminal is electrically connected to the node Nb2.

[0145] Figure 17 The low-frequency operating timing of the intermediate shift register can be referenced. Figure 15 As shown, Figure 17 The high-frequency operating timing of the intermediate shift register can be referenced. Figure 16 As shown.

[0146] Through research, the inventors discovered that the refresh output section of the shift register applicable to this invention is not limited to the above structure. Provided that the shift register functions normally and the output is stable and effective, any refresh output section falls within the scope of this invention. Further details will not be elaborated here.

[0147] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in the embodiments of the present invention. Therefore, this display device possesses the technical features of the display panel and its driving process provided in the embodiments of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiments of the present invention. Similarities can be found in the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0148] For example, Figure 18 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 18 As shown, the display device 1 includes a display panel 10 provided in this embodiment of the invention. The display device 1 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these.

[0149] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0150] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: A first driving circuit, the first driving circuit including a multi-stage shift register; The shift register includes: The first shift control module is electrically connected to an input terminal, a first clock terminal, a first power supply terminal, a first node, a second node, and a third node, and is used to control the signals of the first node, the second node, and the third node. The second shift control module is electrically connected to the input terminal, the first clock terminal, the first node, the second power supply terminal, and the fourth node, and is used to control the signal of the fourth node; The shift output module is electrically connected to the fourth node, the second node, the first power supply terminal, the second power supply terminal, and the shift output terminal, and is used to control the shift output terminal to output a shift signal; A potential control module is electrically connected to the third node, the second clock terminal, and the second node, and is used to control the signal of the second node. The shift register further includes a refresh output section, used to control the output of a gate drive signal from the scan output section according to the signal from the shift output section, the signal from the second node, the first refresh control signal, and the second refresh control signal. The gate drive signal includes an active level and an inactive level. Wherein, the first refresh control signal and the second refresh control signal are signals with opposite phases; The refresh output section includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first terminal of the first transistor is electrically connected to the fourth node, and the second terminal of the first transistor is electrically connected to the gate of the fourth transistor. The gate of the second transistor is electrically connected to a second control terminal, and the first terminal of the second transistor receives a first refresh control signal. The second terminal of the second transistor is also electrically connected to the gate of the first transistor. The first terminal of the fourth transistor is electrically connected to a second power supply terminal, and the second terminal of the fourth transistor is electrically connected to a scan output terminal. The gate of the fifth transistor is electrically connected to a second node, and the first terminal of the fifth transistor is electrically connected to a first power supply terminal. The second terminal of the fifth transistor is also electrically connected to the scan output terminal. The gate of the sixth transistor is electrically connected to the second control terminal, and the first terminal of the sixth transistor receives a second refresh control signal. The second terminal of the sixth transistor is also electrically connected to the gate of the seventh transistor. The first terminal of the seventh transistor is electrically connected to the second power supply terminal, and the second terminal is electrically connected to the gate of the fourth transistor. The second control terminal is any one of the shift output terminal, the first node, the second node, and the third node. The signal output from the first power supply terminal is an invalid level in the gate drive signal, and the signal output from the second power supply terminal is an active level in the gate drive signal.

2. The display panel according to claim 1, characterized in that, The potential control module includes: a first electronic control submodule and a second electronic control module; The first electronic control submodule is electrically connected to the second clock terminal and the third node, and is used to control the signal of the third node; The second electronic control submodule is electrically connected to the third node and the second node, and is used to control the signal of the second node.

3. The display panel according to claim 2, characterized in that, The first electronic control submodule includes: a first electronic control unit and a first coupling unit; The first electronic control unit is electrically connected to the second clock terminal, the third node, and the fifth node, and is used to control the signal of the fifth node; The first end of the first coupling unit is electrically connected to the fifth node, and the second end of the first coupling unit is electrically connected to the third node.

4. The display panel according to claim 3, characterized in that, The first electronic control unit includes: a first transistor; The gate of the first transistor is electrically connected to the third node, the first terminal of the first transistor is electrically connected to the second clock terminal, and the second terminal of the first transistor is electrically connected to the fifth node.

5. The display panel according to claim 3, characterized in that, The first coupling unit includes: a first capacitor; The first plate of the first capacitor is electrically connected to the fifth node, and the second plate of the first capacitor is electrically connected to the third node.

6. The display panel according to claim 1, characterized in that, The phase of the first clock signal provided by the first clock terminal is different from the phase of the second clock signal provided by the second clock terminal.

7. The display panel according to claim 6, characterized in that, The period of the first clock signal is the same as the period of the second clock signal.

8. The display panel according to claim 7, characterized in that, The phase difference between the first clock signal and the second clock signal is 2 / H, where H is the period of the first clock signal.

9. The display panel according to claim 3, characterized in that, The first electronic control submodule includes: a second electronic control unit; The second electronic control unit is electrically connected to the fourth node, the third power supply terminal, and the fifth node, and is used to control the signal of the fifth node.

10. The display panel according to claim 9, characterized in that, The second electronic control unit includes: a second transistor; The gate of the second transistor is electrically connected to the fourth node, the first terminal of the second transistor is electrically connected to the third power supply terminal, and the second terminal of the second transistor is electrically connected to the fifth node.

11. The display panel according to claim 9, characterized in that, The third power supply signal provided by the third power supply terminal is a fixed voltage signal.

12. The display panel according to claim 11, characterized in that, The second power signal provided by the second power supply terminal is the same as the third power signal.

13. The display panel according to claim 2, characterized in that, The second electronic control submodule includes: a third transistor; The gate and first terminal of the third transistor are both electrically connected to the third node, and the second terminal of the third transistor is electrically connected to the second node.

14. The display panel according to claim 1, characterized in that, The first shift control module includes: a first shift control submodule and a second shift control submodule; The first shift control submodule is electrically connected to the input terminal, the first clock terminal, the first power supply terminal, the first node, and the second node, and is used to control the signals of the first node and the second node; The second shift control submodule is electrically connected to the input terminal, the first clock terminal, the first power supply terminal, and the third node, and is used to control the signal of the third node.

15. The display panel according to claim 14, characterized in that, The first shift control submodule includes: a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the first clock terminal, the first terminal of the fourth transistor is electrically connected to the input terminal, and the second terminal of the fourth transistor is electrically connected to the first node; The gate of the fifth transistor is electrically connected to the first power supply terminal, the first terminal of the fifth transistor is electrically connected to the first node, and the second terminal of the fifth transistor is electrically connected to the second node.

16. The display panel according to claim 14, characterized in that, The second shift control submodule includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is electrically connected to the first clock terminal, the first terminal of the sixth transistor is electrically connected to the input terminal, and the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor. The gate of the seventh transistor is electrically connected to the first power supply terminal, and the second terminal of the seventh transistor is electrically connected to the third node.

17. The display panel according to claim 1, characterized in that, The second shift control module includes: a third shift control submodule and a fourth shift control submodule; The third shift control submodule is electrically connected to the input terminal, the second power supply terminal and the sixth node, and is used to control the signal of the sixth node; The fourth shift control submodule is electrically connected to the sixth node, the first clock terminal, the second power supply terminal, the first node, and the fourth node, and is used to control the signal of the fourth node.

18. The display panel according to claim 17, characterized in that, The third shift control submodule includes: an eighth transistor; The gate of the eighth transistor is electrically connected to the input terminal, the first terminal of the eighth transistor is electrically connected to the second power supply terminal, and the second terminal of the eighth transistor is electrically connected to the sixth node.

19. The display panel according to claim 17, characterized in that, The fourth shift control submodule includes: a ninth transistor and a tenth transistor; The gate of the ninth transistor is electrically connected to the sixth node, the first terminal of the ninth transistor is electrically connected to the first clock terminal, and the second terminal of the ninth transistor is electrically connected to the fourth node; The gate of the tenth transistor is electrically connected to the first node, the first terminal of the tenth transistor is electrically connected to the second power supply terminal, and the second terminal of the tenth transistor is electrically connected to the fourth node.

20. The display panel according to claim 17, characterized in that, The fourth shift control submodule includes: a second capacitor; The first plate of the second capacitor is electrically connected to the sixth node, and the second plate of the second capacitor is electrically connected to the first clock terminal.

21. The display panel according to claim 1, characterized in that, The shift output module includes: a first output submodule and a second output submodule; The first output submodule is electrically connected to the fourth node, the second power supply terminal, and the shift output terminal, and is used to control the shift output terminal to output the shift signal; The second output submodule is electrically connected to the second node, the first power supply terminal, and the shift output terminal, and is used to control the shift output terminal to output the shift signal.

22. The display panel according to claim 21, characterized in that, The first output submodule includes: an eleventh transistor and a third capacitor; The gate of the eleventh transistor is electrically connected to the fourth node, the first terminal of the eleventh transistor is electrically connected to the second power supply terminal, and the second terminal of the eleventh transistor is electrically connected to the shift output terminal. The first plate of the third capacitor is electrically connected to the fourth node, and the second plate of the third capacitor is electrically connected to the second power supply terminal.

23. The display panel according to claim 21, characterized in that, The second output submodule includes: a twelfth transistor; The gate of the twelfth transistor is electrically connected to the second node, the first terminal of the twelfth transistor is electrically connected to the first power supply terminal, and the second terminal of the twelfth transistor is electrically connected to the shift output terminal.

24. The display panel according to claim 23, characterized in that, The second output submodule includes: a fourth capacitor; The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is electrically connected to the shift output terminal.

25. The display panel according to claim 1, characterized in that, The operation of the shift register includes: a first stage and a second stage; In the first stage, the transmission path between the first power supply terminal and the shift output terminal in the shift output module is connected, so that the first power signal provided by the first power supply terminal is transmitted to the shift output terminal. In the second stage, the transmission path between the second power supply terminal and the shift output terminal in the shift output module is connected, so that the second power signal provided by the second power supply terminal is transmitted to the shift output terminal.

26. The display panel according to claim 25, characterized in that, The second clock signal provided by the second clock terminal transitions between the first level signal and the second level signal; In the first stage, when the second clock signal changes to the first level signal, the potential control module is turned on; when the second clock signal changes to the second level signal, the potential control module is turned off. The first level signal has the same polarity as the signal of the second node, and the second level signal has the opposite polarity to the signal of the second node. In the second stage, the potential control module is turned off.

27. A display device, characterized in that, include: The display panel as described in any one of claims 1-26.

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