Display device control method and display device

Abstract

The invention discloses a control method of a display device and the display device, the method is applied to the display device comprising a high-frequency refresh area and a low-frequency refresh area, the high-frequency refresh area and the low-frequency refresh area occupy pixel circuits of different rows, and the method comprises the following steps: controlling a data signal corresponding to a first range to be input into a data line at a first frequency, the data signal corresponding to the second range is controlled to be input into the data line at the second frequency; and controlling the data signal to be written into the pixel circuit according to the partition enable signal. The display effect of the display device can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a control method for a display device and a display device. Background Art

[0002] As people's living standards improve, they are exposed to electronic products all the time, so the demand for display panels is increasing, and display technology has developed rapidly. Now the ordinary display effect can no longer meet people's quality of life. For another bright spot technology, zone refresh, because the refresh frequency is different in different areas of the screen, this can have better power consumption benefits and thus extend the use time of electronic products.

[0003] However, when the partition refresh function is turned on, the refresh frequencies of different partitions are inconsistent. If the light load state in the low refresh frequency area is changed to the heavy load state in the high refresh frequency area, the load of the driver chip will jump, causing the voltage stability to be affected and resulting in display abnormalities. Summary of the invention

[0004] In view of this, the present application provides a control method of a display device and a display device to solve the problem of abnormal display when the partition refresh function is turned on in the traditional solution.

[0005] In a first aspect, the present application provides a control method for a display device, which is applied to a display device including a high-frequency refresh zone and a low-frequency refresh zone, wherein the high-frequency refresh zone and the low-frequency refresh zone occupy different rows of pixel circuits, and the method includes: controlling a data signal corresponding to a first range to be input into a data line at a first frequency, and controlling a data signal corresponding to a second range to be input into the data line at a second frequency, wherein the first frequency is greater than the second frequency, the low-frequency refresh zone includes a first sub-zone adjacent to the high-frequency refresh zone and a second sub-zone located on a side of the first sub-zone away from the high-frequency refresh zone, the first range includes the high-frequency refresh zone and the first sub-zone, and the second range includes the second sub-zone; and controlling the data signal to be written into the pixel circuit according to a partition enable signal.

[0006] Optionally, the display device includes a first gate driving circuit, a plurality of rows of pixel circuits, and at least one partition enabling signal line, the first gate driving circuit is connected to the partition enabling signal line, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line.

[0007] Each display frame in at least one display frame includes a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area, and the first time period includes a first sub-time period corresponding to the first sub-area and a second sub-time period corresponding to the second sub-area;

[0008] At least one display frame includes a first type of display frame, the first type of display frame is a refresh frame in a high frequency refresh area, the first type of display frame is a hold frame in a low frequency refresh area,

[0009] The method also includes:

[0010] In the first type of display frame, in the second sub-period, a fixed potential is input to the data line; in the first sub-period, a data signal or a signal with a changing potential is input to the data line, or, in the first sub-period, a potential different from that input to the data line in the second sub-period is input to the data line, and in the second sub-period, a data signal corresponding to the high-frequency refresh area is input to the data line;

[0011] In the first type of display frame, during at least part of the second sub-period, a non-enable level is input to the partition enable signal line; during at least part of the first sub-period, a non-enable level is input to the partition enable signal line, and during at least part of the second sub-period, an enable level is input to the partition enable signal line;

[0012] Optionally, the first gate driving circuit is used to control the first gate driving circuit to output pulse signals of different frequencies to the high-frequency refresh area and the low-frequency refresh area according to the partition enable signal of the partition enable signal line;

[0013] Optionally, the number of rows of pixel circuits in the first sub-area is greater than or equal to 1 row;

[0014] The first sub-period is less than or equal to a row period of the pixel circuit.

[0015] Optionally, at least one display frame includes a second type of display frame, the second type of display frame is a refresh frame in a high frequency refresh area, and the second type of display frame is a refresh frame in a low frequency refresh area.

[0016] The control method of the display device further includes:

[0017] In the second display frame, in the second sub-period, the data signal corresponding to the second sub-area is input to the data line; in the first sub-period, the data signal corresponding to the first sub-area is input to the data line; in the second sub-period, the data signal corresponding to the high-frequency refresh area is input to the data line;

[0018] In the second type of display frame, in the second sub-period, an enable level is input to the partition enable signal line; in the first sub-period, an enable level is input to the partition enable signal line; in the second sub-period, an enable level is input to the partition enable signal line;

[0019] Optionally, M first-category display frames are arranged between adjacent second-category display frames, and a ratio of the first frequency divided by the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

[0020] Optionally, the control method of the display device further includes:

[0021] The at least one low-frequency refresh area includes a first low-frequency refresh area, the first low-frequency refresh area is adjacent to the high-frequency refresh area, and data writing is performed before data writing is performed in the high-frequency refresh area in the second type of display frame; the second sub-period corresponding to the first low-frequency refresh area is before the first sub-period corresponding to the first low-frequency refresh area;

[0022] And / or, at least one low-frequency refresh area includes a second low-frequency refresh area, the second low-frequency refresh area is adjacent to the high-frequency refresh area, and data writing is performed after data writing is performed in the high-frequency refresh area in the second type of display frame; the second sub-period corresponding to the second low-frequency refresh area is after the first sub-period corresponding to the second low-frequency refresh area;

[0023] Optionally, the first low-frequency refresh area and the second low-frequency refresh area are located on opposite sides of the high-frequency refresh area;

[0024] Optionally, the duration of the first sub-period corresponding to the first low-frequency refresh zone is greater than or equal to the duration of the first sub-period corresponding to the second low-frequency refresh zone.

[0025] Optionally, there are multiple partition enable signal lines.

[0026] The first gate driving circuit includes a plurality of cascaded shift register groups, the shift register group includes k cascaded shift register units, k is an integer greater than or equal to 2, the shift register unit includes m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different partition enable signal lines, different shift register groups are connected to the same k partition enable signal lines, and the output end of the first shift register is electrically connected to n rows of pixel circuits, n is an integer greater than or equal to 1;

[0027] The number of rows of pixel circuits in the first sub-area is less than or equal to k*m*n rows;

[0028] The first sub-period is less than or equal to k*m*n times the row period of the pixel circuit;

[0029] Optionally, the number of rows of pixel circuits in the first sub-area is greater than or equal to k*m*n / 4 rows;

[0030] The first sub-period is less than or equal to k*m*n / 4 times the row period of the pixel circuit;

[0031] Optionally, in the first type of display frame, the time when the partition enable signal line jumps from the non-enable level to the enable level and the time when the signal input to the data line switches from the fixed potential to the data signal differ by less than or equal to the row period of k*m*n pixel circuits;

[0032] and / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the non-enable level and the time when the signal input to the data line switches from the data signal to the fixed potential differs by less than or equal to the row period of k*m*n pixel circuits;

[0033] Optionally, in the first type of display frame, the time when the partition enable signal line jumps from the non-enable level to the enable level and the time when the signal input to the data line switches from the fixed potential to the data signal differ by more than or equal to k*m*n / 4 pixel circuit row periods;

[0034] and / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the non-enable level and the time when the signal input to the data line switches from the data signal to the fixed potential differs by more than or equal to k*m*n / 4 pixel circuit row periods;

[0035] Optionally, in the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the enable level are delayed successively; in the second type of display frame, the signals on the k partition enable signal lines are at the enable level.

[0036] Optionally, k-1 shift register units are connected between two adjacent shift register units connected to the same partition enable signal line;

[0037] Optionally, the second period includes a third sub-period and a fourth sub-period, the third sub-period is located before the fourth sub-period, and in the third sub-period of the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the enable level are delayed sequentially;

[0038] In the fourth sub-period of the first display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the non-enable level are delayed in sequence;

[0039] Optionally, in the first type of display frame, the moment when the signals on the k partition enable signal lines jump from the non-enable level to the enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area, and / or, in the first type of display frame, the moment when the signals on the k partition enable signal lines jump from the enable level to the non-enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0040] Optionally, the first gate driving circuit includes a plurality of cascaded shift registers.

[0041] The pixel circuit includes a driving unit and a threshold compensation unit, the threshold compensation unit is connected between the control end and the first end of the driving unit, and the control end of the threshold compensation unit is electrically connected to the output end of the shift register in the first gate driving circuit;

[0042] Optionally, the threshold compensation unit includes an N-type transistor;

[0043] And / or, the shift register includes a shift unit and an output unit, the output unit is electrically connected to the shift unit, and the output unit is connected to the partition enable signal line,

[0044] When the partition enable signal line is at an enable level, when the shift unit outputs a pulse signal, the output unit connected to the shift unit synchronously outputs a pulse signal; when the partition enable signal line is at a non-enable level, when the shift unit outputs a pulse signal, the output unit connected to the shift unit outputs a constant level;

[0045] Optionally, the output unit includes a first transistor and a second transistor;

[0046] The control end of the first transistor and the control end of the second transistor are both connected to the shift unit, the first end of the first transistor is electrically connected to the partition enable signal line, and the second end of the first transistor is electrically connected to the first end of the second transistor and the output end of the shift register;

[0047] The second terminal of the second transistor is electrically connected to the first power signal line.

[0048] Optionally, the display device includes a first gate driving circuit, a plurality of rows of pixel circuits, and at least one partition enabling signal line, the first gate driving circuit is connected to the partition enabling signal line, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line.

[0049] At least one display frame includes a first type of display frame, the first type of display frame is a refresh frame in a high frequency refresh area, the first type of display frame is a hold frame in a low frequency refresh area,

[0050] In the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level is different from the time when the signal input to the data line switches from the fixed potential to the data signal;

[0051] and / or, in the first type of display frame, the time when the signal on the partition enable signal line jumps from the enable level to the non-enable level is different from the time when the signal input to the data line switches from the data signal to the fixed potential;

[0052] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the non-enable level to the enable level is after the moment when the signal input to the data line is switched from the fixed potential to the data signal;

[0053] and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level is before the moment when the signal input to the data line switches from the data signal to the fixed potential;

[0054] Optionally, in the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level and the time when the signal input to the data line switches from the fixed potential to the data signal differ by one or more line cycles of the pixel circuit;

[0055] And / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level and the moment when the signal input to the data line switches from the data signal to the fixed potential differ by one or more pixel circuit row cycles.

[0056] Optionally, the control method of the display device further includes:

[0057] Subtract N1 rows from the starting refresh row position parameter corresponding to the high-frequency refresh area, so that the start time of inputting the data signal to the data line is advanced by the row cycle of N1 pixel circuits, and / or, add N2 rows to the ending refresh row position parameter corresponding to the high-frequency refresh area, so that the end time of inputting the data signal to the data line is delayed by the row cycle of N2 pixel circuits, so as to obtain a first control signal corresponding to the start and end time of inputting the data signal to the data line, wherein N1 and N2 are integers greater than or equal to 1;

[0058] Delaying the first control signal to obtain a second control signal, wherein the second control signal is delayed by N3 row periods of pixel circuits compared to the first control signal; N3 is an integer greater than or equal to 1;

[0059] Adjusting the parameter of the second control signal corresponding to the refresh row end position to obtain a partition enable signal;

[0060] Optionally, the moment when the partition enable signal jumps from the non-enable level to the enable level corresponds to the moment when the data signal corresponding to the start refresh row position corresponding to the high-frequency refresh area is input to the data line; and / or, the moment when the partition enable signal jumps from the enable level to the non-enable level corresponds to the moment when the data signal corresponding to the end refresh row position corresponding to the high-frequency refresh area is input to the data line;

[0061] Optionally, N1=N2=N3.

[0062] According to a second aspect of the present application, there is provided a display device, wherein a display area of ​​the display device comprises a high-frequency refresh area and a low-frequency refresh area, wherein the refresh frequency of the high-frequency refresh area is higher than the refresh frequency of the low-frequency refresh area; the display device comprises: a plurality of pixel circuits located in the high-frequency refresh area and the low-frequency refresh area; a first gate drive circuit; a data line connected to the pixel circuit; at least one partition enable signal line, the first gate drive circuit is connected to the partition enable signal line, and the first gate drive circuit is connected to the pixel circuit, wherein each display frame in at least one display frame comprises a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area, the first time period comprises a first sub-time period and a second sub-time period, and the first sub-time period is located between the second sub-time period and the second time period; at least one display frame comprises a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area, the first time period comprises a first sub-time period and a second sub-time period, and the first sub-time period is located between the second sub-time period and the second time period; A type of display frame, the first type of display frame is a refresh frame in a high-frequency refresh area, and the second type of display frame is a hold frame in a low-frequency refresh area. In the first type of display frame, in a second sub-period, a fixed potential is input to a data line; in a first sub-period, a data signal or a signal with a potential change is input to the data line, and / or, in the first sub-period, a potential different from the potential input to the data line in the second sub-period is input to the data line; in the second period, a data signal corresponding to the high-frequency refresh area is input to the data line; in the first type of display frame, a non-enable level is input to a partition enable signal line in at least part of the second sub-period; in at least part of the first sub-period, a non-enable level is input to the partition enable signal line, and in at least part of the second period, an enable level is input to the partition enable signal line.

[0063] The present application increases the frequency of the data signal input to the data line corresponding to the first sub-area, or in other words, increases the time period of the data signal input to the data line of the first type of display frame (such as a local refresh frame), so as to improve the phenomenon that the boundary line between the high-frequency refresh area and the low-frequency refresh area displays abnormally due to a sudden change in the load of the driving chip at the junction of the high-frequency refresh area and the low-frequency refresh area. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0065] Figure 1 is a flowchart of a method for controlling a display device according to an embodiment of the present application;

[0066] Figure 2A is a schematic diagram of a display device applicable to an embodiment of the present application;

[0067] Figure 2B is a schematic diagram of another display device applicable to an embodiment of the present application;

[0068] Figure 2C is a schematic diagram of another display device applicable to an embodiment of the present application;

[0069] Figure 3A is a signal timing diagram of a first type of display frame according to an embodiment of the present application;

[0070] Figure 3B is a signal timing diagram of a first type of display frame in another embodiment of the present application;

[0071] Figure 3C is a signal timing diagram of a first type of display frame in another embodiment of the present application;

[0072] Figure 4 is a signal timing diagram of another embodiment of the present application;

[0073] Figure 5 is a signal timing diagram of another embodiment of the present application;

[0074] Figure 6 is a schematic diagram of another display device applicable to the embodiment of the present application;

[0075] Figure 7 This is a schematic diagram of a partition enable signal jump according to an embodiment of the present application;

[0076] Figure 8 This is a schematic diagram of a partition enable signal transition according to another embodiment of the present application;

[0077] Fig. 9 is a circuit diagram of a shift register according to an embodiment of the present application;

[0078] Fig.10 is a schematic diagram of a signal waveform in a first type of display frame according to an embodiment of the present application;

[0079] Fig.11 is a schematic diagram of a signal waveform in a second type of display frame according to an embodiment of the present application;

[0080] Fig.12 is a structural schematic diagram of a pixel circuit according to an embodiment of the present application;

[0081] Fig.13 is a signal timing diagram of another embodiment of the present application;

[0082] Fig.14 It is a schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0083] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the embodiments of the present application should fall within the scope of protection of the embodiments of the present application.

[0084] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0085] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0086] The technical solutions in the embodiments of the present application are clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0087] As people’s living standards improve, they are surrounded by electronic products all the time, so the demand for display panels is increasing, and display technology has developed rapidly. At present, ordinary display effects can no longer meet people’s quality of life. Therefore, a new display effect of partition refresh has been developed. The refresh frequencies in different areas of the screen are different, which can provide better power consumption benefits and extend the use time of electronic products. However, when the partition refresh function is turned on, the refresh frequencies of different partitions are inconsistent. If the high refresh frequency area is entered from a light load state in a low refresh frequency area to a heavy load state, the load of the driver chip will jump, resulting in voltage stability being affected, causing display abnormalities. Therefore, the present application proposes a control method, device, electronic device and computer storage medium for a display device to at least partially solve the above problems.

[0088] Figure 1 FIG. 1 is a flowchart of a method for controlling a display device according to an embodiment of the present invention. Figure 1 As shown, the control method of the display device is applied to a display device including a high-frequency refresh area and a low-frequency refresh area. The high-frequency refresh area and the low-frequency refresh area occupy different rows of pixel circuits. The display device can be as shown in Figure 2. In Figure 2, the refresh rate of the low-frequency refresh area is 1HZ, and the refresh rate of the high-frequency refresh area is 120HZ. The actual refresh rates of the high-frequency refresh area and the low-frequency refresh area can have different settings, ensuring that the refresh rate of the high-frequency refresh area is higher than the refresh rate of the low-frequency refresh area.

[0089] The control method of the display device comprises the following steps:

[0090] Step 101: Control a data signal corresponding to a first range to be input to a data line at a first frequency, and control a data signal corresponding to a second range to be input to the data line at a second frequency.

[0091] Among them, the first frequency is greater than the second frequency, the low-frequency refresh area B includes a first sub-area D1 adjacent to the high-frequency refresh area A and a second sub-area D2 located on the side of the first sub-area D1 away from the high-frequency refresh area A, the first range R1 includes the high-frequency refresh area and the first sub-area, and the second range R2 includes the second sub-area. For example, in the first type of display frame, that is, the local refresh frame, in the scanning period corresponding to the first sub-area, a data signal is input to the data line to reduce the degree of load jump of the driver chip at the junction of the high-frequency refresh area and the low-frequency refresh area, so that the load of the driver chip changes slowly in advance or later than that of the high-frequency refresh area A, reducing the risk of display abnormality at the junction of the high-frequency refresh area and the low-frequency refresh area, and improving the display effect at the junction of the high-frequency refresh area and the low-frequency refresh area. Before the data signal transmission moment of the first row of pixel circuits in the high-frequency refresh area A, the data signal is input to the data line in advance for a period of time, and / or, after the data signal transmission moment of the last row of pixel circuits in the high-frequency refresh area A, the data signal continues to be input to the data line for a period of time. The driver chip can input a data signal to the data line.

[0092] Step 102 : Control the data signal to be written into the pixel circuit according to the partition enable signal.

[0093] In order to solve the problem that the load of the driving chip may jump, it is necessary to first configure the data signal (source) so that the data signal corresponding to the first range is input into the data line at a higher first frequency, and the data signal corresponding to the second range is input into the data line at a lower second frequency. The first range R1 includes a high-frequency refresh area and a first sub-area, and the first sub-area is adjacent to the high-frequency refresh area, that is, the first range includes the high-frequency refresh area and part of the low-frequency refresh area adjacent to the high-frequency refresh area, and the second range R2 includes a second sub-area, and the second sub-area is located on the side of the first sub-area away from the high-frequency refresh area, that is, the low-frequency refresh area includes the area of ​​the display device except the high-frequency refresh area. When displaying, the data signal can be written into the pixel circuit to enable the pixel circuit to display. For example, the display device (Display device) can be as follows Figure 2A As shown, it includes a high-frequency refresh area A and two low-frequency refresh areas B. For example, the high-frequency refresh area A occupies 500 rows of pixel circuits, and the two low-frequency refresh areas B each occupy 500 rows of pixel circuits. The first sub-area D1 may include 100 rows of pixel circuits adjacent to the high-frequency refresh area A. The first sub-area D1 adjacent to the high-frequency refresh area A occupies 100 rows of pixel circuits. For example, the first range R1 occupies 600 rows of pixel circuits. Correspondingly, the second range R2 occupies the pixel circuits in the display device except the first range R1, for example, occupies 400 rows of pixel circuits in each of the two low-frequency refresh areas B, for a total of 800 rows of pixel circuits. The display device may also be as follows Figure 2B and Figure 2C As shown, it only includes one high-frequency refresh area A and one low-frequency refresh area B. The high-frequency refresh area can be used to display games and other pictures with high-frequency refresh requirements, and the low-frequency refresh area can be used to display novels or web pages and other pictures with low refresh requirements. In the first type of display frame, that is, the partial refresh frame, that is, when the high-frequency refresh area needs to be refreshed and the low-frequency refresh area does not need to be refreshed, in the scanning period corresponding to the range of the first sub-area, the power load corresponding to the data signal changes slowly, but at this time, the control data signal is not written into the pixel circuit of the first sub-area, so no abnormality will be displayed in the display device, and at the junction of the high-frequency refresh area and the low-frequency refresh area, the power load corresponding to the data signal will not change or change slowly, so the load of the driver chip will not jump sharply instantly, thereby avoiding the abnormal display of bright lines at the junction of the high-frequency refresh area and the low-frequency refresh area in the display screen. The position where the data signal changes (the open position) avoids the starting and ending positions of the partial refresh area A, and has become stable at the starting and ending positions of the partial high-frequency refresh area A, thereby avoiding the load jump of the driver chip.

[0094] Specifically, Figure 6As shown, the display device may include: a first gate driving circuit, multiple rows of pixel circuits 1113, and at least one partition enable signal line VFE, the first gate driving circuit is connected to the partition enable signal line VFE, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line DATA.

[0095] Optionally, the first gate drive circuit is used to control the first gate drive circuit to output pulse signals of different frequencies to the high-frequency refresh area A and the low-frequency refresh area B according to the partition enable signal (including the enable level and the disable level) of the partition enable signal line VFE. One of the enable level and the disable level is a high level, and the other is a low level. For example, the enable level is a high level, and the disable level is a low level. For example, the enable level is a low level, and the disable level is a high level.

[0096] The display device may include one or more display frames. Each display frame in at least one display frame includes a first time period t1 corresponding to the low-frequency refresh area and a second time period t2 corresponding to the high-frequency refresh area, and the first time period t1 includes a first sub-period t11 corresponding to the first sub-area D1 and a second sub-period t12 corresponding to the second sub-area. At least one display frame includes a first type of display frame (i.e., a local refresh frame), the first type of display frame is a refresh frame of the high-frequency refresh area A, and the first type of display frame is a hold frame of the low-frequency refresh area B.

[0097] The first type of display frame is a refresh frame of the high-frequency refresh area A, that is, in the first type of display frame, the pixel circuit of the high-frequency refresh area A will perform data writing, and will refresh the gate voltage of the driving transistor in the pixel circuit of the high-frequency refresh area A. The first type of display frame is a hold frame of the low-frequency refresh area B, that is, in the first type of display frame, the pixel circuit of the low-frequency refresh area B will not perform data writing, and will not refresh the gate voltage of the driving transistor in the pixel circuit of the low-frequency refresh area B, and the gate of the driving transistor in the pixel circuit of the low-frequency refresh area B maintains the voltage of the previous display frame.

[0098] Optionally, the control method of the display device may further include:

[0099] like Figure 3A As shown, in the first type display frame F1, in the second sub-period t12, a fixed potential is input to the data line DATA, and in the first sub-period t11, a data signal (which may be a data signal corresponding to the first sub-area D1 of the previous second type display frame, but will not be written into the pixel circuit of the first sub-area D1) or a signal with a potential change is input to the data line DATA, or, in the first sub-period t11, a potential different from the potential input to the data line DATA in the second sub-period t12 is input to the data line DATA, and in the second period t2, a data signal corresponding to the high-frequency refresh area A is input to the data line DATA.

[0100] Since the first type of display frame is a local refresh frame, in the second sub-period t12 included in the first type of display frame, the second sub-area D2 included in the low-frequency refresh area B does not need to be refreshed. At this time, a fixed potential or a DC potential needs to be input into the data line DATA to reduce power consumption.

[0101] The first sub-period t11 and the second period t2 included in the first type of display frame correspond to the first sub-area D1 and the high-frequency refresh area, respectively. At this time, in the first sub-period t11, a data signal or a signal with a potential change is input to the data line DATA, or a potential different from the potential input to the data line DATA in the second sub-period t12 is input, and in the second period t2, a data signal corresponding to the high-frequency refresh area A is input to the data line DATA to reduce the risk of display abnormalities at the junction (i.e., the dividing line) between the high-frequency refresh area and the low-frequency refresh area.

[0102] like Figure 3A and Fig.10 As shown, in the first type of display frame, a non-enable level (for example, a low level) is input to the partition enable signal line VFE in at least part of the second sub-period t12, so that the first gate drive circuit maintains a constant potential in the second sub-period t12 and does not output a pulse signal to the pixel circuit of the second sub-area D2.

[0103] like Figure 3A and Fig.10 As shown, in the first type of display frame, in at least part of the first sub-period t11, a non-enable level (for example, a low level) is input to the partition enable signal line VFE, so that the first gate drive circuit maintains a constant potential in the first sub-period t11 and does not output a pulse signal to the pixel circuit of the first sub-area D1.

[0104] In the first type of display frame, an enable level (eg, a high level) is input to the partition enable signal line VFE during at least part of the second period t2, so that the first gate drive circuit outputs a pulse signal to the pixel circuit of the high-frequency refresh area A during the second period t2.

[0105] Optionally, the number of rows of pixel circuits in the first sub-area is greater than or equal to 1 row, and the first sub-period is less than or equal to the row period Tc of the pixel circuits. The row period Tc may be equal to the second period t2, the time difference between the start times of two adjacent pulse signals output by the first gate drive circuit.

[0106] Specifically, at least one display frame includes a second type display frame F2 (which may be a global refresh frame), the second type display frame F2 is a refresh frame of the high frequency refresh area A, and the second type display frame is a refresh frame of the low frequency refresh area B.

[0107] The second type of display frame F2 is a refresh frame of the high-frequency refresh area A, that is, in the second type of display frame, the pixel circuit of the high-frequency refresh area A will perform data writing, and will refresh the gate voltage of the driving transistor in the pixel circuit of the high-frequency refresh area A. The second type of display frame F2 is a refresh frame of the low-frequency refresh area B, that is, in the second type of display frame, the pixel circuit of the low-frequency refresh area B will perform data writing, and will refresh the gate voltage of the driving transistor in the pixel circuit of the low-frequency refresh area B.

[0108] Optionally, the control method of the display device may further include:

[0109] In the second type display frame F2, in the second sub-period t12, a data signal corresponding to the second sub-area D2 is input to the data line DATA to refresh the gate voltage of the driving transistor in the pixel circuit of the second sub-area D2.

[0110] In the second type display frame F2, a data signal corresponding to the first sub-region D1 is input to the data line DATA in the first sub-period t11 so as to refresh the gate voltage of the driving transistor in the pixel circuit of the first sub-region D1.

[0111] In the second type display frame F2, a data signal corresponding to the high frequency refresh area A is input to the data line DATA in the second period t2 so as to refresh the gate voltage of the driving transistor in the pixel circuit of the high frequency refresh area A.

[0112] In the second display frame F2, in the second sub-period t12, an enable level is input to the partition enable signal line VFE, so that the first gate driving circuit outputs a pulse signal to the pixel circuit of the second sub-area D2 in the second sub-period t12.

[0113] In the second display frame F2, an enable level is input to the partition enable signal line VFE in the first sub-period t11, so that the first gate driving circuit outputs a pulse signal to the pixel circuit of the first sub-area D1 in the first sub-period t11.

[0114] In the second display frame F2, an enable level is input to the partition enable signal line VFE in the second period t2, so that the first gate driving circuit outputs a pulse signal to the pixel circuit of the high-frequency refresh area A in the second period t2.

[0115] Optionally, M first-type display frames F1 are arranged between adjacent second-type display frames F2, and a ratio of the first frequency divided by the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

[0116] The more the number of the first-type display frames F1 between the adjacent second-type display frames F2 is, the lower the refresh frequency of the low-frequency refresh area B is.

[0117] For example, the number of first-type display frames (local refresh frames) arranged between adjacent second-type display frames (global refresh frames) can be calculated by the following formula:

[0118]

[0119] Wherein, f2 is used to represent the second frequency, and f1 is used to represent the first frequency.

[0120] Specifically, at least one low-frequency refresh area B includes a first low-frequency refresh area B1, which is adjacent to the high-frequency refresh area A and performs data writing before the high-frequency refresh area A performs data writing in the second display frame F2; the second sub-period t12 corresponding to the first low-frequency refresh area B1 is before the first sub-period t11 corresponding to the first low-frequency refresh area B1. The first period t1 corresponding to the first low-frequency refresh area B1 is before the second period t2 corresponding to the high-frequency refresh area A.

[0121] And / or, at least one low-frequency refresh area B includes a second low-frequency refresh area B2, the second low-frequency refresh area B2 is adjacent to the high-frequency refresh area A, and performs data writing after the high-frequency refresh area A performs data writing in the second type display frame F2; the second sub-period t12 corresponding to the second low-frequency refresh area B2 is after the first sub-period t11 corresponding to the second low-frequency refresh area B2. The first period t1 corresponding to the second low-frequency refresh area B2 is after the second period t2 corresponding to the high-frequency refresh area A.

[0122] The display device may include one or more of a first low-frequency refresh area B1 and a second low-frequency refresh area B2. The display device may include two display partitions with different refresh frequencies, for example, the display device may include a first low-frequency refresh area B1 and a high-frequency refresh area A, or the display device may include a high-frequency refresh area A and a second low-frequency refresh area B2. Alternatively, the display device may include three display partitions with different refresh frequencies, for example, a first low-frequency refresh area B1, a high-frequency refresh area A, and a second low-frequency refresh area B2.

[0123] The display device may include two low-frequency refresh areas, which are adjacent to the upper edge of the high-frequency refresh area and the lower edge of the high-frequency refresh area, respectively. Since the data line is connected to the pixel circuit by column, the first gate drive circuit is connected to the pixel circuit by row. For example, in the area to be refreshed, the data signal is input to the data line row by row. Under the synchronous control of the partition enable signal, the first gate drive circuit outputs a scan pulse signal, so that the corresponding transistors in the pixel circuit of the area to be refreshed are turned on, so that the gate voltage of the driving transistor in the pixel circuit of the area to be refreshed in the display device is refreshed row by row. Therefore, in the global refresh frame, the first low-frequency refresh area adjacent to the upper edge of the high-frequency refresh area will perform data writing before the high-frequency refresh area performs data writing, and in the first low-frequency refresh area, the second sub-area will perform data writing before the first sub-area performs data writing, and the second sub-period corresponding to the first low-frequency refresh area is before the first sub-period, that is, the data signal corresponding to the second sub-area corresponding to the first low-frequency refresh area is first input to the data line, and then the data signal corresponding to the first sub-area corresponding to the first low-frequency refresh area is input to the data line. Correspondingly, the second low-frequency refresh zone adjacent to the lower edge of the high-frequency refresh zone will perform data writing after the high-frequency refresh zone, and in the second low-frequency refresh zone, the second sub-zone will perform data writing after the first sub-zone, and the second sub-time period corresponding to the second low-frequency refresh zone is after the first sub-time period, that is, the data signal corresponding to the first sub-zone corresponding to the second low-frequency refresh zone is first input to the data line, and then the data signal corresponding to the second sub-zone corresponding to the second low-frequency refresh zone is input to the data line.

[0124] Optionally, the first low-frequency refresh area B1 and the second low-frequency refresh area B2 are located on opposite sides of the high-frequency refresh area A. For example, the first low-frequency refresh area B1 and the second low-frequency refresh area B2 are located on opposite sides of the high-frequency refresh area A along a first direction. The data lines extend along a first direction y and are arranged along a second direction x, and the first direction and the second direction intersect, for example, perpendicularly.

[0125] Optionally, the duration of the first sub-period t11 corresponding to the first low-frequency refresh zone B1 is greater than or equal to the duration of the first sub-period t11 corresponding to the second low-frequency refresh zone B2.

[0126] Optionally, the second low-frequency refresh area B2 may not be provided with the first sub-area, that is, Figure 5 As shown, in the first display frame F1, in the first period t1 corresponding to the second low-frequency refresh area B2, a fixed potential is input to the data line DATA.

[0127] Optional, such as Figure 6As shown, there are multiple partition enable signal lines, such as VFE1, VFE2, VFE3, and VFE4. The first gate drive circuit includes multiple cascaded shift register groups 10, and the shift register group 10 includes k cascaded shift register units 11, where k is an integer greater than or equal to 2. The shift register unit 11 includes m shift registers 111, where m is an integer greater than or equal to 1. Different shift register units 11 in the same shift register group 10 are electrically connected to different partition enable signal lines, and different shift register groups 10 are connected to the same k partition enable signal lines. The output end of the first shift register 111 is electrically connected to n rows of pixel circuits 1113, where n is an integer greater than or equal to 1. The number of rows of pixel circuits in the first sub-area D1 is less than or equal to k*m*n rows.

[0128] The number of rows of the pixel circuits in the first sub-area D1 cannot be too large, otherwise the power consumption will increase. The number of rows of the pixel circuits in the first sub-area D1 cannot be too small, and needs to be greater than or equal to m*n rows, ensuring that the number of rows of the pixel circuits is greater than or equal to the number of rows of the data signal input controlled by the enable signal in a partition enable signal line, otherwise the boundary between the low-frequency refresh area B and the high-frequency refresh area A will display abnormally.

[0129] For example, the number of rows of pixel circuits in the first sub-area D1 of the first low-frequency refresh area B1 is greater than or equal to k*m*n / 2 rows.

[0130] For example, the number of rows of pixel circuits in the first sub-area D1 of the second low-frequency refresh area B2 is less than or equal to k*m*n / 2 rows.

[0131] For example, Figure 6As shown, the display device includes a first gate driving circuit, multiple rows of pixel circuits 1113, and 4 partition enable signal lines. The multiple rows of pixel circuits 1113 are divided into two low-frequency refresh areas B and one high-frequency refresh area A. The first gate driving circuit includes multiple cascaded shift register groups 10. The shift register group 10 includes 4 cascaded shift register units 11. The shift register unit 11 includes 4 shift registers 111. Different shift register units 11 in the same shift register group 10 are electrically connected to different partition enable signal lines VFE. Different shift register groups 10 are connected to the same 4 partition enable signal lines VFE. The output end of the first-stage shift register 111 is electrically connected to one row of pixel circuits 1113 through a scan line 1112 (which can extend along the second direction x). The number of rows of pixel circuits 1113 in the first sub-area R1 is greater than or equal to 64 rows. When the data signal is input through the data line Data, the shift register 111 controls whether to output the scan pulse signal to the pixel circuit according to the partition enable signal input by the partition enable signal line VFE, so as to control whether the data signal is written into the pixel circuit 1113. Since the data line Data is output by row, in the same row cycle, when the data signal of the pixel circuit corresponding to a row is input, the data line Data will input the data signal to the pixel circuits 1113 of each column. At this time, under the control of the partition enable signal, the corresponding first-level shift register 111 outputs a scan pulse signal. At this time, the row pixel circuit 1113 corresponding to the shift register 111 of this level will write the data signal to refresh the gate voltage of the driving transistor, that is, write the voltage related to the data signal into the gate of the driving transistor, thereby realizing refresh display.

[0132] In some embodiments, all shift registers 111 in the first gate driving circuit may be connected to the same partition enable signal line VFE.

[0133] Specifically, the first sub-period t11 is less than or equal to k*m*n times the row period Tc of the pixel circuit, that is, the number of rows of the pixel circuit in the first sub-area D1 is less than or equal to k*m*n rows.

[0134] Optionally, the number of rows of pixel circuits in the first sub-area D1 is greater than or equal to k*m*n / 4 rows. The first sub-period t11 is less than or equal to k*m*n / 4 times the row period Tc of the pixel circuits.

[0135] Optionally, in the first display frame F1, the time tA when the partition enable signal line VFE jumps from the non-enable level to the enable level is different from the time tB when the signal input to the data line DATA switches from the fixed potential to the data signal (eg, Figure 3A For example, tB is ahead of tA. tA-tB may be equal to the duration of the first sub-period t11 corresponding to the first low-frequency refresh zone B1.

[0136] Optionally, in the first type of display frame F1, the time tA when the partition enable signal line VFE jumps from the non-enable level to the enable level and the time tB when the signal input to the data line DATA switches from a fixed potential to a data signal are less than or equal to the row period Tc of k*m*n pixel circuits.

[0137] Optionally, in the first display frame F1, the time tC when the partition enable signal line VFE jumps from the enable level to the non-enable level is different from the time tD when the signal input to the data line DATA switches from the data signal to the fixed potential (eg, Figure 3A For example, tD lags behind tC. tD-tC may be equal to the duration of the first sub-period t11 corresponding to the second low-frequency refresh zone B2.

[0138] Optionally, in the first display frame F1, the time tC when the partition enable signal line VFE jumps from the enable level to the non-enable level is the same as the time tD when the signal input to the data line DATA switches from the data signal to the fixed potential (eg, Figure 5 shown).

[0139] Optionally, in the first type display frame F1, the time tC when the partition enable signal line VFE jumps from the enable level to the non-enable level and the time tD when the signal input to the data line DATA switches from the data signal to the fixed potential are less than or equal to the row period Tc of k*m*n pixel circuits.

[0140] That is, in the first display frame F1, the range of inputting fixed potential to the data line is shrunk, or the range of inputting data signal to the data line is expanded to the first sub-area, while the enable signal in the sub-area enable signal line is not expanded.

[0141] Optionally, in the first type of display frame F1, the time tA when the partition enable signal line VFE jumps from the non-enable level to the enable level and the time tB when the signal input to the data line DATA switches from a fixed potential to a data signal differ by more than or equal to the row period Tc of k*m*n / 4 pixel circuits.

[0142] And / or, in the first type display frame F1, the moment tC when the partition enable signal line VFE jumps from the enable level to the non-enable level and the moment tD when the signal input to the data line DATA switches from the data signal to the fixed potential differ by more than or equal to the row period Tc of k*m*n / 4 pixel circuits.

[0143] Optional, such as Figure 6 or Fig.10 As shown, in the first display frame F1, the moments when the pulses of the signals on the k partition enable signal lines jump to the enable level are delayed successively, and in the second display frame F2, the signals on the k partition enable signal lines are at the enable level, that is, they maintain a constant potential.

[0144] Since the partition enable signal is related to the data signal, the configuration of the data signal causes the data signal to expand outward relative to the boundary between the high-frequency refresh area and the low-frequency refresh area. Therefore, the signal on the partition enable signal line needs to be delayed in the local refresh frame to ensure that the first partition located above the high-frequency refresh area will not be abnormally refreshed.

[0145] Optionally, k-1 shift register units 11 are connected between two adjacent shift register units 11 connected to the same partition enable signal line. Figure 6 As shown, three shift register units 11 are connected between two adjacent shift register units 11 connected to the partition enable signal line VFE1.

[0146] Optionally, the second period t2 includes a third sub-period t21 and a fourth sub-period t22, the third sub-period t21 is located before the fourth sub-period t23, and in the third sub-period t21 of the first type display frame F1, the moment when the pulse of the signal on the k partition enable signal lines jumps to the enable level is delayed in sequence. In the fourth sub-period t22 of the first type display frame F1, the moment when the pulse of the signal on the k partition enable signal lines jumps to the non-enable level is delayed in sequence.

[0147] Optionally, in the first type of display frame F1, the moment when the signal on the k partition enable signal lines jumps from the non-enable level to the enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area, and / or, in the first type of display frame, the moment when the signal on the k partition enable signal lines jumps from the enable level to the non-enable level is related to the position of the boundary between the high-frequency refresh area and the low-frequency refresh area.

[0148] Optionally, the first gate driving circuit includes a plurality of cascaded shift registers, the pixel circuit 1113 includes a driving unit 310 and a threshold compensation unit 320, the threshold compensation unit 320 is connected between the control end and the first end of the driving unit 310, the control end SN2 of the threshold compensation unit 320 is electrically connected to the output end GOUT of the shift register in the first gate driving circuit, and optionally, the threshold compensation unit 320 may include an N-type transistor, and / or, the shift register includes a shift unit 210 and an output unit 220, the output unit 220 is electrically connected to the shift unit 210, and the output unit 220 is connected to the partition enable signal line VFE. When the partition enable signal line VFE is at an enable level, when the shift unit 210 is a pulse signal, the output unit 220 connected to the shift unit 210 synchronously outputs a pulse signal; when the partition enable signal line VFE is at a non-enable level, when the shift unit 210 outputs a pulse signal, the output of the output unit 220 connected to the shift unit 210 maintains a constant level. The control terminal SN2 of the threshold compensation unit 320 is electrically connected to the output terminal GOUT of the shift register in the first gate driving circuit through the scan line 1112 .

[0149] That is, Figure 7-8 , Figure 10-11 , Fig.12 As shown, when the partition enable signal line is at an enable level (for example, VH), the data signal in the data line needs to be written into the pixel circuit. At this time, the shift unit outputs a pulse signal, so that the output unit connected to the shift unit synchronously outputs a pulse signal to turn on the threshold compensation unit 320 to achieve data writing and refresh the voltage of the control end of the driving unit; while the partition enable signal line is at a non-enable level and the shift unit outputs a pulse signal, the data signal in the data line should not be written into the pixel circuit. Therefore, at this time, the output of the output unit connected to the shift unit maintains a constant level to turn off the threshold compensation unit 320 for data writing, and the voltage of the control end of the driving unit will not be refreshed. The control end of the driving unit maintains the voltage of the previous display frame.

[0150] The pixel circuit may further include a data writing unit 340, and the data writing unit 340 is connected between the data line Data and the second end of the driving unit 310. For example, the data writing unit includes a fifth transistor T5.

[0151] The pixel circuit may further include part or all of an initialization unit, a light emitting control unit, and a reset unit. The initialization unit includes a sixth transistor T6, the light emitting control unit includes a seventh transistor T7 and / or an eighth transistor T8, and the reset unit includes a ninth transistor T9 and / or a tenth transistor T10. A first end of the fifth transistor T5 is connected to the data line Data, a second end of the fifth transistor T5 is connected to the second end of the driving transistor T3 (which can be used as the second end of the driving unit), and a control end of the fifth transistor T5 is connected to the first scan line SP1; the seventh transistor T7, the driving transistor T3, the eighth transistor T8 and the light emitting unit 130 are connected in series between the second power line ELVDD and the third power line ELVSS, and the control end of the seventh transistor T7 and the control end of the eighth transistor T8 are connected to the light emitting control line EM. Two ends of the storage capacitor Cst are respectively connected to the control end of the driving module 310 and the power line ELVDD. The sixth transistor T6 and the fourth transistor T4 are connected in series between the first signal line Vrefn1 and the control end of the driving module 310. The control end of the fourth transistor T4 is electrically connected to the output end of the shift register in the first gate driving circuit as the control end of the threshold compensation unit 320. The control end of the sixth transistor T6 is connected to the third scan line SN1. The second end of the ninth transistor T9 is connected to the second signal line Vrefp, the control end of the ninth transistor T9 is connected to the second scan line SP2, the second end of the tenth transistor T10 is connected to the third signal line Vrefn2, and the control end of the tenth transistor T10 is connected to the second scan line SP2. The first end of the ninth transistor T9 can be connected to the first end or the second end of the driving transistor. The first end of the tenth transistor T10 is connected to the first end of the light emitting unit.

[0152] Optionally, in the first initialization stage, the initialization unit and the threshold compensation unit 320 are turned on to initialize the driving transistor. In the data writing stage, the data writing unit and the threshold compensation unit 320 are turned on to write the voltage obtained by compensating the threshold voltage of the driving transistor T3 to the target driving value to the gate of the driving transistor T3. In the second initialization stage (for example, overlapping or staggered with the first initialization stage or the data writing stage), the reset unit is turned on to reset the first end of the light-emitting unit 130 and / or the first end or the second end of the driving transistor. In the light-emitting stage, the seventh transistor T7 and the eighth transistor T8 are turned on, and the light-emitting unit 130 emits light.

[0153] The refresh frame may include a first initialization phase, a data writing phase, a second initialization phase, and a light emitting phase. The hold frame may include a second initialization phase and a light emitting phase. The hold frame may not include the first initialization phase and the data writing phase. Optionally, the sixth transistor T6 may be connected between the first signal line Vrefn1 and the control end of the driving module 310. The fourth transistor T4 may be connected between the second end of the driving module 310 and the control end of the driving module 310.

[0154] Optional, such as Fig. 9 As shown, the shift register includes a shift unit 210 and an output unit 220, the output unit 220 is electrically connected to the shift unit 210, and the output unit 220 includes a first transistor T21 and a second transistor T2; the control end of the first transistor T1 and the control end of the second transistor T2 are both connected to the shift unit 210, the first end of the first transistor T1 is electrically connected to the partition enable signal line VFE (for example, one of VFE1 to VFE4), the second end of the first transistor T1 is electrically connected to the first end of the second transistor T2 and the output end GOUT of the shift register; the second end of the second transistor T2 is electrically connected to the first power signal line NVGL (which can be a low voltage).

[0155] The shift unit 210 includes an output subunit and a control subunit, and the output subunit may include an eleventh transistor T11 and a twelfth transistor T12. The control subunit may include a part or all of the thirteenth transistor T13 to the twenty-third transistor T23, the first capacitor C1, the second capacitor C2, and the third capacitor C3, wherein the first end of the eighteenth transistor T18, the control end of the seventeenth transistor T17, the control end of the sixteenth transistor T16, and the control end of the thirteenth transistor T13 are all connected to the first power signal line NVGL, the control end of the eighteenth transistor T18 and the control end of the twentieth transistor T20 are all connected to the first clock signal terminal SCK1, and the first end of the fifteenth transistor T15, the control end of the fourteenth transistor T14 The control end of the twenty-second transistor T22, the control end of the twenty-second transistor T22 and the first end of the second capacitor C2 are all connected to the second clock signal end SCK2, the first end of the twenty-first transistor T21 and the first end of the twenty-third transistor T23 are all connected to the fourth power line NVGH, the first end of the twentieth transistor T20 is connected to the start signal line SIN, the first end of the eleventh transistor T11 is connected to the fourth power line NVGH (which can be a high voltage), the second end of the eleventh transistor T11 outputs the shift signal SOUT, and the first end of the twelfth transistor T12 is connected to the first power signal line NVGL.

[0156] Specifically, the display device includes a first gate drive circuit, multiple rows of pixel circuits, and at least one partition enable signal line, the first gate drive circuit is connected to the partition enable signal line, the first gate drive circuit is connected to the pixel circuit, the pixel circuit is connected to the data line, and at least one display frame includes a first type of display frame, the first type of display frame is a refresh frame in a high-frequency refresh area, and the first type of display frame is a hold frame in a low-frequency refresh area.

[0157] In the first type of display frame, the moment when the signal on the partition enable signal line jumps from the non-enable level to the enable level is different from the moment when the signal input to the data line is switched from a fixed potential to a data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level is different from the moment when the signal input to the data line is switched from the data signal to a fixed potential.

[0158] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the non-enable level to the enable level is after the moment when the signal input to the data line is switched from a fixed potential to a data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level is before the moment when the signal input to the data line is switched from the data signal to a fixed potential.

[0159] Optionally, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the non-enable level to the enable level and the moment when the signal input to the data line switches from the fixed potential to the data signal differ by one or more row cycles of the pixel circuit; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level and the moment when the signal input to the data line switches from the data signal to the fixed potential differ by one or more row cycles of the pixel circuit.

[0160] Optional, such as Fig.13 As shown, the control method of the display device may also include: subtracting N1 rows from the starting refresh row position parameter corresponding to the high-frequency refresh zone, so that the start time of inputting the data signal to the data line is advanced by the row cycle of N1 pixel circuits, and / or, adding N2 rows to the ending refresh row position parameter corresponding to the high-frequency refresh zone, so that the end time of inputting the data signal to the data line is delayed by the row cycle of N2 pixel circuits, so as to obtain the first control signal corresponding to the start and end time of inputting the data signal to the data line. N1 and N2 are integers greater than or equal to 1. N1*Tc may be equal to the duration of the first sub-period t11 corresponding to the first low-frequency refresh zone B1. N2*Tc may be equal to the duration of the first sub-period t11 corresponding to the first low-frequency refresh zone B2.

[0161] In the first type of display frame, the first sub-area of ​​the first low-frequency refresh area receives the data signal earlier than the high-frequency refresh area, which can be achieved by setting the starting refresh line position parameter corresponding to the high-frequency refresh area minus N1 lines, so as to modify the starting refresh line position corresponding to the high-frequency refresh area to the edge of the first sub-area on the side away from the high-frequency refresh area. In the first type of display frame, the first sub-area of ​​the second low-frequency refresh area receives the data signal later than the high-frequency refresh area, which can be achieved by setting the starting refresh line position parameter corresponding to the high-frequency refresh area plus N2 lines, so as to modify the starting refresh line position corresponding to the high-frequency refresh area to the edge of the first sub-area on the side away from the high-frequency refresh area.

[0162] Optionally, the control method of the display device may further include: delaying the first control signal to obtain a second control signal, wherein the second control signal is delayed by N3 row periods of pixel circuits compared to the first control signal; N3 is an integer greater than or equal to 1;

[0163] The parameter of the second control signal corresponding to the refresh row end position is adjusted to obtain a partition enable signal.

[0164] Optionally, the moment when the partition enable signal jumps from the non-enable level to the enable level corresponds to the moment when the data signal corresponding to the starting refresh row position corresponding to the high-frequency refresh area is input to the data line; and / or, the moment when the partition enable signal jumps from the enable level to the non-enable level corresponds to the moment when the data signal corresponding to the ending refresh row position corresponding to the high-frequency refresh area is input to the data line.

[0165] like Figure 6 , Figure 10-11 As shown, Figure 6 , Fig.10 and Fig.11 The case where k=4 and m=4 is schematically shown in the figure. The display device may include 3n shift registers, and the two low-frequency refresh areas B and the high-frequency refresh area A are respectively connected to n shift registers, wherein SOUT1-SOUTn are respectively shift pulse signals output by the shift units in the first n-stage shift registers corresponding to the first low-frequency refresh area B1; SOUTn+1-SOUT2n are respectively shift pulse signals output by the shift units in the n+1-stage shift register to the 2n-stage shift register corresponding to the high-frequency refresh area A; SOUT2n+1-SOUT3n are respectively shift pulse signals output by the shift units in the 2n+1-stage shift register to the 3n-stage shift register corresponding to the second low-frequency refresh area B2.

[0166] GOUT1-GOUTn are the scanning pulse signals output from the first n-level shift registers corresponding to the first low-frequency refresh zone B1; GOUTn+1-GOUT2n are the scanning pulse signals output from the n+1-level shift register to the 2n-level shift register corresponding to the high-frequency refresh zone A; GOUT2n+1-GOUT3n are the scanning pulse signals output from the 2n+1-level shift register to the 3n-level shift register corresponding to the second low-frequency refresh zone B2.

[0167] refer to Fig.10 In the first display frame F1, the refresh frequency of the two low-frequency refresh areas B is a low refresh frequency, the corresponding partition enable signals in the partition enable signal lines (e.g., VFE1 to VFE4) are all non-enable levels, such as low level VL, and the output terminal GOUT of the shift register outputs a non-enable level (i.e., an invalid level, such as a shutdown level), such as a low level VL. The two low-frequency refresh areas B will not receive the enable level pulse (i.e., a scan pulse signal, such as a turn-on pulse signal) output by the output terminal GOUT of the corresponding shift register. The refresh frequency of the high-frequency refresh area A is a high refresh frequency, the partition enable signal on the partition enable signal line (for example, VFE1 to VFE4) is an enable level VH, and the moment when the pulse of the signal on the four partition enable signal lines jumps to the enable level is delayed in sequence. For example, within the delay time of the partition enable signal line VFE2 compared to the enable level of the partition enable signal line VFE1, GOUTn+1 to GOUTn+4 are enable level pulses (i.e., the conduction pulses of the threshold compensation unit) in sequence; within the delay time of the partition enable signal line VFE3 compared to the enable level of the partition enable signal line VFE2, GOUTn+5 to GOUTn+8 are enable level pulses in sequence; within the delay time of the partition enable signal line VFE4 compared to the enable level of the partition enable signal line VFE3, GOUTn+9 to GOUTn+12 are enable level pulses in sequence. The high-frequency refresh area A can receive the enable level pulse output by the output terminal GOUT of the corresponding shift register.

[0168] refer to Fig.11 In the second display frame F2, both the low-frequency refresh area B and the high-frequency refresh area A can receive the scan pulse signal outputted by the output end GOUT of the corresponding shift register, that is, GOUT1 to GOUT3n are scan pulse signals in sequence, therefore, the partition enable signals on the four partition enable signal lines (e.g., VFE1 to VFE4) are at the enable level VH. The scan pulse signal outputted by the shift register, that is, the signal outputted by the output end of the output unit 220 is the same as the shift signal outputted by the output end of the shift unit 210.

[0169] The pixel circuit can be Fig.12As shown, the pixel driving circuit includes a threshold compensation unit 120, and the control end of the threshold compensation unit 320 is used to receive the output signal of the first gate driving circuit, and the pulse frequency of the output signal of the first gate driving circuit can be controlled by a partition enable signal. The display device includes a partition enable signal line, and each partition enable signal line can receive a partition enable signal output by the chip. During the scanning process of the first type of display frame, when entering the high-frequency refresh area A from the low-frequency refresh area B1, the partition enable signal changes from a low level to a high level, which is equivalent to the first type of display frame. In the period corresponding to the display partition of the low-frequency refresh area, the partition enable signal is a non-enable level, such as a low level, so that the first gate driving circuit does not output a conduction pulse to the display partition of the low refresh frequency, and continuously outputs the off level of the threshold compensation unit 320. In the scanning period corresponding to the high-frequency refresh area, the partition enable signal is an enable level, such as a high level, so that the first gate driving circuit outputs a conduction pulse to the high-frequency refresh area, so that the threshold compensation unit 320 is turned on.

[0170] Another aspect of the present application provides a display device. The display area of ​​the display device includes a high-frequency refresh area and a low-frequency refresh area, and the refresh frequency of the high-frequency refresh area is higher than the refresh frequency of the low-frequency refresh area.

[0171] The display device comprises:

[0172] A plurality of pixel circuits 1113 are located in a high-frequency refresh area A and a low-frequency refresh area B;

[0173] a first gate driving circuit;

[0174] A data line connected to a pixel circuit;

[0175] At least one partition enable signal line, a first gate drive circuit is connected to the partition enable signal line, and the first gate drive circuit is connected to the pixel circuit, wherein each display frame in at least one display frame includes a first time period t1 corresponding to the low-frequency refresh area B and a second time period t2 corresponding to the high-frequency refresh area A, the first time period includes a first sub-period and a second sub-period, and the first sub-period is located between the second sub-period and the second time period.

[0176] At least one display frame includes a first type of display frame, the first type of display frame is a refresh frame in a high frequency refresh area, the first type of display frame is a hold frame in a low frequency refresh area,

[0177] In the first type of display frame, in the second sub-period, a fixed potential is input to the data line; in the first sub-period, a data signal or a signal with a changing potential is input to the data line, and / or, in the first sub-period, a potential different from the potential input to the data line in the second sub-period is input to the data line; in the second period, a data signal corresponding to the high-frequency refresh area is input to the data line.

[0178] In the first type of display frame, a non-enable level is input to the partition enable signal line during at least part of the second sub-period; a non-enable level is input to the partition enable signal line during at least part of the first sub-period, and an enable level is input to the partition enable signal line during at least part of the second period.

[0179] This embodiment can be combined with some or all of the features of the above embodiments, which will not be described in detail here.

[0180] The display device may include a mobile phone, a smart wearable device, a vehicle-mounted display device, a laptop computer or a tablet computer, etc.

[0181] The specific implementation of each device and module in the display device can refer to the corresponding description of the corresponding steps and units in the above-mentioned display device control method embodiment, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, which will not be repeated here.

[0182] In this embodiment, an electronic device 500 is provided, such as Fig.14 As shown, the electronic device 500 may include: a processor 501, a communication interface 502, a memory 503, and a communication bus 504. Among them:

[0183] The processor 501 , the communication interface 502 , and the memory 503 communicate with each other via the communication bus 504 .

[0184] The communication interface 502 is used to communicate with other electronic devices or servers.

[0185] The processor 501 is used to execute the program 505, and specifically can execute the relevant steps in the above-mentioned display device control method embodiment.

[0186] Specifically, the program 505 may include program codes, which include computer operation instructions.

[0187] The processor 501 may be a CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or may be configured as one or more integrated circuits. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs, or processors of different types, such as one or more CPUs and one or more ASICs.

[0188] The memory 503 is used to store the program 505. The memory 503 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0189] The program 505 can be specifically used to enable the processor 501 to execute the control method of the display device in the aforementioned embodiment.

[0190] The specific implementation of each step in program 505 can refer to the corresponding description of the corresponding steps and units in the above-mentioned control method embodiment of the display device, which will not be repeated here. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, which will not be repeated here.

[0191] The electronic device 500 of the embodiment of the present application increases the frequency of the data signal input to the data line corresponding to the first sub-area, or in other words, increases the time period of the data signal input to the data line of the first type of display frame (such as a local refresh frame), so as to improve the phenomenon that the boundary line between the high-frequency refresh area and the low-frequency refresh area displays abnormally due to a sudden change in the load of the driving chip at the junction of the high-frequency refresh area and the low-frequency refresh area.

[0192] In this embodiment, a computer-readable storage medium is provided, which stores instructions for causing a machine to execute the control method of the display device as described herein. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code for implementing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device is enabled to read and execute the program code stored in the storage medium.

[0193] In this case, the program code read from the storage medium itself can implement the functions in the above method embodiments, so the program code and the storage medium storing the program code constitute part of the present application.

[0194] The storage medium embodiments for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card, and a ROM. Alternatively, the program code can be downloaded from a server computer by a communication network.

[0195] In this embodiment, a computer program product is provided, including computer instructions, which instruct a computing device to perform operations corresponding to the above method embodiments.

[0196] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present application can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present application.

[0197] The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as CD ROM, RAM, floppy disk, hard disk or magneto-optical disk), or implemented as a computer code originally stored in a remote recording medium or a non-temporary machine-readable medium downloaded through a network and stored in a local recording medium, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a special-purpose processor or programmable or special-purpose hardware (such as ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (for example, RAM, ROM, flash memory, etc.) that can store or receive software or computer code, and when the software or computer code is accessed and executed by a computer, a processor or hardware, the method described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method shown here, the execution of the code converts the general-purpose computer into a special-purpose computer for executing the method shown here. Although the present application has been shown and described with respect to one or more implementations, those skilled in the art will think of equivalent deformations and modifications based on the reading and understanding of this specification and the accompanying drawings. The present application includes all such modifications and variations, and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-described components, the terms used to describe such components are intended to correspond to any component that performs the specified function of the component (e.g., which is functionally equivalent) (unless otherwise indicated), even if not structurally equivalent to the disclosed structure that performs the function in the exemplary implementation of the present specification shown herein.

[0198] That is, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the specification and drawings of the present application, such as the mutual combination of technical features between the embodiments, or direct or indirect application in other related technical fields, are also included in the patent protection scope of the present application.

[0199] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0200] In order to enable any technician in the field to implement and use the application, the application provides the above description. In the above description, various details are listed for the purpose of explanation. It should be understood that those of ordinary skill in the art can recognize that the application can also be implemented without using these specific details. In other embodiments, the well-known process will not be elaborated in detail to avoid unnecessary details that make the description of the application obscure. Therefore, the application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the application.

[0201] It should be noted that, under the premise of no conflict, the various embodiments and / or the technical features in the various embodiments described in this application can be arbitrarily combined with each other, and the technical solution obtained after the combination should also fall within the protection scope of this application.

[0202] It should be understood that the specific examples in the embodiments of the present application are only to help those skilled in the art better understand the embodiments of the present application, rather than to limit the scope of the embodiments of the present application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and these improvements or modifications all fall within the scope of protection of the present application. The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be based on the scope of protection of the claims.

Claims

1. A control method for a display device, applied to a display device comprising a high-frequency refresh area and a low-frequency refresh area, wherein the high-frequency refresh area and the low-frequency refresh area occupy different rows of pixel circuits, characterized in that: The method comprises: Controlling a data signal corresponding to a first range to be input to a data line at a first frequency, and controlling a data signal corresponding to a second range to be input to a data line at a second frequency, wherein the first frequency is greater than the second frequency, the low-frequency refresh area includes a first sub-area adjacent to the high-frequency refresh area and a second sub-area located on a side of the first sub-area away from the high-frequency refresh area, the first range includes the high-frequency refresh area and the first sub-area, and the second range includes the second sub-area; The data signal is controlled to be written into the pixel circuit according to a partition enable signal.

2. The method according to claim 1, characterized in that The display device includes a first gate driving circuit, a plurality of rows of pixel circuits, and at least one partition enabling signal line, wherein the first gate driving circuit is connected to the partition enabling signal line, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line. Each display frame in at least one display frame includes a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area, the first time period includes a first sub-time period corresponding to the first sub-area and a second sub-time period corresponding to the second sub-area; The at least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a hold frame of the low-frequency refresh area. The method further comprises: In the first type of display frame, in the second sub-period, a fixed potential is input to the data line; in the first sub-period, a data signal or a signal with a potential change is input to the data line, or, in the first sub-period, a potential different from the potential input to the data line in the second sub-period is input to the data line, and in the second period, a data signal corresponding to the high-frequency refresh area is input to the data line; In the first type of display frame, during at least part of the second sub-period, a non-enable level is input to the partition enable signal line; during at least part of the first sub-period, a non-enable level is input to the partition enable signal line, and during at least part of the second sub-period, an enable level is input to the partition enable signal line; Preferably, the first gate driving circuit is used to control the first gate driving circuit to output pulse signals of different frequencies to the high-frequency refresh area and the low-frequency refresh area according to the partition enable signal of the partition enable signal line; Preferably, the number of rows of pixel circuits in the first sub-area is greater than or equal to 1 row; The first sub-period is less than or equal to a row period of the pixel circuit.

3. The method according to claim 2, characterized in that At least one display frame includes a second type of display frame, the second type of display frame is a refresh frame of the high-frequency refresh area, and the second type of display frame is a refresh frame of the low-frequency refresh area, The method further comprises: In the second type of display frame, in the second sub-period, a data signal corresponding to the second sub-area is input to the data line; in the first sub-period, a data signal corresponding to the first sub-area is input to the data line; in the second sub-period, a data signal corresponding to the high-frequency refresh area is input to the data line; In the second type of display frame, in the second sub-period, an enable level is input to the partition enable signal line; in the first sub-period, an enable level is input to the partition enable signal line; in the second sub-period, an enable level is input to the partition enable signal line; Preferably, M first-category display frames are arranged between adjacent second-category display frames, and a ratio of the first frequency divided by the second frequency is equal to M+1, where M is an integer greater than or equal to 1.

4. The method according to claim 3, characterized in that The method further comprises: At least one of the low-frequency refresh areas includes a first low-frequency refresh area, the first low-frequency refresh area is adjacent to the high-frequency refresh area, and data writing is performed before data writing is performed in the high-frequency refresh area in the second type of display frame; the second sub-period corresponding to the first low-frequency refresh area is before the first sub-period corresponding to the first low-frequency refresh area; And / or, at least one of the low-frequency refresh areas includes a second low-frequency refresh area, the second low-frequency refresh area is adjacent to the high-frequency refresh area, and data writing is performed after data writing is performed in the high-frequency refresh area in the second type of display frame; the second sub-period corresponding to the second low-frequency refresh area is after the first sub-period corresponding to the second low-frequency refresh area; Preferably, the first low-frequency refresh area and the second low-frequency refresh area are located on two opposite sides of the high-frequency refresh area; Preferably, a duration of the first sub-period corresponding to the first low-frequency refresh zone is greater than or equal to a duration of the first sub-period corresponding to the second low-frequency refresh zone.

5. The method according to claim 3, characterized in that: There are multiple partition enable signal lines. The first gate driving circuit includes a plurality of cascaded shift register groups, the shift register groups include k cascaded shift register units, k is an integer greater than or equal to 2, the shift register units include m shift registers, m is an integer greater than or equal to 1, different shift register units in the same shift register group are electrically connected to different partition enable signal lines, different shift register groups are connected to the same k partition enable signal lines, and an output end of a shift register at one level is electrically connected to n rows of pixel circuits, n is an integer greater than or equal to 1; The number of rows of pixel circuits in the first sub-area is less than or equal to k*m*n rows; The first sub-period is less than or equal to k*m*n times the row period of the pixel circuit; Preferably, the number of rows of pixel circuits in the first sub-area is greater than or equal to k*m*n / 4 rows; The first sub-period is less than or equal to k*m*n / 4 times the row period of the pixel circuit; Preferably, in the first type of display frame, the difference between the moment when the partition enable signal line jumps from the non-enable level to the enable level and the moment when the signal input to the data line switches from the fixed potential to the data signal is less than or equal to k*m*n row periods of the pixel circuit; and / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the non-enable level and the time when the signal input to the data line switches from the data signal to the fixed potential differ by less than or equal to k*m*n row periods of the pixel circuit; Preferably, in the first type of display frame, the time when the partition enable signal line jumps from the non-enable level to the enable level and the time when the signal input to the data line switches from the fixed potential to the data signal differ by more than or equal to k*m*n / 4 row periods of the pixel circuit; and / or, in the first type of display frame, the time when the partition enable signal line jumps from the enable level to the non-enable level and the time when the signal input to the data line switches from the data signal to the fixed potential differ by more than or equal to k*m*n / 4 row periods of the pixel circuit; Preferably, in the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the enable level are delayed successively; in the second type of display frame, the signals on the k partition enable signal lines are at the enable level.

6. The method according to claim 5, characterized in that k-1 shift register units are connected between two adjacent shift register units connected to the same partition enable signal line; Preferably, the second period includes a third sub-period and a fourth sub-period, the third sub-period is located before the fourth sub-period, and in the third sub-period of the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the enable level are delayed in sequence; In the fourth sub-period of the first type of display frame, the moments when the pulses of the signals on the k partition enable signal lines jump to the non-enable level are delayed in sequence; Preferably, in the first type of display frame, the moment when the signals on the k partition enable signal lines jump from the non-enable level to the enable level is related to the position of the boundary line between the high-frequency refresh area and the low-frequency refresh area, and / or, in the first type of display frame, the moment when the signals on the k partition enable signal lines jump from the enable level to the non-enable level is related to the position of the boundary line between the high-frequency refresh area and the low-frequency refresh area.

7. The method according to claim 2, characterized in that The first gate driving circuit includes a plurality of cascaded shift registers, The pixel circuit comprises a driving unit and a threshold compensation unit, wherein the threshold compensation unit is connected between a control terminal and a first terminal of the driving unit, and the control terminal of the threshold compensation unit is electrically connected to an output terminal of the shift register in the first gate driving circuit; Preferably, the threshold compensation unit comprises an N-type transistor; And / or, the shift register comprises a shift unit and an output unit, the output unit is electrically connected to the shift unit, and the output unit is connected to the partition enable signal line, When the partition enable signal line is at an enable level and the shift unit outputs a pulse signal, the output unit connected to the shift unit synchronously outputs a pulse signal; When the partition enable signal line is at a non-enable level and the shift unit outputs a pulse signal, the output of the output unit connected to the shift unit maintains a constant level; Preferably, the output unit comprises a first transistor and a second transistor; The control end of the first transistor and the control end of the second transistor are both connected to the shift unit, the first end of the first transistor is electrically connected to the partition enable signal line, and the second end of the first transistor is electrically connected to the first end of the second transistor and the output end of the shift register; The second terminal of the second transistor is electrically connected to the first power signal line.

8. The method according to claim 1, characterized in that The display device includes a first gate driving circuit, a plurality of rows of pixel circuits, and at least one partition enabling signal line, wherein the first gate driving circuit is connected to the partition enabling signal line, the first gate driving circuit is connected to the pixel circuit, and the pixel circuit is connected to the data line. The at least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, and the first type of display frame is a hold frame of the low-frequency refresh area. In the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level is different from the time when the signal input to the data line switches from the fixed potential to the data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level is different from the moment when the signal input to the data line switches from the data signal to the fixed potential; Preferably, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the non-enable level to the enable level is after the moment when the signal input to the data line switches from the fixed potential to the data signal; and / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level is before the moment when the signal input to the data line switches from the data signal to the fixed potential; Preferably, in the first type of display frame, the time when the signal on the partition enable signal line jumps from the non-enable level to the enable level and the time when the signal input to the data line switches from the fixed potential to the data signal differ by one or more row cycles of the pixel circuit; And / or, in the first type of display frame, the moment when the signal on the partition enable signal line jumps from the enable level to the non-enable level and the moment when the signal input to the data line switches from the data signal to the fixed potential differ by one or more row cycles of the pixel circuit.

9. The method according to claim 1, characterized in that: The method further comprises: Subtract N1 rows from the starting refresh row position parameter corresponding to the high-frequency refresh area, so that the start time of inputting the data signal to the data line is advanced by N1 row cycles of the pixel circuit, and / or, add N2 rows to the ending refresh row position parameter corresponding to the high-frequency refresh area, so that the end time of inputting the data signal to the data line is delayed by N2 row cycles of the pixel circuit, so as to obtain a first control signal corresponding to the start and end time of inputting the data signal to the data line, wherein N1 and N2 are integers greater than or equal to 1; Delaying the first control signal to obtain a second control signal, wherein the second control signal is delayed by N3 row periods of the pixel circuit compared to the first control signal; N3 is an integer greater than or equal to 1; Adjusting the parameter of the second control signal corresponding to the refresh row end position to obtain a partition enable signal; Preferably, the moment when the partition enable signal jumps from the non-enable level to the enable level corresponds to the moment when the data signal corresponding to the start refresh row position corresponding to the high-frequency refresh area is input to the data line; and / or, the moment when the partition enable signal jumps from the enable level to the non-enable level corresponds to the moment when the data signal corresponding to the end refresh row position corresponding to the high-frequency refresh area is input to the data line; Preferably, N1=N2=N3.

10. A display device, characterized in that: The display area of ​​the display device includes a high-frequency refresh area and a low-frequency refresh area, and the refresh frequency of the high-frequency refresh area is higher than the refresh frequency of the low-frequency refresh area; The display device comprises: A plurality of pixel circuits are located in the high-frequency refresh area and the low-frequency refresh area; a first gate driving circuit; A data line connected to the pixel circuit; at least one partition enabling signal line, the first gate driving circuit is connected to the partition enabling signal line, the first gate driving circuit is connected to the pixel circuit, Each display frame in at least one display frame includes a first time period corresponding to the low-frequency refresh area and a second time period corresponding to the high-frequency refresh area, the first time period includes a first sub-time period and a second sub-time period, and the first sub-time period is located between the second sub-time period and the second time period; At least one display frame includes a first type of display frame, the first type of display frame is a refresh frame of the high-frequency refresh area, the first type of display frame is a hold frame of the low-frequency refresh area, In the first type of display frame, in the second sub-period, a fixed potential is input to the data line; in the first sub-period, a data signal or a signal with a potential change is input to the data line, and / or, in the first sub-period, a potential different from the potential input to the data line in the second sub-period is input to the data line; in the second period, a data signal corresponding to the high-frequency refresh area is input to the data line; In the first type of display frame, a non-enable level is input to the partition enable signal line during at least part of the second sub-period, a non-enable level is input to the partition enable signal line during at least part of the first sub-period, and an enable level is input to the partition enable signal line during at least part of the second period.

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