Scanning circuit, display panel and display device

Abstract

The embodiment of the invention provides a scanning circuit, a display panel and a display device, the scanning circuit at least comprises a plurality of cascaded first shift register units, each first shift register unit comprises a first input module and a first cascade module, the input end of the first input module is used for receiving a first trigger signal, and the input end of the first cascade module is used for receiving a second trigger signal; the output end of the first cascade module is used for outputting a first cascade signal; the first shift register unit further comprises a first voltage stabilizing switch module, and the output end of the first voltage stabilizing switch module is electrically connected with the output end of the first input unit. And / or the output end of the first voltage stabilizing switch module is electrically connected with part of the control end of the first cascade module. The stability of the potential of the output end of the first input module and / or the stability of the potential of part of the control end of the first cascade module can be improved, and the working reliability of the first shift register unit can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a scanning circuit, a display panel and a display device. Background Art

[0002] In the field of display technology, a plurality of scanning circuits are usually provided in a display panel to drive pixel circuits in a display area to operate. The scanning circuits are usually composed of a plurality of cascaded shift register units.

[0003] However, in the prior art, there is a problem of abnormal node potential in the shift register unit, which easily affects the working reliability of the shift register unit. In view of this, a solution is urgently needed. Summary of the invention

[0004] In view of this, embodiments of the present application provide a scanning circuit, a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a scanning circuit, comprising at least a plurality of cascaded first shift register units, the first shift register unit comprising a first input module and a first cascade module, the input end of the first input module being used to receive a first trigger signal, and the output end of the first cascade module being used to output a first cascade signal; the first shift register unit also comprises a first voltage stabilizing switch module, the output end of the first voltage stabilizing switch module being electrically connected to the output end of the first input unit; and / or the output end of the first voltage stabilizing switch module being electrically connected to part of the control end of the first cascade module.

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present application provides a display panel, comprising a scanning circuit as provided in the first aspect.

[0007] In a third aspect, based on the same inventive concept, an embodiment of the present application provides a display device, comprising a display panel provided in the second aspect.

[0008] In an embodiment of the present application, if the output end of the first voltage-stabilizing switch module is electrically connected to the output end of the first input module, a voltage-stabilizing signal can be provided to the output end of the first input module through the first voltage-stabilizing switch module to compensate for the potential loss during the output process of the first input module, which is beneficial to improving the accuracy and stability of the potential at the output end of the first input module, thereby improving the working reliability of other modules that receive the potential at the output end of the first input module, and further improving the working reliability of the first shift register unit.

[0009] If the output end of the first voltage-stabilizing switch module is electrically connected to part of the control end of the first cascade module, a voltage-stabilizing signal can be provided to part of the control end of the first cascade module through the first voltage-stabilizing switch module, which is beneficial to improving the stability of the potential of the control end of the first cascade module, thereby improving the working reliability of the first cascade module, and further improving the working reliability of the first shift register unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application; Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application; Figure 3 A partial schematic diagram of a first shift register unit provided in an embodiment of the present application; Figure 4 A partial schematic diagram of another first shift register unit provided in an embodiment of the present application; Figure 5 A schematic diagram of a first shift register unit provided in an embodiment of the present application; Figure 6 for Figure 5 A schematic diagram of the first shift register unit shown; Figure 7 A schematic diagram of another first shift register unit provided in an embodiment of the present application; Figure 8 for Figure 7 The schematic diagram of the first shift register unit shown; Fig. 9 A schematic diagram of another first shift register unit provided in an embodiment of the present application; Fig.10 for Fig. 9 A schematic diagram of the first shift register unit shown; Fig.11 A schematic diagram of another first shift register unit provided in an embodiment of the present application; Fig.12 for Fig.11 A schematic diagram of the first shift register unit shown; Fig.13 A schematic diagram of another first shift register unit provided in an embodiment of the present application; Fig.14 for Fig.13 A schematic diagram of the first shift register unit shown; Fig.15 A connection diagram of a pixel circuit provided in an embodiment of the present application; Fig.16 A schematic diagram of a first shift register unit provided in an embodiment of the present application; Fig.17 for Fig.16 A timing diagram of the first shift register unit shown; Fig.18 A schematic plan view of another display panel provided in an embodiment of the present application; Fig.19 A simplified structural diagram of a second shift register unit provided in an embodiment of the present application; Fig. 20 A schematic diagram of a second shift register unit provided in an embodiment of the present application; Fig.21 A schematic diagram of another second shift register unit provided in an embodiment of the present application; Fig. 22 A schematic diagram of another second shift register unit provided in an embodiment of the present application; Fig.23 A timing diagram of a scanning circuit provided in an embodiment of the present application; Fig.24 A timing diagram of another scanning circuit provided in an embodiment of the present application; Fig.25 A connection diagram of a scanning circuit provided in an embodiment of the present application; Fig.26 A connection diagram of another scanning circuit provided in an embodiment of the present application; Fig. 27 A connection diagram of another scanning circuit provided in an embodiment of the present application; Fig.28 A connection diagram of another scanning circuit provided in an embodiment of the present application; Fig.29 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0012] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0014] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0015] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0016] It is obvious to those skilled in the art that various modifications and changes can be made in this application without departing from the spirit or scope of this application. Therefore, this application is intended to cover modifications and changes of this application that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of this application can be combined with each other without contradiction.

[0017] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0018] The present application embodiment provides a scanning circuit 100 for driving a pixel circuit 02. Figure 1 As shown, as a possible application scenario, the scanning circuit 100 and the pixel circuit 02 are both arranged in the display panel 200, and the display panel 200 includes a display area AA and a frame area NA located around the display area AA, and the frame area NA can surround the display area AA.

[0019] The scanning circuit 100 is located in the frame area NA, the pixel circuit 02 is located in the display area AA, and the pixel circuit 02 is electrically connected to the light emitting device 03 to drive the light emitting device 03 to emit light. The scanning circuit 100 is electrically connected to the pixel circuit 02 to provide a gate scanning signal to the pixel circuit 02, thereby driving the pixel circuit 02 to work.

[0020] The scanning circuit 100 includes a plurality of cascaded first shift register units 101 . Optionally, the first shift register unit 101 is used to provide a gate scanning signal to a gate reset transistor and / or a threshold grabbing transistor in the pixel circuit 02 .

[0021] For example, Figure 2 As shown, Figure 2A schematic diagram of a pixel circuit provided in an embodiment of the present application, the pixel circuit 02 includes a driving transistor Md, a gate reset transistor M1, a data writing transistor M2, a threshold capture transistor M3, a power supply voltage writing transistor M4, a light emitting control transistor M5, a light emitting reset transistor M6 and a storage capacitor Cst.

[0022] The first electrode of the gate reset transistor M1 is electrically connected to the first reset signal line SL1, the second electrode is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the first scan line S1N. The first reset signal line SL1 transmits the first reset voltage Vref1. The first electrode of the data write transistor M2 is electrically connected to the data signal line DL1, the second electrode is electrically connected to the first electrode of the driving transistor Md, and the gate is electrically connected to the second scan line SP. The data signal line DL1 transmits the data voltage Data. The first electrode of the threshold capture transistor M3 is electrically connected to the second electrode of the driving transistor Md, the second electrode is electrically connected to the gate of the driving transistor Md, and the gate is electrically connected to the third scan line S2N.

[0023] The first electrode of the power supply voltage writing transistor M4 is electrically connected to the first power supply signal line DL2, the second electrode is electrically connected to the first electrode of the driving transistor Md, and the gate is electrically connected to the light-emitting control signal line EM. The first power supply signal line DL2 transmits the first power supply voltage PVDD. The first electrode of the light-emitting control transistor M5 is electrically connected to the second electrode of the driving transistor Md, the second electrode is electrically connected to the first electrode of the light-emitting device 03, and the gate is electrically connected to the light-emitting control signal line EM. The first electrode of the light-emitting reset transistor M6 is electrically connected to the second reset signal line SL2, the second electrode is electrically connected to the first electrode of the light-emitting device 03, and the gate is electrically connected to the second scanning line SP. The second reset signal line SL2 transmits the second reset voltage Vref2. One plate of the storage capacitor Cst is electrically connected to the gate of the driving transistor Md, and the other plate is electrically connected to the first power supply signal line DL1.

[0024] Taking the case where both the gate reset transistor M1 and the threshold grab transistor M3 include metal oxide, the gate reset transistor M1 and the threshold grab transistor M3 are N-type transistors, the driving transistor Md, the data write transistor M2, the power supply voltage write transistor M4, the light emitting control transistor M5, and the light emitting reset transistor M6 are P-type transistors as an example, the first shift register unit 101 can provide a scan signal to the gate of the gate reset transistor M1 through the first scan line S1N, and / or provide a scan signal to the gate of the threshold grab transistor M3 through the third scan line S2N, and the enable signal output by the first shift register unit 101 can be a high-level signal.

[0025] Figure 3 A partial schematic diagram of a first shift register unit provided in an embodiment of the present application, Figure 4A partial schematic diagram of another first shift register unit provided in an embodiment of the present application.

[0026] like Figure 3 and Figure 4 As shown, the first shift register unit 101 includes a first input module 11 and a first cascade module 12. The input end of the first input module 11 is used to receive the first trigger signal SN_IN, and the output end SN_NEXT of the first cascade module 12 is used to output the first cascade signal. The first cascade signal output by the first cascade module 12 in the first shift register unit 101 of the previous stage can be used as the first trigger signal SN_IN received by the first input module 11 in the first shift register unit 101 of the next stage.

[0027] The first shift register unit 101 further includes a first voltage stabilizing switch module 13 , the output end of the first voltage stabilizing switch module 13 is electrically connected to the output end of the first input module 11 , and / or the output end of the first voltage stabilizing switch module 13 is electrically connected to part of the control end of the first cascade module 12 .

[0028] The first voltage stabilizing switch module 13 can transmit a voltage stabilizing signal to the output end of the first input module 11 and / or part of the control end of the first cascade module 12 to stabilize the potential of the output end of the first input module 11 and / or part of the control end of the first cascade module 12.

[0029] For example, Figure 3 As shown, the first shift register unit 101 also includes a first control module 14, the control end of the first control module 14 is electrically connected to the output end of the first input module 11, the output end of the first control module 14 is electrically connected to the control end of the first cascade module 12, and the output end of the first voltage regulating switch module 13 is electrically connected to the output end of the first input module 11.

[0030] For example, Figure 4 As shown, the first shift register unit 101 also includes a first control module 14, the first cascade module 12 includes a first control end and a second control end, the first control end of the first cascade module 12 is electrically connected to the output end of the first control module 14, and the second control end is coupled to the output end of the first input module 11, and a first coupling module 15 is arranged between the second control end of the first cascade module 12 and the first input module 11.

[0031] The first control module 14 includes a first control end and a second control end. The output end of the first input module 11 is also electrically connected to the first control end of the first control module 14. The second control end of the first cascade module 12 is also electrically connected to the second control end of the first control module 14. The output end of the first voltage regulating switch module 13 is electrically connected to the second control end of the first cascade module 12.

[0032] It should be noted that in Figure 4 In the first shift register unit 101 shown, the output end of the first input module 11 and the second control end of the first cascade module 12 can also be directly electrically connected, that is, the first coupling module 15 is not provided between the output end of the first input module 11 and the second control end of the first cascade module 12. In this case, the output end of the first voltage stabilizing switch module 13 can be electrically connected to the second control end of the first cascade module 12, and to the output end of the first input module 11.

[0033] After research, the inventors of the present application found that in the prior art, there is usually a threshold loss after the first trigger signal passes through the first input module, which can easily lead to inaccurate output potential of the first input module, thereby causing abnormalities in the functional module located after the first input module, affecting the normal operation of the first shift register unit.

[0034] In addition, when the output terminal potential of the first input module is used as part of the control signal of the first cascade module, since a first coupling module may be provided between the output terminal of the first input module and the control terminal of the first cascade module, if only the output terminal potential of the first input module is adjusted, the stabilizing effect on the control terminal potential of the first cascade module may be limited, and the first cascade module may still be prone to operating abnormally.

[0035] In view of this, in the embodiment of the present application, the output end of the first voltage stabilizing switch module 13 is electrically connected to the output end of the first input module 11, and / or the output end of the first voltage stabilizing switch module 13 is electrically connected to part of the control ends of the first cascade module 12, so as to improve the working reliability of the first shift register unit.

[0036] In an embodiment of the present application, if the output end of the first voltage-stabilizing switch module 13 is electrically connected to the output end of the first input module 11, a voltage-stabilizing signal can be provided to the output end of the first input module 11 through the first voltage-stabilizing switch module 13 to compensate for the potential loss during the output process of the first input module 11, which is beneficial to improving the accuracy and stability of the potential at the output end of the first input module 11, thereby helping to improve the working reliability of other modules that receive the potential at the output end of the first input module 11, and further helping to improve the working reliability of the first shift register unit 101.

[0037] If the output end of the first voltage-stabilizing switch module 13 is electrically connected to part of the control end of the first cascade module 12, a voltage-stabilizing signal can be provided to part of the control end of the first cascade module 12 through the first voltage-stabilizing switch module 13, which is beneficial to improving the stability of the potential of the control end of the first cascade module 12, thereby helping to improve the working reliability of the first cascade module 12, and further helping to improve the working reliability of the first shift register unit 101.

[0038] Figure 5 A schematic diagram of a first shift register unit provided in an embodiment of the present application, Figure 6 for Figure 5 A schematic diagram of the first shift register unit is shown.

[0039] In one embodiment of the present application, Figure 5 As shown, the output end of the first input module 11 is electrically connected to the first node N1, and the control end receives the first clock signal CK1. The first input end of the first cascade module 12 receives the first fixed potential signal VGH, the second input end receives the second fixed potential signal VGL, and the control end is electrically connected to the second node N2. The first fixed potential signal VGH is a high-level potential signal, and the second fixed potential signal VGL is a low-level potential signal.

[0040] The first shift register unit 101 further includes a first control module 14 having a first input terminal receiving a first fixed potential signal VGH, a second input terminal receiving a second fixed potential signal VGL, a control terminal electrically connected to the first node N1, and an output terminal electrically connected to the second node N2.

[0041] The first voltage stabilizing switch module 13 has an input terminal receiving the second fixed potential signal VGL, an output terminal electrically connected to the first node N1 , and a control terminal electrically connected to the second node N2 .

[0042] Exemplary, combined Figure 6 As shown, the first input module 11 includes a first transistor T1, a first electrode of the first transistor T1 receives a first trigger signal SN_IN, a second electrode is electrically connected to a first node N1, and a gate receives a first clock signal CK1.

[0043] The first control module 14 includes a second transistor T2 and a third transistor T3 of different channel types, wherein the first electrode of the second transistor T2 receives the first fixed potential signal VGH, the second electrode is electrically connected to the second node N2, and the gate is electrically connected to the first node N1, and the first electrode of the third transistor T3 receives the second fixed potential signal VGL, the second electrode is electrically connected to the second node N2, and the gate is electrically connected to the first node N1. The first control module 14 transmits the first fixed potential signal VGH or the second fixed potential signal VGL to the second node N2 in response to the potential of the first node N1. The potential level of the first node N1 may be opposite to the potential level of the second node N2.

[0044] The first cascade module 12 includes a fourth transistor T4 and a fifth transistor T5 of different channel types, wherein a first electrode of the fourth transistor T4 receives a first fixed potential signal VGH, a second electrode is electrically connected to an output terminal SN_NEXT of the first cascade module 12, and a gate is electrically connected to a second node N2, and a first electrode of the fifth transistor T5 receives a second fixed potential signal VGL, a second electrode is electrically connected to an output terminal SN_NEXT of the first cascade module 12, and a gate is electrically connected to a second node N2. The first cascade module 12 outputs the first fixed potential signal VGH or the second fixed potential signal VGL as a first cascade signal in response to the potential of the second node N2, and the potential level of the output terminal SN_NEXT of the first cascade module 12 may be opposite to the potential level of the second node N2.

[0045] The first voltage stabilizing switch module 13 includes a first voltage stabilizing transistor TF1 , wherein a first electrode of the first voltage stabilizing transistor TF1 receives a second fixed potential signal VGL, a second electrode is electrically connected to a first node N1 , and a gate is electrically connected to a second node N2 .

[0046] The second transistor T2 and the fourth transistor T4 have the same channel type, and the third transistor T3, the first voltage-stabilizing transistor TF1 and the fifth transistor T5 have the same channel type.

[0047] Exemplarily, the second transistor T2 and the fourth transistor T4 are both P-type transistors, and the third transistor T3 , the first voltage-stabilizing transistor TF1 , and the fifth transistor T5 are all N-type transistors.

[0048] Optionally, the third transistor T3 , the first voltage-stabilizing transistor TF1 , and the fifth transistor T5 include metal oxides, and the third transistor T3 , the first voltage-stabilizing transistor TF1 , and the fifth transistor T5 may all be top-bottom dual-gate structures.

[0049] For example, Figure 6 As shown, the bottom gate of the third transistor T3 is electrically connected to the first electrode thereof, and the bottom gate of the first voltage-stabilizing transistor TF1 is electrically connected to the first electrode thereof, so as to improve the stability of the threshold voltage of the third transistor T3 and the first voltage-stabilizing transistor TF1 during long-term operation, thereby improving the working stability of the third transistor T3 and the first voltage-stabilizing transistor TF1. The bottom gate of the fifth transistor T5 can be electrically connected to the top gate, so as to improve the driving capability of the fifth transistor T5.

[0050] In an embodiment of the present application, when a low-level first trigger signal SN_IN is transmitted to the first node N1 through the first transistor T1, the second transistor T2 is turned on, and a high-level first fixed potential signal VGH is transmitted to the second node N2 through the second transistor T2. The high-level potential of the second node N2 controls the first voltage-stabilizing transistor TF1 to turn on, and the low-level second fixed potential VGL is transmitted to the first node N1 through the first voltage-stabilizing transistor TF1, thereby compensating for the loss of the low-level first trigger signal SN_IN passing through the first transistor T1, which is beneficial to stabilizing the low-level potential of the first node N1, thereby improving the reliability of turning on the second transistor T2 and the reliability of turning off the third transistor T3, and further helping to improve the working reliability of the first shift register unit 101.

[0051] In one embodiment of the present application, Figure 5 As shown, the first shift register unit 101 also includes a first type of signal output module 16, and the output terminal SN_OUT of the first type of signal output module 16 is used to output a first type of scanning signal. The first type of scanning signal can be a gate scanning signal transmitted to a gate reset transistor in the pixel circuit 02, and / or a threshold capture transistor. The enable signal in the first type of scanning signal can be a high-level signal.

[0052] The first type signal output module 16 includes a first output module 161 and a second output module 162. The input end of the first output module 161 receives the first fixed potential signal VGH, and the output end is electrically connected to the output end SN_OUT of the first type signal output module 16. The input end of the second output module 162 receives the second fixed potential signal VGL, and the output end is electrically connected to the output end SN_OUT of the first type signal output module 16.

[0053] The first shift register unit 101 further includes a gating module 17 , a first input terminal of the gating module 17 receives a first fixed potential signal VGH, and a second input terminal of the gating module 17 is electrically connected to a gating signal line CTRL.

[0054] Among them, the control end of at least one of the first output module 161 and the second output module 162 is electrically connected to the output end of the selection module 17. That is, at least one of the first output module 161 and the second output module 162 can transmit a signal to the output end SN_OUT of the first type signal output module 16 in response to the output signal of the selection module 17.

[0055] For example, Figure 6 As shown, the first output module 161 includes a sixth transistor T6 , a first electrode of the sixth transistor T6 receives the first fixed potential signal VGH, and a second electrode is electrically connected to the output terminal SN_OUT of the first type signal output module 16 .

[0056] The second output module 162 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 receives the second fixed potential signal VGL, and a second electrode of the seventh transistor T7 is electrically connected to the output terminal SN_OUT of the first type signal output module 16 .

[0057] The sixth transistor T6 and the seventh transistor T7 have different channel types.

[0058] Exemplarily, the sixth transistor T6 is a P-type transistor, and the seventh transistor T7 is an N-type transistor.

[0059] As a possible implementation, Figure 5 As shown, the gating module 17 includes a first submodule 171 and a second submodule 172 . The first submodule 171 has an input terminal receiving a first fixed potential signal VGH, a control terminal electrically connected to the second node N2 , and an output terminal electrically connected to the control terminal of the first output module 161 .

[0060] The input end of the second submodule 172 is electrically connected to the selection signal line CTRL, the output end is electrically connected to the control end of the first output module 161 , and the control end is electrically connected to the output end SN_NEXT of the first cascade module 12 .

[0061] The control end of the second output module 162 is electrically connected to the output end SN_NEXT of the first cascade module 12 .

[0062] In this implementation, the gating module 17 transmits the first fixed potential signal VGH or the signal on the gating signal line CTRL to the control end of the first output module 161 in response to the potential of the second node N2 and the first cascade signal output by the first cascade module 12. The first type signal output module 16 outputs the first type scanning signal in response to the output signal of the gating module 17 and the first cascade signal output by the first cascade module 12.

[0063] For example, Figure 6 As shown, the first submodule 171 includes an eighth transistor T8 , a first electrode of the eighth transistor T8 receives the first fixed potential signal VGH, a second electrode is electrically connected to the gate of the sixth transistor T6 , and a gate is electrically connected to the second node N2 .

[0064] The second submodule 172 includes a ninth transistor T9 , a first electrode of the ninth transistor T9 is electrically connected to the selection signal line CTRL, a second electrode of the ninth transistor T9 is electrically connected to the gate of the sixth transistor T6 , and a gate of the ninth transistor T9 is electrically connected to the output terminal SN_NEXT of the first cascade module 12 .

[0065] The gate of the seventh transistor T7 is electrically connected to the output terminal SN_NEXT of the first cascade module 12 .

[0066] The channel type of the eighth transistor T8 is the same as that of the ninth transistor T9 , and is different from that of the seventh transistor T7 .

[0067] Exemplarily, the sixth transistor T6 , the eighth transistor T8 , and the ninth transistor T9 are all P-type transistors, and the seventh transistor T7 is an N-type transistor.

[0068] Optionally, the seventh transistor T7 includes metal oxide, and the seventh transistor T7 may be a top-bottom dual-gate structure.

[0069] Exemplarily, the bottom gate of the seventh transistor T7 may be electrically connected to the top gate to improve the driving capability of the seventh transistor T7.

[0070] When the selection signal line CTRL transmits a high level signal, the eighth transistor T8 and the ninth transistor T9 can only transmit a high level signal to the sixth transistor T6, the sixth transistor T6 remains in a closed state, and the output terminal SN_OUT of the first type signal output module 16 keeps outputting a low level second fixed potential signal VGL. At this time, the first cascade module 12 can output a normal first-level transmission signal.

[0071] When the selection signal line CTRL transmits a low level signal, the eighth transistor T8 and the ninth transistor T9 can transmit a high level signal and a low level signal to the sixth transistor T6 respectively, and the sixth transistor T6 can remain in an on state or an off state, and the output terminal SN_OUT of the first type signal output module 16 can output the scanning signal normally. At this time, the potential of the output terminal SN_NEXT of the first cascade module 12 is opposite to the potential level of the output terminal SN_OUT of the first type signal output module 16.

[0072] Based on this configuration, the frequency of the output enable signal at the output terminal SN_OUT of the first type signal output module 16 can be controlled by controlling the signal on the selection signal line CTRL.

[0073] Figure 7 A schematic diagram of another first shift register unit provided in an embodiment of the present application, Figure 8 for Figure 7 A schematic diagram of the first shift register unit is shown.

[0074] As another possible implementation, Figure 7As shown, the gating module 17 includes a first submodule 171 and a second submodule 172. The input end of the first submodule 171 receives the first fixed potential signal VGH, the control end is electrically connected to the second node N2, and the output end is electrically connected to the second subnode N2A. The second subnode N2A is electrically connected to the control end of the first output module 161 and the second output module 162. That is, the output end of the first submodule 171 is electrically connected to the control end of the first output module 161 and the second output module 162.

[0075] The input end of the second submodule 172 is electrically connected to the selection signal line CTRL, the control end is electrically connected to the second node N2, and the output end is electrically connected to the second sub-node N2A, that is, the output end of the second submodule 172 is electrically connected to the control end of the first output module 161 and the second output module 162.

[0076] In this implementation, the gating module 17 responds to the potential of the second node N2 and outputs the first fixed potential signal VGH or the signal on the gating signal line CTRL to the control terminal of the first type signal output module 16. The first type signal output module 16 responds to the output signal of the gating module 17 and outputs the first type scanning signal, which may include the first fixed potential signal VGH and the second fixed potential signal VGL.

[0077] Among them, the potential level of the output terminal SN_OUT of the first type signal output module 16 can be opposite to the potential level of the output terminal of the strobe module 17. In this way, during the operation of the first shift register unit 101, no matter whether the output terminal potential of the strobe module 17 is high or low, one of the first output module 161 and the second output module 162 can be turned on, and the potential of the output terminal SN_OUT of the first type signal output module 16 will not float, which is conducive to improving the stability of the potential of the output terminal SN_OUT of the first type signal output module 16.

[0078] For example, Figure 8 As shown, the first submodule 171 includes an eighth transistor T8 , a first electrode of the eighth transistor T8 receives the first fixed potential signal VGH, a second electrode is electrically connected to the gates of the sixth transistor T6 and the seventh transistor T7 , and a gate is electrically connected to the second node N2 .

[0079] The second submodule 172 includes a ninth transistor T9 , a first electrode of the ninth transistor T9 is electrically connected to the selection signal line CTRL, a second electrode of the ninth transistor T9 is electrically connected to the gates of the sixth transistor T6 and the seventh transistor T7 , and a gate of the ninth transistor T9 is electrically connected to the second node N2 .

[0080] The channel types of the eighth transistor T8 and the ninth transistor T9 are different, and the channel types of the eighth transistor T8 and the sixth transistor T6 are the same.

[0081] Exemplarily, the sixth transistor T6 and the eighth transistor T8 are P-type transistors, and the seventh transistor T7 and the ninth transistor T9 are N-type transistors.

[0082] Optionally, the seventh transistor T7 and the ninth transistor T9 both include metal oxide, and the seventh transistor T7 and the ninth transistor T9 may both be a top-bottom double-gate structure.

[0083] For example, Figure 8 As shown, the bottom gate of the ninth transistor T9 is electrically connected to its first electrode to improve the stability of the threshold voltage of the ninth transistor T9 during long-term operation. The bottom gate of the seventh transistor T7 can be electrically connected to the top gate to improve the driving capability of the seventh transistor T7.

[0084] When the selection signal line CTRL transmits a high-level signal, the eighth transistor T8 and the ninth transistor T9 can only transmit high-level signals to the gates of the sixth transistor T6 and the seventh transistor T7, the sixth transistor T6 remains in a closed state, and the output terminal SN_OUT of the first type signal output module 16 outputs the low-level second fixed potential signal VGL transmitted by the seventh transistor T7. At this time, the first cascade module 12 can output a normal first-stage transmission signal.

[0085] When the selection signal line CTRL transmits a low level signal, the eighth transistor T8 and the ninth transistor T9 can transmit a high level signal and a low level signal to the gate of the sixth transistor T6 and the seventh transistor T7 respectively, and the sixth transistor T6 can remain in an on state or an off state, and the output terminal SN_OUT of the first type signal output module 16 can output the scanning signal normally. At this time, the potential of the output terminal SN_NEXT of the first cascade module 12 is opposite to the potential level of the output terminal SN_OUT of the first type signal output module 16.

[0086] Based on this configuration, the frequency of the output enable signal at the output terminal SN_OUT of the first type signal output module 16 can be controlled by controlling the signal on the selection signal line CTRL.

[0087] Optional, such as Figure 5-Figure 8 As shown, the first shift register unit 101 further includes a first capacitor C1, one plate of the first capacitor C1 is electrically connected to the first node N1, and the other plate receives the second fixed potential signal VGL. In this way, the first capacitor C1 can be used to further improve the potential stability of the first node N1.

[0088] Fig. 9 A schematic diagram of another first shift register unit provided in an embodiment of the present application, Fig.10 for Fig. 9 A schematic diagram of the first shift register unit is shown.

[0089] In one embodiment of the present application, Fig. 9 As shown, the first output end of the first input module 11 is electrically connected to the first main node N1a, the second output end is electrically connected to the first sub-node N1b, the control end receives the first clock signal CK1, the first main node N1a is coupled to the second main node N2a, the first sub-node N1b is coupled to the second sub-node N2b. A first coupling module 15 is provided between the first main node N1a and the second main node N2a, and a first coupling module 15 is provided between the first sub-node N1b and the second sub-node N2b.

[0090] The first cascade module 12 includes a first sub-cascade module 121 and a second sub-cascade module 122. The first sub-cascade module 121 has an input end receiving a first fixed potential signal VGH, an output end electrically connected to an output end SN_NEXT of the first cascade module 12, and a control end electrically connected to a third node N3. The second sub-cascade module 122 has an input end receiving a second fixed potential signal VGL, an output end electrically connected to an output end SN_NEXT of the first cascade module 12, and a control end electrically connected to a second main node N2a.

[0091] The first shift register unit 101 further includes a first control module 14, which includes a first sub-control module 141 and a second sub-control module 142. The first sub-control module 141 has an input terminal receiving a first fixed potential signal VGH, an output terminal electrically connected to the third node N3, and a control terminal electrically connected to the first main node N1a. The second sub-control module 142 has an input terminal receiving a second fixed potential signal VGL, an output terminal electrically connected to the third node N3, and a control terminal electrically connected to the second main node N2.

[0092] In this embodiment, the first sub-control module 141 can transmit the first fixed potential signal VGH to the third node N3 in response to the potential of the first main node N1a, and the second sub-control module 142 can transmit the second fixed potential signal VGL to the third node in response to the potential of the second main node N2a. The first sub-cascade module 121 can transmit the first fixed potential signal VGH to the output terminal SN_NEXT of the first cascade module 12 in response to the potential of the third node N3, and the second sub-cascade module 122 can transmit the second fixed potential signal VGL to the output terminal SN_NEXT of the first cascade module 12 in response to the potential of the second main node N2a. The first fixed potential signal VGH or the second fixed potential signal VLG outputted from the output terminal SN_NEXT of the first cascade module 12 can be used as the first cascade signal.

[0093] The first voltage stabilizing switch module 13 has an input terminal electrically connected to the secondary node N2b, an output terminal electrically connected to the second main node N2a, and a control terminal electrically connected to the secondary node N2b.

[0094] Based on this setting method, the first voltage-stabilizing switch module 13 can transmit the potential of the second secondary node N2b to the second main node N2a. Since the potential of the first main node N1a can be the same as the potential of the first primary node N1b, and the second main node N2a is coupled to the first main node N1a, and the second secondary node N2b is coupled to the first primary node N1b, the potential of the second secondary node N2b can be used to stabilize the potential of the second main node N2a to avoid the problem that the potential of the second main node N2a is not low enough when the potentials of the first main node N1a and the first primary node N1b are at a low level.

[0095] For example, Fig.10 As shown, the first input module 11 includes a first transistor T1 and a second transistor T2, the first electrode of the first transistor T1 receives the first trigger signal SN_IN, the second electrode is electrically connected to the first main node N1a, and the gate receives the first clock signal CK1, the first electrode of the second transistor T2 receives the first trigger signal SN_IN, the second electrode is electrically connected to the first sub-node N1b, and the gate receives the first clock signal CK1, and during the operation of the first shift register unit 101, the potentials of the first main node N1a and the first sub-node N1b can be basically the same.

[0096] The first sub-cascade module 121 includes a third transistor T3, a first electrode of the third transistor T3 receives a first fixed potential signal VGH, a second electrode is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and a gate is electrically connected to the third node N3. The second sub-cascade module 122 includes a fourth transistor T4, a first electrode of the fourth transistor T4 receives a second fixed potential signal VGL, a second electrode is electrically connected to the output terminal SN_NEXT of the first cascade module 12, and a gate is electrically connected to the second main node N2a.

[0097] The first sub-control module 141 includes a fifth transistor T5, a first electrode of the fifth transistor T5 receives the first fixed potential signal VGH, a second electrode is electrically connected to the third node N3, and a gate is electrically connected to the first main node N1a. The second sub-control module 142 includes a sixth transistor T6, a first electrode of the sixth transistor T6 receives the second fixed potential signal VGH, a second electrode is electrically connected to the third node N3, and a gate is electrically connected to the second main node N2a.

[0098] The first voltage stabilizing switch module 13 includes a first voltage stabilizing transistor TF1 , wherein a first electrode of the first voltage stabilizing transistor TF1 is electrically connected to the secondary subnode N2 b , a second electrode of the first voltage stabilizing transistor TF1 is electrically connected to the second main node N2 a , and a gate of the first voltage stabilizing transistor TF1 is electrically connected to the secondary subnode N2 b .

[0099] The channel type of the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the first voltage stabilizing transistor TF1 are the same, and the channel type of the sixth transistor T6 is different.

[0100] Exemplarily, the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 and the first voltage-stabilizing transistor TF1 are all P-type transistors, and the sixth transistor T6 is an N-type transistor.

[0101] Optionally, the sixth transistor T6 includes metal oxide, and the sixth transistor T6 may be a top-bottom dual-gate structure.

[0102] For example, Fig.10 As shown, the bottom gate of the sixth transistor T6 is electrically connected to the first electrode thereof, so as to improve the stability of the threshold voltage of the sixth transistor T6 during long-term operation.

[0103] Based on this configuration, the first cascade module 12 that outputs the first cascade signal can include only P-type transistors without including N-type transistors, which is beneficial to improving the signal output capability of the first cascade module 12. In particular, it is beneficial to avoid using transistors including metal oxides (such as indium gallium zinc oxide) as signal output tubes, which leads to poor signal output capability and large occupied space.

[0104] Please continue to refer to Fig.10 In one embodiment of the present application, a first coupling transistor TO1 is included between the first main node N1a and the second main node N2a, a second coupling transistor TO2 is included between the first secondary node N1b and the second secondary node N2b, and the gate of the first coupling transistor TO1 and the gate of the second coupling transistor TO2 both receive the second fixed potential signal VGL.

[0105] The first coupling transistor TO1 and the second coupling transistor TO2 have the same channel type. During the operation of the first shift register unit 101 , the first coupling transistor TO1 and the second coupling transistor TO2 can remain in an on state.

[0106] Exemplarily, both the first coupling transistor TO1 and the second coupling transistor TO2 are P-type transistors.

[0107] In this implementation, the settings of the first coupling transistor TO1 and the second coupling transistor TO2 are conducive to stabilizing the potentials of the first main node N1a and the first sub-node N1b. When the potential of the second main node N2a is disturbed, the first coupling transistor TO1 can reduce the influence of the disturbance on the first main node N1a, and when the potential of the second sub-node N2b is disturbed, the second coupling transistor TO1 can reduce the influence of the disturbance on the first sub-node N1b. That is, it is conducive to reducing the influence on the potential of the output terminal of the first input module 11, and can play a role in stabilizing the potential of the output terminal of the first input module 11.

[0108] Optional, such as Fig. 9 As shown, the first shift register unit 101 also includes an auxiliary voltage stabilizing module 18, a first input end of the auxiliary voltage stabilizing module 18 receives a first fixed potential signal VGH, a second input end receives a second clock signal CK2, and an output end is electrically connected to the secondary node N2b, and the auxiliary voltage stabilizing module 18 is used to adjust the potential of the secondary node N2b, and then stabilize the potential of the second main node N2a through the first voltage stabilizing transistor TF1.

[0109] For example, Fig.10 As shown, the auxiliary voltage stabilizing module 18 includes a first capacitor C1, a seventh transistor T7 and an eighth transistor T8, and the seventh transistor T7 and the eighth transistor T8 have the same channel type.

[0110] One plate of the first capacitor C1 is electrically connected to the second secondary node N2b, and the other plate is electrically connected to the fourth node N4. The first electrode of the seventh transistor T7 receives the second clock signal CK2, the second electrode is electrically connected to the fourth node N4, and the gate is electrically connected to the second secondary node N2b. The first electrode of the eighth transistor T8 receives the first fixed potential signal VGH, the second electrode is electrically connected to the fourth node N4, and the gate is electrically connected to the third node N3.

[0111] Exemplarily, both the seventh transistor T7 and the eighth transistor T8 are P-type transistors.

[0112] When the first main node N1a and the first sub-node N1b are at a low level, the second main node N2a and the second sub-node N2b are at a low level. At this time, the fifth transistor T5 is turned on, the sixth transistor T6 is turned off, and the third node N3 is at a high level. At the same time, the potential of the third node N3 controls the eighth transistor T8 to be turned off, and the potential of the second sub-node N2b controls the seventh transistor T7 to be turned on. The second clock signal CK2 is a pulse signal. The level change of the second clock signal CK2 can lower the potential of the fourth node N4, and then lower the potential of the second sub-node N2b through the first capacitor C1, and then lower the potential of the second main node N2a through the first voltage-stabilizing transistor TF1, so that the second main node N2a has a stable low potential, so as to avoid the problem that the potential of the second main node N2a is not low enough, resulting in the incomplete closing of the sixth transistor T6 and the insufficient opening of the fourth transistor T4.

[0113] In one embodiment of this application, please continue to refer to Fig. 9 and Fig.10 The first cascade module 12 is also used to output the first type of scanning signal. That is, the first stage transmission signal output by the output terminal SN_NEXT of the first cascade module 12 can be multiplexed as the first type of scanning signal output by the first shift register unit 101.

[0114] The first cascade module 12 can be multiplexed as the first type signal output module 16 in the first shift register unit 101, and the output end SN_NEXT of the first cascade module 12 is multiplexed as the output end SN_OUT of the first type signal output module 16, which transmits the first cascade signal to the next-level first shift register unit 101 and transmits the first type scanning signal to the pixel circuit 02.

[0115] Based on this configuration, it is beneficial to reduce the number of transistors in the first shift register unit 101, thereby reducing the occupied area of ​​the first shift register unit 101, which can simplify the structure of the first shift register unit 101 and help achieve a narrow frame of the display panel 200.

[0116] Optional, such as Fig.10 As shown, the first shift register unit 101 also includes a second capacitor C2 and a third capacitor C3, one plate of the second capacitor C2 receives the first fixed potential signal VGH, and the other plate is electrically connected to the control end of the first sub-cascade module 121 to stabilize the potential of the control end of the first sub-cascade module 121.

[0117] One plate of the third capacitor C3 is electrically connected to the output terminal SN_NEXT of the first cascade module 12 , and the other plate is electrically connected to the control terminal of the second sub-cascade module 122 to further stabilize the potential of the control terminal of the second sub-cascade module 122 .

[0118] Fig.11 A schematic diagram of another first shift register unit provided in an embodiment of the present application, Fig.12 for Fig.11 A schematic diagram of the first shift register unit is shown.

[0119] In one embodiment of the present application, Fig.11 As shown, the first shift register unit 101 further includes a gating module 17 and a first type signal output module 16. The output terminal SN_OUT of the first type signal output module 16 is used to output a first type scanning signal.

[0120] The first type signal output module 16 includes a first output module 161 and a second output module 162. The input end of the first output module 161 receives the first fixed potential signal VGH, the output end is electrically connected to the output end SN_OUT of the first type signal output module 16, and the control end is electrically connected to the output end of the selection module 17. The input end of the second output module 162 receives the second fixed potential signal VGL, the output end is electrically connected to the output end SN_OUT of the first type signal output module 16, and the control end is electrically connected to the second main node N2a.

[0121] The first input terminal of the selection module 17 is electrically connected to the selection signal line CTRL, the second input terminal is electrically connected to the third node N3, and the third input terminal receives the first fixed potential signal VGH. The selection module 17 transmits a control signal to the first output module 161 in response to the output potential of the first main node N1a and the first cascade module 12.

[0122] In this implementation, the first type of signal output module 16 outputs a first type of scanning signal in response to the output terminal potential of the selection module 17 and the potential of the second main node N2a, which is beneficial to controlling the frequency of the output enable signal at the output terminal SN_OUT of the first type of signal output module 16 by adjusting the output signal of the selection module 17.

[0123] For example, Fig.12 As shown, the first output module 161 includes a ninth transistor T9, a first electrode of the ninth transistor T9 receives the first fixed potential signal VGH, a second electrode is electrically connected to the output terminal SN_OUT of the first type signal output module 16, and a gate is electrically connected to the fifth node N5. The second output module 162 includes a tenth transistor T10, a first electrode of the tenth transistor T10 receives the second fixed potential signal VGL, a second electrode is electrically connected to the output terminal SN_OUT of the first type signal output module 16, and a gate is electrically connected to the second main node N2a.

[0124] The selection module 17 includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13 and a fourth capacitor C4 and a fifth capacitor C5. The first electrode of the eleventh transistor T11 is electrically connected to the selection signal line CTRL, the second electrode is electrically connected to the sixth node N6, and the gate is electrically connected to the output end SN_NEXT of the first cascade module 12. The first electrode of the twelfth transistor T12 is electrically connected to the third node N3, the second electrode is electrically connected to the fifth node N5, and the gate is electrically connected to the sixth node N6. The first electrode of the thirteenth transistor T13 receives the first fixed potential signal VGH, the second electrode is electrically connected to the fifth node N5, and the gate is electrically connected to the first main node N1a.

[0125] One plate of the fourth capacitor C4 receives the second fixed potential signal VGL, and the other plate is electrically connected to the sixth node N6 to improve the potential stability of the sixth node N6. One plate of the fifth capacitor C5 receives the first fixed potential signal VGH, and the other plate is electrically connected to the fifth node N5 to improve the potential stability of the fifth node N5.

[0126] The ninth transistor T9 , the tenth transistor T10 , the eleventh transistor T11 , the twelfth transistor T12 , and the thirteenth transistor T13 have the same channel type.

[0127] Exemplarily, the ninth transistor T9 , the tenth transistor T10 , the eleventh transistor T11 , the twelfth transistor T12 , and the thirteenth transistor T13 are all P-type transistors.

[0128] When the selection signal line CTRL transmits a high-level signal, the sixth node N6 can only maintain a high level, the eleventh transistor T11 remains in a turned-off state, the fifth node N5 can only receive the high-level first fixed potential signal VGH transmitted by the twelfth transistor T12, the eighth transistor T8 remains in a turned-off state, and the output terminal SN_OUT of the first type signal output module 16 can only output the low-level second fixed potential signal VGL transmitted by the ninth transistor T9.

[0129] When the selection signal line CTRL transmits a low level signal, the eleventh transistor T11 and the twelfth transistor T12 can transmit the potential of the third node N3 and the first fixed potential signal VGH to the fifth node N5 respectively, and the potential of the third node N3 can be a high level or a low level. Therefore, the fifth node N5 can maintain a high level potential or a low level potential, the eighth transistor T8 can remain in an on state or a off state, and the output terminal SN_OUT of the first type signal output module 16 can output the scan signal normally. The potential of the output terminal SN_OUT of the first type signal output module 16 can be the same as the potential of the output terminal SN_NEXT of the first cascade module 12.

[0130] In this way, the frequency of the output enable signal at the output terminal SN_OUT of the first type signal output module 16 can be controlled by controlling the signal on the selection signal line CTRL.

[0131] Fig.13 A schematic diagram of another first shift register unit provided in an embodiment of the present application, Fig.14 for Fig.13 A schematic diagram of the first shift register unit is shown.

[0132] In one embodiment of the present application, Fig.13 and Fig.14 As shown, the first shift register unit 101 also includes a second type signal output module 19, and the output terminal SP_OUT of the second type signal output module 19 is used to output a second type scanning signal. The second type scanning signal can be a gate scanning signal received by a data writing transistor in a pixel circuit, that is, the second type signal output module 19 can be used to increase the gate scanning signal to the data writing transistor in the pixel circuit. The enable signal output by the output terminal SP_OUT of the second type signal output module 19 can be a low level signal.

[0133] For example, Fig.15 As shown, Fig.15 A connection diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Fig.15 The structure of the pixel circuit shown is similar to Figure 3 The structures of the pixel circuits shown can be the same. The first type signal output module 16 in the first shift register unit 101 is electrically connected to the first scan line S1N and the third scan line S2N in the pixel circuit 02, and the first type signal output module 16 can provide a scan signal to the gate of the gate reset transistor M1 through the first scan line S1N, and provide a scan signal to the gate of the threshold capture transistor M3 through the third scan line S2N.

[0134] The second type signal output module 19 in the first shift register unit 101 is electrically connected to the second scan line SP in the pixel circuit 02 , and the second type signal output module 19 can provide a scan signal to the gate of the data writing transistor M2 through the second scan line SP.

[0135] The second type of signal output module 19 includes a first scanning signal output module 191 and a second scanning signal output module 192 . The first scanning signal output module 191 and the second scanning signal output module 192 can be electrically connected to the gates of the data writing transistors M2 in different rows of pixel circuits 02 , respectively.

[0136] Exemplarily, the first scanning signal output module 191 and the second scanning signal output module 192 are electrically connected to the gates of the data writing transistors M2 in two adjacent rows of pixel circuits 02. The first shift register unit 101 can drive two adjacent rows of pixel circuits.

[0137] The first scan signal output module 191 includes a third output module 1911 and a fourth output module 1912. The input end of the third output module 1911 receives the first fixed potential signal VGH, the output end is electrically connected to the output end SP_OUT1 of the first scan signal output module 191, and the control end is electrically connected to the output end SN_NEXT of the first cascade module 12. The input end of the fourth output module 1912 receives the second clock signal CK2, and the output end is electrically connected to the output end SP_OUT1 of the first scan signal output module 191.

[0138] The second scan signal output module 192 includes a fifth output module 1921 and a sixth output module 1922. The fifth output module 1921 has an input end receiving the first fixed potential signal VGH, an output end electrically connected to the output end SP_OUT2 of the second scan signal output module 192, and a control end electrically connected to the output end SN_NEXT of the first cascade module 12. The sixth output module 1922 has an input end receiving the third clock signal CK3, and an output end electrically connected to the output end SP_OUT1 of the second scan signal output module 192.

[0139] It should be noted that the output terminal SP1_OUT of the first scanning signal output module 191 and the output terminal SP2_OUT of the second scanning signal output module 192 may both be the output terminal SP_OUT of the second type signal output module 19 .

[0140] The first shift register unit 101 further includes a second input module 20 and a second voltage stabilizing switch module 21. The input end of the second input module 20 receives the second trigger signal SP_IN, the output end is electrically connected to the seventh node N7, and the control end receives the first clock signal CK1. The seventh node N7 is coupled to the control end of the fourth output module 1912 and the control end of the sixth output module 1922. A second coupling module 151 may be provided between the seventh node N7 and the control end of the fourth output module 1912, and a third coupling module 152 may be provided between the seventh node N7 and the control end of the sixth output module 1922. The signal outputted by the output end SP_OUT2 of the second scan signal output module 192 in the first shift register unit 101 of the previous stage may be the second trigger signal SP_IN received by the second input module 20 in the first shift register unit 101 of the next stage.

[0141] The input end of the second voltage stabilizing switch module 21 receives the first fixed potential signal VGH, the output end is electrically connected to the seventh node N7 , and the control end is electrically connected to the output end SN_NEXT of the first cascade module 12 .

[0142] In this embodiment, the first shift register unit 101 can output both the first type of scanning signal and the second type of scanning signal, which is beneficial to reducing the number of peripheral scanning circuits required for the pixel circuit 02. When the scanning circuit 100 and the pixel circuit 02 are applied to the display panel 200, it is beneficial to reduce the area occupied by the peripheral scanning circuit, thereby facilitating the realization of a narrow frame of the display panel 200. Moreover, reducing the number of peripheral scanning circuits required for the pixel circuit 02 can also reduce the number of clock signals required for the peripheral scanning circuit, which is beneficial to reducing the power consumption of the display panel 200.

[0143] In addition, the output end of the second voltage-stabilizing switch module 21 is electrically connected to the seventh node N7. During the period when the second input module 20 transmits a high level to the seventh node N7, the second voltage-stabilizing switch module 21 can be controlled to be turned on, so that the second voltage-stabilizing switch module 21 transmits the high-level first fixed potential signal VGH to the seventh node N7, thereby improving the potential stability of the seventh node N7, that is, improving the potential stability of the output end of the second input module 16, and further stabilizing the control end of the fourth output module 1912 and the control end of the sixth output module 1922 to a high potential, which is beneficial to improving the coupling effect of the second clock signal CK2 on the control end of the output module 1912, and the coupling effect of the third clock signal CK3 on the control end of the sixth output module 1922.

[0144] For example, Fig.14 As shown, the third output module 1911 includes a fourteenth transistor T14, a first electrode of the fourteenth transistor T14 receives the first fixed potential signal VGH, a second electrode is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and a gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12. The fourth output module 1912 includes a fifteenth transistor T15, a first electrode of the fifteenth transistor T15 receives the second clock signal CK2, a second electrode is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, and a gate is coupled to the seventh node N7.

[0145] The fifth output module 1921 includes a sixteenth transistor T16, a first electrode of the sixteenth transistor T16 receives the first fixed potential signal VGH, a second electrode is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and a gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12. The sixth output module 1922 includes a seventeenth transistor T17, a first electrode of the seventeenth transistor T17 receives the third clock signal CK3, a second electrode is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and a gate is coupled to the seventh node N7.

[0146] The second input module 20 includes an eighteenth transistor T18 , a first electrode of the eighteenth transistor T18 receives the second trigger signal SP_IN, a second electrode is electrically connected to the seventh node N7 , and a gate of the eighteenth transistor T18 receives the first clock signal CK1 .

[0147] The second voltage stabilizing switch module 21 includes a second voltage stabilizing transistor TF2 , a first electrode of the second voltage stabilizing transistor TF2 receives the first fixed point signal VGH, a second electrode is electrically connected to the seventh node N7 , and a gate is electrically connected to the output terminal SN_NEXT of the first cascade module 12 .

[0148] The fourteenth transistor T14 , the fifteenth transistor T15 , the sixteenth transistor T16 , the seventeenth transistor T17 , the eighteenth transistor T18 and the second voltage stabilizing transistor TF2 have the same channel type.

[0149] Exemplarily, the fourteenth transistor T14 , the fifteenth transistor T15 , the sixteenth transistor T16 , the seventeenth transistor T17 , the eighteenth transistor T18 and the second voltage-stabilizing transistor TF2 are all P-type transistors.

[0150] Please continue to refer to Fig.14 In one embodiment of the present application, the control end of the fourth output module 1912 is electrically connected to the seventh node N7a, and a third coupling transistor TO3 is disposed between the seventh node N7 and the seventh node N7a, that is, the third coupling transistor TO3 is included between the seventh node N7 and the control end of the fourth output module 1912. The control end of the sixth output module 1922 is electrically connected to the seventh node N7b, and a fourth coupling transistor TO4 is disposed between the seventh node N7 and the seventh node N7b, that is, the fourth coupling transistor TO4 is included between the seventh node N7 and the control end of the sixth output module 1922. The gate of the third coupling transistor TO3 and the gate of the fourth coupling transistor TO4 both receive the second fixed potential signal VGL.

[0151] The third coupling transistor TO3 and the fourth coupling transistor TO4 have the same channel type. During the operation of the first shift register unit 101, the third coupling transistor TO3 and the fourth coupling transistor TO4 can remain in an on state.

[0152] Exemplarily, the third coupling transistor TO3 and the fourth coupling transistor TO4 are both P-type transistors.

[0153] In the real-time mode of the present application, the settings of the third coupling transistor TO3 and the fourth coupling transistor TO4 are conducive to stabilizing the potential of the seventh node N7, that is, it is conducive to stabilizing the output terminal potential of the second input module 20. When the control terminal potential of the fourth output module 1912 changes, the third coupling transistor TO3 can reduce the influence of the potential change on the potential of the seventh node N7, thereby stabilizing the potential of the seventh node N7. When the control terminal potential of the sixth output module 1922 changes, the fourth coupling transistor TO4 can reduce the influence of the potential change on the potential of the seventh node N7, thereby stabilizing the potential of the seventh node N7. This is conducive to ensuring the accuracy of the second input module 20 outputting the second trigger signal SN_IN.

[0154] Please continue to refer to Fig.14 The first shift register unit 101 further includes a sixth capacitor C6 and a seventh capacitor C7, one plate of the sixth capacitor C6 is electrically connected to the control terminal of the fourth output module 1912, and the other plate is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191, so as to stabilize the potential of the control terminal of the fourth output module 1912. One plate of the seventh capacitor C7 is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192, and the other plate is electrically connected to the control terminal of the sixth output module 1922, so as to stabilize the potential of the control terminal of the sixth output module 1922.

[0155] It should be noted that in Fig.13 and 14 In the first shift register unit shown in FIG. 1 , the first cascade module 12 and the first type signal output module 16 may be set to be independent of each other. The first shift register unit may include: Fig.11 and Fig.12 The first type signal output module 16 and the gating module 17 are shown.

[0156] Fig.16 A schematic diagram of a first shift register unit provided in an embodiment of the present application, Fig.16 The first shift register unit shown in FIG. Fig.14The difference between the first shift register units shown is that the gate of the eighteenth transistor T18 receives the second clock signal CK2, the first electrode of the fifteenth transistor T15 receives the third clock signal CK3, and the first electrode of the seventeenth transistor T17 receives the fourth clock signal CK4.

[0157] So, relative to Fig.14 The first shift register unit shown is beneficial to reducing the load of the first clock signal CK1 and improving the signal output difference caused by the unbalanced clock signal load.

[0158] Combination Fig.17 As shown, Fig.17 for Fig.16 A timing diagram of the first shift register unit is shown. In the signal output period Z of the first shift register unit 101, the first trigger signal SN_IN is a high level signal, the first main node N1a, the first secondary node N1b, the second main node N2a, and the second secondary node N2b are all high level signals, the third node N3 is a low level signal, and the output terminal SN_NEXT of the first cascade module 12 (the output terminal SN_OUT of the first type of signal output module) outputs a high level signal.

[0159] The signal output period Z of the first shift register unit 101 includes a first stage Z1, a second stage Z2 and a third stage Z3. In the first stage Z1, the second stage Z2 and the third stage Z3, the first clock signal CK1 is a high level signal.

[0160] In the first phase Z1, the second trigger signal SP_IN is a low level signal, the second clock signal CK2 is a low level signal, the seventh node N7 is a low level signal, the third clock signal CK3 and the fourth clock signal CK4 are both high level. The output terminal SP_OUT1 of the first scanning signal output module 191 and the output terminal SP_OUT2 of the second scanning signal output module 192 both output high level signals.

[0161] In the second phase Z2, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the fourth clock signal CK4 are high level signals, the seventh node N7 maintains a low level signal, and the third clock signal CK3 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a low level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a high level signal.

[0162] In the third stage Z3, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the third clock signal CK3 are high level signals, the seventh node N7 maintains a low level signal, and the fourth clock signal CK4 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a high level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a low level signal.

[0163] Fig.18 A schematic diagram of another display panel provided in an embodiment of the present application, Fig.19 A simplified structural diagram of a second shift register unit provided in an embodiment of the present application.

[0164] In one embodiment of the present application, Fig.18 As shown, the scanning circuit 100 further includes a plurality of cascaded second shift register units 102. The second shift register units 102 and the first shift register units 101 can respectively provide scanning signals to different transistors in the pixel circuit.

[0165] Exemplarily, the first shift register unit 101 is used to provide a gate scan signal to a gate reset transistor and / or a threshold capture transistor in a pixel circuit. The second shift register unit 102 is used to provide a gate scan signal to a data write transistor in a pixel circuit.

[0166] like Fig.19 As shown, the second shift register unit 102 includes a second type signal output module 19 and a second input module 20. The output terminal SP_OUT of the second type signal output module 19 is used to output a second type scanning signal. The second type scanning signal can be a gate scanning signal received by a data writing transistor in a pixel circuit. The enable signal output by the output terminal SP_OUT of the second type signal output module 19 can be a low level signal.

[0167] The second input module 20 is used to receive the second trigger signal SP_IN. The output end of the second input module 20 is electrically connected to the seventh node N7. The seventh node N7 is coupled to part of the control end of the second type signal output module 19.

[0168] The second shift register unit 102 further includes a second voltage stabilizing switch module 21, and an output end of the second voltage stabilizing switch module 21 is electrically connected to the seventh node N7.

[0169] In this implementation, the second shift register unit 102 and the first shift register unit 101 can be independent of each other, which is beneficial to improving the flexibility of the working sequence of the second shift register unit 102 and the first shift register unit 101. In addition, the output end of the second voltage stabilizing switch module 21 is electrically connected to the seventh node N7, which is also beneficial to improving the stability of the potential of the seventh node N7 and reducing the probability of abnormal output of the second type signal output module 19.

[0170] Optional, such as Fig.19 As shown, the control end of the second input module 20 receives the first clock signal CK1, and the second type signal output module 10 includes a first scanning signal output module 191 and a second scanning signal output module 192. The first scanning signal output module 191 and the second scanning signal output module 192 can be electrically connected to the gate of the data writing transistor M2 in different rows of pixel circuits 02, respectively.

[0171] Exemplarily, the first scanning signal output module 191 and the second scanning signal output module 192 are electrically connected to the gates of the data writing transistors M2 in two adjacent rows of pixel circuits 02. The second shift register unit 102 can drive two adjacent rows of pixel circuits.

[0172] The first scan signal output module 191 includes a third output module 1911 and a fourth output module 1912. The input end of the third output module 1911 receives the first fixed potential signal VGH, the output end is electrically connected to the output end SP_OUT1 of the first scan signal output module 191, and the control end is electrically connected to the eighth node N8. The input end of the fourth output module 1912 receives the second clock signal CK2, the output end is electrically connected to the output end SP_OUT1 of the first scan signal output module 191, and the control end is coupled to the seventh node N7. Exemplarily, the control end of the fourth output module 1912 is electrically connected to the seventh node N7a, and a second coupling module 151 is provided between the seventh node N7 and the seventh node N7a.

[0173] The second scan signal output module 192 includes a fifth output module 1921 and a sixth output module 1922. The input end of the fifth output module 1921 receives the first fixed potential signal VGH, the output end is electrically connected to the output end SP_OUT2 of the second scan signal output module 192, and the control end is electrically connected to the eighth node N8. The input end of the sixth output module 1922 receives the third clock signal CK3, the output end is electrically connected to the output end SP_OUT2 of the second scan signal output module 192, and the control end is coupled to the seventh node N7. Exemplarily, the control end of the sixth output module 1922 is electrically connected to the seventh second node N7b, and a third coupling module 152 is provided between the seventh node N7 and the seventh second node N7b.

[0174] It should be noted that the output terminal SP1_OUT of the first scanning signal output module 191 and the output terminal SP2_OUT of the second scanning signal output module 192 can both be the output terminal SP_OUT of the second type signal output module 19. The signal output by the output terminal SP_OUT2 of the second scanning signal output module 192 in the second shift register unit 102 of the previous stage can be the second trigger signal SP_IN received by the second input module 20 in the second shift register unit 102 of the next stage.

[0175] The second shift register unit 102 further includes a second control module 22 , and an output end of the second control module 22 is electrically connected to the eighth node N8 and the second voltage stabilizing switch module 21 .

[0176] Among them, the first scan signal output module 191 outputs the first fixed potential signal VGH or the second clock signal CK2 in response to the potential of the eighth node N8 and the potential of the seventh node N7, and the second scan signal output module 192 outputs the first fixed potential signal VGH or the third clock signal CK3 in response to the potential of the eighth node N8 and the potential of the seventh node N7.

[0177] For example, Fig. 20 As shown, Fig. 20 A schematic diagram of a second shift register unit provided in an embodiment of the present application, the third output module 1911 includes a fourteenth transistor T14, the first electrode of the fourteenth transistor T14 receives the first fixed potential signal VGH, the second electrode is electrically connected to the output end SP_OUT1 of the first scan signal output module 191, and the gate is electrically connected to the eighth node N8.

[0178] The fourth output module 1912 includes a fifteenth transistor T15 , a first electrode of the fifteenth transistor T15 receives the second clock signal CK2 , a second electrode is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191 , and a gate is coupled to the seventh node N7 .

[0179] The fifth output module 1921 includes a sixteenth transistor T16 , a first electrode of the sixteenth transistor T16 receives the first fixed potential signal VGH, a second electrode is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192 , and a gate is electrically connected to the eighth node N8 .

[0180] The sixth output module 1922 includes a seventeenth transistor T17 , a first electrode of the seventeenth transistor T17 receives the third clock signal CK3 , a second electrode of the seventeenth transistor T17 is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192 , and a gate of the seventeenth transistor T17 is coupled to the seventh node N7 .

[0181] The second input module 20 includes an eighteenth transistor T18 , a first electrode of the eighteenth transistor T18 receives the second trigger signal SP_IN, a second electrode is electrically connected to the seventh node N7 , and a gate of the eighteenth transistor T18 receives the first clock signal CK1 .

[0182] The fourteenth transistor T14 , the fifteenth transistor T15 , the sixteenth transistor T16 , the seventeenth transistor T17 and the eighteenth transistor T18 have the same channel type.

[0183] Exemplarily, the fourteenth transistor T14 , the fifteenth transistor T15 , the sixteenth transistor T16 , the seventeenth transistor T17 , and the eighteenth transistor T18 are all P-type transistors.

[0184] In addition, if Fig. 20 As shown, the gate of the fifteenth transistor T15 is electrically connected to the seventh node N7a, and a third coupling transistor TO3 is disposed between the seventh node N7 and the seventh node N7a, that is, the third coupling transistor TO3 is included between the seventh node N7 and the gate of the fifteenth transistor T15. The gate of the seventeenth transistor T17 is electrically connected to the seventh node N7b, and a fourth coupling transistor TO4 is disposed between the seventh node N7 and the seventh node N7b, that is, the fourth coupling transistor TO4 is included between the seventh node N7 and the gate of the seventeenth transistor T17. The gate of the third coupling transistor TO3 and the gate of the fourth coupling transistor TO4 both receive the second fixed potential signal VGL.

[0185] The third coupling transistor TO3 and the fourth coupling transistor TO4 have the same channel type. During the operation of the second shift register unit 102, the third coupling transistor TO3 and the fourth coupling transistor TO4 can remain in an on state.

[0186] Exemplarily, the third coupling transistor TO3 and the fourth coupling transistor TO4 are both P-type transistors.

[0187] The configuration of the third coupling transistor TO3 and the fourth coupling transistor TO4 can reduce the influence of the seventh node N7a and the seventh node N7b potential changes on the seventh node N7, which is beneficial to improving the stability of the potential of the seventh node N7.

[0188] Further, such as Fig. 20 As shown, the second shift register unit 102 also includes a sixth capacitor C6, a seventh capacitor C7 and an eighth capacitor C8, one plate of the sixth capacitor C6 is electrically connected to the gate of the fifteenth transistor T15, and the other plate is electrically connected to the output terminal SP_OUT1 of the first scan signal output module 191 to stabilize the gate potential of the fifteenth transistor T15.

[0189] One plate of the seventh capacitor C7 is electrically connected to the output terminal SP_OUT2 of the second scan signal output module 192 , and the other plate is electrically connected to the gate of the seventeenth transistor T17 to stabilize the gate potential of the seventeenth transistor T17 .

[0190] One plate of the eighth capacitor C8 receives the first fixed potential signal VGH, and the other plate is electrically connected to the eighth node N8 to stabilize the potential of the eighth node N8 and improve the gate potential stability of the fourteenth transistor T14 and the sixteenth transistor T16.

[0191] As a possible implementation, Fig. 20 As shown, the second control module 22 includes a nineteenth transistor T19 and a twentieth transistor T20, wherein the first electrode of the nineteenth transistor T19 receives the first clock signal CK1, the second electrode is electrically connected to the eighth node N8, and the gate is electrically connected to the seventh node N7, and the first electrode of the twentieth transistor T20 receives the second fixed potential signal VGL, the second electrode is electrically connected to the eighth node N8, and the gate receives the first clock signal. The second control module 22 can transmit the second fixed potential signal VGL or the first clock signal CK1 to the eighth node N8 in response to the potential of the seventh node N7 and the first clock signal CK1.

[0192] The second voltage-stabilizing switch module 21 includes a second voltage-stabilizing transistor TF2, a third voltage-stabilizing transistor TF3 and a fourth voltage-stabilizing transistor TF4. The first electrode of the second voltage-stabilizing transistor TF2 receives the first fixed potential signal VGH, the second electrode is electrically connected to the ninth node N9, and the gate is electrically connected to the eighth node N8. The first electrode of the third voltage-stabilizing transistor TF3 is electrically connected to the ninth node N9, the second electrode is electrically connected to the seventh node N7, and the gate receives the second clock signal CK2. The first electrode of the fourth voltage-stabilizing transistor TF4 is electrically connected to the ninth node N9, the second electrode is electrically connected to the seventh node N7, and the gate receives the third clock signal CK3.

[0193] The second voltage regulating switch module 21 can transmit the first fixed potential signal VGH to the seventh node N7 in response to the potential of the eighth node N8 and the second clock signal CK2 and the third clock signal CK3.

[0194] The channel types of the nineteenth transistor T19 , the twentieth transistor T20 , the second voltage-stabilizing transistor TF2 , the third voltage-stabilizing transistor TF3 and the fourth voltage-stabilizing transistor TF4 are the same.

[0195] Exemplarily, the nineteenth transistor T19 , the twentieth transistor T20 , the second voltage-stabilizing transistor TF2 , the third voltage-stabilizing transistor TF3 , and the fourth voltage-stabilizing transistor TF4 are all P-type transistors.

[0196] In the present implementation, during the period when the seventh node N7 maintains a high level, the twentieth transistor T20 can transmit the low-level second fixed potential signal VGL to the eighth node N8, the low-level signal of the eighth node N8 controls the second voltage-stabilizing transistor TF2 to turn on, the high-level first fixed potential signal VGH can be transmitted to the ninth node N9 through the second voltage-stabilizing transistor TF2, when the second clock signal CK2 transmits a low-level signal, the high level of the ninth node N9 can be transmitted to the seventh node N7 through the third voltage-stabilizing transistor TF3, maintaining the high-level potential of the seventh node N7 and the seventh-second node N7a, which is conducive to avoiding the situation that the second clock signal CK2 jumps to pull down the potential of the seventh-second node N7a and causes the fifteenth transistor T15 to be turned on multiple times. When the third clock signal CK3 transmits a low-level signal, the high level of the ninth node N9 can be transmitted to the seventh node N7 through the fourth voltage-stabilizing transistor TF4, maintaining the high-level potential of the seventh node N7 and the seventh-second node N7b, which is conducive to avoiding the situation that the third clock signal CK3 jumps to pull down the potential of the seventh-second node N7b and causes the seventeenth transistor T17 to be turned on multiple times.

[0197] As another possible implementation, Fig.21 As shown, Fig.21 A schematic diagram of another second shift register unit provided in an embodiment of the present application, wherein the second control module 22 includes a nineteenth transistor T19 and a twentieth transistor T20 of different channel types, wherein the first electrode of the nineteenth transistor T19 receives the first fixed potential signal VGH, the second electrode is electrically connected to the eighth node N8, and the gate is electrically connected to the seventh node N7, and the first electrode of the twentieth transistor T20 receives the second fixed potential signal VGL, the second electrode is electrically connected to the eighth node N8, and the gate is electrically connected to the seventh node N7. The second control module 22 transmits the first fixed potential signal VGH or the second fixed potential signal VGL to the eighth node N8 in response to the potential of the seventh node N7, and the potential level of the eighth node N8 may be opposite to the potential level of the seventh node N7.

[0198] The second voltage-stabilizing switch module 21 includes a second voltage-stabilizing transistor TF2 and a third voltage-stabilizing transistor TF3 of different channel types, wherein the first electrode of the second voltage-stabilizing transistor TF2 receives the first fixed potential signal VGH, the second electrode is electrically connected to the seventh node N7, and the gate is electrically connected to the eighth node N8, and the first electrode of the third voltage-stabilizing transistor TF3 receives the second fixed potential signal VGL, the second electrode is electrically connected to the seventh node N7, and the gate is electrically connected to the eighth node N8. In response to the potential of the eighth node N8, the second voltage-stabilizing switch module 21 transmits the first fixed potential signal VGH or the second fixed potential signal VGL to the seventh node N7.

[0199] The nineteenth transistor T19 has the same channel type as the second voltage-stabilizing transistor TF2 , and the twentieth transistor T20 has the same channel type as the third voltage-stabilizing transistor TF3 .

[0200] Exemplarily, the nineteenth transistor T19 and the second voltage-stabilizing transistor TF2 are P-type transistors, and the twentieth transistor T20 and the third voltage-stabilizing transistor TF3 are N-type transistors.

[0201] In the present implementation, during the period when the seventh node N7 maintains a high level, the nineteenth transistor T19 is turned off, the twentieth transistor T20 is turned on, the low-level second fixed potential signal VGL is transmitted to the eighth node N8 through the twentieth transistor T20, the eighth node N8 maintains a low level, the low-level potential of the eighth node N8 controls the second voltage-stabilizing transistor TF2 to turn on, the third voltage-stabilizing transistor TF3 is turned off, and the high-level first fixed potential signal VGH is transmitted to the seventh node N7 through the second voltage-stabilizing transistor TF2 to maintain the high-level potential of the seventh node N7 and the seventh-second node N7a and the seventh-second node N7b. This is helpful to avoid the situation where the second clock signal CK2 jumps and pulls down the seventh-second node N7a, causing the fifteenth transistor T15 to be turned on multiple times, and avoid the situation where the third clock signal CK3 jumps and pulls down the seventh-second node N7b, causing the seventeenth transistor T17 to be turned on multiple times.

[0202] During the period when the seventh node N7 maintains a low level, the nineteenth transistor T19 is turned on and the twentieth transistor T20 is turned off. The high-level first fixed potential signal VGH is transmitted to the eighth node N8 through the nineteenth transistor T19. The eighth node N8 maintains a high level. The high-level potential of the eighth node N8 controls the second voltage-stabilizing transistor TF2 to turn off, and the third voltage-stabilizing transistor TF3 to turn on. The low-level second fixed potential signal VGL is transmitted to the seventh node N7 through the third voltage-stabilizing transistor TF3, maintaining the low-level potentials of the seventh node N7 and the seventh-first node N7a and the seventh-second node N7b.

[0203] This implementation method can enable the seventh node N7 to maintain a stable high-level potential or a low-level potential, and will not cause the potential of the seventh node N7 to float, which is beneficial to improving the potential stability of the seventh node N7.

[0204] Fig. 22 A schematic diagram of another second shift register unit provided in an embodiment of the present application, Fig. 22 The second shift register unit shown in FIG. Fig. 20The difference between the second shift register units shown may be that the gate of the eighteenth transistor T18, the first electrode of the nineteenth transistor T19, and the gate of the twentieth transistor T20 all receive the second clock signal CK2, the first electrode of the fifteenth transistor T15 and the gate of the third voltage-stabilizing transistor TF3 all receive the third clock signal CK3, and the first electrode of the seventeenth transistor T17 and the gate of the fourth voltage-stabilizing transistor TF4 all receive the fourth clock signal CK4.

[0205] So, in Fig. 22 The second shift register unit shown, and Figure 6 , Figure 8 , Fig.10 , Fig.12 In the scan circuit 100 composed of the first shift register unit 101 shown in any one of the above, the load of the first clock signal CK1 can be reduced, which is beneficial to reducing the signal output difference caused by the imbalance of the clock signal load.

[0206] Fig.23 A timing diagram of a scanning circuit provided in an embodiment of the present application, Fig.23 The timing diagram shown includes Figure 8 The first shift register unit 101 and Fig. 22 A timing diagram of the scan circuit 100 of the second shift register unit 102 is shown.

[0207] like Fig.23 As shown, in the signal output period Z of the scanning circuit 100, the first trigger signal SN_IN is a low level signal, the first node N1 is a low level signal, the second node N2 is a high level signal, the second branch node N2A is a low level signal, the first cascade signal outputted from the output terminal SN_NEXT of the first cascade module 12 is a low level signal, and the first type of scanning signal outputted from the output terminal SN_OUT of the first type of signal output module 16 is a high level signal.

[0208] The signal output period Z of the scanning circuit 100 further includes a first stage Z1 , a second stage Z2 and a third stage Z3 . In the first stage Z1 , the second stage Z2 and the third stage Z3 , the first clock signal CK1 is a high level signal.

[0209] In the first phase Z1, the second trigger signal SP_IN is a low level signal, the second clock signal CK2 is a low level signal, the seventh node N7 is a low level signal, the eighth node N8 is a low level signal, the third clock signal CK3 and the fourth clock signal CK4 are both high level. The output terminal SP_OUT1 of the first scanning signal output module 191 and the output terminal SP_OUT2 of the second scanning signal output module 192 both output high level signals.

[0210] In the second phase Z2, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the fourth clock signal CK4 are high level signals, the seventh node N7 maintains a low level signal, the eighth node N8 is a high level signal, and the third clock signal CK3 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a low level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a high level signal.

[0211] In the third stage Z3, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the third clock signal CK3 are high level signals, the seventh node N7 maintains a low level signal, the eighth node N8 maintains a high level signal, and the fourth clock signal CK4 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a high level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a low level signal.

[0212] It should be noted that in Fig.23 In the timing diagram shown, the selection signal line CTRL transmits a low level signal.

[0213] Fig.24 A timing diagram of another scanning circuit provided in an embodiment of the present application, Fig.24 The timing diagram shown includes Fig.12 The first shift register unit 101 and Fig. 22 A timing diagram of the scan circuit 100 of the second shift register unit 102 is shown.

[0214] like Fig.24 As shown, in the signal output period Z of the scanning circuit 100, the first trigger signal SN_IN is a high-level signal, the first main node N1a and the second main node N2a are both high-level signals, the third node N3 is a low-level signal, the first cascade signal outputted by the output terminal SN_NEXT of the first cascade module 12 is a high-level signal, the sixth node N6 is a low-level signal, and the first type of scanning signal outputted by the output terminal SN_OUT of the first type of signal output module 16 is a high-level signal.

[0215] The signal output period Z of the scanning circuit 100 further includes a first stage Z1 , a second stage Z2 and a third stage Z3 . In the first stage Z1 , the second stage Z2 and the third stage Z3 , the first clock signal CK1 is a high level signal.

[0216] In the first phase Z1, the second trigger signal SP_IN is a low level signal, the second clock signal CK2 is a low level signal, the seventh node N7 is a low level signal, the eighth node N8 is a low level signal, the third clock signal CK3 and the fourth clock signal CK4 are both high level. The output terminal SP_OUT1 of the first scanning signal output module 191 and the output terminal SP_OUT2 of the second scanning signal output module 192 both output high level signals.

[0217] In the second phase Z2, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the fourth clock signal CK4 are high level signals, the seventh node N7 maintains a low level signal, the eighth node N8 is a high level signal, and the third clock signal CK3 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a low level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a high level signal.

[0218] In the third stage Z3, the second trigger signal SP_IN is a high level signal, the second clock signal CK2 and the third clock signal CK3 are high level signals, the seventh node N7 maintains a low level signal, the eighth node N8 maintains a high level signal, and the fourth clock signal CK4 is a low level signal. The output terminal SP_OUT1 of the first scanning signal output module 191 outputs a high level signal, and the output terminal SP_OUT2 of the second scanning signal output module 192 outputs a low level signal.

[0219] Fig.25 A connection diagram of a scanning circuit provided in an embodiment of the present application.

[0220] In one embodiment of the present application, Figure 8 , Fig. 20 and Fig.25 As shown, in the odd-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the first clock signal line CL1, and in the even-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the third clock signal line CL3. That is, in the odd-numbered first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the control end of the first input module 11, and in the even-numbered first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 is used as the first clock signal CK1 received by the control end of the first input module 11.

[0221] In the odd-row second shift register unit 102, the control end of the second input module 20 is electrically connected to the first clock signal line CL1, the input end of the fourth output module 1912 is electrically connected to the second clock signal line CL2, and the input end of the sixth output module 1922 is electrically connected to the third clock signal CL3.

[0222] In the even-row second shift register unit 102, the control end of the second input module 20 is electrically connected to the third clock signal line CL3, the input end of the fourth output module 1912 is electrically connected to the fourth clock signal line CL4, and the input end of the sixth output module 1922 is electrically connected to the first clock signal CL1.

[0223] That is to say, in the second shift register unit 102 in the odd row, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the second shift register unit 102, the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the third clock signal CL3 is used as the third clock signal CK3 received by the second shift register unit 102.

[0224] In the second shift register unit 102 in the even row, the clock signal transmitted by the third clock signal CL3 is used as the first clock signal CK1 received by the second shift register unit 102, the clock signal transmitted by the fourth clock signal line CL4 is used as the second clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the first clock signal line CL1 is used as the third clock signal CK3 received by the second shift register unit 102.

[0225] In this implementation, the first shift register unit 101 and the second shift register unit 102 can share a clock signal line, which is beneficial to reducing the number of clock signal lines required by the scanning circuit 100 and reducing power consumption.

[0226] Fig.26 A connection diagram of another scanning circuit provided in an embodiment of the present application.

[0227] In one embodiment of the present application, Figure 8 , Fig. 20 and Fig.26As shown, in the odd-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the first clock signal line CL1, and in the even-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the third clock signal line CL3. That is, in the odd-numbered first shift register unit 101, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the control end of the first input module 11, and in the even-numbered first shift register unit 101, the clock signal transmitted by the third clock signal line CL3 is used as the first clock signal CK1 received by the control end of the first input module 11.

[0228] In the odd-row second shift register unit 102, the control end of the second input module 20 is electrically connected to the second clock signal line CL2, the input end of the fourth output module 1912 is electrically connected to the third clock signal line CL3, and the input end of the sixth output module 1922 is electrically connected to the fourth clock signal CL4.

[0229] In the even-row second shift register unit 102, the control end of the second input module 20 is electrically connected to the fourth clock signal line CL4, the input end of the fourth output module 1912 is electrically connected to the first clock signal line CL1, and the input end of the sixth output module 1922 is electrically connected to the second clock signal CL2.

[0230] That is to say, in the second shift register unit 102 in the odd row, the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the second shift register unit 102, the clock signal transmitted by the third clock signal line CL3 is used as the third clock signal CK2 received by the second shift register unit 102, and the clock signal transmitted by the fourth clock signal CL4 is used as the fourth clock signal CK4 received by the second shift register unit 102.

[0231] In the second shift register unit 102 in the even row, the clock signal transmitted by the fourth clock signal CL4 is used as the second clock signal CK2 received by the second shift register unit 102, the clock signal transmitted by the first clock signal line CL1 is used as the third clock signal CK3 received by the second shift register unit 102, and the clock signal transmitted by the second clock signal line CL2 is used as the fourth clock signal CK3 received by the second shift register unit 102.

[0232] In this implementation, while the first shift register unit 101 and the second shift register unit 102 can share a clock signal line, it is also beneficial to make the load of clock signals transmitted by different clock signal lines more balanced, which is beneficial to improving the signal output difference of the shift register unit caused by the unbalanced load of the clock signal line.

[0233] Fig. 27A connection diagram of another scanning circuit provided in an embodiment of the present application.

[0234] In one embodiment of the present application, Fig.10 , Fig. 20 and Fig. 27 , or combined Fig.12 , Fig. 20 and Fig. 27 As shown, in the odd-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the first clock signal line CL1, and the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the second clock signal line CL2.

[0235] In the even-numbered first shift register unit 101, the control end of the first input module 11 is electrically connected to the third clock signal line CL3, and the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the fourth clock signal line CL4.

[0236] That is, in the odd-numbered first shift register unit 101 , the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the first shift register unit 101 , and the clock signal transmitted by the second clock signal line CL2 is used as the second clock signal CK2 received by the first shift register unit 101 .

[0237] In the even-numbered row first shift register unit 101 , the clock signal transmitted by the third clock signal line CL3 is used as the first clock signal CK1 received by the first shift register unit 101 , and the clock signal transmitted by the fourth clock signal line CL4 is used as the second clock signal CK2 received by the first shift register unit 101 .

[0238] In this implementation, the clock signal line connected to the first shift register unit 101 can be shared with the clock signal line connected to the second shift register unit 102 in the above solution, for example, Fig. 20 The second shift register unit 102 shares a clock signal line, which is beneficial to reducing the number of clock signal lines connected to the scanning circuit 100 composed of the first shift register unit 101 and the second shift register unit 102, thereby reducing power consumption.

[0239] Fig.28 A connection diagram of another scanning circuit provided in an embodiment of the present application.

[0240] In one embodiment of the present application, Fig.10 , Fig. 20 and Fig.28 , or combined Fig.12 , Fig. 20 and Fig.28As shown, in the odd-row first shift register unit 101, the control end of the first input module 11 is electrically connected to the first clock signal line CL1, and the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the third clock signal line CL3 or the fourth clock signal line CL4.

[0241] In the even-numbered row first shift register unit 101 , the control end of the first input module 11 is electrically connected to the third clock signal line CL3 , and the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the first clock signal line CL1 or the second clock signal line CL2 .

[0242] That is, in the first shift register unit 101 in the odd row, the clock signal transmitted by the first clock signal line CL1 is used as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the third clock signal line CL3 or the fourth clock signal line CL4 is used as the second clock signal CK2 received by the first shift register unit 101.

[0243] In the first shift register unit 101 in the even row, the clock signal transmitted by the third clock signal line CL3 is used as the first clock signal CK1 received by the first shift register unit 101, and the clock signal transmitted by the first clock signal line CL1 or the second clock signal line CL2 is used as the second clock signal CK2 received by the first shift register unit 101.

[0244] It should be noted that Fig.28 It only illustrates that in the first shift register units 101 in odd rows, the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the third clock signal line CL3, and in the first shift register units 101 in even rows, the second input end of the auxiliary voltage stabilizing module 18 is electrically connected to the first clock signal line CL1.

[0245] In this embodiment, when the first shift register unit 101 and the second shift register unit 102 (for example Fig. 20 When a second shift register unit (as shown in the figure) shares a clock signal line, the clock signal line connected to the second input end of the auxiliary voltage stabilizing module 18 can be flexibly adjusted according to the load on different clock signal lines to improve the load uniformity of each clock signal line connected to the scanning circuit 100 and improve the signal output difference of the shift register unit caused by the unbalanced load of the clock signal line.

[0246] like Figure 1 and Fig.18As shown, the embodiment of the present application further provides a display panel 200, and the display panel 200 includes the scanning circuit 100 provided in the above embodiment. Exemplarily, the display panel 200 can be any one of an organic light emitting diode (OLED) display panel, a micro light emitting diode (Micro-LED) display panel, and a sub-millimeter light emitting diode (Mini-LED) display panel, and the present application does not make specific limitations.

[0247] In the display panel 200, if the output end of the first voltage-stabilizing switch module 13 is electrically connected to the output end of the first input module 11, a voltage-stabilizing signal can be provided to the output end of the first input module 11 through the first voltage-stabilizing switch module 13 to compensate for the potential loss during the output process of the first input module 11, which is beneficial to improving the accuracy and stability of the potential at the output end of the first input module 11, thereby helping to improve the working reliability of other modules that receive the potential at the output end of the first input module 11, and further helping to improve the working reliability of the first shift register unit 101.

[0248] If the output end of the first voltage-stabilizing switch module 13 is electrically connected to part of the control end of the first cascade module 12, a voltage-stabilizing signal can be provided to part of the control end of the first cascade module 12 through the first voltage-stabilizing switch module 13, which is beneficial to improving the stability of the potential of the control end of the first cascade module 12, thereby helping to improve the working reliability of the first cascade module 12, and further helping to improve the working reliability of the first shift register unit 101.

[0249] Fig.29 A schematic diagram of a display device provided in an embodiment of the present application.

[0250] like Fig.29 As shown, the embodiment of the present application provides a display device 300, including the display panel 200 provided in the above embodiment. Exemplarily, the display device 200 can be an electronic device such as a mobile phone, a computer, a television, a car display, a wearable display, etc., and the present application does not make specific limitations.

[0251] In the display device 300, if the output end of the first voltage-stabilizing switch module 13 is electrically connected to the output end of the first input module 11, a voltage-stabilizing signal can be provided to the output end of the first input module 11 through the first voltage-stabilizing switch module 13 to compensate for the potential loss during the output process of the first input module 11, which is beneficial to improving the accuracy and stability of the potential at the output end of the first input module 11, thereby helping to improve the working reliability of other modules that receive the potential at the output end of the first input module 11, and further helping to improve the working reliability of the first shift register unit 101.

[0252] If the output end of the first voltage-stabilizing switch module 13 is electrically connected to part of the control end of the first cascade module 12, a voltage-stabilizing signal can be provided to part of the control end of the first cascade module 12 through the first voltage-stabilizing switch module 13, which is beneficial to improving the stability of the potential of the control end of the first cascade module 12, thereby helping to improve the working reliability of the first cascade module 12, and further helping to improve the working reliability of the first shift register unit 101.

[0253] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A scanning circuit, characterized in that: At least comprising a plurality of cascaded first shift register units, wherein the first shift register unit comprises a first input module and a first cascade module, wherein an input end of the first input module is used to receive a first trigger signal, and an output end of the first cascade module is used to output a first cascade signal; The first shift register unit further includes a first voltage stabilizing switch module, and an output end of the first voltage stabilizing switch module is electrically connected to an output end of the first input module; And / or, the output end of the first voltage stabilizing switch module is electrically connected to part of the control ends of the first cascade module.

2. The scanning circuit according to claim 1, characterized in that: The output end of the first input module is electrically connected to the first node, and the control end receives the first clock signal; the first input end of the first cascade module receives the first fixed potential signal, the second input end receives the second fixed potential signal, and the control end is electrically connected to the second node; The first shift register unit further includes a first control module, wherein a first input terminal of the first control module receives the first fixed potential signal, a second input terminal receives the second fixed potential signal, a control terminal is electrically connected to the first node, and an output terminal is electrically connected to the second node; The input end of the first voltage-stabilizing switch module receives the second fixed potential signal, the output end is electrically connected to the first node, and the control end is electrically connected to the second node.

3. The scanning circuit according to claim 2, characterized in that: The first input module comprises a first transistor, wherein a first electrode of the first transistor receives the first trigger signal, a second electrode is electrically connected to the first node, and a gate receives a first clock signal; The first control module includes a second transistor and a third transistor of different channel types, wherein the first electrode of the second transistor receives the first fixed potential signal, the second electrode is electrically connected to the second node, and the gate is electrically connected to the first node; the first electrode of the third transistor receives the second fixed potential signal, the second electrode is electrically connected to the second node, and the gate is electrically connected to the first node; The first cascade module includes a fourth transistor and a fifth transistor of different channel types, wherein a first electrode of the fourth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the first cascade module, and a gate is electrically connected to the second node; a first electrode of the fifth transistor receives the second fixed potential signal, a second electrode is electrically connected to the output end of the first cascade module, and a control end is electrically connected to the second node; The first voltage stabilizing switch module comprises a first voltage stabilizing transistor, wherein a first electrode of the first voltage stabilizing transistor receives the second fixed potential signal, a second electrode is electrically connected to the first node, and a gate is electrically connected to the second node; The second transistor and the fourth transistor have the same channel type, and the third transistor, the first voltage-stabilizing transistor and the fifth transistor have the same channel type.

4. The scanning circuit according to claim 2, characterized in that: The first shift register unit comprises a first type signal output module, and the output end of the first type signal output module is used to output a first type scanning signal; The first type of signal output module includes a first output module and a second output module, the input end of the first output module receives the first fixed potential signal, and the output end is electrically connected to the output end of the first type of signal output module, and the input end of the second output module receives the second fixed potential signal, and the output end is electrically connected to the output end of the first type of signal output module; The first shift register unit further includes a gating module, wherein a first input terminal of the gating module receives the first fixed potential signal, and a second input terminal of the gating module is electrically connected to a gating signal line; Among them, a control end of at least one of the first output module and the second output module is electrically connected to the output end of the selection module.

5. The scanning circuit according to claim 4, characterized in that: The first output module comprises a sixth transistor, a first electrode of the sixth transistor receives the first fixed potential signal, and a second electrode is electrically connected to an output end of the first type signal output module; The second output module comprises a seventh transistor, a first electrode of the seventh transistor receives the second fixed potential signal, and a second electrode is electrically connected to the output end of the first type signal output module; The sixth transistor and the seventh transistor have different channel types.

6. The scanning circuit according to claim 5, characterized in that: The gating module comprises a first submodule and a second submodule, wherein the input end of the first submodule receives the first fixed potential signal, the control end is electrically connected to the second node, and the output end is electrically connected to the control end of the first output module; The input end of the second submodule is electrically connected to the selection signal line, the output end is electrically connected to the control end of the first output module, and the control end is electrically connected to the output end of the first cascade module; The control end of the second output module is electrically connected to the output end of the first cascade module.

7. The scanning circuit according to claim 6, characterized in that: The first submodule includes an eighth transistor, wherein a first electrode of the eighth transistor receives the first fixed potential signal, a second electrode is electrically connected to the gate of the sixth transistor, and a gate is electrically connected to the second node; The second submodule includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the selection signal line, a second electrode is electrically connected to the gate of the sixth transistor, and a gate is electrically connected to the output end of the first cascade module; The gate of the seventh transistor is electrically connected to the output end of the first cascade module; The channel type of the eighth transistor is the same as that of the ninth transistor, and different from that of the seventh transistor.

8. The scanning circuit according to claim 5, characterized in that: The gating module includes a first submodule and a second submodule, wherein the input end of the first submodule receives the first fixed potential signal, the control end is electrically connected to the second node, and the output end is electrically connected to the control end of the first output module and the second output module; The input end of the second submodule is electrically connected to the selection signal line, the control end is electrically connected to the second node, and the output end is electrically connected to the control ends of the first output module and the second output module.

9. The scanning circuit according to claim 8, characterized in that: The first submodule includes an eighth transistor, wherein a first electrode of the eighth transistor receives the first fixed potential signal, a second electrode is electrically connected to the gates of the sixth transistor and the seventh transistor, and a gate is electrically connected to the second node; The second submodule includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the selection signal line, a second electrode of the ninth transistor is electrically connected to the gates of the sixth transistor and the seventh transistor, and a gate of the ninth transistor is electrically connected to the second node; The channel types of the eighth transistor and the ninth transistor are different, and the channel types of the eighth transistor and the sixth transistor are the same.

10. The scanning circuit according to claim 2, characterized in that: The first shift register unit includes a first capacitor, one plate of the first capacitor is electrically connected to the first node, and the other plate of the first capacitor receives the second fixed potential signal.

11. The scanning circuit according to claim 1, characterized in that: The first output terminal of the first input module is electrically connected to the first main node, the second output terminal is electrically connected to the first secondary node, the control terminal receives a first clock signal, the first main node is coupled to the second main node, and the first secondary node is coupled to the second secondary node; The first cascade module includes a first sub-cascade module and a second sub-cascade module, wherein the input end of the first sub-cascade module receives a first fixed potential signal, the output end is electrically connected to the output end of the first cascade module, and the control end is electrically connected to the third node; the input end of the second sub-cascade module receives a second fixed potential signal, the output end is electrically connected to the output end of the first cascade module, and the control end is electrically connected to the second main node; The first shift register unit further includes a first control module, the first control module includes a first sub-control module and a second sub-control module, the first sub-control module has an input end receiving the first fixed potential signal, an output end electrically connected to the third node, and a control end electrically connected to the first main node, the second sub-control module has an input end receiving the second fixed potential signal, an output end electrically connected to the third node, and a control end electrically connected to the second main node; The input end of the first voltage stabilizing switch module is electrically connected to the second secondary node, the output end is electrically connected to the second main node, and the control end is electrically connected to the second secondary node.

12. The scanning circuit according to claim 11, characterized in that: The first input module includes a first transistor and a second transistor, wherein the first electrode of the first transistor receives the first trigger signal, the second electrode is electrically connected to the first main node, and the gate receives the first clock signal; the first electrode of the second transistor receives the first trigger signal, the second electrode is electrically connected to the first sub-node, and the gate receives the first clock signal; The first sub-cascade module includes a third transistor, a first electrode of the third transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the first cascade module, and a gate is electrically connected to the third node; the second sub-cascade module includes a fourth transistor, a first electrode of the fourth transistor receives the second fixed potential signal, a second electrode is electrically connected to the output end of the first cascade module, and a gate is electrically connected to the second main node; The first sub-control module includes a fifth transistor, a first electrode of the fifth transistor receives the first fixed potential signal, a second electrode is electrically connected to the third node, and a gate is electrically connected to the first main node; the second sub-control module includes a sixth transistor, a first electrode of the sixth transistor receives the second fixed potential signal, a second electrode is electrically connected to the third node, and a gate is electrically connected to the second main node; The first voltage stabilizing switch module comprises a first voltage stabilizing transistor, wherein a first electrode of the first voltage stabilizing transistor is electrically connected to the secondary node, a second electrode is electrically connected to the second main node, and a gate is electrically connected to the secondary node; The channel type of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor and the first voltage-stabilizing transistor is the same, and is different from the channel type of the sixth transistor.

13. The scanning circuit according to claim 12, characterized in that: The first transistor is a P-type transistor, and the sixth transistor is an N-type transistor.

14. The scanning circuit according to claim 11, characterized in that: A first coupling transistor is included between the first main node and the second main node, a second coupling transistor is included between the first sub-node and the second sub-node, and a gate of the first coupling transistor and a gate of the second coupling transistor both receive the second fixed potential signal; The first coupling transistor and the second coupling transistor have the same channel type.

15. The scanning circuit according to claim 11, characterized in that: The first shift register unit also includes an auxiliary voltage stabilization module, a first input end of the auxiliary voltage stabilization module receives the first fixed potential signal, a second input end receives a second clock signal, and an output end is electrically connected to the second secondary node, and the auxiliary voltage stabilization module is used to adjust the potential of the second secondary node.

16. The scanning circuit according to claim 15, characterized in that: The auxiliary voltage stabilization module includes a first capacitor, a seventh transistor and an eighth transistor, and the seventh transistor and the eighth transistor have the same channel type; One plate of the first capacitor is electrically connected to the second node, and the other plate is electrically connected to the fourth node. The first electrode of the seventh transistor receives the second clock signal, the second electrode is electrically connected to the fourth node, and the gate is electrically connected to the second node. The first electrode of the eighth transistor receives the first fixed potential signal, the second electrode is electrically connected to the fourth node, and the gate is electrically connected to the third node.

17. The scanning circuit according to claim 16, characterized in that: The seventh transistor and the eighth transistor are both P-type transistors.

18. The scanning circuit according to claim 11, characterized in that: The first cascade module is also used to output a first type of scanning signal.

19. The scanning circuit according to claim 11, characterized in that: The first shift register unit also includes a second capacitor and a third capacitor, one plate of the second capacitor receives the first fixed potential signal, and the other plate is electrically connected to the control end of the first sub-cascade module, and one plate of the third capacitor is electrically connected to the output end of the first cascade module, and the other plate is electrically connected to the control end of the second sub-cascade module.

20. The scanning circuit according to claim 11, characterized in that: The first shift register unit further includes a gating module and a first type signal output module, and the output end of the first type signal output module is used to output a first type scanning signal; The first type of signal output module includes a first output module and a second output module, the first output module has an input end receiving the first fixed potential signal, an output end electrically connected to the output end of the first type of signal output module, and a control end electrically connected to the output of the gating module, the second output module has an input end receiving the second fixed potential signal, an output end electrically connected to the output end of the first type of signal output module, and a control end electrically connected to the second main node; The first input end of the selection module is electrically connected to the selection signal line, the second input end is electrically connected to the third node, and the third input end receives the first fixed potential signal. The selection module transmits a control signal to the first output module in response to the output potential of the first main node and the first cascade module.

21. The scanning circuit according to claim 20, characterized in that: The first output module includes a ninth transistor, a first electrode of the ninth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the first type signal output module, and a gate is electrically connected to the fifth node; the second output module includes a tenth transistor, a first electrode of the tenth transistor receives the second fixed potential signal, a second electrode is electrically connected to the output end of the first type signal output module, and a gate is electrically connected to the second main node; The gating module includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, a fourth capacitor, and a fifth capacitor, wherein a first electrode of the eleventh transistor is electrically connected to the gating signal line, a second electrode is electrically connected to the sixth node, and a gate is electrically connected to the output end of the first cascade module, a first electrode of the twelfth transistor is electrically connected to the third node, a second electrode is electrically connected to the fifth node, and a gate is electrically connected to the sixth node, and a first electrode of the thirteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the fifth node, and a gate is electrically connected to the first main node; One plate of the fourth capacitor receives the second fixed potential signal, and the other plate is electrically connected to the sixth node; one plate of the fifth capacitor receives the first fixed potential signal, and the other plate is electrically connected to the fifth node; The ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor and the thirteenth transistor have the same channel type.

22. The scanning circuit according to claim 18 or 20, characterized in that: The first shift register unit further includes a second type signal output module, and the output end of the second type signal output module is used to output a second type scanning signal; The second type of signal output module includes a first scanning signal output module and a second scanning signal output module, the first scanning signal output module includes a third output module and a fourth output module, the input end of the third output module receives the first fixed potential signal, the output end is electrically connected to the output end of the first scanning signal output module, and the control end is electrically connected to the output end of the first cascade module; the input end of the fourth output module receives the second clock signal, and the output end is electrically connected to the output end of the first scanning signal output module; The second scanning signal output module includes a fifth output module and a sixth output module, wherein the input end of the fifth output module receives the first fixed potential signal, the output end is electrically connected to the output end of the second scanning signal output module, and the control end is electrically connected to the output end of the first cascade module; the input end of the sixth output module receives the third clock signal, and the output end is electrically connected to the output end of the second scanning signal output module; The first shift register unit further includes a second input module and a second voltage stabilizing switch module, wherein the input end of the second input module receives the second trigger signal, the output end is electrically connected to the seventh node, and the control end receives the first clock signal, and the seventh node is coupled to the control end of the fourth output module and the control end of the sixth output module; The input end of the second voltage-stabilizing switch module receives the first fixed potential signal, the output end is electrically connected to the seventh node, and the control end is electrically connected to the output end of the first cascade module.

23. The scanning circuit according to claim 22, characterized in that: The third output module includes a fourteenth transistor, a first electrode of the fourteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the first scanning signal output module, and a gate is electrically connected to the output end of the first cascade module; The fourth output module includes a fifteenth transistor, a first electrode of the fifteenth transistor receives the second clock signal, a second electrode is electrically connected to the output end of the first scan signal output module, and a gate is coupled to the seventh node; The fifth output module includes a sixteenth transistor, a first electrode of the sixteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the second scanning signal output module, and a gate is electrically connected to the output end of the first cascade module; The sixth output module comprises a seventeenth transistor, wherein a first electrode of the seventeenth transistor receives the third clock signal, a second electrode is electrically connected to an output end of the second scan signal output module, and a gate is coupled to the seventh node; The second input module comprises an eighteenth transistor, wherein a first electrode of the eighteenth transistor receives the second trigger signal, a second electrode is electrically connected to the seventh node, and a gate receives the first clock signal; The second voltage-stabilizing switch module comprises a second voltage-stabilizing transistor, wherein a first electrode of the second voltage-stabilizing transistor receives the first fixed potential signal, a second electrode is electrically connected to the seventh node, and a gate is electrically connected to the output end of the first cascade module; The fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor and the second voltage-stabilizing transistor have the same channel type.

24. The scanning circuit according to claim 22, characterized in that: A third coupling transistor is included between the seventh node and the control end of the fourth output module, a fourth coupling transistor is included between the seventh node and the control end of the sixth output module, and a gate of the third coupling transistor and a gate of the fourth coupling transistor both receive the second fixed potential signal; The third coupling transistor and the fourth coupling transistor have the same channel type.

25. The scanning circuit according to claim 22, characterized in that: The first shift register unit also includes a sixth capacitor and a seventh capacitor, one plate of the sixth capacitor is electrically connected to the control end of the fourth output module, and the other plate is electrically connected to the output end of the first scan signal output module; one plate of the seventh capacitor is electrically connected to the output end of the second scan signal output module, and the other plate is electrically connected to the control end of the sixth output module.

26. The scanning circuit according to claim 2 or 11, characterized in that: The scanning circuit further includes a plurality of cascaded second shift register units, the second shift register units including a second input module and a second type signal output module, the second input module is used to receive a second trigger signal, the output end of the second type signal module is used to output a second type scanning signal, the output end of the second input module is electrically connected to a seventh node, and the seventh node is coupled to a part of the control end of the second type scanning signal module; The second shift register unit further includes a second voltage stabilizing switch module, and an output end of the second voltage stabilizing switch module is electrically connected to the seventh node.

27. The scanning circuit according to claim 26, characterized in that: The control end of the second input module receives a first clock signal, and the second type of signal output module includes a first scanning signal output module and a second scanning signal output module; The first scanning signal output module includes a third output module and a fourth output module, wherein the input end of the third output module receives the first fixed potential signal, the output end is electrically connected to the output end of the first scanning signal output module, and the control end is electrically connected to the eighth node; the input end of the fourth output module receives the second clock signal, the output end is electrically connected to the output end of the first scanning signal output module, and the control end is coupled to the seventh node; The second scan signal output module includes a fifth output module and a sixth output module, wherein the input end of the fifth output module receives the first fixed potential signal, the output end is electrically connected to the output end of the second scan signal output module, and the control end is electrically connected to the eighth node; the input end of the sixth output module receives the third clock signal, the output end is electrically connected to the output end of the second scan signal output module, and the control end is coupled to the seventh node N7; The second shift register unit further includes a second control module, and an output end of the second control module is electrically connected to the eighth node and the second voltage stabilizing switch module.

28. The scanning circuit according to claim 27, characterized in that: The third output module includes a fourteenth transistor, a first electrode of the fourteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the first scanning signal output module, and a gate is electrically connected to the eighth node; The fourth output module includes a fifteenth transistor, a first electrode of the fifteenth transistor receives the second clock signal, a second electrode is electrically connected to the output end of the first scan signal output module, and a gate is coupled to the seventh node; The fifth output module comprises a sixteenth transistor, a first electrode of the sixteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the output end of the second scanning signal output module, and a gate is electrically connected to the eighth node; The sixth output module comprises a seventeenth transistor, wherein a first electrode of the seventeenth transistor receives the third clock signal, a second electrode is electrically connected to an output end of the second scan signal output module, and a gate is coupled to the seventh node; The second input module comprises an eighteenth transistor, wherein a first electrode of the eighteenth transistor receives the second trigger signal, a second electrode is electrically connected to the seventh node, and a gate receives the first clock signal; Among them, the channel types of the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor and the eighteenth transistor are the same.

29. The scanning circuit according to claim 27, characterized in that: The second control module includes a nineteenth transistor and a twenty-third transistor, wherein a first electrode of the nineteenth transistor receives the first clock signal, a second electrode is electrically connected to the eighth node, and a gate is electrically connected to the seventh node; and a first electrode of the twenty-third transistor receives the second fixed potential signal, a second electrode is electrically connected to the eighth node, and a gate receives the first clock signal; The second voltage-stabilizing switch module includes a second voltage-stabilizing transistor, a third voltage-stabilizing transistor and a fourth voltage-stabilizing transistor, wherein the first electrode of the second voltage-stabilizing transistor receives the first fixed potential signal, the second electrode is electrically connected to the ninth node, and the gate is electrically connected to the eighth node, the first electrode of the third voltage-stabilizing transistor is electrically connected to the ninth node, the second electrode is electrically connected to the seventh node, and the gate receives the second clock signal, and the first electrode of the fourth voltage-stabilizing transistor is electrically connected to the ninth node, the second electrode is electrically connected to the seventh node, and the gate receives the third clock signal; The channel types of the nineteenth transistor, the twentieth transistor, the second voltage-stabilizing transistor, the third voltage-stabilizing transistor and the fourth voltage-stabilizing transistor are the same.

30. The scanning circuit according to claim 27, characterized in that: The second control module includes a nineteenth transistor and a twenty-third transistor with different channel types, wherein a first electrode of the nineteenth transistor receives the first fixed potential signal, a second electrode is electrically connected to the eighth node, and a gate is electrically connected to the seventh node; and a first electrode of the twenty-third transistor receives the second fixed potential signal, a second electrode is electrically connected to the eighth node, and a gate is electrically connected to the seventh node; The second voltage-stabilizing switch module includes a second voltage-stabilizing transistor and a third voltage-stabilizing transistor of different channel types, wherein the first electrode of the second voltage-stabilizing transistor receives the first fixed potential signal, the second electrode is electrically connected to the seventh node, and the gate is electrically connected to the eighth node; the first electrode of the third voltage-stabilizing transistor receives the second fixed potential signal, the second electrode is electrically connected to the seventh node, and the gate is electrically connected to the eighth node; The channel type of the nineteenth transistor is the same as that of the second voltage-stabilizing transistor, and the channel type of the twentieth transistor is the same as that of the third voltage-stabilizing transistor.

31. The scanning circuit according to claim 27, characterized in that: In the first shift register units of odd-numbered rows, the control end of the first input module is electrically connected to the first clock signal line, and in the first shift register units of even-numbered stages, the control end of the first input module is electrically connected to the third clock signal line; In the second shift register units of odd-numbered rows, the control end of the second input module is electrically connected to the first clock signal line, the input end of the fourth output module is electrically connected to the second clock signal line, and the output end of the sixth output module is electrically connected to the third clock signal line; In the second shift register unit in the even row, the control end of the second input module is electrically connected to the third clock signal line, the input end of the fourth output module is electrically connected to the fourth clock signal line, and the output end of the sixth output module is electrically connected to the first clock signal line.

32. The scanning circuit according to claim 27, characterized in that: In the first shift register units of odd-numbered rows, the control end of the first input module is electrically connected to the first clock signal line, and in the first shift register units of even-numbered stages, the control end of the first input module is electrically connected to the third clock signal line; In the second shift register unit of the odd-numbered row, the control end of the second input module is electrically connected to the second clock signal line, the input end of the fourth output module is electrically connected to the third clock signal line, and the output end of the sixth output module is electrically connected to the fourth clock signal line; In the second shift register unit in the even row, the control end of the second input module is electrically connected to the fourth clock signal line, the input end of the fourth output module is electrically connected to the first clock signal line, and the output end of the sixth output module is electrically connected to the second clock signal line.

33. The scanning circuit according to claim 15, characterized in that: In the first shift register unit of the odd-numbered row, the control end of the first input module is electrically connected to the first clock signal line, and the second input end of the auxiliary voltage stabilization module is electrically connected to the second clock signal line; In the even-numbered first shift register unit, the control end of the first input module is electrically connected to the third clock signal line, and the second input end of the auxiliary voltage stabilization module is electrically connected to the fourth clock signal line.

34. The scanning circuit according to claim 15, characterized in that: In the first shift register unit of the odd-numbered row, the control end of the first input module is electrically connected to the first clock signal line, and the second input end of the auxiliary voltage stabilizing module is electrically connected to the third clock signal line or the fourth clock signal line; In the first shift register units in even rows, the control end of the first input module is electrically connected to the third clock signal line, and the second input end of the auxiliary voltage stabilization module is electrically connected to the first clock signal line or the second clock signal line.

35. A display panel, characterized in that: Comprising a scanning circuit as described in any one of claims 1-34.

36. A display device, characterized in that: Comprising the display panel as claimed in claim 35.

Images