Display device

Abstract

Disclosed is a display device including a display panel that displays an image by using a data signal, a data driving circuit that supplies the data signal to the display panel via a channel, and a driving controller that controls the data driving circuit. The data driving circuit includes: an output buffer that outputs the data signal to the channel; a determination circuit connected to the channel, receiving the data signal, and determining a driving capability of the output buffer by using a transition period of the data signal; and a control circuit outputting a current control signal for adjusting the driving strength of the output buffer to the output buffer according to the determination result of the determination circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display device, and more particularly, to a display device including a data driving circuit. Background Art

[0002] Among the display devices, a light emitting display device displays an image by using a light emitting diode that generates light through recombination of electrons and holes. The light emitting display device supports a fast response speed while providing low power consumption.

[0003] The light-emitting display device includes pixels connected to data lines and scan lines. Each of the plurality of pixels generally includes a light-emitting element and a pixel circuit unit for controlling the amount of current flowing to the light-emitting element. In response to a data signal, the pixel circuit unit controls the amount of current flowing from a line to which a first driving voltage is applied to a line to which a second driving voltage is applied via the light-emitting element. In this case, light of a brightness corresponding to the amount of current flowing through the light-emitting element is generated. Summary of the invention

[0004] One or more embodiments of the present disclosure may provide a display device for preventing unnecessary consumption of power by optimally setting a driving capability of a data driving circuit.

[0005] According to one or more embodiments of the present disclosure, a display device includes a display panel that displays an image by using a data signal, a data driving circuit that supplies the data signal to the display panel through a channel, and a driving controller that controls the data driving circuit.

[0006] The data driving circuit may include: an output buffer that outputs a data signal to a channel; a determination circuit that is connected to the channel, receives the data signal, and determines the driving capability of the output buffer by utilizing a transition period of the data signal; and a control circuit that outputs a current control signal for adjusting the driving strength of the output buffer to the output buffer according to a determination result of the determination circuit.

[0007] In one or more embodiments, the determination circuit may include a counting circuit configured to count transition cycles to output a count value.

[0008] In one or more embodiments, the transition period may include: a rising transition period, which is set as the time period from the data signal reaching a first threshold point of a low threshold voltage to the data signal reaching a second threshold point of a high threshold voltage; and a falling transition period, which is set as the time period from the data signal reaching a third threshold point of a high threshold voltage to the data signal reaching a fourth threshold point of a low threshold voltage.

[0009] In one or more embodiments, the determination circuit may further include: a first comparator configured to compare the data signal with the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal with the low threshold voltage to output a second comparison result. The counting circuit may be configured to determine a counting start point and a counting end point by using the first comparison result and the second comparison result.

[0010] In one or more embodiments, the counting circuit may be configured to: output a first count value by counting a duration of a rising transition period; and output a second count value by counting a duration of a falling transition period.

[0011] In one or more embodiments, the control circuit can be configured to: compare the first count value and the second count value with a threshold range; when both the first count value and the second count value are within the threshold range, output a current control signal having a reference value; and when at least one of the first count value and the second count value is outside the threshold range, output a current control signal having a compensation value different from the reference value.

[0012] In one or more embodiments, the transition period can be set to a time period from when the data signal reaches a first threshold point of a low threshold voltage to when the data signal reaches a second threshold point of a high threshold voltage, and the counting circuit can be configured to output a count value by counting the duration of the transition period.

[0013] In one or more embodiments, the determination circuit may further include: a first comparator configured to compare the data signal with the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal with the low threshold voltage to output a second comparison result. The counting circuit may be configured to determine a counting start point and a counting end point by using the first comparison result and the second comparison result.

[0014] In one or more embodiments, the control circuit can be configured to: compare the count value with a threshold range; when the count value is within the threshold range, output a current control signal having a reference value; and when the count value is outside the threshold range, output a current control signal having a compensation value different from the reference value.

[0015] In one or more embodiments, the determination circuit may be configured to receive an enable signal or a disable signal from the drive controller to be activated in response to the enable signal, or to be deactivated in response to the disable signal.

[0016] In one or more embodiments, the data driving circuit may further include: a switching circuit configured to switch a connection between the channel and the determination circuit in response to a switching signal.

[0017] In one or more embodiments, the drive controller may be configured to provide a switching signal to the switching circuit.

[0018] In one or more embodiments, the channel may include a plurality of channels, the output buffer may include a plurality of output buffers respectively connected to the plurality of channels, and the determination circuit may be connected to some channels among the plurality of channels.

[0019] In one or more embodiments, the determination circuit may include: a first determination circuit connected to a first channel among multiple channels, and the first determination circuit is configured to output a first result value associated with a transition period of a first data signal output to the first channel; a second determination circuit connected to a second channel among the multiple channels, and the second determination circuit is configured to output a second result value associated with a transition period of a second data signal output to the second channel; and a third determination circuit connected to a third channel among the multiple channels, and the third determination circuit is configured to output a third result value associated with a transition period of a third data signal output to the third channel.

[0020] In one or more embodiments, the control circuit can be configured to: compare each of the first result value to the third result value with a threshold range; when all of the first result value to the third result value are within the threshold range, output a current control signal having a reference value to multiple output buffers; and when at least one of the first result value, the second result value, and the third result value is outside the threshold range, output a current control signal having a compensation value different from the reference value to the multiple output buffers.

[0021] In one or more embodiments, the first channel and the third channel may be outermost channels among the plurality of channels, and the second channel may be a centrally positioned channel among the plurality of channels.

[0022] In one or more embodiments, each of the first to third determination circuits may receive an enable signal or a disable signal from the driving controller, may be activated in response to the enable signal, or may be deactivated in response to the disable signal.

[0023] In one or more embodiments, the data driving circuit may further include: a first switching circuit configured to switch the connection between the first channel and the first determination circuit in response to a first switching signal; a second switching circuit configured to switch the connection between the second channel and the second determination circuit in response to a second switching signal; and a third switching circuit configured to switch the connection between the third channel and the third determination circuit in response to a third switching signal.

[0024] In one or more embodiments, the driving controller may be configured to provide first to third switching signals to the data driving circuit.

[0025] In one or more embodiments, the control circuit may be configured to commonly supply a current control signal to a plurality of output buffers. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other aspects and features of the present disclosure will become apparent by describing the embodiments of the present disclosure in detail with reference to the attached drawings.

[0027] Figure 1 is a perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0028] Figure 2A is an exploded perspective view of an electronic device according to one or more embodiments of the present disclosure.

[0029] Figure 2B is a cross-sectional view of a display device according to one or more embodiments of the present disclosure.

[0030] Figure 3 is a block diagram of a display device according to one or more embodiments of the present disclosure.

[0031] Figure 4 is a block diagram of a data driving circuit according to one or more embodiments of the present disclosure.

[0032] Figure 5 It is shown Figure 4 A block diagram of the output buffer unit and the current control unit shown in FIG.

[0033] Fig. 6A yes Figure 5 The internal block diagram of the determination circuit shown in .

[0034] Figure 6B It shows Fig. 6A The waveform diagram of the first transition period and the second transition period and the data signal shown in .

[0035] Figure 7 is a waveform diagram illustrating a data signal and a transition period according to one or more embodiments of the present disclosure.

[0036] Figure 8 is a block diagram illustrating an output buffer unit, a switch circuit, and a current control unit according to one or more embodiments of the present disclosure.

[0037] Fig. 9 is a block diagram illustrating an output buffer unit and a current control unit according to one or more embodiments of the present disclosure.

[0038] Fig.10is a block diagram illustrating an output buffer unit, a switch circuit, and a current control unit according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0039] In the specification, the expression that a first component (or region, layer, part or portion) is "on", "connected to" or "coupled to" a second component means that the first component is directly on / directly connected to / directly coupled to the second component, or that a third component is between the first component and the second component.

[0040] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components may be exaggerated to effectively describe the technical features. The expression "and / or" includes one or more combinations that the relevant components can define. For example, "A and / or B" can be understood to mean "A, B, or A and B". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one (person / kind) of..." is intended to include the meaning of "at least one (person / kind) selected from the group of...". For example, "at least one (person / kind) of A and B" can be understood to mean "A, B, or A and B".

[0041] Although terms such as "first", "second", etc. may be used to describe various components, these components should not be construed as being limited by these terms. These terms are only used to distinguish one component from another. For example, a first component may be referred to as a "second component" without departing from the scope and spirit of the present invention, and similarly, a second component may be referred to as a "first component". Unless the context clearly indicates otherwise, a singular form is intended to include a plural form.

[0042] Additionally, the terms "below," "beneath," "on," and "above," etc., are used to describe the relationship of components shown in the drawings. These terms are relative and are described with respect to the directions indicated in the drawings.

[0043] It will also be understood that the terms “including,” “comprising,” and “having” indicate the presence of stated features, quantities, steps, operations, elements, components, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0044] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formalized meaning.

[0045] In view of the entire content of the present disclosure, it will be understood by those of ordinary skill in the art that, unless otherwise specified or implied, each suitable feature of the various embodiments of the present disclosure may be combined in part or in whole or in combination with each other, and may be technically interlocked and operated in various suitable ways, and each embodiment may be implemented independently of each other or in combination with each other in any suitable manner.

[0046] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0047] Figure 1 is a perspective view of an electronic device ED according to one or more embodiments of the present disclosure.

[0048] Reference Figure 1 , the electronic device ED according to one or more embodiments of the present disclosure may be in the shape of a rectangle having short sides parallel to the first direction DR1 and long sides parallel to the second direction DR2 intersecting the first direction DR1. However, the present disclosure is not limited thereto. For example, the electronic device ED may be implemented in various suitable shapes such as a circle and / or other polygons.

[0049] The electronic device ED may be a device activated by an electrical signal. The electronic device ED may include various suitable embodiments. For example, the electronic device ED may be applied to electronic devices such as smart phones, smart watches, computers (such as tablet computers, notebook computers), smart TVs, and / or navigation systems, but the present disclosure is not limited thereto.

[0050] Hereinafter, a normal direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In the specification, the expressions "when viewed from above a plane" and "in a plan view" may mean "when viewed in the third direction DR3".

[0051] An upper surface of the electronic device ED may be defined as a display surface IS and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. An image IM or images IM generated by the electronic device ED may be provided to a user via the display surface IS.

[0052] The display surface IS may be divided into a transmission area TA and a frame area BZA. The transmission area TA may be an area in which one image IM or multiple images IM are displayed. The user visually perceives one image IM or multiple images IM via the transmission area TA. In one or more embodiments, the transmission area TA is shown as a quadrilateral shape whose vertices are rounded. However, this is shown as an example, and the present disclosure is not limited thereto. In one or more embodiments of the present disclosure, the transmission area TA may be implemented to have various suitable shapes and may not be limited to any one specific shape.

[0053] The border area BZA is adjacent to the transmission area TA. The border area BZA may have a given color. The border area BZA may be around the transmission area TA (or may surround the transmission area TA). Therefore, the shape of the transmission area TA may be substantially defined by the border area BZA. However, this is shown as an example, and the present disclosure is not limited thereto. For example, the border area BZA may be positioned adjacent to only one side or some sides of the transmission area TA, or the border area BZA may be omitted.

[0054] The electronic device ED can sense external input applied from the outside. The external input may include various suitable types of input provided from the outside of the electronic device ED. For example, in addition to contact by a part of a human body such as a user's hand or contact by a separate device (e.g., an active pen and / or a digitizer), the external input may also include an external input applied in a state where the user's hand is close to the electronic device ED or adjacent to the electronic device ED within a given distance (e.g., hovering). In addition, the external input may be provided as various suitable types such as a force type, a pressure type, a temperature type, and / or a light type (e.g., an optical type).

[0055] Figure 2A is an exploded perspective view of an electronic device ED according to one or more embodiments of the present disclosure, and Figure 2B is a cross-sectional view of a display device DD according to one or more embodiments of the present disclosure.

[0056] Reference Figure 2A and Figure 2B , the electronic device ED may include a display device DD, an electronic module and a housing EDC. The display device DD may include a window WM and a display module DM, and may be accommodated in the housing EDC. In one or more embodiments, the appearance of the electronic device ED is achieved or defined by coupling the window WM and the housing EDC.

[0057] The front surface of the window WM defines the display surface IS of the electronic device ED. The window WM may include an optically transparent material. For example, the window WM may include glass or plastic. The window WM may be implemented in a multilayer structure or a single-layer structure. For example, the window WM may include a plurality of plastic films bonded to each other by an adhesive, or may have a glass substrate and a plastic film bonded to each other by an adhesive.

[0058] The display module DM may include a display panel DP and an input sensing layer ISL. The display panel DP may display an image according to an electrical signal, and the input sensing layer ISL may sense an external input applied from the outside. The external input may be provided in various forms.

[0059] The display panel DP according to one or more embodiments of the present disclosure may be a light-emitting display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material, and the light-emitting layer of the inorganic light-emitting display panel may include an inorganic light-emitting material. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots, quantum rods, etc. Below, a description will be given that the display panel DP is an organic light-emitting display panel. However, the present disclosure is not limited thereto.

[0060] Reference Figure 2B , the display panel DP includes a base layer BL, a circuit layer DP_CL, an element layer DP_ED, and an encapsulation layer TFE. The display panel DP according to one or more embodiments of the present disclosure may be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP may be a foldable display panel folded around a folding axis, or a rigid display panel.

[0061] The base layer BL may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and the material of the synthetic resin layer is not particularly limited. In addition, the base layer BL may include a glass substrate, a metal substrate, an organic / inorganic composite material substrate, and the like.

[0062] The circuit layer DP_CL is disposed on the base layer BL. The circuit layer DP_CL is disposed between the base layer BL and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and a circuit element. Below, the insulating layer included in the circuit layer DP_CL may be referred to as an "intermediate insulating layer". The intermediary insulating layer includes at least one intermediary inorganic film and at least one intermediary organic film. The circuit element may include a pixel driving circuit included in each of a plurality of pixels for displaying an image and a sensor driving circuit included in each of a plurality of sensors for identifying external information. The external information may be biometric information. As an example according to one or more embodiments of the present disclosure, the sensor may include a fingerprint recognition sensor, a proximity sensor, an iris recognition sensor, a blood pressure measurement sensor, and / or an illumination sensor, etc. In addition, the sensor may include an optical sensor that recognizes biometric information by utilizing (or using) an optical method. The circuit layer DP_CL may also include a signal line connected to the pixel driving circuit and / or the sensor driving circuit.

[0063] The element layer DP_ED may include a light emitting element included in each of the plurality of pixels and a light receiving element included in each of the plurality of sensors. As an example of the present disclosure, the light receiving element may be a photodiode. The light receiving element may be a sensor that senses light reflected by a user's fingerprint or reacts to light.

[0064] The encapsulation layer TFE seals the element layer DP_ED. The encapsulation layer TFE may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from moisture / oxygen. The inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer and / or an aluminum oxide layer, etc., but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign matter such as dust particles.

[0065] The input sensing layer ISL may be formed on the display panel DP. The input sensing layer ISL may be directly disposed on the encapsulation layer TFE. According to one or more embodiments of the present disclosure, the input sensing layer ISL may be formed on the display panel DP via the same or substantially the same process as the display panel DP. That is, when the input sensing layer ISL is directly disposed on the display panel DP, the adhesive film may not be disposed between the input sensing layer ISL and the encapsulation layer TFE. Alternatively, the adhesive film may be disposed between the input sensing layer ISL and the display panel DP. In this case, the input sensing layer ISL may not be manufactured by the same or substantially the same process as the display panel DP. For example, the input sensing layer ISL may be manufactured via a process independent of the process of the display panel DP, and may then be fixed to the upper surface of the display panel DP by an adhesive film.

[0066] The input sensing layer ISL may sense an external input (e.g., a user's touch), may change the sensed input into a given input signal, and may provide the input signal to the display panel DP. The input sensing layer ISL may include a plurality of sensing electrodes for sensing the external input. The sensing electrodes may sense the external input by utilizing (or using) a capacitive method. The display panel DP may receive an input signal from the input sensing layer ISL, and may generate an image corresponding to the input signal.

[0067] The display module DM may further include an anti-reflection layer ARL. The anti-reflection layer ARL reduces or minimizes the reflectivity of external light incident from above the window WM. As an example according to one or more embodiments of the present disclosure, the anti-reflection layer ARL may be disposed on the input sensing layer ISL. However, the present disclosure is not limited thereto. The anti-reflection layer ARL may be disposed between the display panel DP and the input sensing layer ISL. The anti-reflection layer ARL may include a plurality of color filters and a black matrix. It may be considered that from a plurality of pixels PX (e.g., referring to Figure 3 ) determines the arrangement of the color filter. Alternatively, the anti-reflection layer ARL may include a phase retarder and a polarizer. The phase retarder may be implemented as a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may also be implemented as a film type or a liquid crystal coating type. The film type polarizer may include a stretched synthetic resin film, and the liquid crystal coating type polarizer may include liquid crystals arranged in a given direction. The phase retarder and the polarizer may be implemented with one polarizing film.

[0068] The display device DD according to one or more embodiments of the present disclosure may further include an adhesive layer AL. The window WM may be attached to the anti-reflection layer ARL by the adhesive layer AL. The adhesive layer AL may include an optically transparent adhesive, an optically transparent adhesive resin, and / or a pressure sensitive adhesive (PSA).

[0069] Reference Figure 2A , the display module DM may further include a display driving circuit DIC (or a display driving chip) and a flexible circuit film FCB. According to one or more embodiments of the present disclosure, the display driving circuit DIC may be implemented in the form of a chip (e.g., an integrated chip) and may be mounted on the flexible circuit film FCB. However, the present disclosure is not limited thereto. Alternatively, the display driving circuit DIC may be disposed on the display panel DP. The display driving circuit DIC may include a data driving circuit 200 (e.g., referring to FIG. 1 ) that provides a data signal to the display panel DP. Figure 3 Alternatively, the display driving circuit DIC may further include a driving controller 100 (eg, referring to Figure 3). That is, the display driving circuit DIC may be implemented in the form of a chip (eg, an integrated chip) in which the data driving circuit 200 and the driving controller 100 are integrally formed.

[0070] The flexible circuit film FCB may be coupled to the display panel DP. The flexible circuit film FCB may be coupled to one end portion of the display panel DP so that the display driving circuit DIC is electrically connected to the display panel DP.

[0071] The display module DM may further include a touch driving circuit mounted on the flexible circuit film FCB and electrically connected to the input sensing layer ISL.

[0072] The electronic module may include a main circuit board MCB. According to one or more embodiments of the present disclosure, the main circuit board MCB may be electrically connected to the flexible circuit film FCB via a connector CNT. The main processor MCU and the power management integrated circuit PMIC (or power management chip) may be provided on the main circuit board MCB. For example, the main processor MCU and the power management integrated circuit PMIC may be electrically connected to the display drive circuit DIC via the connector CNT.

[0073] The main processor MCU can control the overall operation of the electronic device ED. The main processor MCU may include one or more of a central processing unit (CPU) and an application processor (AP). The main processor MCU may also include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP). The main processor MCU may provide an image signal and various control signals used for (or for) displaying an image to the display drive circuit DIC.

[0074] The power management integrated circuit PMIC may receive external power (e.g., battery voltage). As an example, the power management integrated circuit PMIC may generate a voltage to be supplied to the display device DD based on the external power. The power management integrated circuit PMIC may include at least one regulator. The at least one regulator may generate output voltages of various suitable voltage levels based on the external power.

[0075] Figure 2A , a structure in which the power management integrated circuit PMIC is mounted on the main circuit board MCB in the form of a chip (e.g., an integrated chip), but the present disclosure is not limited thereto. For example, the power management integrated circuit PMIC may be mounted on a flexible circuit film FCB in the form of a chip (e.g., an integrated chip), that is, may be provided as a component included in the display device DD.

[0076] The electronic module may also include one or more of various functional modules (eg, a camera module and / or a sensor module, etc.) as well as a main circuit board MCB, a main processor MCU, and / or a power management integrated circuit PMIC.

[0077] The housing EDC is coupled to the window WM. The housing EDC is coupled to the window WM to provide a suitable internal space (e.g., a given internal space). The display device DD and the electronic module can be accommodated in the internal space of the housing EDC. The housing EDC may include a material whose rigidity is relatively high. For example, the housing EDC may include glass, plastic and / or metal, and / or may include a plurality of frames and / or plates formed by a combination thereof. The housing EDC may stably protect the components of the display device DD and the electronic module accommodated in the internal space from external impacts.

[0078] In one or more embodiments, a battery module that supplies power necessary for overall operations of the display device DD may be provided between the display module DM and the housing EDC.

[0079] Figure 3 is a block diagram of a display device DD according to one or more embodiments of the present disclosure.

[0080] Reference Figure 3 , the display device DD includes a display panel DP, a driving controller 100 , a data driving circuit 200 , a scan driving circuit 300 , an emission driving circuit 350 , and a voltage generator 400 .

[0081] The driving controller 100 is driven from the main processor MCU (for example, Figure 2A ) receives the input image signal RGB and the control signal CTRL. The driving controller 100 generates the image data DATA by converting the data format of the input image signal RGB according to the specification of the interface with the data driving circuit 200. The control signal CTRL may include a vertical synchronization signal, an input data enable signal and / or a main clock signal, etc. The driving controller 100 generates a first driving control signal (e.g., a scanning control signal) SCS, a second driving control signal DCS, and a third driving control signal (e.g., an emission control signal) ECS based on the control signal CTRL.

[0082] The data driving circuit 200 receives the second driving control signal DCS and the image data DATA from the driving controller 100. The data driving circuit 200 converts the image data DATA into a data signal and outputs the data signal to a plurality of data lines DL1 to DLm to be described later. The data signal refers to an analog voltage corresponding to a gray value (e.g., gray scale value) of the image data DATA. Herein, "m" is an integer of 1 or greater.

[0083] The scan driving circuit 300 receives a first driving control signal SCS from the driving controller 100. The scan driving circuit 300 may output a scan signal to the scan line in response to the first driving control signal SCS.

[0084] The voltage generator 400 generates voltages utilized for (or used in) the operation of the display panel DP. In one or more embodiments, the voltage generator 400 generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT.

[0085] The display panel DP includes initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, the emission control lines EML1 to EMLn, the data lines DL1 to DLm, and the pixels PX may overlap with the active area AA (e.g., may be positioned in the active area AA). The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn extend in the first direction DR1. The initialization scan lines SIL1 to SILn, the compensation scan lines SCL1 to SCLn, the write scan lines SWL1 to SWLn+1, and the emission control lines EML1 to EMLn are spaced apart from each other along the second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are spaced apart from each other along the first direction DR1. Herein, "n" is an integer of 1 or more.

[0086] A plurality of pixels PX are electrically connected to initialization scan lines SIL1 to SILn, compensation scan lines SCL1 to SCLn, write scan lines SWL1 to SWLn+1, emission control lines EML1 to EMLn, and data lines DL1 to DLm. Each of the plurality of pixels PX may be electrically connected to four scan lines. For example, the pixels PX belonging to the first row may be connected to the first initialization scan line SIL1, the first compensation scan line SCL1, the first write scan line SWL1, and the second write scan line SWL2. In addition, the pixels PX belonging to the second row may be connected to the second initialization scan line SIL2, the second compensation scan line SCL2, the second write scan line SWL2, and the third write scan line SWL3. However, the number of scan lines connected to each pixel PX may be changed or modified differently, and the present disclosure is not limited thereto. In one or more other embodiments, each of the plurality of pixels PX may be electrically connected to five scan lines; in this case, the display panel DP may also include a black scan line.

[0087] The scan driving circuit 300 may be disposed in the non-active area NAA of the display panel DP. The scan driving circuit 300 receives a first driving control signal SCS from the driving controller 100. In response to the first driving control signal SCS, the scan driving circuit 300 may output an initialization scan signal to the initialization scan lines SIL1 to SILn, may output a compensation scan signal to the compensation scan lines SCL1 to SCLn, and may output a write scan signal to the write scan lines SWL1 to SWLn+1.

[0088] The emission driving circuit 350 receives the third driving control signal ECS from the driving controller 100. The emission driving circuit 350 may output the emission control signal to the emission control lines EML1 to EMLn in response to the third driving control signal ECS. In one or more embodiments, the scan driving circuit 300 may be connected to the emission control lines EML1 to EMLn. In this case, the scan driving circuit 300 may output the emission control signal to the emission control lines EML1 to EMLn, and the emission driving circuit 350 may be omitted.

[0089] Each of the plurality of pixels PX may include a light emitting element and a pixel circuit unit for controlling the emission of the light emitting element. The pixel circuit unit may include a plurality of transistors and capacitors. The scanning driving circuit 300 and the emission driving circuit 350 may include transistors formed via the same or substantially the same process as the transistors of the pixel circuit unit.

[0090] Each of the plurality of pixels PX receives a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage AINT from the voltage generator 400 .

[0091] Figure 4 is a block diagram of a data driving circuit 200 according to one or more embodiments of the present disclosure.

[0092] Reference Figure 4 The data driving circuit 200 includes a shift register 210 , a latch unit 220 , a level shifter 230 , a digital-to-analog converter unit 240 , an output buffer unit 250 , and a current control unit 260 .

[0093] The shift register 210 may start operating in response to a horizontal start signal STH and may sequentially output a data clock signal CLK. The horizontal start signal STH may be included in the slave drive controller 100 (eg, reference Figure 3 ) provides a second drive control signal DCS (for example, referring to Figure 3 ) in the signal.

[0094] The data clock signal CLK output from the shift register 210 may be provided to the latch unit 220. The latch unit 220 receives the data clock signal CLK from the driving controller 100 (eg, referring to Figure 3 ) receives the image data DATA in a serial form, and stores the image data DATA in sequence in response to the data clock signal CLK. In one or more embodiments, "k" image data DATA corresponding to the "k" channels CH1 to CHk of the data driving circuit 200, respectively, may be stored in the latch unit 220. For the convenience of description, the "k" image data DATA stored in the latch unit 220 may be referred to as "multiple latch data". In this document, "k" may be an integer of 1 or greater. The number of channels CH1 to CHk indicated as "k" may be equal to or less than the number of data lines DL1 to DLm indicated as "m" (for example, refer to Figure 3 ). For example, "k" may be equal to "m", or may be 1 / 2 of "m". However, the present disclosure is not limited thereto. Alternatively, "k" may be 1 / 3 or 1 / 4 of "m".

[0095] The latch unit 220 can output a plurality of latch data in parallel. Herein, receiving a plurality of image data in a serial form means that a plurality of image data corresponding to a plurality of pixels are received one by one in sequence, and outputting a plurality of image data in a parallel form means that a plurality of image data corresponding to a plurality of pixels are output simultaneously (e.g., concurrently or at the same time).

[0096] The level shifter 230 may receive a plurality of latch data from the latch unit 220, and may output a plurality of level-shifted data respectively by shifting the levels of the plurality of latch data. Each of the plurality of level-shifted data may be p-bit digital data. Herein, "p" may be an integer of 1 or greater.

[0097] The digital-to-analog converter unit 240 receives a plurality of level-shifted data from the level shifter 230. The digital-to-analog converter unit 240 converts the plurality of level-shifted data in digital form into data signals in analog form. The digital-to-analog converter unit 240 may receive a gamma reference voltage VGM, and may convert the plurality of level-shifted data into data signals based on the gamma reference voltage VGM. Each of the plurality of data signals may be a voltage signal whose voltage level is determined differently depending on the grayscale.

[0098] The data signal generated from the digital-to-analog converter unit 240 is provided to the output buffer unit 250. The output buffer unit 250 may be connected to the channels CH1 to CHk and may output the data signal to the channels CH1 to CHk in response to the output enable signal OE. The output enable signal OE may be included in the output of the drive controller 100 (e.g., refer to Figure 3) provides a second drive control signal DCS (for example, referring to Figure 3 ) in the signal.

[0099] The current control unit 260 may provide a current control signal CCS to the output buffer unit 250. The output buffer unit 250 may include a plurality of output buffers respectively connected to the channels CH1 to CHk. The current control unit 260 may adjust the driving strength of each of the plurality of output buffers by providing the current control signal CCS in common to the plurality of output buffers.

[0100] Figure 5 It is shown Figure 4 2 is a block diagram of the output buffer unit 250 and the current control unit 260 shown in FIG. Fig. 6A yes Figure 5 An internal block diagram of the determination circuit 261 is shown in FIG. Figure 6B It shows Fig. 6A ] The waveform diagram of the first transition period and the second transition period and the data signal Vd shown in FIG.

[0101] Reference Figure 5 , the current control unit 260 includes a determination circuit 261 and a control circuit 262. Figure 5 , a structure in which the current control unit 260 is connected to one (eg, the first channel CH1) of the plurality of channels CH1 to CHk is shown as an example. However, the present disclosure is not limited thereto. For example, some or all of the plurality of channels CH1 to CHk may be connected to the current control unit 260.

[0102] The determination circuit 261 is connected to the first channel CH1 to receive the data signal Vd, and determines the driving capability of the first output buffer AMP1 (e.g., of the output buffer unit 250) by utilizing (or using) the transition period of the data signal Vd. According to one or more embodiments of the present disclosure, the determination circuit 261 can obtain the driving capability of the first output buffer AMP1 (e.g., of the output buffer unit 250) from the driving controller 100 (e.g., referring to Figure 3) receives an enable signal EN or a disable signal DN. The determination circuit 261 may be activated in response to the enable signal EN, or may be deactivated in response to the disable signal DN. The enable signal EN and the disable signal DN may be signals that are activated or deactivated by the selection of a user or an operator. For example, when the operator selects an option for activating the determination circuit 261 for the purpose of the initial setting of the current control signal CCS to be supplied to the output buffer unit 250, the determination circuit 261 may be activated in response to the enable signal EN. Thereafter, after the initial setting is completed, when the operator cancels the selection of the option, the determination circuit 261 may be deactivated in response to the disable signal DN. Even if the determination circuit 261 is in the deactivated state, the current control signal CCS of the initial setting state may continue to be provided to the output buffer unit 250. This may mean that the output buffer unit 250 continues to operate with a driving strength corresponding to the current control signal CCS of the initial setting state.

[0103] Alternatively, the enable signal EN may be activated every preset cycle (that is, periodically). In this case, the determination circuit 261 may periodically determine the driving capability of the output buffer unit 250 .

[0104] The control circuit 262 may output a current control signal CCS for adjusting the driving strength of the first output buffer AMP1 to the first output buffer AMP1 (e.g., of the output buffer unit 250) according to the determination result. Even if the current control unit 260 is connected to the first channel CH1 and determines the driving capability of the first output buffer AMP1 based on the data signal Vd (i.e., determines the driving capability of only one output buffer), the current control signal CCS may be commonly supplied to the remaining output buffers as well as the first output buffer AMP1.

[0105] Reference Fig. 6A and Figure 6B The determination circuit 261 may include a counting circuit TPC, a first comparator Comp1, and a second comparator Comp2. The counting circuit TPC may count the transition period of the data signal Vd, and may convert the counting result (ie, the count value CV (eg, reference Figure 5 )) is output to the control circuit 262.

[0106] According to one or more embodiments of the present disclosure, the transition period may include a rising transition period TP1 and a falling transition period TP2. The rising transition period TP1 may be set to a time period from a first threshold point P1 at which the data signal Vd reaches a low threshold voltage VL to a second threshold point P2 at which the data signal Vd reaches a high threshold voltage VH. The falling transition period TP2 may be set to a time period from a third threshold point P3 at which the data signal Vd reaches a high threshold voltage VH to a fourth threshold point P4 at which the data signal Vd reaches a low threshold voltage VL. The low threshold voltage VL may be lower than the high threshold voltage VH. According to one or more embodiments of the present disclosure, the low threshold voltage VL may be higher than the minimum voltage Vmin that the data signal Vd can have, and the high threshold voltage VH may be lower than the maximum voltage Vmax that the data signal Vd can have. However, the present disclosure may not be limited thereto. For example, the low threshold voltage VL may be the same as the minimum voltage Vmin of the data signal Vd, and the high threshold voltage VH may be the same as the maximum voltage Vmax of the data signal Vd.

[0107] The first comparator Comp1 compares the data signal Vd and the high threshold voltage VH to output a first comparison result CR1, and the second comparator Comp2 compares the data signal Vd and the low threshold voltage VL to output a second comparison result CR2. For example, when the data signal Vd is lower than the high threshold voltage VH, the first comparison result CR1 may have a logic "1" state; when the data signal Vd is higher than the high threshold voltage VH, the first comparison result CR1 may have a logic "0" state. When the data signal Vd is higher than the low threshold voltage VL, the second comparison result CR2 may have a logic "1" state; when the data signal Vd is lower than the low threshold voltage VL, the second comparison result CR2 may have a logic "0" state.

[0108] When all (or both) of the first comparison result CR1 and the second comparison result CR2 are in a state of logic "1", the counting operation of the counting circuit TPC can be activated. The counting circuit TPC can start the counting operation at the first threshold point P1 where the data signal Vd reaches the low threshold voltage VL, and can terminate the counting operation at the second threshold point P2 where the data signal Vd reaches the high threshold voltage VH. That is, in the rising transition period TP1, the first threshold point P1 can be the counting starting point, and the second threshold point P2 can be the counting ending point. In addition, the counting circuit TPC can start the counting operation again at the third threshold point P3 where the data signal Vd reaches the high threshold voltage VH, and can terminate the counting operation at the fourth threshold point P4 where the data signal Vd reaches the low threshold voltage VL. That is, in the falling transition period TP2, the third threshold point P3 can be the counting starting point, and the fourth threshold point P4 can be the counting ending point.

[0109] When the counting circuit TPC performs the counting operation in the rising transition period TP1 and the falling transition period TP2, the count value CV (for example, referring to Figure 5 ) may include a first count value CV1 and a second count value CV2. Herein, the first count value CV1 corresponds to a result of counting the duration of the rising transition period TP1, and the second count value CV2 corresponds to a result of counting the duration of the falling transition period TP2.

[0110] In the described embodiment, the first count value CV1 and the second count value CV2 may be provided to the control circuit 262, and the control circuit 262 may generate a current control signal CCS based on the first count value CV1 and the second count value CV2. In detail, the control circuit 262 may compare the first count value CV1 and the second count value CV2 with a threshold range (e.g., a preset threshold range), and may adjust the current control signal CCS according to the comparison result. When all (or both) of the first count value CV1 and the second count value CV2 exist within (or are in) the threshold range, the control circuit 262 may output a current control signal CCS having a reference value (e.g., a preset reference value). According to one or more embodiments, when at least one of the first count value CV1 and the second count value CV2 (i.e., at least one of the first count value CV1 and the second count value CV2) is outside (or outside) the threshold range, the control circuit 262 may output a current control signal CCS having a compensation value different from the reference value. For example, when at least one of the first count value CV1 and the second count value CV2 is higher than a threshold range (ie, when the first count value CV1 and / or the second count value CV2 is higher than the threshold range), the compensation value may be greater than the reference value.

[0111] According to one or more embodiments, the existence of the first count value CV1 and the second count value CV2 within (or in) the threshold range means that the duration of each of the rising transition period TP1 and the falling transition period TP2 exists within (or in) a threshold time range (e.g., a preset threshold time range). That is, as the duration of each of the rising transition period TP1 and the falling transition period TP2 becomes shorter, the first output buffer AMP1 can change the data signal Vd to a desired level in a shorter time, which is considered to be that the first output buffer AMP1 has a higher driving capability. Because the first output buffer AMP1 has a higher driving capability, it may not be necessary to adjust the current control signal CCS for the purpose of compensating for the driving capability of the first output buffer AMP1; in this case, the current control signal CCS may be maintained at the reference value.

[0112] According to one or more embodiments, at least one of the first count value CV1 and the second count value CV2 (i.e., at least one of the first count value CV1 and the second count value CV2) being outside (or outside) the threshold range means that the duration of at least one of the rising transition period TP1 and the falling transition period TP2 is outside (or outside) the threshold time range (e.g., a preset threshold time range). That is, as the duration of at least one of the rising transition period TP1 and the falling transition period TP2 becomes longer, the time taken by the first output buffer AMP1 to change the data signal Vd to a desired level may increase, which is regarded as the first output buffer AMP1 having a lower driving capability. Because the first output buffer AMP1 has a lower driving capability, it may be necessary to adjust the current control signal CCS for the purpose of compensating for the driving capability of the first output buffer AMP1; in this case, the current control signal CCS may have a compensation value higher than the reference value.

[0113] The data driving circuit 200 (for example, see Figure 5 ) may also include a lookup table in which the compensation value of the current control signal CCS is stored for each size of the count value CV. Therefore, when at least one of the first count value CV1 and the second count value CV2 (i.e., at least one of the first count value CV1 and the second count value CV2) is outside (or outside) the threshold range, the control circuit 262 may refer to the lookup table to obtain a compensation value corresponding to the count value outside (or outside) the threshold range, and may adjust the current control signal CCS to have the obtained compensation value.

[0114] When the first output buffer AMP1 receives the current control signal CCS having the compensation value, the driving capability of the first output buffer AMP1 can be compensated, and therefore, the duration of each of the rising transition period TP1 and the falling transition period TP2 can be adjusted to belong to the threshold time range. Because the first output buffer AMP1 and the remaining output buffers receive the current control signal CCS having the compensation value, the driving capabilities of the remaining output buffers can be compensated together. Therefore, the rising transition period TP1 and the falling transition period TP2 of each of the plurality of data signals output to the channels CH1 to CHk can have a duration within the threshold time range (or exist within the threshold time range).

[0115] As described above, since the current control unit 260 is connected to some or all of the channels CH1 to CHk of the data driving circuit 200, the current control unit 260 can directly measure the driving capability of the data driving circuit 200. In addition, since the driving capability of the data driving circuit 200 is compensated based on the measurement result, the data driving circuit 200 can drive the channels CH1 to CHk (or data signals / lines) with the optimal (or improved) driving strength (for example, the driving strength of the data driving circuit 200 can be optimized (or improved)). In addition, when the data driving circuit 200 operates with the optimal or improved driving strength, unnecessary power consumption can be prevented. This can mean that power consumption is optimized or reduced.

[0116] exist Fig. 6A and Figure 6B 2 shows a case where the determination circuit 261 outputs the first count value CV1 and the second count value CV2 corresponding to the rising transition period TP1 and the falling transition period TP2, respectively, but the present disclosure is not limited thereto. For example, the determination circuit 261 may only output the count value corresponding to the rising transition period TP1 or the falling transition period TP2.

[0117] Figure 7 is a waveform diagram showing a data signal Vd and a transition period according to one or more embodiments of the present disclosure.

[0118] Reference Figure 5-7 , only when the first comparison result CR1 and the second comparison result CR2 are all (or both) in the state of logic "1" and the first comparison result CR1 changes from logic "0" to logic "1" (i.e., only in the rising transition period TP1), the counting operation of the counting circuit TPC can be activated. That is, even if the first comparison result CR1 and the second comparison result CR2 are all (or both) in the state of logic "1", when the first comparison result CR1 changes from logic "1" to logic "0" (i.e., in the falling transition period TP2), the counting operation of the counting circuit TPC may not be activated.

[0119] The counting circuit TPC may start the counting operation at the first threshold point P1 where the data signal Vd reaches the low threshold voltage VL, and may terminate the counting operation at the second threshold point P2 where the data signal Vd reaches the high threshold voltage VH. That is, in the rising transition period TP1, the first threshold point P1 may be the counting start point, and the second threshold point P2 may be the counting end point. In addition, in the falling transition period TP2, the counting operation of the counting circuit TPC may not be activated.

[0120] When the counting circuit TPC performs the counting operation only in the rising transition period TP1, the counting circuit TPC may output only one count value CV. Herein, the count value CV corresponds to the result of counting the duration of the rising transition period TP1.

[0121] In the described embodiments, the count value CV may be provided to the control circuit 262, and the control circuit 262 may generate a current control signal CCS based on the count value CV. For example, the control circuit 262 may compare the count value CV with a threshold range (e.g., a preset threshold range), and may adjust the current control signal CCS based on the comparison result. When the count value CV exists within (or is in) the threshold range, the control circuit 262 may output a current control signal CCS having a reference value (e.g., a preset reference value). According to one or more embodiments, when the count value CV is outside (or outside) the threshold range, the control circuit 262 may output a current control signal CCS having a compensation value different from the reference value.

[0122] Figure 8 is a block diagram illustrating an output buffer unit 250 , a switch circuit 270 , and a current control unit 260 according to one or more embodiments of the present disclosure.

[0123] Reference Figure 8 The data driving circuit 201 may further include a switch circuit 270 between the output buffer unit 250 and the current control unit 260 .

[0124] The switch circuit 270 may be provided between the first channel CH1 and the determination circuit 261 . Figure 8 2 shows a structure in which the first channel CH1 is connected to the switch circuit 270 as an example. However, the present disclosure is not limited thereto. For example, some or all of the plurality of channels CH1 to CHk may be connected to the switch circuit 270.

[0125] As an example according to one or more embodiments of the present disclosure, the switch circuit 270 may include a switch element ST connected to the first channel CH1. The switch element ST may be turned on or off in response to a switch signal SS. The switch signal SS may be a signal from the drive controller 100 (e.g., referring to Figure 3) provided by the output buffer unit 250. The switch signal SS may be a signal activated or deactivated by the selection of a user or an operator. For example, when the operator selects an option for activating the determination circuit 261 for the purpose of the initial setting of the current control signal CCS to be supplied to the output buffer unit 250, the switch element ST may be turned on in response to the switch signal SS. In this case, the determination circuit 261 may be connected to the first channel CH1 via the switch element ST. Therefore, the determination circuit 261 may be electrically connected to the first channel CH1 to receive the data signal Vd, and the driving capability of the first output buffer AMP1 may be determined by utilizing (or using) the transition period of the data signal Vd. Thereafter, after the initial setting is completed, when the operator cancels the selection option, the switch element ST may be turned off in response to the switch signal SS. In this case, the determination circuit 261 is not electrically connected to the first channel CH1 by the switch element ST. Therefore, after the initial setting is completed, the determination circuit 261 may not act as a load of the first channel CH1. Therefore, even if the determination circuit 261 is added, the load of the first channel CH1 can be prevented from increasing.

[0126] Alternatively, the switch signal SS may be activated every preset period (that is, periodically). In this case, the determination circuit 261 may periodically determine the driving capability of the output buffer unit 250 .

[0127] Fig. 9 is a block diagram illustrating an output buffer unit 250 and a current control unit 260 a according to one or more embodiments of the present disclosure.

[0128] Reference Fig. 9 The data driving circuit 200a includes a current control unit 260a connected to some of the channels CH1 to CHc-1, CHc to CHk-1, and CHk. The current control unit 260a includes a first determination circuit 261a, a second determination circuit 261b, a third determination circuit 261c, and a control circuit 262a. Fig. 9 , a structure in which the current control unit 260a is connected to three channels (i.e., the first channel CH1, the second channel CHc, and the third channel CHk) among the channels CH1 to CHc-1, CHc to CHk-1, and CHk is shown. However, the present disclosure is not limited thereto. For example, the current control unit 260a may be connected to all channels CH1 to CHc-1, CHc to CHk-1, and CHk, or may be connected only to one or more other suitable channels.

[0129] Herein, the first channel CH1 and the third channel CHk may be the outermost channels among the channels CH1 to CHc-1, CHc to CHk-1, and CHk, and the second channel CHc may be a channel disposed at the center of the channels CH1 to CHc-1, CHc to CHk-1, and CHk. The output buffer unit 250 may include a plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk connected to the channels CH1 to CHc-1, CHc to CHk-1, and CHk, respectively. For convenience of description, the output buffer connected to the first channel CH1 may be referred to as a "first output buffer AMP1", the output buffer connected to the second channel CHc may be referred to as a "second output buffer AMPc", and the output buffer connected to the third channel CHk may be referred to as a "third output buffer AMPk".

[0130] The first determination circuit 261a is connected to the first channel CH1 to receive the first data signal Vd1, and determines the driving capability of the first output buffer AMP1 by utilizing (or using) the transition period of the first data signal Vd1. The second determination circuit 261b is connected to the second channel CHc to receive the second data signal Vdc, and determines the driving capability of the second output buffer AMPc by utilizing (or using) the transition period of the second data signal Vdc. The third determination circuit 261c is connected to the third channel CHk to receive the third data signal Vdk, and determines the driving capability of the third output buffer AMPk by utilizing (or using) the transition period of the third data signal Vdk.

[0131] According to one or more embodiments, the first determination circuit 261a performs a counting operation during the transition period of the first data signal Vd1. That is, the first determination circuit 261a counts the duration of the transition period of the first data signal Vd1, and outputs the counting result as a first count value CVa (or referred to as a "first result value"). According to one or more embodiments, the second determination circuit 261b performs a counting operation during the transition period of the second data signal Vdc. That is, the second determination circuit 261b counts the duration of the transition period of the second data signal Vdc, and outputs the counting result as a second count value CVb (or referred to as a "second result value"). According to one or more embodiments, the third determination circuit 261c performs a counting operation during the transition period of the third data signal Vdk. That is, the third determination circuit 261c counts the duration of the transition period of the third data signal Vdk, and outputs the counting result as a third count value CVc (or referred to as a "third result value").

[0132] Each of the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c may be determined from the driving controller 100 (eg, referring to Figure 3 ) receives an enable signal EN or a disable signal DN. Each of the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c may be activated in response to the enable signal EN, or may be deactivated in response to the disable signal DN. The enable signal EN and the disable signal DN may be signals activated or deactivated by a selection of a user or an operator.

[0133] Each of the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c may be similar in structure to Fig. 6A The determination circuit 261 shown in FIG. 261A , and therefore, additional description associated with the first determination circuit 261 a , the second determination circuit 261 b , and the third determination circuit 261 c may be omitted to avoid redundancy.

[0134] The control circuit 262a receives the first count value CVa, the second count value CVb, and the third count value CVc from the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c, respectively. The control circuit 262a outputs a current control signal CCS for adjusting the driving capability of the plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk based on the first count value CVa, the second count value CVb, and the third count value CVc. The control circuit 262a may be commonly connected to the plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk, and may commonly supply the current control signal CCS to the plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk.

[0135] The control circuit 262a may compare each of the first count value CVa, the second count value CVb, and the third count value CVc with a threshold range (e.g., a preset threshold range), and may adjust the current control signal CCS according to the comparison result. For example, when the first count value CVa, the second count value CVb, and the third count value CVc are all within (or in) the threshold range, the control circuit 262a may output a current control signal CCS having a reference value (e.g., a preset reference value). According to one or more embodiments, when at least one of the first count value CVa, the second count value CVb, and the third count value CVc (i.e., at least one of the first count value CVa, the second count value CVb, and the third count value CVc) is outside (or outside) the threshold range, the control circuit 262a may output a current control signal CCS having a compensation value different from the reference value.

[0136] When the plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk receive the current control signal CCS having the compensation value, driving capabilities of the plurality of output buffers AMP1 to AMPc-1, AMPc to AMPk-1, and AMPk may be compensated.

[0137] As described above, when the current control unit 260a is connected to some channels CH1, CHc and CHk among the channels CH1 to CHc-1, CHc to CHk-1 and CHk of the data driving circuit 200a, the current control unit 260a can directly measure the driving capability of the data driving circuit 200a. In addition, since the driving capability of the data driving circuit 200a is compensated based on the measurement result, the driving strength of the data driving circuit 200a can be optimized or improved. In addition, when the data driving circuit 200a operates with the optimal or improved driving strength, unnecessary power consumption can be prevented. This can mean that power consumption is optimized or reduced.

[0138] Fig.10 is a block diagram illustrating an output buffer unit 250 , a switch circuit 270 a , and a current control unit 260 a according to one or more embodiments of the present disclosure.

[0139] Reference Fig.10 , the data driving circuit 200 b may further include a switch circuit 270 a between the output buffer unit 250 and the current control unit 260 a .

[0140] The switch circuit 270a may include a first switch circuit 271 connected between the first channel CH1 and the first determination circuit 261a, a second switch circuit 272 connected between the second channel CHc and the second determination circuit 261b, and a third switch circuit 273 connected between the third channel CHk and the third determination circuit 261c. Fig.10 270a. A structure in which the first switch circuit 271, the second switch circuit 272, and the third switch circuit 273 are connected to the first channel CH1, the second channel CHc, and the third channel CHk, respectively, is shown as an example. However, the present disclosure is not limited thereto. For example, all of the channels CH1 to CHk may be connected to the switch circuit 270a.

[0141] As an example of the present disclosure, the first switch circuit 271 may include a first switch element ST1 connected to the first channel CH1. The first switch element ST1 may be turned on or off in response to a first switch signal SS1. The second switch circuit 272 may include a second switch element ST2 connected to the second channel CHc. The second switch element ST2 may be turned on or off in response to the second switch signal SS2. The third switch circuit 273 may include a third switch element ST3 connected to the third channel CHk. The third switch element ST3 may be turned on or off in response to a third switch signal SS3. The first switch signal SS1, the second switch signal SS2, and the third switch signal SS3 may be from the drive controller 100 (e.g., refer to Figure 3 ) provided by the first switching signal SS1, the second switching signal SS2, and the third switching signal SS3 may be signals activated or deactivated by the selection of a user or an operator. Alternatively, the first switching signal SS1, the second switching signal SS2, and the third switching signal SS3 may be activated at each preset cycle (that is, periodically). In this case, the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c may periodically determine the driving capability of the output buffer unit 250.

[0142] When the first switch circuit 271, the second switch circuit 272, and the third switch circuit 273 are connected to the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c, respectively, the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c may not act as a load on the first channel CH1, the second channel CHc, and the third channel CHk. Therefore, even if the first determination circuit 261a, the second determination circuit 261b, and the third determination circuit 261c are added, the load on the first channel CH1, the second channel CHc, and the third channel CHk can be prevented from increasing.

[0143] According to one or more embodiments of the present disclosure, the driving capability of the data driving circuit can be directly measured by connecting some or all of the channels of the data driving circuit to the current control unit. In addition, by compensating the driving capability of the data driving circuit based on the measurement result, the driving strength of the data driving circuit can be optimized or improved.

[0144] Furthermore, when the data driving circuit operates with an optimal or improved driving strength, unnecessary power consumption can be prevented. This can mean that power consumption is optimized or reduced.

[0145] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims and their equivalents.

Claims

1. A display device, wherein: The display device comprises: a display panel configured to display an image by utilizing a data signal; a data driving circuit configured to supply the data signal to the display panel via a channel; and a driving controller configured to control the data driving circuit, Wherein, the data driving circuit comprises: an output buffer configured to output the data signal to the channel; a determination circuit connected to the channel, and the determination circuit is configured to receive the data signal and determine the driving capability of the output buffer by utilizing a transition cycle of the data signal; and The control circuit is configured to output a current control signal for adjusting the driving strength of the output buffer to the output buffer according to a determination result of the determination circuit.

2. The display device according to claim 1, wherein: The determining circuit comprises: The counting circuit is configured to count the transition cycles to output a count value.

3. The display device according to claim 2, wherein: The transformation cycle includes: a rising transition period, which is set as a time period from a first threshold point where the data signal reaches a low threshold voltage to a second threshold point where the data signal reaches a high threshold voltage; and The falling transition period is set as a time period from when the data signal reaches the third threshold point of the high threshold voltage to when the data signal reaches the fourth threshold point of the low threshold voltage.

4. The display device according to claim 3, wherein: The determining circuit further comprises: a first comparator configured to compare the data signal and the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal with the low threshold voltage to output a second comparison result, and The counting circuit is configured to determine a counting start point and a counting end point by using the first comparison result and the second comparison result.

5. The display device according to claim 3, wherein: The counting circuit is configured as follows: outputting a first count value by counting the duration of the rising transition period; and A second count value is output by counting the duration of the falling transition period.

6. The display device according to claim 5, wherein: The control circuit is configured as follows: comparing the first count value and the second count value to a threshold range; When both the first count value and the second count value are within the threshold range, outputting the current control signal having a reference value; and When at least one of the first count value and the second count value is outside the threshold range, the current control signal having a compensation value different from the reference value is output.

7. The display device according to claim 2, wherein: The transition period is set to a time period from a first threshold point where the data signal reaches a low threshold voltage to a second threshold point where the data signal reaches a high threshold voltage, and Wherein, the counting circuit is configured as follows: The count value is output by counting the duration of the transition period.

8. The display device according to claim 7, wherein: The determining circuit further comprises: a first comparator configured to compare the data signal and the high threshold voltage to output a first comparison result; and a second comparator configured to compare the data signal with the low threshold voltage to output a second comparison result, and The counting circuit is configured to determine a counting start point and a counting end point by using the first comparison result and the second comparison result.

9. The display device according to claim 7, wherein: The control circuit is configured as follows: comparing the count value to a threshold range; When the count value is within the threshold range, outputting the current control signal having a reference value; and When the count value is outside the threshold range, the current control signal having a compensation value different from the reference value is output.

10. The display device according to claim 1, wherein: The determination circuit is configured to receive an enable signal or a disable signal from the drive controller to be activated in response to the enable signal, or to be deactivated in response to the disable signal.

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