Display panel and its driving method, display device

Abstract

This invention provides a display panel and its driving method and display device, relating to the field of display technology, and is used to prevent screen flickering when the display panel experiences an abnormal power outage. In the display panel, the light-emitting control unit includes an output module, which, in response to a signal from a first node, is electrically connected to a first-level signal terminal and the output terminal of the output module; and, in response to a signal from a second node, is electrically connected to a second-level signal terminal and the output terminal of the output module; a first control module, in response to a signal from a first control signal terminal, is electrically connected to a second-level signal terminal and the first node; the light-emitting control circuit further includes a second control module, which, in response to a signal from the second control signal terminal, is electrically connected to a first adjustment signal terminal and the first control signal terminal; when the display panel is operating, both the first control signal terminal and the second control signal terminal provide an inactive level; the potential of the first adjustment signal terminal is lower than the potential of the signal from the first control signal terminal.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and its driving method, and a display device. Background Technology

[0002] With the continuous development of display technology, consumers' demands for displays are constantly increasing. Currently, various types of displays, including organic light-emitting diode (OLED) displays, are emerging in large numbers and have developed rapidly. Based on this, display technologies such as 3D display, touch display technology, curved display, and ultra-high resolution display are also constantly emerging.

[0003] Currently, the display panel exhibits screen flickering when there is an abnormal power outage. Summary of the Invention

[0004] In view of this, this application provides a display panel and its driving method and display device to improve the screen flickering problem of the display panel when there is an abnormal power failure.

[0005] In a first aspect, embodiments of the present invention provide a display panel, including a light-emitting control circuit, the light-emitting control circuit including a plurality of cascaded light-emitting control units, the light-emitting control units including:

[0006] The output module, in response to the signal of the first node, is electrically connected to the first level signal terminal and the output terminal of the output module; and, in response to the signal of the second node, is electrically connected to the second level signal terminal and the output terminal of the output module.

[0007] The first control module, in response to the signal at the first control signal terminal, is electrically connected to the second level signal terminal and the first node;

[0008] The light-emitting control circuit also includes a second control module, which responds to a second control signal and is electrically connected to a first level signal terminal and a first control signal terminal;

[0009] When the display panel is working, both the first control signal terminal and the second control signal terminal provide an inactive level, and the potential of the signal at the first adjustment signal terminal is less than the potential of the signal at the first control signal terminal.

[0010] Secondly, embodiments of the present invention provide a driving method for the above-mentioned display panel, the driving method comprising:

[0011] When the display panel is working, a non-enable level is provided to both the first control signal terminal and the second control signal terminal, and the potential of the first adjustment signal terminal is controlled to be less than the potential of the signal of the first control signal terminal.

[0012] Thirdly, embodiments of the present invention provide a display device including the display panel described above.

[0013] Using the solution provided in this embodiment of the invention, when the display panel experiences an abnormal power outage, such as a sudden power cut, the potential of the signal on the second control signal terminal drops rapidly, controlling the second control module to conduct. Since the potential of the first adjustment signal terminal at the instant of the abnormal power outage is the same as the potential of the display panel during normal operation—that is, at the instant of the abnormal power outage, the potential of the first adjustment signal terminal is lower than the potential of the signal on the first control signal terminal—the charge on the first control signal terminal can flow to the first adjustment signal terminal through the conducting second control module, thereby forming a charge discharge path. In other words, the signal on the first adjustment signal terminal can be quickly written to the first control signal terminal through the conducting second control module, causing the voltage of the first control signal terminal to decrease.

[0014] Under the control of the signal at the first control signal terminal, the first control module is turned on, thereby quickly providing the voltage provided by the second level signal terminal to the first node, so as to avoid the voltage provided by the first level signal terminal being output to the output terminal of the light-emitting control unit, thereby avoiding the light-emitting control module of the pixel driving circuit from being turned on, thereby avoiding the light-emitting element from lighting up, and avoiding display abnormalities such as screen flickering on the display panel. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention;

[0017] Figure 2 A circuit diagram of a sub-pixel provided in an embodiment of the present invention;

[0018] Figure 3 A schematic diagram of a light-emitting control circuit provided in an embodiment of the present invention;

[0019] Figure 4 A circuit diagram of a light-emitting control unit provided in an embodiment of the present invention;

[0020] Figure 5 A timing diagram of the operation of a light-emitting control unit provided in an embodiment of the present invention;

[0021] Figure 6 This is a schematic diagram illustrating the positional relationship between a light-emitting control unit, a second control module, and a chip bonding area, provided in an embodiment of the present invention.

[0022] Figure 7A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0023] Figure 8 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0024] Figure 9 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0025] Figure 10 A schematic diagram of another display panel provided in an embodiment of the present invention;

[0026] Figure 11 A schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention;

[0027] Figure 12 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0028] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0030] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0032] This invention provides a display panel, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. The display panel includes a plurality of sub-pixels 1 and a light-emitting control circuit 2. The light-emitting control circuit 2 is capable of generating light-emitting control signals for controlling the sub-pixels 1 to light up or turn off. Figure 1As shown, sub-pixel 1 is located in the display area AA of the display panel, and the light-emitting control circuit 2 is located in the non-display area NA of the display panel.

[0033] Combination Figure 2 As shown, Figure 2 This is a circuit diagram of a sub-pixel provided in an embodiment of the present invention. The sub-pixel 1 includes a pixel driving circuit 11 and a light-emitting element 12 electrically connected. The pixel driving circuit 11 receives a data voltage Data, a first power supply voltage PVDD, and a second power supply voltage PVEE, and generates a driving current. When the light-emitting control signal E is at an enabled level, the driving current flows through the light-emitting element 12 to illuminate the light-emitting element 12. When the light-emitting control signal E is at a disabled level, the driving current cannot flow through the light-emitting element 12, thereby controlling the light-emitting element 12 to turn off. Exemplarily, the light-emitting element 12 includes any one of an organic light-emitting diode (OLED), a micro light-emitting diode (Micro-LED), and a quantum light-emitting diode (QLED), and the present invention does not limit this.

[0034] Optional, such as Figure 2 As shown, the pixel driving circuit 11 includes a storage capacitor Cst, a driving transistor M11, a first reset module 111, a data writing module 112, a threshold compensation module 113, a light emission control module 114, and a second reset module 115.

[0035] The storage capacitor Cst has two plates electrically connected to the first power supply voltage terminal PVDD and the gate of the driving transistor M11, respectively. The first reset module 111, in response to the first scan signal, resets the potential of the gate of the driving transistor M11 during the reset period. The data writing module 112, in response to the second scan signal, writes a data voltage to the first electrode of the driving transistor M11 during the data writing and threshold compensation period. The threshold compensation module 113 compensates for the threshold voltage of the driving transistor M11 during the data writing and threshold compensation period. The second reset module 115, in response to the first scan signal, resets the electrodes of the light-emitting element 12 during the reset period. The light-emitting control module 114, in response to the aforementioned light-emitting control signal, controls the light-emitting element 12 to light up during the light-emitting period; and controls the light-emitting element 12 to turn off during the reset period and the data writing and threshold compensation period.

[0036] Optional, such as Figure 2As shown, the first reset module 111 includes a first reset transistor M12, whose gate is electrically connected to the first scan signal terminal S1, and whose first and second terminals are electrically connected to the reset signal terminal Vref and the gate of the driving transistor M11, respectively. The data writing module 112 includes a data writing transistor M13, whose gate is electrically connected to the second scan signal terminal S2, and whose first and second terminals are electrically connected to the data signal terminal Data and the first terminal of the driving transistor M11, respectively. The threshold compensation module 113 includes a threshold compensation transistor M14, whose gate is electrically connected to the second scan signal terminal S2, whose first terminal is electrically connected to the second terminal of the driving transistor M11, and whose second terminal is electrically connected to the gate of the driving transistor M11. The light emission control module 114 includes a first light emission control transistor M15 and a second light emission control transistor M16, both of whose gates are electrically connected to the light emission control signal terminal E. The first terminal of the first light emission control transistor M15 is electrically connected to the first power supply voltage terminal PVDD, and its second terminal is electrically connected to the first terminal of the driving transistor M11. The first terminal of the second light emission control transistor M16 is electrically connected to the second terminal of the driving transistor M11, and its second terminal is electrically connected to the first electrode of the light-emitting element 12. The second reset module 115 includes a second reset transistor M17, whose gate is electrically connected to the first scan signal terminal S1, its first electrode is electrically connected to the reset signal terminal Vref, and its second electrode is electrically connected to the first electrode of the light-emitting element 12. The second electrode of the light-emitting element 12 is electrically connected to the second power supply voltage terminal PVEE.

[0037] For example, such as Figure 1 As shown, the display panel also includes multiple light-emitting control lines EL, which are electrically connected to the light-emitting control circuit 2 and the sub-pixel 1, so as to provide the light-emitting control signal generated by the light-emitting control circuit 2 to the light-emitting control signal terminal E of the sub-pixel 1.

[0038] It should be noted that, Figure 2 The pixel driving circuit 11 shown is only an illustration. The structure of the pixel driving circuit 11 can be adjusted according to different display requirements. For example, the pixel driving circuit 11 can be configured to include other numbers of transistors. The present invention does not limit this.

[0039] In addition, the display panel also includes a scan control circuit for providing the aforementioned first and second scan signals, as well as scan lines electrically connecting the scan control circuit and sub-pixels. For clarity and simplicity, the following are not shown in the diagram: Figure 1 The diagram omits other structures besides the light emission control circuit 2, the light emission control signal line EL, and the sub-pixel 1, such as the scan control circuit and the scan line.

[0040] Optional, such as Figure 3 As shown, Figure 3This is a schematic diagram of a light-emitting control circuit provided in an embodiment of the present invention. The light-emitting control circuit 2 includes multiple cascaded light-emitting control units 21.

[0041] Combination Figure 4 As shown, Figure 4 This is a circuit diagram of a light-emitting control unit provided in an embodiment of the present invention. The light-emitting control unit 21 includes an output module 211 and a first control module 212. The output module 211 is electrically connected to the output terminal OUT of the light-emitting control unit 21.

[0042] like Figure 4 As shown, the output module 211 includes a first output transistor M21 and a second output transistor M22. The gate of the first output transistor M21 is electrically connected to the first node N1, its first electrode is electrically connected to the first level signal terminal VGL, and its second electrode is electrically connected to the output terminal OUT. The gate of the second output transistor M22 is electrically connected to the second node N2, its first electrode is electrically connected to the second level signal terminal VGH, and its second electrode is electrically connected to the output terminal OUT.

[0043] Wherein, the potential of the signal provided by the first level signal terminal VGL is lower than the potential of the signal provided by the second level signal terminal VGH. For example, the signal provided by the first level signal terminal VGL can control... Figure 3 The light-emitting control module 114 in the pixel driving circuit 11 shown is turned on. The signal provided by the second-level signal terminal VGH can control... Figure 3 The light emission control module 114 in the pixel driving circuit 11 shown is turned off.

[0044] like Figure 4 As shown, the first control module 212 responds to the signal of the first control signal terminal RST1 and electrically connects the second level signal terminal VGH and the first node N1.

[0045] like Figure 3 As shown, the light-emitting control circuit 2 also includes a second control module 22. The second control module 22 responds to the signal of the second control signal terminal RST2 and is electrically connected to the first adjustment signal terminal V1 and the first control signal terminal RST1 of the multi-level light-emitting control unit 21.

[0046] When the display panel is operating normally, both the first control signal terminal RST1 and the second control signal terminal RST2 provide a disabled level. In this embodiment of the invention, the disabled level of the first control signal terminal RST1 refers to the level that enables the first control module 212 to be turned off. The disabled level of the second control signal terminal RST2 refers to the level that enables the second control module 22 to be turned off. The first adjustment signal terminal V1 receives a DC voltage; exemplarily, the potential of the first adjustment signal terminal V1 is lower than the potential of the signal at the first control signal terminal RST1.

[0047] For example, the de-enable level of the first control signal terminal RST1 and the de-enable level of the second control signal terminal RST2 can be equal to the voltage of the signal provided by the second level signal terminal VGH.

[0048] Using the solution provided in this embodiment of the invention, when the display panel experiences an abnormal power outage, such as a sudden power cut, the potential of the signal on the second control signal terminal RST2 drops rapidly, controlling the second control module 22 to conduct. Since the potential of the first adjustment signal terminal V1 at the instant of the abnormal power outage is the same as the potential of the display panel during normal operation, that is, at the instant of the abnormal power outage, the potential of the first adjustment signal terminal V1 is lower than the potential of the signal on the first control signal terminal RST1. Therefore, the charge on the first control signal terminal RST1 can flow to the first adjustment signal terminal V1 through the conducting second control module 22, thereby forming a charge discharge path. In other words, the signal of the first adjustment signal terminal V1 can be quickly written to the first control signal terminal RST1 through the conducting second control module 22, causing the voltage of the first control signal terminal RST1 to drop rapidly.

[0049] Combination Figure 4 As shown, under the control of the signal at the first control signal terminal RST1, the first control module 212 is turned on, thereby quickly providing the voltage provided by the second level signal terminal VGH to the first node N1, so as to control the first output transistor M21 to be quickly turned off, preventing the voltage provided by the first level signal terminal VGL from being output to the output terminal OUT of the light-emitting control unit 21, thereby preventing... Figure 2 The light-emitting control module 114 of the pixel driving circuit 11 shown is turned on, thereby preventing the light-emitting element 12 from lighting up and avoiding display abnormalities such as screen flickering on the display panel.

[0050] Optional, such as Figure 4 As shown, the light-emitting control unit 21 also includes a first processing module 213 and a second processing module 214. The first processing module 213 is electrically connected to the input terminal IN and the second clock signal terminal XCK, providing signals to the first node N1. The second processing module 214 is electrically connected to the first clock signal terminal CK, the second level signal terminal VGH, the first level signal terminal VGL, and the second clock signal terminal XCK, providing signals to the second node N2.

[0051] Combination Figure 5 As shown, Figure 5 The present invention provides a timing diagram for the operation of a light-emitting control unit, wherein the signals of the first clock signal terminal CK and the second clock signal terminal XCK are both pulse signals. For example, their periods can be the same.

[0052] For example, such as Figure 4As shown, the first processing module 213 includes a first transistor M31, a fourth transistor M34, and an eighth transistor M38. The gate of the first transistor M31 is electrically connected to the first node N1, its first electrode is electrically connected to the second clock signal terminal XCK, and its second electrode is electrically connected to the third node N3. The gate of the fourth transistor M34 is electrically connected to the first clock signal terminal CK, its first electrode is electrically connected to the input terminal IN, and its second electrode is electrically connected to the first node N1. The gate of the eighth transistor M38 is electrically connected to the fourth node N4, its first electrode is electrically connected to the second level signal terminal VGH, and its second electrode is electrically connected to the aforementioned third node N3.

[0053] like Figure 4 As shown, the first processing module 213 also includes a second capacitor C22, whose two plates are connected to the third node N3 and the first node N1, respectively. When the second clock signal terminal XCK transitions from a high level to a low level, the potential of the first node N1 changes from a low level to a third level lower than the low level under the action of the second capacitor C22. The first output transistor M21 can then be stably turned on, providing the signal from the first level signal terminal VGL to the output terminal OUT stably.

[0054] For example, such as Figure 4 As shown, the second processing module 214 includes a second transistor M32, a third transistor M33, a fifth transistor M35, a sixth transistor M36, and a seventh transistor M37. The gate of the second transistor M32 is electrically connected to the first node N1, and its first and second terminals are electrically connected to the first clock signal terminal CK and the fourth node N4, respectively. For example, the second transistor M32 may include two transistors connected in series. The gate of the fifth transistor M35 is electrically connected to the first clock signal terminal CK, its first terminal is electrically connected to the first level signal terminal VGL, and its second terminal is electrically connected to the fourth node N4.

[0055] like Figure 4 As shown, the second processing module 214 also includes a first capacitor C21, the first plate of the first capacitor C21 is electrically connected to the fourth node N4, and the second plate is electrically connected to the fifth node N5.

[0056] like Figure 4 As shown, the gate of the third transistor M33 is electrically connected to the fourth node N4, the first terminal is electrically connected to the second clock signal terminal XCK, and the second terminal is electrically connected to the fifth node N5. When the fourth node N4 is low and the second clock signal terminal XCK transitions from high to low, the low-level signal provided by the second clock signal terminal XCK writes the fifth node N5 low through the conducting third transistor M23. The fourth node N4 is pulled even lower by the first capacitor C21, keeping the third transistor M33 stably in the conducting state.

[0057] like Figure 4As shown, the gate of the seventh transistor M37 is electrically connected to the second clock signal terminal XCK, the first terminal is electrically connected to the fifth node N5, and the second terminal is electrically connected to the aforementioned second node N2; the gate of the sixth transistor M36 is electrically connected to the aforementioned first node N1, the first terminal is electrically connected to the second level signal terminal VGH, and the second terminal is electrically connected to the aforementioned second node N2.

[0058] For example, such as Figure 4 As shown, the light-emitting control unit 21 also includes a first protection transistor M41 and a second protection transistor M42, both of which have their gates electrically connected to the first level signal terminal VGL.

[0059] Optional, such as Figure 4 As shown, the first node N1 includes a first sub-node N11 and a second sub-node N12. The first sub-node N11 is electrically connected to the gate of the first output transistor M21 and the second capacitor C2. The second sub-node N12 is electrically connected to the gate of the second transistor M32 and the second electrode of the fourth transistor M34.

[0060] The first terminal of the first protection transistor M31 is electrically connected to the second sub-node N12, and the second terminal is electrically connected to the first sub-node N11. When the potential of the first sub-node N11 is coupled to a potential lower than the potential of the first level signal terminal VGL by the second capacitor C2, the first protection transistor M31 can be disconnected, thereby preventing the potential of the second sub-node N12 from becoming too low. This improves the reliability of the second transistor M32 and the fourth transistor M34, which are electrically connected to the second sub-node N12.

[0061] For example, such as Figure 4 As shown, the fourth node N4 includes a third sub-node N41 and a fourth sub-node N42. The third sub-node N41 is electrically connected to the gate of the first capacitor C21 and the third transistor M33, and the fourth sub-node N42 is electrically connected to the gate of the eighth transistor M38 and the second electrode of the fifth transistor M35.

[0062] The first terminal of the second protection transistor M42 is electrically connected to the fourth sub-node N42, and the second terminal is electrically connected to the third sub-node N41. When the potential of the third sub-node N41 is coupled to a potential lower than the potential of the first level signal terminal VGL by the first capacitor C1, the second protection transistor M32 can be disconnected, thereby preventing the potential of the fourth sub-node N42 from becoming too low. This, in turn, improves the reliability of the eighth transistor M38 and the fifth transistor M35, which are electrically connected to the fourth sub-node N42.

[0063] Optional, such as Figure 4 As shown, the light-emitting control unit 21 also includes a third capacitor C23, the two plates of which are electrically connected to the second level signal terminal VGH and the aforementioned second node N2, respectively.

[0064] For example, such as Figure 3 As shown, the display panel also includes a start signal line STV, a first level signal line LL, a second level signal line LH, a first clock signal line LK1, a second clock signal line LK2, a first control signal line LR1, a second control signal line LR2, and a first adjustment signal line LV1.

[0065] The input terminal IN of the first-level light-emitting control unit 21 is electrically connected to the start signal line STV, and the input terminal IN of other-level light-emitting control units 21 is electrically connected to the output terminal OUT of the previous-level light-emitting control unit 21.

[0066] The first clock signal line LK1 is electrically connected to the first clock signal terminal CK of the odd-level light-emitting control unit 21 and the second clock signal terminal XCK of the even-level light-emitting control unit 21.

[0067] The second clock signal line LK2 is electrically connected to the second clock signal terminal XCK of the odd-level light-emitting control unit 21 and the first clock signal terminal CK of the even-level light-emitting control unit 21.

[0068] The first level signal line LL is electrically connected to the first level signal terminal VGL of the multi-level light-emitting control unit 21; the second level signal line LH is electrically connected to the second level signal terminal VGH of the multi-level light-emitting control unit 21.

[0069] The first control signal line LR1 is electrically connected to the first control signal terminal RST1 of the multi-level light-emitting control unit 21. The second control signal line LR2 is electrically connected to the second control signal terminal RST2 of the second light-emitting control module 22. The first adjustment signal line LV1 is electrically connected to the first adjustment signal terminal V1 of the second light-emitting control module 22.

[0070] For example, in this embodiment of the invention, the length of the second control signal line LR2 is less than the length of the first control signal line LR1. Based on this configuration, the coupling capacitance between the second control signal line LR2 and other structures in the display panel can be less than the coupling capacitance between the first control signal line LR1 and other structures in the display panel. Therefore, when the display panel experiences an abnormal power outage, the signal on the second control signal line LR2 can drop rapidly.

[0071] For example, the length of the first control signal line LR1 is L1, the length of the second control signal line LR2 is L2, and L2 / L1≤1 / 10.

[0072] For example, such as Figure 6 As shown, Figure 6This is a schematic diagram illustrating the positional relationship between a light-emitting control unit, a second control module, and a chip bonding area provided in an embodiment of the present invention. The display panel further includes a chip bonding area BA, which is used to house a driver chip 3. At least one of the aforementioned start signal line STV, first level signal line LL, second level signal line LH, first clock signal line LK1, second clock signal line LK2, first control signal line LR1, second control signal line LR2, and first adjustment signal line LV1 is electrically connected to the driver chip 3 to receive the corresponding required electrical signal from the driver chip 3. Figure 6 The diagram illustrates the connection of the start signal line STV, the first level signal line LL, the second level signal line LH, the first clock signal line LK1, the second clock signal line LK2, the first control signal line LR1, the second control signal line LR2, and the first adjustment signal line LV1 to the driver chip 3.

[0073] For example, such as Figure 6 As shown, at least a portion of the second control module 22 is located on the side of the light-emitting control unit 21 near the chip bonding area BA. Based on this arrangement, the distance between the second control module 22 and the driver chip 3 can be reduced, which is beneficial to shorten the length of the second control signal line LR2, reduce the parasitic capacitance of the second control signal line LR2, and facilitate rapid signal changes on the second control signal line LR2 when the display panel is abnormally powered off.

[0074] Optional, such as Figure 4 As shown, the first control module 212 includes a first control transistor M51, whose gate is electrically connected to the first control signal terminal RST1, its first electrode is electrically connected to the second level signal terminal VGH, and its second electrode is electrically connected to the first node N1. Optionally, the first control transistor M51 includes a P-type transistor.

[0075] like Figure 7 As shown, Figure 7 The diagram shows another light-emitting control circuit provided in an embodiment of the present invention. The second control module 22 includes a second control transistor M52, whose gate is electrically connected to the second control signal terminal RST2. The second control signal terminal RST2 is electrically connected to the second control signal line LR2. The first electrode is electrically connected to the first adjustment signal terminal V1, and the second electrode is electrically connected to the first control signal line LR1. That is, the second electrode of the second control transistor M52 is electrically connected to the first control signal terminal RST1 of the multi-level light-emitting control unit 21.

[0076] Optional, such as Figure 3As shown, in this embodiment of the invention, the second control signal line LR2 is connected to only one second control transistor M52, while the first control signal line LR1 is connected to multiple first control transistors M51. That is, the parasitic capacitance of the second control signal line LR2 is smaller than that of the first control signal line LR1. Therefore, when the display panel experiences an abnormal power outage, the potential drop rate of the signal on the second control signal line LR2 is greater than that of the signal on the first control signal line LR1. Thus, in this embodiment, the second control transistor M52 can be quickly turned on under the control of the second control signal line LR2, allowing the charge on the first control signal line LR1 to quickly flow into the first adjustment signal terminal V1 and be released through the turned-on second control transistor M52. In other words, the first adjustment signal terminal V1 can quickly write the potential of the first control signal line LR1 low, thereby solving the problem that the signal potential on the first control signal line LR1 cannot drop quickly when the display panel experiences an abnormal power outage due to the large parasitic capacitance of the first control signal line LR1.

[0077] For example, the second control transistor M52 may include a P-type transistor.

[0078] In one optional implementation, the first level signal terminal VGL can be reused as the first adjustment signal terminal V1, that is, the second terminal of the second control module 22 can be electrically connected to the first level signal terminal VGL. Alternatively, in this embodiment of the invention, the ground terminal GND of the display panel can also be reused as the first adjustment signal terminal V1.

[0079] In another alternative implementation, Figure 3 Either the second power supply voltage terminal PVEE and the reset signal terminal Vref of the pixel driving circuit 11 shown can be reused as the first adjustment signal terminal V1.

[0080] Based on the above configuration, the signals required for the operation of the display panel can be fully utilized without the need to add new signals as the first adjustment signal terminal V1. This helps to reduce the number of signals required by the light-emitting control circuit 2 and simplifies the structure of the display panel.

[0081] When the display panel experiences an abnormal power failure, the potential of the signal on the second control signal terminal RST2 drops rapidly, causing the second control transistor M52 to turn on. Since the potentials of the first level signal terminal VGL, the ground terminal GND, the second power supply voltage terminal PVEE, and the reset signal terminal Vref at the moment of the abnormal power failure are at their respective low potentials during normal operation, the charge accumulated on the first control signal terminal RST1 can flow through the turned-on second control transistor M52 to the first adjustment signal terminal V1, which is multiplexed by any one of the first level signal terminal VGL, the ground terminal GND, the second power supply voltage terminal PVEE, and the reset signal terminal Vref, thus forming a charge discharge path. In other words, the signal of the first adjustment signal terminal V1 can be quickly written to the first control signal terminal RST1 through the conducting second control transistor M52, thereby rapidly reducing the potential of the first control signal terminal RST1, thus controlling the first control transistor M51 to quickly turn on, thereby rapidly providing the high potential of the second level signal terminal VGH to the first node N1, thereby controlling the first output transistor M21 to quickly turn off, preventing the light-emitting control unit 21 from outputting a low level, thus preventing the sub-pixels from lighting up and avoiding screen flickering problems on the display panel.

[0082] Furthermore, for transistors, the charge on the gate is generally more stable and less prone to change due to the lack of a discharge path. Compared to the gate, the charge accumulated on the first and second terminals of the transistor is more easily released by flowing from one to the other. Therefore, in this embodiment of the invention, by electrically connecting the first control signal line LR1 to the second terminal of the second control transistor M52, compared to not using the second control transistor M52, in the event of an abnormal power outage in the display panel, the leakage path between the second and first terminals of the second control transistor M52 can further accelerate the potential drop rate of the signal on the first control signal line LR1.

[0083] Optionally, the aspect ratio of the channel of the second control transistor M52 is greater than or equal to the aspect ratio of the channel of at least one transistor in the first processing module 213 and the second processing module 214. For example, the aspect ratio of the channel of the second control transistor M52 may be greater than... Figure 4 The width-to-length ratio of the channel of any one of the following transistors shown: first transistor M31, second transistor M32, third transistor M33, fourth transistor M34, fifth transistor M35, sixth transistor M36, seventh transistor M37, and eighth transistor M38.

[0084] As mentioned earlier, since the first control signal line LR1 is connected to multiple light-emitting control units 21, the parasitic capacitance of the first control signal line LR1 is relatively large. Therefore, when the display panel experiences an abnormal power failure, a large amount of charge is stored on the first control signal line LR1. This embodiment of the invention improves the signal transmission speed of the second control transistor M52 by setting a larger channel width-to-length ratio. When the display panel experiences an abnormal power failure, the charge transmission speed between the first adjustment signal terminal V1 and the first control signal line LR1 can be increased, thereby enabling a faster decrease in the potential on the first control signal line LR1.

[0085] For example, the channel width-to-length ratio of the second control transistor M52 is less than or equal to the channel width-to-length ratio of the first output transistor M21 or the second output transistor M22. Based on this configuration, excessively increasing the space occupied by the second control transistor M52 can be avoided, as can increasing the width of the bezel area of ​​the display panel where the second control transistor M52 is located.

[0086] For example, such as Figure 8 As shown, Figure 8 The present invention provides a schematic diagram of another light-emitting control circuit. The light-emitting control circuit 2 further includes a third control transistor M53, whose gate is electrically connected to the third control signal terminal RST3, the third control signal terminal RST3 is electrically connected to the third control signal line LR3, the first electrode is electrically connected to the second adjustment signal terminal V2, and the second electrode is electrically connected to the second control signal line LR2.

[0087] When the display panel is operating, the third control signal terminal RST3 is provided with a disabled level. This disabled level refers to the level that enables the third control transistor M53 to be turned off. For example, the third control transistor M53 may include a P-type transistor, and the disabled level of the third control signal terminal RST3 can be a high level.

[0088] When the display panel is working, the second adjustment signal terminal V2 can receive a DC signal. For example, the potential of the second adjustment signal terminal V2 is less than the potential of the signal on the second control signal line LR2.

[0089] For example, the length of the third control signal line LR3 is less than the length of the first control signal line LR1.

[0090] When the display panel experiences an abnormal power failure, the potential of the signal on the third control signal terminal RST3 drops rapidly, causing the third control transistor M53 to turn on. Since the potential of the second adjustment signal terminal V2 at the moment of the abnormal power failure of the display panel is its low potential when the display panel is working normally, the charge accumulated on the second control signal line LR2 can flow to the second adjustment signal terminal V2 through the turned-on third control transistor M53, thus forming a charge discharge path. In other words, the signal at the second adjustment signal terminal V2 can be quickly written into the second control signal line LR2 through the conducting third control transistor M53, thereby rapidly reducing the potential of the second control signal terminal RST2. This overcomes the problem of the slow gate signal drop of the second control transistor M52 caused by the large coupling capacitance formed between the gate and the second electrode of the second control transistor M52. Consequently, the second control transistor M52 can be quickly turned on, allowing the low-level signal on the first adjustment signal terminal V1 to be quickly provided to the first control signal line LR1 through the conducting second control transistor M52. This, in turn, controls the first control transistor M51 in each stage of the light-emitting control unit 21 to be quickly turned on, thereby controlling the high-level signal provided by the second level signal terminal VGH to be quickly provided to the gate of the first output transistor M21 through the conducting first control transistor M51. This, in turn, controls the first output transistor M21 to be quickly turned off, preventing the output terminal OUT of each stage of the light-emitting control unit 21 from outputting the signal controlling the light emission of the sub-pixel.

[0091] Optionally, the potential of the second adjustment signal terminal V2 is less than or equal to the potential of the first adjustment signal terminal V1.

[0092] For example, the aspect ratio of the channel of the third control transistor M53 is less than or equal to the aspect ratio of the channel of the second control transistor M52. Compared with the first control signal line LR1, the parasitic capacitance of the second control signal line LR2 is smaller. Therefore, when the display panel experiences an abnormal power failure, less charge accumulates on the second control signal line LR2. By setting the aspect ratio of the channel of the third control transistor M53 to be less than or equal to the aspect ratio of the channel of the second control transistor M52, this embodiment of the invention ensures that the charge on the second control signal line LR2 can be quickly discharged while reducing the area occupied by the third control transistor M53.

[0093] For example, the first adjustment signal terminal V1 can be reused as the second adjustment signal terminal V2.

[0094] In one alternative implementation, the first level signal terminal VGL can be multiplexed as the second adjustment signal terminal V2, that is, the second terminal of the third control transistor M53 can be electrically connected to the first level signal terminal VGL. Alternatively, Figure 3Either the second power supply voltage terminal PVEE and the reset signal terminal Vref of the pixel driving circuit 11 shown can be reused as the second adjustment signal terminal V2. Alternatively, in this embodiment of the invention, the ground terminal GND can also be reused as the second adjustment signal terminal V2.

[0095] Based on the above configuration, the signals required for the operation of the display panel can be fully utilized without the need to add new signals as the second adjustment signal terminal V2. This helps to reduce the number of signals required by the light-emitting control circuit 2 and simplifies the structure of the display panel.

[0096] Optional, such as Figure 9 As shown, Figure 9 The present invention provides a schematic diagram of another light-emitting control circuit. The light-emitting control circuit 2 further includes an adjusting capacitor C3. The first plate of the adjusting capacitor C3 is electrically connected to the third adjusting signal terminal V3, and the second plate is electrically connected to the second control signal line LR2.

[0097] When the display panel is operating normally, the third adjustment signal terminal V3 can receive a DC signal. For example, the potential of the third adjustment signal terminal V3 is greater than the potential of the first level signal terminal VGL.

[0098] When the display panel experiences an abnormal power failure, the signal on the third adjustment signal terminal V3 changes from a high potential to a low potential. This potential change will lower the potential on the second control signal line LR2 through the coupling effect of the adjustment capacitor C3, thereby accelerating the voltage drop on the second control signal line LR2 and thus accelerating the start-up of the second control module 22.

[0099] For example, in this embodiment of the invention, the capacitance value of the adjusting capacitor C3 is less than 500fF.

[0100] In one optional implementation, the second level signal terminal VGH can be multiplexed as the third adjustment signal terminal V3, that is, the first plate of the first adjustment capacitor C31 can be electrically connected to the second level signal terminal.

[0101] In another alternative implementation, Figure 3 The first power supply voltage terminal PVDD of the pixel driving circuit 11 shown can be reused as the third adjustment signal terminal V3.

[0102] In yet another alternative implementation, combined with Figure 9 and Figure 10 As shown, Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention. The display panel further includes a driver chip 3, which includes a power reference terminal VCI for receiving a power reference voltage. The driver chip 3 outputs power according to the power reference voltage. Figure 4The first level voltage received by the first level signal terminal VGL and the second level voltage VGH received by the second level signal terminal VGH, as shown, and the output Figure 2 The first power supply voltage received by the first power supply voltage terminal PVDD and the second power supply voltage received by the second power supply voltage terminal PVEE are shown.

[0103] For example, the aforementioned power supply reference voltage terminal VCI can be reused as the third adjustment signal terminal V3, that is, the first plate of the first adjustment capacitor C31 can be electrically connected to the power supply input voltage terminal VCI.

[0104] Based on the above configuration, the signals required for the operation of the display panel can be fully utilized without the need to add new signals as the third adjustment signal terminal V3. This helps to reduce the number of signals required by the light-emitting control circuit 2 and simplifies the structure of the display panel.

[0105] For example, such as Figure 9 As shown, in this embodiment of the invention, the regulating capacitor C3 can consist of only one capacitor.

[0106] Alternatively, in embodiments of the present invention, the light-emitting control circuit 2 may include at least two adjustable capacitors connected in series; and the second plates of the at least two adjustable capacitors may be electrically connected to the third adjustment signal terminal in a one-to-one correspondence. For example... Figure 11 As shown, Figure 11 This is a schematic diagram of another light-emitting control circuit provided in an embodiment of the present invention, wherein the light-emitting control circuit 2 includes three series-connected regulating capacitors, and the second plates of the three series-connected regulating capacitors are respectively electrically connected to three third regulating signal terminals in a one-to-one correspondence. Figure 11 As shown, the three regulating capacitors are labeled C3_1, C3_2 and C3_3, respectively, and the three third regulating signal terminals V3 are labeled V3_1, V3_2 and V3_3, respectively.

[0107] Among them, the regulating capacitor C3_1 is electrically connected to the second control signal line LR2 and the third regulating signal terminal V3_1; the regulating capacitor C3_2 is electrically connected to the third regulating signal terminal V3_1 and the third regulating signal terminal V3_2; and the regulating capacitor C3_3 is electrically connected to the third regulating signal terminal V3_2 and the third regulating signal terminal V3_3.

[0108] When the display panel is working normally, the third adjustment signal terminal V3_1, the third adjustment signal terminal V3_2 and the third adjustment signal terminal V3_3 all receive DC signals, and the potentials of the three are all greater than the potential of the first level signal terminal VGL.

[0109] For example, the potentials of the third adjustment signal terminals V3_1, V3_2, and V3_3 can be equal or unequal.

[0110] When the display panel experiences an abnormal power outage, the signals on the multiple third adjustment signal terminals V3 will change from high to low. These multiple changes will superimpose and affect the potential change on the second control signal line LR2, thereby reducing the voltage on the second control signal line LR2 more quickly. This can help to further accelerate the start-up of the second control module 22.

[0111] For example, the third adjustment signal terminal V3_1 can reuse any one of the above-mentioned second level signal terminal VGH, first power supply voltage terminal PVDD, and power supply reference voltage terminal VCI. The third adjustment signal terminal V3_2 can reuse any one of the above-mentioned second level signal terminal VGH, first power supply voltage terminal PVDD, and power supply reference voltage terminal VCI. The third adjustment signal terminal V3_3 can reuse any one of the above-mentioned second level signal terminal VGH, first power supply voltage terminal PVDD, and power supply reference voltage terminal VCI.

[0112] Optionally, the capacitance values ​​of at least two regulating capacitors C3 can be equal, or, in embodiments of the present invention, the capacitance value of the regulating capacitor C3 closest to the second control signal terminal RST2 can be smaller than the capacitance values ​​of the other regulating capacitors C3. Figure 11 For example, in this embodiment of the invention, the capacitance value of the regulating capacitor C3_1, which is directly electrically connected to the second control signal line LR2, can be made smaller than the capacitance value of the regulating capacitor C3_2, or the capacitance value of the regulating capacitor C3_1 can be made smaller than the capacitance value of the regulating capacitor C3_3. By adopting this setting, the voltage stabilizing effect of the regulating capacitor C3_1 on the second control signal line LR2 can be weakened. In the event of an abnormal power outage in the display panel, it is more beneficial for the regulating capacitor C3_1 to quickly lower the potential of the signal on the second control signal line LR2.

[0113] This invention also provides a driving method for the aforementioned display panel, combined with... Figure 3 and Figure 4 As shown, the driving method includes:

[0114] When the display panel is operating, both the first control signal terminal RST1 and the second control signal terminal RST2 are provided with an enable level. Under the action of the enable level provided by the first control signal terminal RST1, the first control module 212 is turned off, thereby preventing the first control module 212 from affecting the potential of the first node N1 during the normal operation of the display panel.

[0115] Under the action of the non-enable level provided by the second control signal terminal RST2, the second control module 22 is turned off, thereby preventing the second control module 22 from affecting the potential of the first control signal terminal RST1 of each level of light-emitting control unit 21 during the normal operation of the display panel.

[0116] Optionally, when the display panel is working, the timing sequence of the first clock signal terminal CK and the second clock signal terminal XCK of the primary light-emitting control unit 21 can be according to... Figure 5 The settings are shown to allow the output terminal OUT of each level of the light-emitting control unit 21 to output sequentially.

[0117] For example, when the display panel is in operation, the driving method further includes:

[0118] The potential of the first adjustment signal terminal V1 is controlled to be less than the potential of the signal at the first control signal terminal RST1. For example, the first adjustment signal terminal V1 receives a DC voltage.

[0119] When the display panel experiences an abnormal power outage, such as a sudden power cut, the potential of the signal on the second control signal terminal RST2 drops rapidly, causing the second control module 22 to conduct. Since the potential of the first adjustment signal terminal V1 at the instant of the abnormal power outage is the same as the potential of the display panel during normal operation, that is, at the instant of the abnormal power outage, the potential of the first adjustment signal terminal V1 is lower than the potential of the signal on the first control signal terminal RST1. Therefore, the charge on the first control signal terminal RST1 can flow to the first adjustment signal terminal V1 through the conducting second control module 22, thus forming a charge discharge path. In other words, the signal on the first adjustment signal terminal V1 can be quickly written to the first control signal terminal RST1 through the conducting second control module 22, thereby reducing the voltage of the first control signal terminal RST1.

[0120] Combination Figure 4 As shown, under the control of the signal at the first control signal terminal RST1, the first control module 212 is turned on, thereby quickly providing the voltage provided by the second level signal terminal VGH to the first node N1, so as to control the first output transistor M21 to be quickly turned off, preventing the voltage provided by the first level signal terminal VGL from being output to the output terminal OUT of the light-emitting control unit 21, thereby preventing... Figure 2 The light-emitting control module 114 of the pixel driving circuit 11 shown is turned on, thereby preventing the light-emitting element 12 from lighting up and avoiding display abnormalities such as screen flickering on the display panel.

[0121] Based on the same inventive concept, embodiments of the present invention also provide a display device, such as... Figure 12 As shown, Figure 12This is a schematic diagram of a display device provided in an embodiment of the present invention. The display device includes the display panel 100 described above. The specific structure of the display panel 100 has been described in detail in the above embodiments and will not be repeated here. Of course, Figure 12 The display device shown is for illustrative purposes only. The display device can be any device with a display function, such as a mobile phone, tablet computer, laptop computer, e-reader, television set, smartwatch, etc. This embodiment of the invention does not limit the scope of the invention.

[0122] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The circuit includes a light-emitting control circuit, which comprises multiple cascaded light-emitting control units, each of which includes: The output module, in response to a signal from the first node, is electrically connected to a first-level signal terminal and the output terminal of the output module; and, in response to a signal from the second node, is electrically connected to a second-level signal terminal and the output terminal of the output module. The first control module, in response to a signal from the first control signal terminal, is electrically connected to the second level signal terminal and the first node; The light-emitting control circuit further includes a second control module, which, in response to a signal from the second control signal terminal, is electrically connected to the first adjustment signal terminal and the first control signal terminal; When the display panel is in operation, both the first control signal terminal and the second control signal terminal provide an enabled level; the potential of the first adjustment signal terminal is lower than the potential of the signal at the first control signal terminal.

2. The display panel according to claim 1, characterized in that, The display panel also includes a ground terminal, and either the first level signal terminal or the ground terminal is multiplexed as the first adjustment signal terminal.

3. The display panel according to claim 1, characterized in that, The display panel further includes a pixel driving circuit, which includes a first power supply voltage terminal, a second power supply voltage terminal, and a reset signal terminal. The potential of the signal at the first power supply voltage terminal is greater than the potential of the signal at the second power supply voltage terminal, and the potential of the signal at the first power supply voltage terminal is greater than the potential of the signal at the reset signal terminal. Either the second power supply voltage terminal or the reset signal terminal is multiplexed as the first adjustment signal terminal.

4. The display panel according to claim 1, characterized in that, The display panel includes a first control signal line and a second control signal line, wherein the first control signal line is electrically connected to the first control signal terminal of the plurality of light-emitting control units; The second control signal line is electrically connected to the second control signal terminal; The length of the second control signal line is less than the length of the first control signal line.

5. The display panel according to claim 1, characterized in that, The display panel also includes a chip bonding area, and at least a portion of the second control module is located on the side of the light-emitting control unit near the chip bonding area.

6. The display panel according to claim 1, characterized in that, The first control module includes a first control transistor, whose gate is electrically connected to the first control signal terminal, its first electrode is electrically connected to the second level signal terminal, and its second electrode is electrically connected to the first node; The second control module includes a second control transistor, whose gate is electrically connected to the second control signal terminal, its first terminal is electrically connected to the first adjustment signal terminal, and its second terminal is electrically connected to the first control signal terminal.

7. The display panel according to claim 6, characterized in that, The light-emitting control unit further includes a first processing module and a second processing module. The first processing module is electrically connected to the input terminal and the second clock signal terminal, and provides a signal to the first node; The second processing module is electrically connected to the first clock signal terminal, the second level signal terminal, the first level signal terminal, and the second clock signal terminal, and provides signals to the second node; Both the first processing module and the second processing module include multiple transistors; The width-to-length ratio of the channel of the second control transistor is greater than or equal to the width-to-length ratio of the channel of at least one of the transistors in the first processing module and the second processing module.

8. The display panel according to claim 6, characterized in that, The output module includes a first output transistor and a second output transistor; wherein... The gate of the first output transistor is electrically connected to the first node, the first electrode is electrically connected to the first level signal terminal, and the second electrode is electrically connected to the output terminal; The gate of the second output transistor is electrically connected to the second node, the first electrode is electrically connected to the second level signal terminal, and the second electrode is electrically connected to the output terminal; The width-to-length ratio of the channel of the second control transistor is less than or equal to the width-to-length ratio of the channel of the first output transistor; or, the width-to-length ratio of the channel of the second control transistor is less than or equal to the width-to-length ratio of the channel of the second output transistor.

9. The display panel according to claim 6, characterized in that, The light-emitting control circuit further includes a third control transistor, the gate of which is electrically connected to a third control signal terminal, the first electrode of which is electrically connected to a second adjustment signal terminal, and the second electrode of which is electrically connected to the second control signal terminal; When the display panel is in operation, the third control signal terminal provides an enable level, and the potential of the second adjustment signal terminal is lower than the potential of the second control signal terminal.

10. The display panel according to claim 9, characterized in that, The width-to-length ratio of the channel of the third control transistor is less than or equal to the width-to-length ratio of the channel of the second control transistor.

11. The display panel according to claim 9, characterized in that, The potential of the second adjustment signal terminal is less than or equal to the potential of the first adjustment signal terminal.

12. The display panel according to claim 9, characterized in that, The first adjustment signal terminal is multiplexed as the second adjustment signal terminal.

13. The display panel according to claim 1, characterized in that, The light-emitting control circuit also includes an adjusting capacitor, wherein the first plate of the adjusting capacitor is electrically connected to the third adjusting signal terminal, and the second plate is electrically connected to the second control signal terminal. When the display panel is working, the potential of the third adjustment signal terminal is greater than the potential of the first level signal terminal.

14. The display panel according to claim 13, characterized in that, The second level signal terminal is multiplexed as the third adjustment signal terminal.

15. The display panel according to claim 13, characterized in that, The display panel further includes a pixel driving circuit, which includes a first power supply voltage terminal, a second power supply voltage terminal, and a reset signal terminal. The potential of the first power supply voltage terminal is greater than the potential of the second power supply voltage terminal, and the potential of the reset signal terminal is greater than the potential of the reset signal terminal. The first power supply voltage terminal is multiplexed as the third adjustment signal terminal.

16. The display panel according to claim 13, characterized in that, The display panel also includes a driver chip, which includes a power reference voltage terminal, and the power reference voltage terminal is multiplexed as the third adjustment signal terminal.

17. The display panel according to claim 13, characterized in that, The capacitance of the regulating capacitor is less than or equal to 500fF.

18. The display panel according to claim 13, characterized in that, The light-emitting control circuit includes at least two of the aforementioned regulating capacitors; At least two of the regulating capacitors are electrically connected to the third regulating signal terminal in a one-to-one correspondence, and at least two of the regulating capacitors are connected in series with each other.

19. The display panel according to claim 18, characterized in that, The capacitance of the regulating capacitor closest to the second control signal terminal is less than the capacitance of the other regulating capacitors.

20. A driving method for a display panel according to any one of claims 1-19, characterized in that, The driving method includes: When the display panel is working, an enable level is provided to the first control signal terminal and the second control signal terminal, and the potential of the signal controlling the first adjustment signal terminal is less than the potential of the signal controlling the first control signal terminal.

21. A display device, characterized in that, Includes the display panel as described in any one of claims 1-19.

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