Display device

Abstract

A display device is provided. The display device includes a first pixel and a second pixel. Each of the first pixel and the second pixel may include a light emitting element, a driving transistor connected to the light emitting element and a power line and controlled by a voltage of a first node, a switching transistor connected to a data line and a second node and controlled by a write scan signal, a capacitor connected to the first node and the second node, and a bias transistor connected to the driving transistor and the bias line and controlled by the bias scan signal. The first pixel and the second pixel may share a bias transistor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0156245, filed on November 13, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure herein relates to a display device. Background Art

[0004] Generally, electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs that provide images to users include a display device for displaying images. The display device generates images and provides the generated images to the user through a display screen.

[0005] Each display device includes a plurality of pixels for generating an image and a driving section for driving the plurality of pixels. Each of the plurality of pixels includes a light emitting element, a plurality of transistors connected to the light emitting element, and at least one capacitor connected to the plurality of transistors.

[0006] Since each of the multiple pixels includes various elements, it is necessary to ensure the surface area for arranging these elements. As the surface area for arranging the elements increases, the resolution of the display device may decrease. Technical development is needed to reduce the arrangement area for the elements to improve the resolution of the display device. Summary of the invention

[0007] The present disclosure provides a display device capable of improving resolution and reducing a brightness difference between second pixels.

[0008] Embodiments of the present inventive concept provide a display device including a first pixel and a second pixel. Each of the first pixel and the second pixel may include a light emitting element, a driving transistor, a switching transistor, a capacitor, and a bias transistor, wherein the driving transistor is connected to the light emitting element and a power line, wherein the driving transistor is controlled by a voltage of a first node, the switching transistor is connected to a data line and a second node, wherein the switching transistor is controlled by a write scan signal, the capacitor is connected to the first node and the second node, and the bias transistor is connected to the driving transistor and a bias line, wherein the bias transistor is controlled by a bias scan signal. The first pixel and the second pixel may share a bias transistor.

[0009] In an embodiment of the present invention, the display device includes a first pixel and a second pixel. Each of the first pixel and the second pixel may include a light emitting element, a driving transistor, a dummy electrode and a switching transistor, the driving transistor including a source region connected to a power line, a drain region connected to the light emitting element and a semiconductor layer of a channel region between the source region and the drain region, and a gate electrode disposed on the channel region, the dummy electrode is disposed on the gate electrode, and the switching transistor is connected to the data line and the dummy electrode and is controlled by a write scan signal. The source region of the driving transistor of the first pixel and the source region of the driving transistor of the second pixel may be connected to a shared node. The dummy electrode may include a first portion and a second portion, the first portion extending outward from the gate electrode to overlap with the source region when viewed on a plane, and providing a first parasitic capacitance, the second portion extending outward from the gate electrode to overlap with the drain region when viewed on a plane, and providing a second parasitic capacitance. The first parasitic capacitance may be smaller than the second parasitic capacitance.

[0010] In an embodiment of the present invention, a display device includes a first pixel and a second pixel. Each of the first pixel and the second pixel may include a light emitting element, a driving transistor, a dummy electrode, a switching transistor, and a bias transistor, the driving transistor including a semiconductor layer including a source region connected to a power line, a drain region connected to the light emitting element, and a channel region between the source region and the drain region, and a gate electrode disposed on the channel region, the dummy electrode is disposed on the gate electrode, the switching transistor is connected to the data line and the dummy electrode, wherein the switching transistor is controlled by a write scan signal, and the bias transistor is connected to the source region and the bias line, wherein the bias transistor is controlled by a bias scan signal. The first pixel and the second pixel may share a bias transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0012] Figure 1 is a perspective view of a display device according to an embodiment of the present inventive concept;

[0013] Figure 2 It is shown Figure 1 A view of an example of a cross section of a display device shown in FIG.

[0014] Figure 3 It is shown Figure 2 A view of an example of a cross section of a display panel shown in FIG.

[0015] Figure 4 yes Figure 2 A plan view of the display panel shown in ;

[0016] Figure 5 It is shown Figure 4 A view of an equivalent circuit of one pixel shown in ;

[0017] Figure 6 Is used to drive Figure 5 A timing diagram of a signal of a pixel shown in ;

[0018] Figure 7 It is shown Figure 5 A view of an example of a cross section of a light emitting element, a first transistor, and a sixth transistor of a pixel shown in FIG.

[0019] FIG. 8A to FIG. 8F It is shown that for each step Figure 5 A view of a planar structure of a pixel shown in;

[0020] Fig. 9 It is shown in Fig. 8E and Figure 8F A schematic diagram of a cross section of a contact hole defined at different positions in FIG.

[0021] Fig.10 It specifically shows Figure 8C A view of a type of pixel shown in FIG. 1 and additionally showing the region of the first capacitor and the region of the parasitic capacitor around the first capacitor in separate hatching;

[0022] Fig.11 are shown as separate shadings Fig.8D a view of a region of a second capacitor in FIG.

[0023] Fig.12 It is shown Fig.10 A schematic block diagram of a first pixel and a second pixel shown in ; and

[0024] Fig.13 and Fig.14 is a view illustrating the shape of a first portion according to various embodiments of the inventive concept. DETAILED DESCRIPTION

[0025] In the present specification, it should be understood that when an element (or region, layer, part, etc.) is referred to as being "on", "connected to" or "coupled to" another element, it can be directly set on, connected to or coupled to the other element, or a third element may be set between the elements.

[0026] Throughout the specification, the same reference numerals or reference signs refer to the same elements. In addition, in the drawings, the thickness, ratio and size of the elements are exaggerated for effective description of the technical contents.

[0027] The term "and / or" includes one or more combinations that can be defined by the relevant elements.

[0028] It should be understood that although various elements may be described using terms such as first, second, etc., in this article, these elements should not be limited to a specific order by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. Unless otherwise clearly indicated in the context, the singular form as used herein is also intended to include the plural form.

[0029] In addition, terms such as "below", "beneath", "on", and "above" are used to explain the relationship of elements shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0030] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It should also be understood that, unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0031] It should also be understood that when terms such as “includes” or “has” are used in this document, they specify the presence of stated features, numbers, steps, operations, elements, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, parts, or combinations thereof.

[0032] Hereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0033] Figure 1 is a perspective view of a display device according to an embodiment of the inventive concept.

[0034] Reference Figure 1 , the display device DD according to an embodiment of the inventive concept may have long sides extending in a first direction DR1 and short sides extending in a second direction DR2 intersecting the first direction DR1. Corners of the display device DD may have a rounded shape. Figure 1 The shape of the display device DD shown in FIG. 1 is shown as an example, and the display device DD is not limited to Figure 1 The shapes shown in .

[0035] Hereinafter, the third direction DR3 is defined as a direction substantially perpendicularly intersecting a plane defined by the first direction DR1 and the second direction DR2. The term “when viewed on a plane” herein may mean a state when viewed in the third direction DR3.

[0036] An image IM generated by the display device DD may be provided to a user through the top surface of the display device DD observed in the third direction DR3. The top surface of the display device DD may include a display area DA and a non-display area NDA around the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define an edge of the display device DD printed in a predetermined color.

[0037] A mobile phone is shown as an example of the display device DD. However, the display device DD is not limited to the mobile phone and can be used for various electronic devices. For example, the display device DD can be used for large electronic devices such as a television, a monitor, or an outdoor billboard. In addition, the display device DD can be used for small and medium-sized electronic devices such as a personal computer, a notebook computer, a vehicle navigation unit, a game console, a tablet computer, or a camera.

[0038] Figure 2 It is shown Figure 1 0 is a view of an example of a cross section of a display device shown in FIG.

[0039] As an example, Figure 2 A cross section of the display device DD viewed in a first direction DR1 is shown.

[0040] Reference Figure 2 , the display device DD may include a display panel DP, an input sensing part ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.

[0041] The display panel DP according to an embodiment of the present inventive concept may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The emission layer of the organic light-emitting display panel may include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0042] The input sensing part ISP may be disposed on the display panel DP. The input sensing part ISP may include a plurality of sensing parts (not shown) for sensing external input by using a capacitive method. The input sensing part ISP may be directly manufactured on the display panel DP during a manufacturing process of the display device DD. However, embodiments of the inventive concept are not limited thereto, and the input sensing part ISP may be manufactured as a panel separated from the display panel DP to be attached to the display panel DP through an adhesive layer.

[0043] The anti-reflection layer RPL may be disposed on the input sensing part ISP. During the manufacturing process of the display device DD, the anti-reflection layer RPL may be directly manufactured on the input sensing part ISP. However, embodiments of the inventive concept are not limited thereto, and the anti-reflection layer RPL may be manufactured as a separate panel to be attached to the input sensing part ISP through an adhesive layer.

[0044] The anti-reflection layer RPL may be a film that prevents external light from being reflected. The anti-reflection layer RPL may reduce the reflectivity of external light incident from above the display device DD toward the display panel DP. The external light may be invisible to the user due to the anti-reflection layer RPL.

[0045] When external light traveling toward the display panel DP is reflected back to the user by the display panel DP, the surface of the display device DD may look like a mirror to the user. To prevent this phenomenon, the anti-reflection layer RPL may include, for example, a plurality of color filters that respectively emit the same colors as the pixels of the display panel DP.

[0046] The color filter may filter external light to have the same color as the color of the pixel. Through such filtering, the external light may be invisible to the user. However, embodiments of the inventive concept are not limited thereto, and the anti-reflection layer RPL may include a retarder and / or a polarizer to reduce the reflectivity of the external light.

[0047] The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing part ISP, and the anti-reflection layer RPL from external scratches and impacts.

[0048] The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect a lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).

[0049] The first adhesive layer AL1 may be disposed between the display panel DP and the panel protection film PPF, and the display panel DP and the panel protection film PPF may be bonded to each other through the first adhesive layer AL1. The second adhesive layer AL2 may be disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be bonded to each other through the second adhesive layer AL2.

[0050] Figure 3 It is shown Figure 2 0 is a view of an example of a cross section of a display panel shown in FIG.

[0051] For example, Figure 3 A cross section of the display panel DP viewed in the first direction DR1 is shown.

[0052] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0053] The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may include glass or a flexible plastic material such as polyimide (PI). The display element layer DP-OLED may be disposed in the display area DA.

[0054] A plurality of pixels may be provided in the circuit element layer DP-CL and the display element layer DP-OLED. Each of the plurality of pixels may include a transistor provided in the circuit element layer DP-CL and a light emitting element provided in the display element layer DP-OLED to be connected to the transistor.

[0055] The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED. The thin film encapsulation layer TFE may protect the pixels from moisture, oxygen, and external foreign matter.

[0056] Figure 4 yes Figure 2 A plan view of the display panel shown in FIG.

[0057] Reference Figure 4 , the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, an emission driver EDV, and a plurality of pads PD.

[0058] The display panel DP may have a rectangular shape with long sides extending in the first direction DR1 and short sides extending in the second direction DR2. However, the shape of the display panel DP is not limited thereto. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0059] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, first and second power lines PL1 and PL2, and a plurality of connection lines CNL. Here, m and n are natural numbers greater than 1.

[0060] The pixels PX may be disposed in the display area DA. The scan driver SDV and the emission driver EDV may be disposed in the non-display area NDA adjacent to both sides of the display panel DP opposite to each other in the second direction DR2, respectively. The data driver DDV may be disposed in the non-display area NDA adjacent to one of both sides of the display panel DP opposite to each other in the first direction DR1. In a plan view, the data driver DDV may be adjacent to a first short side of the display panel DP.

[0061] The scan lines SL1 to SLm may extend in the second direction DR2 to be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 to be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 to be connected to the pixels PX and the emission driver EDV.

[0062] The first power line PL1 may extend in the first direction DR1 in the non-display area NDA. The first power line PL1 may be disposed between the display area DA and the emission driver EDV.

[0063] The connection line CNL may extend in the second direction DR2 and be arranged in the first direction DR1 to be connected to the first power line PL1 and the pixel. A first voltage may be applied to the pixel PX through the first power line PL1 and the connection line CNL connected to each other.

[0064] The second power line PL2 may be disposed in the non-display area NDA and extend along the long sides of the display panel DP and the short sides of the display panel DP on which the data driver DDV is not disposed. The second power line PL2 may be disposed outside the scan driver SDV and the emission driver EDV.

[0065] Although not shown, the second power line PL2 may extend toward the display area DA to be connected to the pixel PX. A second voltage having a level lower than that of the first voltage may be applied to the pixel PX through the second power line PL2.

[0066] The first control line CSL1 may be connected to the scan driver SDV and extend toward the first short side of the display panel DP. The second control line CSL2 may be connected to the emission driver EDV and extend toward the first short side of the display panel DP. The data driver DDV may be disposed between the first control line CSL1 and the second control line CSL2.

[0067] The pad PD may be disposed in the non-display area NDA adjacent to the first short side of the display panel DP and may be closer to the edge of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be connected to the pad PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0068] Although not shown, the display device DD may further include a timing controller for controlling the operation of each of the scan driver SDV, the data driver DDV, and the emission driver EDV, and a voltage generator for generating a first voltage and a second voltage. The timing controller and the voltage generator may be connected to the pad PD through a printed circuit board.

[0069] The scan driver SDV may generate a plurality of scan signals and may apply the scan signals to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages and may apply the data voltages to the pixels PX through the data lines DL1 to DLn. The emission driver EDV may generate a plurality of emission signals and may apply the emission signals to the pixels PX through the emission lines EL1 to ELm.

[0070] The pixel PX may receive a data voltage in response to the scan signal, and the pixel PX may display an image by emitting light having brightness corresponding to the data voltage in response to the emission signal.

[0071] Figure 5 It is shown Figure 4 A view of the equivalent circuit of one pixel is shown in FIG.

[0072] Reference Figure 5 , the pixel PXij may include a pixel circuit PC and a light emitting element ED connected to the pixel circuit PC. Here, i and j are natural numbers greater than 0. The pixel circuit PC may drive the light emitting element ED. The light emitting element ED may be defined as an organic light emitting element. The light emitting element ED may include an anode AE ​​and a cathode CE.

[0073] The pixel circuit PC may include a plurality of transistors T1 to T9 and a plurality of capacitors C1 and C2. The transistors T1 to T9 and the capacitors C1 and C2 may control the amount of current flowing through the light emitting element ED. The light emitting element ED may generate light with a predetermined brightness according to the amount of current supplied thereto.

[0074] The pixel PXij can be connected to the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th first emission line EML1i, the i-th second emission line EML2i, the j-th data line DLj, the first initialization line VIL1, the second initialization line VIL2, the reference line VL, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0075] The i-th write scan line GWLi may receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi may receive the i-th compensation scan signal GCi. The i-th initialization scan line GILi may receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi may receive the i-th bias scan signal GBi. The i-th first emission line EML1i may receive the i-th first emission signal EM1i, and the i-th second emission line EML2i may receive the i-th second emission signal EM2i.

[0076] The first initialization line VIL1 may receive a first initialization voltage VINT, and the second initialization line VIL2 may receive a second initialization voltage VAINT. The bias line VBL may receive a bias voltage VBIAS, and the reference line VL may receive a reference voltage VR. The first power line PL1 may receive a first voltage ELVDD, and the second power line PL2 may receive a second voltage ELVSS.

[0077] Each of the transistors T1 to T9 may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, for convenience, one of the source electrode and the drain electrode is defined as a first electrode, and the other is defined as a second electrode. In addition, the gate electrode is defined as a control electrode.

[0078] The transistors T1 to T9 may include first to ninth transistors T1 to T9. The first to ninth transistors T1 to T9 may be PMOS transistors. However, the first to ninth transistors T1 to T9 are not limited thereto and may be NMOS transistors. The capacitors C1 and C2 may include a first capacitor C1 and a second capacitor C2.

[0079] The first transistor T1 may be connected to the light emitting element ED and the first power line PL1, and may be controlled by the voltage of the first node N1. Specifically, the first transistor T1 may be connected to the anode AE ​​of the light emitting element ED through the sixth transistor T6, and may be connected to the first power line PL1 through the ninth transistor T9. The first transistor T1 may be disposed between the sixth transistor T6 and the ninth transistor T9 to be connected to the sixth transistor T6 and the ninth transistor T9.

[0080] The first transistor T1 may include a first electrode connected to the ninth transistor T9, a second electrode connected to the sixth transistor T6, and a control electrode connected to the first node N1. The first transistor T1 may control the amount of current flowing through the light emitting element ED according to a voltage of the first node N1 applied to the control electrode of the first transistor T1. The first transistor T1 may be defined as a driving transistor.

[0081] The second transistor T2 may be disposed between the jth data line DLj and the second node N2 to be connected to the jth data line DLj and the second node N2. The second transistor T2 may be controlled by the i-th write scan signal GWi. The second transistor T2 may include a first electrode connected to the jth data line DLj, a second electrode connected to the second node N2, and a control electrode connected to the i-th write scan line GWLi. The second transistor T2 may be defined as a switching transistor.

[0082] The first capacitor C1 may be connected to a first node N1 and a second node N2. The first capacitor C1 may be connected to a control electrode of the first transistor T1 through the first node N1 and to a second electrode of the second transistor T2 through the second node N2. The first capacitor C1 may include a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0083] The second transistor T2 may be turned on by the i-th write scan signal GWi received through the i-th write scan line GWLi. The turned-on second transistor T2 may receive the data voltage VD through the j-th data line DLj. The data voltage VD may be supplied to the first capacitor C1 through the turned-on second transistor T2.

[0084] The third transistor T3 may be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0085] The third transistor T3 may be turned on by the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi, and connects the second electrode of the first transistor T1 to the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 and the third transistor T3 may be diode-connected. The third transistor T3 may be referred to as a compensation transistor.

[0086] The fourth transistor T4 may be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi.

[0087] The fourth transistor T4 may be turned on by the i-th initialization scan signal GIi received through the i-th initialization scan line GILi. The turned-on fourth transistor T4 may supply the first initialization voltage VINT received through the first initialization line VIL1 to the first node N1. The fourth transistor T4 may be defined as a first initialization transistor.

[0088] Although not in Figure 5 , but each of the third transistor T3 and the fourth transistor T4 may have a dual-gate structure. Fig. 8A and Figure 8B The layout diagram in FIG. 1 shows a dual-gate structure of the third transistor T3 and the fourth transistor T4 .

[0089] The fifth transistor T5 may be disposed between the reference line VL and the second node N2 to be connected to the reference line VL and the second node N2. The fifth transistor T5 may be controlled by the i-th compensation scan signal GCi.

[0090] The fifth transistor T5 may include a first electrode connected to the second node N2, a second electrode connected to the reference line VL, and a control electrode connected to the i-th compensation scan line GCLi. The fifth transistor T5 may be turned on by the i-th compensation scan signal GCi received through the i-th compensation scan line GCLi. The turned-on fifth transistor T5 may supply a reference voltage VR received through the reference line VL to the second node N2. The fifth transistor T5 may be defined as a reference transistor.

[0091] The sixth transistor T6 may be connected to the first transistor T1 and the anode AE ​​and controlled by the i-th second emission signal EM2i. The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the anode AE, and a control electrode connected to the i-th second emission line EML2i.

[0092] The sixth transistor T6 may be turned on by the i-th second emission signal EM2i received through the i-th second emission line EML2i. The sixth transistor T6 may be defined as a first emission control transistor.

[0093] The seventh transistor T7 may be connected to the anode AE ​​and the second initialization line VIL2 and controlled by the i-th bias scan signal GBi. The seventh transistor T7 may include a first electrode connected to the anode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi.

[0094] The seventh transistor T7 may be turned on by the i-th bias scan signal GBi received through the i-th bias scan line GBLi. The turned-on seventh transistor T7 may supply the second initialization voltage VAINT received through the second initialization line VIL2 to the anode AE ​​of the light emitting element ED. The seventh transistor T7 may be defined as a second initialization transistor.

[0095] The eighth transistor T8 may be connected to the first transistor T1 and the bias line VBL and controlled by the i-th bias scan signal GBi. The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0096] The eighth transistor T8 may be turned on by the i-th bias scan signal GBi received through the i-th bias scan line GBLi. The turned-on eighth transistor T8 may supply the bias voltage VBIAS received through the bias line VBL to the first electrode of the first transistor T1. The eighth transistor T8 may be defined as a bias transistor.

[0097] The ninth transistor T9 may be connected to the first power line PL1 and the first transistor T1 and controlled by the i-th first emission signal EM1i. The ninth transistor T9 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th first emission line EML1i.

[0098] The ninth transistor T9 may be turned on by the i-th first emission signal EM1i received through the i-th first emission line EML1i. The ninth transistor T9 may be referred to as a second emission control transistor. When the sixth transistor T6 and the ninth transistor T9 are turned on, the first voltage ELVDD may be supplied to the light emitting element ED so that the driving current Id flows through the light emitting element ED. In response to the driving current Id, the light emitting element ED may emit light.

[0099] The second capacitor C2 may include a first electrode connected to the second node N2 and a second electrode connected to the first power line PL1 .

[0100] The anode AE ​​may be connected to the first power line PL1 through the sixth transistor T6, the first transistor T1, and the ninth transistor T9. The anode AE ​​may receive the first voltage ELVDD through the sixth transistor T6, the first transistor T1, and the ninth transistor T9.

[0101] The cathode CE may be connected to the second power line PL2. The cathode CE may receive the second voltage ELVSS having a level lower than that of the first voltage ELVDD through the second power line PL2.

[0102] Figure 6 Is used to drive Figure 5 0 is a timing diagram of the signals of the pixel shown in .

[0103] In the following, the activation period of each signal is shown Figure 6 The low level in the timing diagram, and the deactivation period of each signal is shown Figure 6 The high level in the timing diagram.

[0104] Reference Figure 5 and Figure 6 , the i-th first transmission signal EM1i may be activated and deactivated in the non-transmission period NLP. The i-th first transmission signal EM1i may be activated in the transmission period LP. The i-th second transmission signal EM2i may be deactivated in the non-transmission period NLP and activated in the transmission period LP.

[0105] During the non-emission period NLP, the i-th initialization scan signal GIi and the i-th compensation scan signal GCi may be repeatedly activated within the activation period of the i-th first emission signal EM1i. The i-th initialization scan signal GIi may be activated first, and then the i-th compensation scan signal GCi may be activated. The activation period of the i-th initialization scan signal GIi may not overlap with the activation period of the i-th compensation scan signal GCi.

[0106] During the non-emission period NLP, the i-th initialization scan signal GIi and the i-th compensation scan signal GCi may be deactivated within the deactivation period of the i-th first emission signal EM1i. Figure 6 As shown in , the deactivation period is shorter than the non-emission period NLP. During the deactivation period of the i-th first emission signal EM1i, the i-th write scan signal GWi may be activated, and then the i-th bias scan signal GBi may be activated. The i-th bias scan signal GBi may be repeatedly activated within the deactivation period of the i-th first emission signal EM1i.

[0107] For example, each of the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, and the i-th bias scan signal GBi may be activated three times, but the number of activations is not limited thereto. During the emission period LP, the i-th initialization scan signal GIi, the i-th compensation scan signal GCi, the i-th write scan signal GWi, and the i-th bias scan signal GBi may be deactivated.

[0108] During the non-emission period NLP, the ninth transistor T9 may be turned on by the activated i-th first emission signal EM1i, thereby applying the first voltage ELVDD to the first electrode (or source electrode) of the first transistor T1.

[0109] During the non-emission period NLP, the fourth transistor T4 may be turned on by the activated i-th initialization scan signal GIi. The first initialization voltage VINT may be supplied to the first node N1 through the fourth transistor T4, and the first transistor T1 may be initialized. This operation may be defined as an initialization operation.

[0110] Thereafter, during the non-emission period NLP, the activated i-th compensation scan signal GCi may be applied to the third transistor T3 to turn on the third transistor T3. The first transistor T1 and the third transistor T3 may be turned on to be diode-connected. In this case, a compensation voltage ELVDD-Vth, which is obtained by subtracting the threshold voltage Vth of the first transistor T1 from the first voltage ELVDD, may be applied to the control electrode of the first transistor T1. This operation may be defined as a threshold voltage compensation operation.

[0111] During the non-emission period NLP, the activated i-th compensation scan signal GCi may be applied to the fifth transistor T5 so that the fifth transistor T5 is turned on. The reference voltage VR may be applied to the second node N2 through the turned-on fifth transistor T5.

[0112] When the i-th initialization scan signal GIi and the i-th compensation scan signal GCi are repeatedly activated in an alternating manner, the above initialization operation and threshold voltage compensation operation may be repeatedly performed. As the initialization operation is repeatedly performed, the data written in the first node N1 in the previous frame may be erased, thereby initializing the first transistor T1.

[0113] A parasitic capacitor may be present in the third transistor T3 and the fourth transistor T4. The gate-source voltage of the third transistor T3 and the fourth transistor T4 may be changed by the parasitic capacitor. The second capacitor C2 may have a capacitance greater than the capacitance of the parasitic capacitor. The second capacitor C2 having a larger capacitance may be connected to the third transistor T3 and the fourth transistor T4 through the first node N1. The second capacitor C2 having a larger capacitance may suppress the change in the gate-source voltage of the third transistor T3 and the fourth transistor T4.

[0114] Thereafter, during the non-emission period NLP, the activated i-th write scan signal GWi may be applied to the second transistor T2, so that the second transistor T2 is turned on. The data voltage VD may be supplied to the first capacitor C1 through the second transistor T2. In this case, the data voltage VD may be applied to the second node N2, and the voltage of the first node N1 may be ELVDD-Vth+VD-VR.

[0115] Thereafter, the seventh transistor T7 and the eighth transistor T8 may be turned on by the activated i-th bias scan signal GBi. The second initialization voltage VAINT may be supplied to the anode AE ​​through the seventh transistor T7, and the bias voltage VBIAS may be applied to the first electrode of the first transistor T1 through the eighth transistor T8.

[0116] Thereafter, during the emission period LP, the activated i-th first emission signal EM1i and i-th second emission signal EM2i may be applied to the ninth transistor T9 and the sixth transistor T6, respectively, so that the ninth transistor T9 and the sixth transistor T6 are turned on. The driving current Id may be supplied to the light emitting element ED through the sixth transistor T6, so that the light emitting element ED emits light.

[0117] The source-gate voltage Vsg of the first transistor T1 may be defined as a voltage difference between the first voltage ELVDD and the voltage of the first node N1 (ELVDD-Vth+VD-VR). When the source-gate voltage Vsg of the first transistor T1 is substituted into the following equation 1, the threshold voltage Vth may be removed, and the driving current Id of equation 1 may be obtained by comparing (VR-VD) 2 , or the square of the difference between the reference voltage VR and the data voltage VD. Therefore, the driving current Id can be determined regardless of the threshold voltage Vth of the first transistor T1.

[0118] Id=(1 / 2)μCox(W / L)(Vsg-Vth) 2 [Equation 1]

[0119] Equation 1 is a formula for the relationship between current and voltage in a general transistor.

[0120] After the threshold voltage of the first transistor T1 is compensated and before the light emitting element ED emits light, the bias voltage VBIAS can be applied to the first electrode of the first transistor T1 through the eighth transistor T8. The bias voltage VBIAS can suppress the offset of the hysteresis loop of the first transistor T1. This operation can be defined as a bias operation.

[0121] Figure 7 It is shown Figure 5 0 is a view of an example of a cross section of a light emitting element, a first transistor, and a sixth transistor of a pixel shown in .

[0122] Reference Figure 7 The light emitting element ED may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL and an emission layer EML. The first electrode AE ​​may be Figure 5 The anode AE ​​shown in FIG. 1 and the second electrode CE may be Figure 5 The cathode CE shown in FIG. The second electrode CE may be disposed on the first electrode AE, and the hole control layer HCL, the electron control layer ECL, and the emission layer EML may be disposed between the first electrode AE ​​and the second electrode CE.

[0123] The first and sixth transistors T1 and T6 and the light emitting element ED may be disposed on the substrate SUB. The display area DA may include an emission area LEA corresponding to the pixel PXij and a non-emission area NLEA adjacent to the emission area LEA. The light emitting element ED may be disposed in the emission area LEA.

[0124] A buffer layer BFL may be disposed on the substrate SUB, and the buffer layer BFL may be an inorganic layer. The semiconductor layers S1, A1, and D1 of the first transistor T1 and the semiconductor layers S6, A6, and D6 of the sixth transistor T6 may be disposed on the buffer layer BFL. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include polycrystalline silicon. However, embodiments of the inventive concept are not limited thereto, and the semiconductor layers S1, A1, D1, S6, A6, and D6 may include amorphous silicon.

[0125] Each of the semiconductor layers S1, A1, D1, S6, A6, and D6 may be doped with an n-type dopant or a p-type dopant. The semiconductor layers S1, A1, D1, S6, A6, and D6 may include a heavily doped region and a lightly doped region. The heavily doped region (e.g., source region and drain region) may have a higher conductivity than that of the lightly doped region and may be substantially used as a source electrode and a drain electrode of the first transistor T1 and the sixth transistor T6. The lightly doped region may substantially correspond to a channel region (or channel) of the first transistor T1 and the sixth transistor T6.

[0126] The first source region S1, the first channel region A1, and the first drain region D1 of the first transistor T1 may be made of semiconductor layers S1, A1, and D1. The sixth source region S6, the sixth channel region A6, and the sixth drain region D6 of the sixth transistor T6 may be made of semiconductor layers S6, A6, and D6. The first channel region A1 may be disposed between the first source region S1 and the first drain region D1. The sixth channel region A6 may be disposed between the sixth source region S6 and the sixth drain region D6.

[0127] A first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, D1, S6, A6, and D6. A first gate electrode G1 (or control electrode) of the first transistor T1 and a sixth gate electrode G6 (or control electrode) of the sixth transistor T6 may be disposed on the first insulating layer INS1. The first gate electrode G1 may be disposed on the first channel region A1, and the sixth gate electrode G6 may be disposed on the sixth channel region A6.

[0128] Although not shown, the other transistors T2 to T5 and T7 to T9 may also have components substantially the same as those of the first transistor T1 and the sixth transistor T6 .

[0129] A second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. A first dummy electrode DME1 may be disposed on the second insulating layer INS2. The first dummy electrode DME1 may be disposed on the first gate electrode G1 and overlap the first gate electrode G1 when viewed on a plane.

[0130] The first dummy electrode DME1 and the first gate electrode G1 may together provide the above-mentioned first capacitor C1. The first gate electrode G1 may define a first electrode of the first capacitor C1, and the first dummy electrode DME1 may define a second electrode of the first capacitor C1. The first gate electrode G1 may substantially define the above-mentioned first node N1, and the first dummy electrode DME1 may substantially define the above-mentioned second node N2.

[0131] A third insulating layer INS3 may be provided on the second insulating layer INS2 to cover the first dummy electrode DME1. A second dummy electrode DME2 may be provided on the third insulating layer INS3. The second dummy electrode DME2 and the first dummy electrode DME1 may together provide the above-mentioned second capacitor C2. The first dummy electrode DME1 may define a first electrode of the second capacitor C2, and the second dummy electrode DME2 may define a second electrode of the second capacitor C2.

[0132] A fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the second dummy electrode DME2. The buffer layer BFL and the first to fourth insulating layers INS1 to INS4 may include an inorganic layer.

[0133] A connection electrode CNE may be disposed between the sixth transistor T6 and the light emitting element ED. The connection electrode CNE may electrically connect the sixth transistor T6 and the light emitting element ED to each other. The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 disposed on the first connection electrode CNE1.

[0134] The first connection electrode CNE1 may be disposed on the fourth insulating layer INS4 and connected to the sixth drain region D6 through a first contact hole CH1 defined in the first to fourth insulating layers INS1 to INS4. A fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the first connection electrode CNE1.

[0135] The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a second contact hole CH2 defined in the fifth insulating layer INS5. A sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the second connection electrode CNE2. The fifth insulating layer INS5 and the sixth insulating layer INS6 may include an inorganic layer or an organic layer.

[0136] The first electrode AE ​​may be disposed on the sixth insulating layer INS6. The first electrode AE ​​may be connected to the second connection electrode CNE2 through a third contact hole CH3 defined in the sixth insulating layer INS6.

[0137] A pixel defining layer PDL exposing a predetermined portion of the first electrode AE ​​may be disposed on the first electrode AE ​​and the sixth insulating layer INS6 . An opening portion PX_OP exposing the predetermined portion of the first electrode AE ​​may be defined in the pixel defining layer PDL.

[0138] The hole control layer HCL may be disposed on the first electrode AE ​​and the pixel definition layer PDL. The hole control layer HCL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0139] The emission layer EML may be disposed on the hole control layer HCL. The emission layer EML may be disposed in a region corresponding to the opening portion PX_OP. The emission layer EML may include an organic substance and / or an inorganic substance. The emission layer EML may generate light having any one color among red, green, and blue.

[0140] The electron control layer ECL may be disposed on the emission layer EML and the hole control layer HCL. The electron control layer ECL may be commonly disposed in the emission area LEA and the non-emission area NLEA. The electron control layer ECL may include an electron transport layer and an electron injection layer.

[0141] The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may be commonly disposed in the plurality of pixels PX. That is, the second electrode CE may be commonly disposed on the plurality of emission layers EML of the plurality of pixels PX.

[0142] The layers from the buffer layer BFL to the sixth insulating layer INS6 may be defined as a circuit element layer DP-CL. The layer on which the light emitting element ED is disposed may be defined as a display element layer DP-OLED.

[0143] The thin film encapsulation layer TFE may be disposed on the light emitting element ED. The thin film encapsulation layer TFE may include an inorganic layer, an organic layer, and an inorganic layer stacked sequentially. The inorganic layer may include an inorganic substance and protect the pixel from moisture / oxygen. The organic layer may include an organic substance and protect the pixel PX from foreign matter such as dust particles.

[0144] A first voltage ELVDD may be applied to the first electrode AE, and a second voltage ELVSS may be applied to the second electrode CE. Holes and electrons injected into the emission layer EML may be combined with each other to generate excitons, and the light emitting element ED may emit light when the excitons transition to a ground state. When the light emitting element ED emits light, an image may be displayed.

[0145] FIG. 8A to FIG. 8F It is shown that for each step Figure 5 A view of the planar structure of a pixel shown in FIG.

[0146] FIG. 8A to FIG. 8F The plan view shown in FIG. 1 may be a plan view of the first to ninth transistors T1 to T9 and the first and second capacitors C1 and C2 . FIG. 8A to FIG. 8F The view shown in may be a layout diagram. FIG. 8A to FIG. 8F When describing the embodiments, the term "overlap" refers to a state in which components are located on top of each other when viewed on a plane.

[0147] exist FIG. 8A to FIG. 8F FIG. 4 shows a planar structure of pixels PX adjacent to each other in the second direction DR2. The planar structure of the pixels PX is symmetrical with respect to a line extending in the first direction DR1. FIG. 8A to FIG. 8F The structure of the pixel PX on the right side in the figure.

[0148] Reference Fig. 8A , Fig. 8A The semiconductor pattern SMP shown in the figure may be disposed on the substrate SUB. The semiconductor pattern SMP is not limited to Fig. 8A The shape shown in , and may have various shapes.

[0149] The semiconductor pattern SMP may include first to ninth source regions S1 to S9 , first to ninth drain regions D1 to D9 , first to ninth channel regions A1 to A9 , and a lower reference line VL-L.

[0150] The first semiconductor layer S1, A1 and D1 of the first transistor T1, the second semiconductor layer S2, A2 and D2 of the second transistor T2, the third semiconductor layer S3, A3 and D3 of the third transistor T3, the fourth semiconductor layer S4, A4 and D4 of the fourth transistor T4, the fifth semiconductor layer S5, A5 and D5 of the fifth transistor T5, the sixth semiconductor layer S6, A6 and D6 of the sixth transistor T6, the seventh semiconductor layer S7, A7 and D7 of the seventh transistor T7, the eighth semiconductor layer S8, A8 and D8 of the eighth transistor T8, and the ninth semiconductor layer S9, A9 and D9 of the ninth transistor T9 can be provided by the semiconductor pattern SMP.

[0151] The first to ninth channel regions A1 to A9 may be disposed between the first source region S1 and the first drain region D1 to the ninth source region S9 and the ninth drain region D9, respectively. The third transistor T3 and the fourth transistor T4 may each have a dual-gate structure. The third transistor T3 and the fourth transistor T4 may each have a dual-gate structure, and each of the third channel region A3 of the third transistor T3 and the fourth channel region A4 of the fourth transistor T4 may be provided as two.

[0152] The second semiconductor layer S2, A2, D2, the fifth semiconductor layer S5, A5 and D5 and the lower reference line VL-L may be spaced apart from the first semiconductor layer S1, A1, D1, the third semiconductor layer S3, A3, D3, the fourth semiconductor layer S4, A4, D4, the sixth semiconductor layer S6, A6, D6, the seventh semiconductor layer S7, A7, D7, the eighth semiconductor layer S8, A8, D8 and the ninth semiconductor layer S9, A9 and D9.

[0153] The second drain region D2 of the second transistor T2 may extend from the fifth source region S5 of the fifth transistor T5. The lower reference line VL-L may extend from the fifth drain region D5 of the fifth transistor T5 in the first direction DR1 and then in the second direction DR2.

[0154] The third source region S3 of the third transistor T3 and the sixth source region S6 of the sixth transistor T6 may extend from the first drain region D1 of the first transistor T1. The fourth source region S4 of the fourth transistor T4 may extend from the third drain region D3 of the third transistor T3. The seventh source region S7 of the seventh transistor T7 may extend from the sixth drain region D6 of the sixth transistor T6.

[0155] The eighth drain region D8 of the eighth transistor T8 and the ninth drain region D9 of the ninth transistor T9 may extend from the first source region S1 of the first transistor T1 .

[0156] In the following, for the convenience of explanation, when referring to FIG. 8B to FIG. 8F When the lines are shown in , “ith” and “jth” are omitted from the names and reference symbols.

[0157] Reference Fig. 8A and Figure 8B A first gate pattern GPT1 may be disposed on the semiconductor pattern SMP. The first gate pattern GPT1 may include first, second and ninth gate electrodes G1, G2 and G9, an initialization scan line GIL, a compensation scan line GCL, a second emission line EML2 and a bias scan line GBL.

[0158] The first gate electrode G1 of the first transistor T1, the second gate electrode G2 of the second transistor T2, and the ninth gate electrode G9 of the ninth transistor T9 may be provided by the first gate pattern GPT1. The first gate electrode G1 may overlap the first channel region A1, the second gate electrode G2 may overlap the second channel region A2, and the ninth gate electrode G9 may overlap the ninth channel region A9.

[0159] The initialization scan line GIL, the compensation scan line GCL, the second emission line EML2, and the bias scan line GBL may extend in the second direction DR2 to be arranged in the first direction DR1. The initialization scan line GIL and the second emission line EML2 may be separated between the left pixel PX and the right pixel PX. The separated initialization scan line GIL and the separated second emission line EML2 may be connected by a first connection pattern SDP1 to be described later.

[0160] The initialization scan line GIL may be adjacent to the upper side of the pixel PX, and the bias scan line GBL may be adjacent to the lower side of the pixel PX. The compensation scan line GCL may be disposed between the initialization scan line GIL and the second emission line EML2. The second emission line EML2 may be disposed between the compensation scan line GCL and the bias scan line GBL.

[0161] The initialization scan line GIL may extend at least partially across the semiconductor pattern SMP. The fourth gate electrode G4 of the fourth transistor T4 may be provided by the initialization scan line GIL. A portion of the initialization scan line GIL overlapping the semiconductor pattern SMP may be defined as the fourth gate electrode G4. The fourth gate electrode G4 may overlap the fourth channel region A4. The fourth gate electrode G4 having a dual-gate structure may be provided as two.

[0162] The compensation scan line GCL may extend across the semiconductor pattern SMP. The third gate electrode G3 of the third transistor T3 and the fifth gate electrode G5 of the fifth transistor T5 may be provided by the compensation scan line GCL. The portion of the compensation scan line GCL overlapping the semiconductor pattern SMP may be defined as the third gate electrode G3 and the fifth gate electrode G5. The third gate electrode G3 may overlap the third channel region A3, and the fifth gate electrode G5 may overlap the fifth channel region A5. The third gate electrode G3 having a dual-gate structure may be provided as two.

[0163] The second emission line EML2 may extend across the semiconductor pattern SMP. A sixth gate electrode G6 of the sixth transistor T6 may be provided by the second emission line EML2. A portion of the second emission line EML2 overlapping the semiconductor pattern SMP may be defined as a sixth gate electrode G6. The sixth gate electrode G6 may overlap the sixth channel region A6.

[0164] The bias scan line GBL may extend across the semiconductor pattern SMP. The seventh gate electrode G7 of the seventh transistor T7 and the eighth gate electrode G8 of the eighth transistor T8 may be provided by the bias scan line GBL. The portion of the bias scan line GBL overlapping the semiconductor pattern SMP may be defined as the seventh gate electrode G7 and the eighth gate electrode G8. The seventh gate electrode G7 may overlap the seventh channel region A7, and the eighth gate electrode G8 may overlap the eighth channel region A8. The left pixel PX and the right pixel PX may be provided to share one eighth transistor T8.

[0165] In the following, FIG. 8C to FIG. 8F , for convenience of explanation and to simply indicate reference symbols, reference symbols for the first source region S1, the first drain region D1, the first channel region A1, and the first gate electrode G1 of the first transistor T1 to the ninth source region S9, the ninth drain region D9, the ninth channel region A9, and the ninth gate electrode G9 of the ninth transistor T9 are omitted, and reference symbols for the first transistor T1 to the ninth transistor T9 are shown. Figure 8C Reference symbols for the first gate electrode G1 are shown.

[0166] In the following, FIG. 8C to FIG. 8F , the reference symbols for the first source region S1 to the ninth source region S9, the first drain region D1 to the ninth drain region D9, the first channel region A1 to the ninth channel region A9, and the first gate electrode G1 to the ninth gate electrode G9 are omitted with reference to Fig. 8A and Figure 8B In.

[0167] Reference FIG. 8A to FIG. 8C , a second gate pattern GPT2 may be disposed on the first gate pattern GPT1. The second gate pattern GPT2 may include a first dummy electrode DME1 and a sub-dummy electrode SDE.

[0168] The first dummy electrode DME1 may overlap the first gate electrode G1. The first dummy electrode DME1 and the first gate electrode G1 may provide a first capacitor C1 together. A first opening portion OP1 may be defined in the first dummy electrode DME1. A portion of the first gate electrode G1 may be exposed through the first opening portion OP1.

[0169] The sub-dummy electrode SDE may overlap a portion of the semiconductor pattern SMP of each of the third and fourth transistors T3 and T4. Specifically, the sub-dummy electrode SDE may overlap a portion of the semiconductor pattern SMP between the third channel regions A3 and a portion of the semiconductor pattern SMP between the fourth channel regions A4.

[0170] In the following, FIG. 8D to FIG. 8F In the figure, reference symbols for the first capacitor C1 and the sub-dummy electrode SDE are omitted, and in FIG. 8D to FIG. 8F The reference symbols for the first capacitor C1 and the sub-dummy electrode SDE omitted in Figure 8C In.

[0171] Reference FIG. 8A to FIG. 8D A third gate pattern GPT3 may be disposed on the second gate pattern GPT2. The third gate pattern GPT3 may include a horizontal reference line VLH, a second dummy electrode DME2, and a second initialization line VIL2.

[0172] The horizontal reference line VLH, the second dummy electrode DME2, and the second initialization line VIL2 may extend in the second direction DR2 to be arranged in the first direction DR1. The horizontal reference line VLH may be adjacent to the upper side of the pixel PX, and the second initialization line VIL2 may be adjacent to the lower side of the pixel PX. The second dummy electrode DME2 may be disposed between the horizontal reference line VLH and the second initialization line VIL2.

[0173] The horizontal reference line VLH may extend across the lower reference line VL-L extending in the first direction DR1. The horizontal reference line VLH may extend to intersect the semiconductor pattern SMP of each of the second transistor T2 and the fifth transistor T5. The second initialization line VIL2 may be adjacent to the seventh transistor T7.

[0174] The second dummy electrode DME2 may overlap the first dummy electrode DME1. The second dummy electrode DME2 and the first dummy electrode DME1 may together provide a second capacitor C2. A second opening portion OP2 may be defined in the second dummy electrode DME2. The second opening portion OP2 may be defined to be larger than the first opening portion OP1 and overlap the first opening portion OP1.

[0175] A portion of the first gate electrode G1 may be exposed through the first opening portion OP1 and a portion of the second opening portion OP2 overlapping the first opening portion OP1. A portion of the first dummy electrode DME1 may be exposed through a portion of the second opening portion OP2 not overlapping the first opening portion OP1.

[0176] In the following, Fig. 8E and Figure 8FIn the embodiment, reference symbols for the second capacitor C2 and the first and second dummy electrodes DME1 and DME2 are omitted, and Fig. 8E and Figure 8F The reference symbols for the second capacitor C2 and the first and second dummy electrodes DME1 and DME2 omitted in FIG. Fig.8D In.

[0177] Reference FIG. 8A to FIG. 8E , the first connection pattern SDP1 may be disposed on the third gate pattern GPT3. The first connection pattern SDP1 may be defined as a first source-drain pattern.

[0178] The first connection pattern SDP1 may include a plurality of first connection electrodes CNE1 and CNE1-1 to CNE1-10, a first initialization line VIL1, a write scan line GWL, a first emission line EML1, and a bias line VBL. The first connection electrode CNE1 may be Figure 7 The first connection electrode CNE1 is shown in FIG.

[0179] The first initialization line VIL1 may be adjacent to the upper side of the pixel PX, and the bias line VBL may be adjacent to the lower side of the pixel PX. The initialization scan line GIL may be disposed between the first initialization line VIL1 and the write scan line GWL. The write scan line GWL may be disposed between the initialization scan line GIL and the horizontal reference line VLH. The horizontal reference line VLH may be disposed between the write scan line GWL and the compensation scan line GCL.

[0180] The compensation scan line GCL may be disposed between the horizontal reference line VLH and the second dummy electrode DME2. The second dummy electrode DME2 may be disposed between the compensation scan line GCL and the second emission line EML2. The second emission line EML2 may be disposed between the second dummy electrode DME2 and the first emission line EML1.

[0181] The first emission line EML1 may be disposed between the second emission line EML2 and the bias scan line GBL. The bias scan line GBL may be disposed between the first emission line EML1 and the second initialization line VIL2. The second initialization line VIL2 may be disposed between the bias scan line GBL and the bias line VBL.

[0182] The first connection electrodes CNE1-1 to CNE1-10, the first initialization line VIL1, the write scan line GWL, the first emission line EML1, and the bias line VBL may be disposed at the same layer as the first connection electrode CNE1. The first connection electrodes CNE1-1 to CNE1-10, the first initialization line VIL1, the write scan line GWL, the first emission line EML1, and the bias line VBL may be formed by synchronously patterning with the same material as that of the first connection electrode CNE1.

[0183] A plurality of first contact holes CH1 and CH1-1 to CH1-14 may be defined. The first contact hole CH1 may be Figure 7 The first contact hole CH1 is shown in FIG.

[0184] The first connection electrode CNE1 may be connected to the sixth drain region D6 of the sixth transistor T6 through the first contact hole CH1. The first connection electrode CNE1-1 may be connected to the separated initialization scan line GIL through the plurality of first contact holes CH1-1. Therefore, the separated initialization scan line GIL may be connected through the first connection electrode CNE1-1.

[0185] The first connection electrode CNE1-2 may be connected to the second source region S2 of the second transistor T2 through the first contact hole CH1-2. The first connection electrode CNE1-3 may be connected to the fifth drain region D5 of the fifth transistor T5 and the horizontal reference line VLH through a plurality of first contact holes CH1-3. Since the lower reference line VL-L extends from the fifth drain region D5, the lower reference line VL-L may be connected to the horizontal reference line VLH through the first connection electrode CNE1-3.

[0186] The first connection electrode CNE1-4 may be connected to the fifth source region S5 of the fifth transistor T5 and the first dummy electrode DME1 through a plurality of first contact holes CH1-4. The first connection electrode CNE1-4 may be connected to the first dummy electrode DME1 through a portion of the second opening portion OP2 that does not overlap the first opening portion OP1. The fifth transistor T5 may be connected to the first capacitor C1 (e.g., the first dummy electrode DME1) through the first connection electrode CNE1-4.

[0187] Since the second drain region D2 of the second transistor T2 extends from the fifth source region S5 , the second transistor T2 may also be connected to the first dummy electrode DME1 through the first connection electrode CNE1 - 4 .

[0188] The first connection electrode CNE1-5 may be connected to the third drain region D3 of the third transistor T3 and the first gate electrode G1 of the first transistor T1 through a plurality of first contact holes CH1-5. The first connection electrode CNE1-5 may be connected to the first gate electrode G1 through the first opening portion OP1 and the second opening portion OP2. The first transistor T1 and the third transistor T3 may be connected to each other through the first connection electrode CNE1-5.

[0189] The first connection electrode CNE1-6 may be connected to the sub-dummy electrode SDE and the horizontal reference line VLH through the plurality of first contact holes CH1-6. The sub-dummy electrode SDE may be connected to the horizontal reference line VLH through the first connection electrode CNE1-6.

[0190] The reference voltage VR may be applied to the sub-dummy electrode SDE through the horizontal reference line VLH. That is, the sub-dummy electrode SDE may receive a constant voltage. As described above, the sub-dummy electrode SDE may overlap with a portion of the semiconductor pattern SMP of the third transistor T3 and the fourth transistor T4. In this case, when the constant voltage is applied to the sub-dummy electrode SDE, the threshold voltage Vth of each of the third transistor T3 and the fourth transistor T4 overlapping the sub-dummy electrode SDE may be maintained without changing.

[0191] The first connection electrode CNE1-7 may be connected to the second dummy electrode DME2 through the first contact hole CH1-7. The first connection electrode CNE1-8 may be connected to the separated second emission line EML2 through the plurality of first contact holes CH1-8. Therefore, the separated second emission line EML2 may be connected through the first connection electrode CNE1-8.

[0192] The first connection electrode CNE1-9 may be connected to the second dummy electrode DME2 and the ninth source region S9 of the ninth transistor T9 through a plurality of first contact holes CH1-9. The second dummy electrode DME2 may be connected to the ninth source region S9 of the ninth transistor T9. Figure 8F The first power line PL1 will be described.

[0193] The first connection electrode CNE1-10 may be connected to the seventh drain region D7 of the seventh transistor T7 and the second initialization line VIL2 through the plurality of first contact holes CH1-10. The seventh transistor T7 may be connected to the second initialization line VIL2 through the first connection electrode CNE1-10.

[0194] The first initialization line VIL1 may be connected to the fourth drain region D4 of the fourth transistor T4 through the first contact hole CH1-11. The write scan line GWL may be connected to the second gate electrode G2 of the second transistor T2 through the first contact hole CH1-12. The first emission line EML1 may be connected to the ninth gate electrode G9 of the ninth transistor T9 through the first contact hole CH1-13. The bias line VBL may be connected to the eighth source region S8 of the eighth transistor T8 through the first contact hole CH1-14.

[0195] In the following, Figure 8F , reference symbols for the first connection electrodes CNE1 and CNE1-1 to CNE1-10 and the first contact holes CH1 and CH1-1 to CH1-14 are omitted, and in Figure 8F Reference symbols for the first connection electrodes CNE1 and CNE1-1 to CNE1-10 and the first contact holes CH1 and CH1-1 to CH1-14 omitted in Fig. 8E In.

[0196] Reference FIG. 8A to FIG. 8F, a second connection pattern SDP2 may be disposed on the first connection pattern SDP1. The second connection pattern SDP2 may be defined as a second source-drain pattern.

[0197] The second connection pattern SDP2 may include a second connection electrode CNE2, a data line DL, a first power line PL1, and a vertical reference line VLV. The second connection electrode CNE2 may be Figure 7 The second connection electrode CNE2 is shown in FIG.

[0198] The data line DL, the first power line PL1 and the vertical reference line VLV may be disposed at the same layer as the second connection electrode CNE2. The data line DL, the first power line PL1 and the vertical reference line VLV may be provided by being simultaneously patterned with the same material as the second connection electrode CNE2.

[0199] The data line DL, the first power line PL1, and the vertical reference line VLV may extend in the first direction DR1 to be arranged in the second direction DR2. The first power line PL1 may be disposed between the data line DL and the vertical reference line VLV.

[0200] A plurality of second contact holes CH2 and CH2-1 to CH2-3 may be defined. The second contact hole CH2 may be Figure 7 The second contact hole CH2 is shown in FIG.

[0201] The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through the second contact hole CH2. The second connection electrode CNE2 may be connected to the first electrode AE ​​through the third contact hole CH3. For convenience of explanation, the first electrode AE ​​is omitted in the layout diagram of the pixel PX. The first electrode AE ​​may be connected to the sixth transistor T6 through the first connection electrode CNE1 and the second connection electrode CNE2.

[0202] The sixth semiconductor layer S6, A6, and D6 of the sixth transistor T6 may extend to the first drain region D1, and the sixth drain region D6 may be connected to the first electrode AE. Therefore, the first drain region D1 may be connected to the light emitting element ED.

[0203] The data line DL may be connected to the first connection electrode CNE1-2 through the second contact hole CH2-1. The data line DL may be connected to the second transistor T2 through the first connection electrode CNE1-2.

[0204] The first power line PL1 may be connected to the first connection electrode CNE1-7 through the second contact hole CH2-2. The first power line PL1 may be connected to the second dummy electrode DME2 through the first connection electrode CNE1-7. Therefore, the ninth transistor T9 and the second capacitor C2 (eg, the second dummy electrode DME2) may be connected to the first power line PL1.

[0205] The ninth semiconductor layer S9, A9 and D9 of the ninth transistor T9 may extend from the first source region S1, the ninth drain region D9 may be connected to the second dummy electrode DME2, and the second dummy electrode DME2 may be connected to the first power line PL1. Therefore, the first source region S1 may be connected to the first power line PL1.

[0206] The vertical reference line VLV may be connected to the horizontal reference line VLH through the second contact hole CH2-3. Therefore, the vertical reference line VLV, the horizontal reference line VLH, and the lower reference line VL-L may be connected to each other. The reference voltage VR may be applied to the fifth transistor T5 through the vertical reference line VLV, the horizontal reference line VLH, and the lower reference line VL-L. The above-mentioned reference line VL may include the vertical reference line VLV, the horizontal reference line VLH, and the lower reference line VL-L.

[0207] Fig. 9 It is shown in Fig. 8E and Figure 8F Schematic diagram of the cross section of the contact holes defined at different positions in the FIG.

[0208] Reference Fig. 9 The first connection electrodes CNE1-2, CNE1-4, CNE1-5, CNE1-7, and CNE1 may be disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may be disposed on the first connection electrodes CNE1-2, CNE1-4, CNE1-5, CNE1-7, and CNE1. The second connection electrode CNE2 may be disposed on the fifth insulating layer INS5.

[0209] The second source region S2 of the second transistor T2 may be disposed on the buffer layer BFL, and the first insulating layer INS1 may be disposed on the second source region S2. The first gate electrode G1 of the first transistor T1 may be disposed on the first insulating layer INS1, and the second insulating layer INS2 may be disposed on the first gate electrode G1.

[0210] The first dummy electrode DME1 may be disposed on the second insulating layer INS2, and the third insulating layer INS3 may be disposed on the first dummy electrode DME1. The second dummy electrode DME2 may be disposed on the third insulating layer INS3, and the fourth insulating layer INS4 may be disposed on the second dummy electrode DME2.

[0211] The first connection electrode CNE1-2 may be connected to the second source region S2 through a first contact hole CH1-2 defined in the first to fourth insulating layers INS1 to INS4. The first connection electrode CNE1-5 may be connected to the first gate electrode G1 through a first contact hole CH1-5 defined in the second to fourth insulating layers INS2 to INS4.

[0212] The first link electrode CNE1-4 may be connected to the first dummy electrode DME1 through a first contact hole CH1-4 defined in the third and fourth insulating layers INS3 and INS4. The first link electrode CNE1-7 may be connected to the second dummy electrode DME2 through a first contact hole CH1-7 defined in the fourth insulating layer INS4.

[0213] The connection structure between each of the first and second link electrodes CNE1 and CNE2 and the sixth drain region D6 is as described above with reference to Figure 7 description is made, and thus it is omitted.

[0214] Fig.10 It specifically shows Figure 8C A view of the type of pixel shown in FIG. 1 and additionally showing the region of the first capacitor and the region of the parasitic capacitor around the first capacitor in separate hatching. Fig.11 are shown as separate shadings Fig.8D A view of the area of ​​the second capacitor.

[0215] As an example, in Fig.10 , the region of the first capacitor C1 and the regions of the parasitic capacitors PC1 and PC2 around the first capacitor C1 are shown with different shadings.

[0216] Reference Figure 8C and Fig.10 ,exist Fig.10 middle, Figure 8C The pixel PX shown in the figure may include a first pixel PXr and a second pixel PXg adjacent to each other in the second direction DR2, or a third pixel PXb and a second pixel PXg arranged in the second direction DR2. The first pixel PXr may be defined as a red pixel emitting light having a red color, the second pixel PXg may be defined as a green pixel emitting light having a green color, and the third pixel PXb may be defined as a blue pixel emitting light having a blue color.

[0217] The planar structure (or layout) of the first pixel PXr and the second pixel PXg may be substantially the same as the planar structure (or layout) of the third pixel PXb and the second pixel PXg. Therefore, hereinafter, the configuration of the first pixel PXr and the second pixel PXg will be described based on the first pixel PXr and the second pixel PXg.

[0218] The layout of the first pixel PXr and the layout of the second pixel PXg may be symmetrical with respect to a boundary line extending in the first direction DR1 between the first pixel PXr and the second pixel PXg. Therefore, the first transistor T1 to the ninth transistor T9 and the first capacitor C1 and the second capacitor C2 of the first pixel PXr may have a structure symmetrical with the first transistor T1 to the ninth transistor T9 and the first capacitor C1 and the second capacitor C2 of the second pixel PXg in the second direction DR2.

[0219] The first pixel PXr and the second pixel PXg may share an eighth transistor T8 (eg, a bias transistor). One eighth transistor T8 may be disposed between the first pixel PXr and the second pixel PXg, and one eighth transistor T8 may be a bias transistor of the first pixel PXr and a bias transistor of the second pixel PXg.

[0220] When the first pixel PXr includes the eighth transistor T8 and the second pixel PXg also includes the eighth transistor T8, two eighth transistors T8 may need to be provided in the first pixel PXr and the second pixel PXg. Therefore, in order to provide two eighth transistors T8, more surface areas of the first pixel PXr and the second pixel PXg may be required.

[0221] However, in an embodiment of the present inventive concept, the first pixel PXr and the second pixel PXg share one eighth transistor T8, avoiding the need for more surface area of ​​the first pixel PXr and the second pixel PXg. In fact, by making the first pixel PXr and the second pixel PXg share the eighth transistor T8, the total surface area of ​​the first pixel PXr and the second pixel PXg required can even be reduced. When the surface area of ​​the first pixel PXr and the second pixel PXg is reduced, the number of pixels PX of the display panel DP can be increased, and the resolution of the display device DD can be improved.

[0222] A sharing node CN may be defined between the first pixel PXr and the second pixel PXg. A first source region S1 of a first transistor T1 (e.g., a driving transistor) of the first pixel PXr and a first source region S1 of a first transistor T1 (e.g., a driving transistor) of the second pixel PXg may be commonly connected to the sharing node CN. An eighth transistor T8 may be connected to the sharing node CN.

[0223] The first source region S1 of the first transistor T1 of the first pixel PXr and the first source region S1 of the first transistor T1 of the second pixel PXg may be integrally formed with the same semiconductor pattern SMP. Figure 8B The eighth transistors T8 and T9 may be connected in common to the first source region S1.

[0224] In the following, reference is made to Fig.10 and Fig.11 The configuration of the first capacitor C1 and the second capacitor C2 of the first pixel PXr is described.

[0225] The first capacitor C1 may include the first gate electrode G1 and a portion of the first dummy electrode DME1 overlapping the first gate electrode G1 when viewed in a plane. That is, the first capacitor C1 may be provided by the first gate electrode G1 and a portion of the first dummy electrode DME1 overlapping the first gate electrode G1.

[0226] The first dummy electrode DME1 may overlap the first semiconductor layers S1, A1, and D1 of the first transistor T1 when viewed on a plane. The first dummy electrode DME1 may extend outward from the first gate electrode G1. The first dummy electrode DME1 may extend further in the second direction DR2 than in the first direction DR1.

[0227] The first dummy electrode DME1 may include a first portion PT1 and a second portion PT2 extending outward from the first gate electrode G1. The first portion PT1 and the second portion PT2 may extend in a second direction DR2. The first portion PT1 and the second portion PT2 may extend in opposite directions relative to the first gate electrode G1. The first portion PT1 may be located between the second portion PT2 and the shared node CN.

[0228] In each figure (for example, Fig.10 ), the first capacitor C1 and the first portion PT1 and the second portion PT2 are shown with different shadings.

[0229] The first portion PT1 may be defined as a portion of the first dummy electrode DME1 overlapping the first source region S1 outside the first gate electrode G1 when viewed on a plane. The second portion PT2 may be defined as a portion of the first dummy electrode DME1 overlapping the first drain region D1 outside the first gate electrode G1 when viewed on a plane.

[0230] When viewed on a plane, the surface area of ​​the first portion PT1 may be different in size from the surface area of ​​the second portion PT2. Specifically, the surface area of ​​the first portion PT1 may be smaller than the surface area of ​​the second portion PT2.

[0231] In the extension direction (eg, second direction DR2 ) of the first dummy electrode DME1 , the length of the first portion PT1 may be different from the length of the second portion PT2 . Specifically, the length of the first portion PT1 may be smaller than the length of the second portion PT2 .

[0232] The first parasitic capacitor PC1 may be provided by the first portion PT1 and the first source region S1. The second parasitic capacitor PC2 may be provided by the second portion PT2 and the first drain region D1.

[0233] The first parasitic capacitance of the first parasitic capacitor PC1 may be different from the second parasitic capacitance of the second parasitic capacitor PC2. Since the capacitance of a capacitor is proportional to the surface area, the first parasitic capacitance of the first parasitic capacitor PC1 may be smaller than the second parasitic capacitance of the second parasitic capacitor PC2.

[0234] The ninth transistor T9 (or the second emission control transistor) of the first pixel PXr and the ninth transistor T9 (or the second emission control transistor) of the second pixel PXg may be commonly connected to the sharing node CN to be connected to the first source region S1.

[0235] The lower reference line VL-L may be disposed between the first pixel PXr and the second pixel PXg to extend in the first direction DR1. The lower reference line VL-L may be formed from the semiconductor layers S5, A5, and D5 (reference symbols in FIG. 1 ) of the fifth transistor T5 (or reference transistor) of each of the first pixel PXr and the second pixel PXg. Figure 8B ) extension.

[0236] The fifth transistor T5 (or reference transistor) of the first pixel PXr and the fifth transistor T5 (or reference transistor) of the second pixel PXg may be commonly connected to the lower reference line VL-L extending in the first direction DR1. That is, the fifth transistor T5 of the first pixel PXr and the fifth transistor T5 of the second pixel PXg may share the lower reference line VL-L extending in the first direction DR1.

[0237] When the lower reference line VL-L extending in the first direction DR1 is disposed in the first pixel PXr and also separately disposed in the second pixel PXg, more surface areas of the first pixel PXr and the second pixel PXg may be required to accommodate the two lower reference lines VL-L.

[0238] However, in an embodiment of the present inventive concept, the first pixel PXr and the second pixel PXg share a lower reference line VL-L, avoiding the need for a larger surface area of ​​the first pixel PXr and the second pixel PXg. In fact, by having the first pixel PXr and the second pixel PXg share the lower reference line VL-L, the required total surface area of ​​the first pixel PXr and the second pixel PXg can even be reduced. When the surface area of ​​the first pixel PXr and the second pixel PXg is reduced, the number of pixels PX of the display panel DP can be increased, and thus the resolution of the display device DD can be improved.

[0239] Reference Fig.11, the second capacitor C2 may include the first dummy electrode DME1, and a portion of the second dummy electrode DME2 overlapping the first dummy electrode DME1 when viewed on a plane. That is, the second capacitor C2 may be provided by the first dummy electrode DME1, and a portion of the second dummy electrode DME2 overlapping the first dummy electrode DME1. The second dummy electrode DME2 may overlap the second portion PT2 more than the first portion PT1.

[0240] Fig.12 It is shown Fig.10 Schematic block diagram of a first pixel and a second pixel shown in .

[0241] exist Fig.12 In the embodiment of FIG. 5 , a first pixel PXr and a second pixel PXg adjacent to each other in the second direction DR2 and a third pixel PXb and a second pixel PXg adjacent to each other in the second direction DR2 are shown.

[0242] Reference Fig.10 , Fig.11 and Fig.12 , the above-mentioned pixels PX may be grouped into a first pixel group PG1 and a second pixel group PG2. For example, the first pixel group PG1 may include a first pixel PXr and a second pixel PXg, and the second pixel group PG2 may include a third pixel PXb and a second pixel PXg. Although not shown, each of the first pixel group PG1 and the second pixel group PG2 may be provided in plurality, and the first pixel group PG1 and the second pixel group PG2 may be repeatedly arranged in the first direction DR1 and the second direction DR2.

[0243] The first pixel PXr and the second pixel PXg may be disposed adjacent to each other in the second direction DR2 and connected to each other through the first sharing node CN1. The first sharing node CN1 may be positioned between the first pixel PXr and the second pixel PXg. The third pixel PXb and the second pixel PXg may be disposed adjacent to each other in the second direction DR2 to be connected to each other through the second sharing node CN2. The second sharing node CN2 may be positioned between the third pixel PXb and the second pixel PXg. Each of the first sharing node CN1 and the second sharing node CN2 may correspond to Fig.10 The shared node CN shown in .

[0244] The layout of the first pixel PXr and the second pixel PXg may be similar to Fig.10 The layout of the third pixel PXb and the second pixel PXg may also be the same as shown in FIG. Fig.10 The layout shown in is essentially the same.

[0245] For convenience of explanation, in each of the first pixel PXr, the second pixel PXg and the third pixel PXb, the first to seventh transistors T1 to T7, the ninth transistor T9, the first capacitor C1 and the second capacitor C2, and the light emitting element ED are shown as a large block, and the eighth transistor T8 is shown as a separate small block.

[0246] The first pixel PXr and the second pixel PXg may include one eighth transistor T8 connected to the first sharing node CN1. In addition, the third pixel PXb and the second pixel PXg may include one eighth transistor T8 connected to the second sharing node CN2. The eighth transistor T8 may be disposed at a boundary between the first pixel PXr and the second pixel PXg and at a boundary between the third pixel PXb and the second pixel PXg, respectively.

[0247] The display device DD may include a plurality of first switches SW1 respectively connected to the first and third pixels PXr and PXb, and a plurality of second switches SW2 respectively connected to the second pixels PXg. The first and second switches SW1 and SW2 may be respectively connected to the data lines DL.

[0248] The first switch SW1 may be switched by the first control signal CS1, and the second switch SW2 may be switched by the second control signal CS2. The first switch SW1 and the second switch SW2 may be turned on alternately. The first switch SW1 and the second switch SW2 may be turned on to supply the first data voltage Vr, the second data voltage Vg, and the third data voltage Vb received through the data line DL to the first pixel PXr, the second pixel PXg, and the third pixel PXb, respectively.

[0249] When the first switch SW1 is turned on, the first data voltage Vr may be applied to the first pixel PXr and the third data voltage Vb may be applied to the third pixel PXb through the data line DL. When the second switch SW2 is turned on, the second data voltage Vg may be applied to the second pixels PXg through the data lines DL, respectively.

[0250] Reference Fig.10 The first parasitic capacitance of the first parasitic capacitor PC1 provided by the first portion PT1 may affect the voltage of the shared node CN. For example, a kick back voltage may be generated due to the first parasitic capacitance, thereby affecting the shared node CN.

[0251] The first data voltage Vr applied to the first pixel PXr and the third data voltage Vb applied to the third pixel PXb may have different levels. The first parasitic capacitance (eg, Fig.10The first parasitic capacitance of the first parasitic capacitor PC1 in FIG. 4 may affect the first sharing node CN1. The second pixel PXg connected to the first pixel PXr may be affected by the voltage of the first sharing node CN1.

[0252] The first parasitic capacitance of the third pixel PXb (eg, Fig.10 The first parasitic capacitance of the first parasitic capacitor PC1 in the first pixel PXb may affect the second sharing node CN2. The second pixel PXg connected to the third pixel PXb may be affected by the voltage of the second sharing node CN2.

[0253] When the first data voltage Vr and the third data voltage Vb have different levels, a kickback voltage according to the first parasitic capacitance of the first pixel PXr and a kickback voltage according to the first parasitic capacitance of the third pixel PXb may be different from each other. In this case, even if the second data voltage Vg is applied to the second pixels PXg, respectively, the brightness of the second pixel PXg connected to the first pixel PXr and the brightness of the second pixel PXg connected to the third pixel PXb may be different from each other.

[0254] As the first parasitic capacitance of the first pixel PXr and the first parasitic capacitance of the third pixel PXb increase, the difference in kickback voltage may increase more. Therefore, the brightness difference between the second pixel PXg connected to the first pixel PXr and the second pixel PXg connected to the third pixel PXb may increase more. When the brightness difference increases, striped stains that cause the user to recognize the brightness difference may be generated.

[0255] like Fig.10 As shown in , in an embodiment of the present inventive concept, the first portion PT1 may have a surface area smaller than that of the second portion PT2, so that the first portion PT1 has a parasitic capacitance smaller than that of the second portion PT2. That is, the first parasitic capacitance of the first parasitic capacitor PC1 provided by the first portion PT1 may be reduced.

[0256] Therefore, the first parasitic capacitance of the first pixel PXr adjacent to the first sharing node CN1 and the first parasitic capacitance of the third pixel PXb adjacent to the second sharing node CN2 can be reduced. In this case, the difference between the kickback voltage according to the first parasitic capacitance of the first pixel PXr and the kickback voltage according to the first parasitic capacitance of the third pixel PXb can be reduced. Therefore, the brightness difference between the second pixel PXg connected to the first pixel PXr and the second pixel PXg connected to the third pixel PXb can be reduced.

[0257] Since the capacitance of the second capacitor C2 increases, the change in the gate-source voltage level of the third transistor T3 and the fourth transistor T4 can be further reduced. In an embodiment of the inventive concept, the second portion PT2 can be made larger than the first portion PT1, rather than making the first portion PT1 smaller. The second portion PT2 of the first dummy electrode DME1 can be enlarged so that the surface area of ​​the first dummy electrode DME1 overlapping with the second dummy electrode DME2 is larger. Therefore, the first parasitic capacitance of the first parasitic capacitor PC1 can be reduced, and the capacitance of the second capacitor C2 can be increased.

[0258] Fig.13 and Fig.14 is a view illustrating the shape of a first portion according to various embodiments of the inventive concept.

[0259] Fig.13 and Fig.14 Shown with Fig.10 The view shown in the figure corresponds to the plan view. Fig.10 The components shown in the figure are different from the components described in Fig.13 and Fig.14 The parts shown in .

[0260] Reference Fig.13 When viewed on a plane, a groove GV1 may be defined in one side of the first source region S1 extending to the outside of the first gate electrode G1. As used herein, the phrase "one side" of the first source region S1 may be one of two sides of the first source region S1 opposite to each other in the first direction DR1.

[0261] The first portion PT1-1 may be defined as a portion of the first dummy electrode DME1 extending to the outside of the first gate electrode G1 to overlap the first source region S1. Fig.10 The surface area of ​​the first portion PT1 shown in FIG. 1 is small. Therefore, the first parasitic capacitance of the first parasitic capacitor PC1 - 1 provided by the first portion PT1 - 1 and the first source region S1 may be reduced.

[0262] Reference Fig.14 , when viewed on a plane, a groove GV2 may be defined in the other side of the first source region S1 extending to the outside of the first gate electrode G1. As used herein, the "other side" of the first source region S1 may be a side of the first source region S1 opposite to the "one side".

[0263] The first portion PT1-2 may be a portion of the first dummy electrode DME1 extending to the outside of the edge of the first gate electrode G1 to overlap the first source region S1. Fig.10The surface area of ​​the first portion PT1 shown in FIG. 1 is small. Therefore, the first parasitic capacitance of the first parasitic capacitor PC1 - 2 provided by the first portion PT1 - 2 and the first source region S1 may be reduced.

[0264] According to an embodiment of the inventive concept, the first pixel and the second pixel may share a bias transistor and a reference line extending in the first direction. Therefore, a surface area for arrangement of elements may be reduced, and thus, a resolution of a display device may be improved.

[0265] Furthermore, the capacitance of the parasitic capacitor adjacent to the shared node between each of the first and third pixels and the second pixel may be reduced to reduce a brightness difference between the second pixel of the first pixel group and the second pixel of the second pixel group.

[0266] Although the embodiments of the present disclosure are described, it should be understood that the present disclosure should not be limited to these embodiments. Within the spirit and scope of the present disclosure, those of ordinary skill in the art can make various changes and modifications. The embodiments set forth herein are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art.

Claims

1. A display device, comprising: First pixel; as well as The second pixel, Wherein, each of the first pixel and the second pixel comprises: Light emitting element; a driving transistor connected to the light emitting element and a power supply line, wherein the driving transistor is controlled by the voltage of the first node; a switch transistor connected to the data line and the second node, wherein the switch transistor is controlled by a write scan signal; a capacitor connected to the first node and the second node; and a bias transistor connected to the drive transistor and a bias line, wherein the bias transistor is controlled by a bias scan signal, The first pixel and the second pixel share the bias transistor.

2. The display device according to claim 1, wherein: The driving transistor comprises: a semiconductor layer, the semiconductor layer comprising a source region, a drain region, and a channel region between the source region and the drain region; and a gate electrode disposed on the channel region to define the first node, The source region of the driving transistor of the first pixel and the source region of the driving transistor of the second pixel are connected to a shared node.

3. The display device according to claim 2, wherein: The source region of the driving transistor of the first pixel and the source region of the driving transistor of the second pixel are integrally formed.

4. The display device according to claim 2, wherein: The bias transistor is connected to the shared node.

5. The display device according to claim 2, wherein: The semiconductor layer of the bias transistor extends from the source region of the drive transistor of the first pixel and is integrated with the source region of the drive transistor of the second pixel.

6. The display device according to claim 2, wherein: The source region of the driving transistor is connected to the power supply line, and the drain region of the driving transistor is connected to the light emitting element.

7. The display device according to claim 2, further comprising: a dummy electrode disposed on the gate electrode to define the second node and overlap the semiconductor layer, Wherein, the dummy electrode comprises: a first portion extending from the gate electrode and overlapping the source region; and A second portion extends from the gate electrode and overlaps the drain region.

8. The display device according to claim 7, wherein: The capacitor comprises: the gate electrode; and A portion of the dummy electrode overlaps with the gate electrode.

9. The display device according to claim 7, wherein: A first parasitic capacitance provided by the source region and the first portion is different from a second parasitic capacitance provided by the drain region and the second portion.

10. The display device according to claim 9, wherein: The first parasitic capacitance is smaller than the second parasitic capacitance.

11. The display device according to claim 7, wherein: A surface area of ​​the first portion and a surface area of ​​the second portion are different from each other.

12. The display device according to claim 11, wherein: The surface area of ​​the first portion is smaller than the surface area of ​​the second portion.

13. The display device according to claim 7, wherein: In an extending direction of the dummy electrode, a length of the first portion is different from a length of the second portion.

14. The display device according to claim 13, wherein: In the extending direction of the dummy electrode, the length of the first portion is smaller than the length of the second portion.

15. The display device according to claim 2, wherein: Each of the first pixel and the second pixel further includes an emission control transistor connected to the power supply line and the source region, Wherein, the emission control transistor is controlled by an emission signal, Wherein the emission control transistor of the first pixel and the emission control transistor of the second pixel are connected to the shared node.

16. The display device according to claim 1, wherein: The first pixels and the second pixels are arranged in a second direction intersecting the first direction, and Each of the first pixel and the second pixel further includes a reference transistor connected to the second node and a reference line extending in the first direction, wherein the reference transistor is controlled by a compensation scan signal, The reference transistor of the first pixel and the reference transistor of the second pixel share the reference line.

17. The display device according to claim 16, wherein: The reference line extends from a semiconductor layer of each of the reference transistor of the first pixel and the reference transistor of the second pixel.

18. The display device according to claim 1, wherein: A layout of the driving transistor and the switching transistor of the first pixel and a layout of the driving transistor and the switching transistor of the second pixel are symmetrical with respect to a boundary line between the first pixel and the second pixel.

19. A display device comprising: First pixel; as well as The second pixel, Wherein, each of the first pixel and the second pixel comprises: Light emitting element: A driving transistor, wherein the driving transistor comprises a semiconductor layer including a source region connected to a power line, a drain region connected to the light emitting element, and a channel region between the source region and the drain region, and a gate electrode disposed on the channel region; a dummy electrode, the dummy electrode being disposed on the gate electrode; and a switching transistor connected to the data line and the dummy electrode, Wherein, the switch transistor is controlled by a write scan signal, wherein the source region of the driving transistor of the first pixel and the source region of the driving transistor of the second pixel are connected to a shared node, Wherein, the dummy electrode comprises: a first portion extending from the gate electrode and overlapping the source region to provide a first parasitic capacitance; and a second portion extending from the gate electrode and overlapping the drain region to provide a second parasitic capacitance, Wherein, the first parasitic capacitance is smaller than the second parasitic capacitance.

20. A display device, comprising: First pixel; as well as The second pixel, Wherein, each of the first pixel and the second pixel comprises: Light emitting element: A driving transistor, wherein the driving transistor comprises a semiconductor layer including a source region connected to a power line, a drain region connected to the light emitting element, and a channel region between the source region and the drain region; and a gate electrode arranged on the channel region; a dummy electrode, wherein the dummy electrode is disposed on the gate electrode; a switching transistor connected to the data line and the dummy electrode, the switching transistor being controlled by a write scan signal; and a bias transistor connected to the source region and a bias line, the bias transistor being controlled by a bias scan signal, The first pixel and the second pixel share the bias transistor.

Images