Integrated circuit device, memory circuit and operating method thereof

Abstract

An integrated circuit device includes first and second transistors and a memory device. The first transistor includes a first source / drain (S / D) terminal coupled to the first select line, a second S / D terminal, and a gate coupled to the first word line. The second transistor includes a first S / D terminal coupled to the first bit line, a second S / D terminal, and a gate. The memory device is coupled to a second S / D terminal of the second transistor, and the first storage node includes a second S / D terminal of the first transistor and a gate of the second transistor. The embodiment of the invention also discloses a memory circuit and a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices, memory circuits, and methods of operating the same. Background Art

[0002] In many applications, integrated circuits (ICs) include memory circuits that store data used by other circuit components (e.g., logic, processor, or computing circuits). The memory circuits may include volatile memory, such as dynamic random access memory (DRAM), where data retention depends on the IC being powered on, and in some cases, the stored data is refreshed periodically. The memory circuits may also include non-volatile memory (NVM), such as resistive random access memory (RRAM), where data is retained during periods when the IC is powered off. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, an integrated circuit (IC) device is provided, comprising: a first transistor, comprising: a first source / drain (S / D) terminal, coupled to a first selection line; a second S / D terminal; and a gate, coupled to a first word line; a second transistor, comprising: a first S / D terminal, coupled to a first bit line; a second S / D terminal; and a gate; a first memory device, coupled to the second S / D terminal of the second transistor; and a first storage node, comprising the second S / D terminal of the first transistor and the gate of the second transistor.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: an array of memory cells arranged in rows and columns; a row decoder coupled to a plurality of first word lines corresponding to the rows of memory cells; and a read / write (R / W) interface coupled to a plurality of selection bit lines and a first bit line corresponding to the columns of memory cells, wherein each memory cell of the array comprises: a first transistor comprising: a first source / drain (S / D) terminal coupled to a corresponding selection line among a plurality of selection lines; a second S / D terminal; and a gate coupled to a corresponding first word line among a plurality of first word lines; a second transistor comprising: a first S / D terminal coupled to a corresponding first bit line among a plurality of first bit lines; a second S / D terminal; and a gate; a memory device coupled to the second S / D terminal of the second transistor; and a first storage node comprising the second S / D terminal of the first transistor and the gate of the second transistor.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, the method comprising: writing a data bit to a first memory cell by the following steps: outputting a word line signal having a first logic level to a gate of a first transistor of the first memory cell, the first transistor comprising a first source / drain (S / D) terminal coupled to a first selection line and a second S / D terminal coupled to a storage node of the first memory cell; outputting a first selection signal having a first logic level to the first selection line; receiving a first charge corresponding to the first logic level of the first selection signal from the first transistor at a storage node and a gate of a second transistor of the first memory cell coupled to the storage node; in response to receiving the first charge, coupling a memory device of the first memory cell to a first bit line using a second transistor; and outputting the data bit to the first bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a memory circuit according to some embodiments.

[0008] Figure 2A and Figure 2B is a schematic diagram of a memory cell according to some embodiments.

[0009] Figure 3A , Figure 3B and Figure 3C is a schematic diagram of a memory cell according to some embodiments.

[0010] Figure 4 is a cross-sectional view of an IC device according to some embodiments.

[0011] Figure 5 is a cross-sectional view of an IC device according to some embodiments.

[0012] Figure 6A-6F Operational parameters of a memory circuit according to some embodiments are depicted.

[0013] Figure 7 is a flow chart of a method of operating a memory circuit according to some embodiments.

[0014] Figure 8 is a flow chart of a method of manufacturing a memory circuit according to some embodiments. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0017] In various embodiments, a memory cell and method include first and second transistors, a memory device coupled to a first source / drain (S / D) terminal of the second transistor, and a storage node including a first S / D terminal of the first transistor and a gate of the second transistor. The second S / D terminal and gate of the first transistor are coupled to a select line and a word line, respectively, and the second S / D terminal of the second transistor is coupled to a bit line. Thus, the memory cell can be used in a memory circuit in which a combination of a word line and a select signal is used to uniquely couple a selected memory device to a corresponding bit line, thereby avoiding a disturb condition of a half-selected memory cell.

[0018] By avoiding half-select disturb conditions, power consumption during write operations is reduced, for example, by selecting memory cells using only word line signals, compared to methods that rewrite data to address half-select disturb conditions caused by coupling non-selected memory devices to bit lines.

[0019] According to various embodiments, Figure 1 is a schematic diagram of a memory circuit 100, Figure 2A-Figure 3C is a schematic diagram of memory cells 200N and 200P that may be used in the memory circuit 100, Figure 4 and Figure 5 is a cross-sectional view of IC devices 400 and 500 that can be used in memory cells 200N and 200P, 6A to 6F depicts non-limiting examples of operating parameters of memory circuit 100, Figure 7 FIG. 8 is a flow chart of a method 700 of operating a memory circuit, and FIG. 9 is a flow chart of a method 800 of manufacturing a memory circuit.

[0020] In some embodiments, the memory circuit 100 is some or all of an integrated circuit (IC). In some embodiments, the memory circuit 100 is included in another IC circuit and / or package, such as a digital circuit, an analog circuit, a computing-in-memory (CIM) circuit, a near-memory computing (NMC) circuit located in a fan-out, 3D, 2.5D or other IC package, and / or other suitable circuit.

[0021] For ease of explanation, Figure 1-6F In some embodiments, one or more of the memory circuit 100, the memory cell 200N or 200P, or the IC device 400 or 500 may be simplified. Figure 1-6F In addition to the features shown in , other features may be included, such as global control and / or input / output (I / O) circuits configured to generate one or more signals including and / or in addition to the signals discussed below. Figure 1-6F Some of the circuit elements depicted in include corresponding input and / or output terminals, which are not labeled for the sake of clarity.

[0022] Figure 1 1 is a schematic diagram of a memory circuit 100 according to some embodiments. The memory circuit 100 includes an array 110 of memory cells 112 coupled to a word line driver 120 and a read / write (R / W) interface 130, and a control circuit 140 coupled to the word line driver 120 and the R / W interface 130 via a control signal bus CTRLB. The memory circuit 100 is configured to be able to perform some or all of the methods, such as the following about Figure 7 The method 700 is discussed, wherein data is written to and / or read from one or more instances in the memory unit 112, as follows.

[0023] Two or more circuit elements are considered coupled based on one or more direct signal connections between the two or more circuit elements and / or one or more indirect signal connections including one or more logic devices (e.g., inverters or logic gates). In some embodiments, signal communication between two or more coupled circuit elements can be modified by one or more logic devices (e.g., such as inversion or conditional).

[0024] exist Figure 1In the illustrated embodiment, the memory circuit 100 is configured as a dynamic random access memory (DRAM) circuit, including a memory cell 112 configured as a DRAM cell, wherein the stored data is refreshed over time, such as periodically. In some embodiments, the memory circuit 100 is configured as a memory circuit in other ways, such as, for example, as a non-volatile memory (NVM) circuit, including the memory cell 112 configured as an NVM cell.

[0025] The array 110 includes memory cells 112 (single instances labeled for clarity) arranged in rows and columns (not labeled). Each memory cell 112 in each row of memory cells 112 is coupled to each of word lines WWL1-WL4 and word lines RWL1-RWL4, and each memory cell 112 in each column of memory cells 112 is coupled to each of bit lines WBL1-WBL4, bit lines RBL1-RBL4, and select lines YSEL1-YSEL4.

[0026] For clarity, in addition to corresponding word lines, bit lines, and select lines, reference indicators WWL1-WL4 and RWL1-RWL4 also represent word line signals, reference indicators WBL1-WBL4 and RBL1-RBL4 also represent bit line signals, and reference indicators YSEL1-YSEL4 also represent select signals, each of which is discussed below.

[0027] exist Figure 1 In the illustrated embodiment, for purposes of illustration, array 110 includes a total number of rows and columns equal to four. In various embodiments, array 110 includes a total number of rows and / or columns less than or greater than four.

[0028] exist Figure 1 In the illustrated embodiment, array 110 includes rows and columns (not labeled) arranged along respective row and column dimensions. In some embodiments, array 110 has a three-dimensional (3D) arrangement, also referred to as a stacked arrangement, which includes one or more array layers (not shown) that are arranged perpendicular to the Figure 1 The row and column dimensions of the single layer shown are arranged so that the array 110 includes, in addition to Figure 1 rows and columns other than those shown in .

[0029] exist Figure 1 In the illustrated embodiment, each memory cell 112 is a five-terminal device including terminals coupled to respective ones of word lines WWL1-WL4, word lines RWL1-RWL4, bit lines WBL1-WBL4, bit lines RBL1-RBL4, and select lines YSEL1-YSEL4. Each memory cell 112 corresponds to the following reference numerals: Figure 2A-Figure 5 One of the memory cells 200N or 200P is discussed.

[0030] In some embodiments, for example, as described below with reference to Figure 3C As discussed, the memory circuit 100 does not include one or both of the word lines RWL1-RWL4 or the bit lines RBL1-RBL4, and each memory cell 112 is a four-terminal device including terminals coupled to respective ones of the word lines WWL1-WL4, the bit lines WBL1-WBL4, and the select lines YSEL1-YSEL4.

[0031] Through the configuration discussed below, each memory cell 112 includes a memory device ( Figure 1 1-14), such as a memory device 210 discussed below, and configured to couple the memory device to respective bit lines WBL1-WBL4 in response to a combination of word line signals received from respective word lines WWL1-WL4 and select signals received from respective select lines YSEL1-YSEL4 during a write operation. In some embodiments, the memory cell 112 is referred to as a cross-point memory cell 112.

[0032] The word line driver 120, also referred to as a row decoder 120 or a multiplexer 120 in some embodiments, is an electronic circuit configured to output word line signals WWL1-WWL4 and RWL1-RWL4 on corresponding word lines WWL1-WWL4 and RWL1-RWL4 (also referred to as write word lines WWL1-WWL4 and read word lines RWL1-RWL4 in some embodiments) in response to a control signal CTRL received from a control circuit 140 on a control signal bus CTRLB and / or from one or more circuits (not shown) external to the memory circuit 100.

[0033] In some embodiments, the signal (e.g., control signal CTRL or word line signal) is a time-based series of transitions between a high voltage level and a low voltage level, for example, corresponding to a high logic level and a low logic level. The high voltage or high logic level corresponds to a voltage within a predefined range of a power supply voltage level (e.g., a VDD voltage level), and the low voltage or low logic level corresponds to a current within a predefined range of a reference voltage level (e.g., a VSS or ground voltage level).

[0034] In a write operation, the word line driver 120 is configured to output a word line signal WWL1-WWL4, also referred to as a word line write signal WWL1-WL4 in some embodiments, on a corresponding one of the word lines WWL1-WWL4, for example, corresponding to the row address Xaddr, including one of a high or low logic level, in response to one or more control signals CTRL. Each memory cell 112 coupled to one of the word lines WWL1-WL4 is configured to couple the memory device to a corresponding one of the bit lines WBL1-WBL4 in response to the word line signal WWL1-WWL4 having one of a high or low logic level, and also in response to a corresponding select signal YSEL1-YSEL4 as described below.

[0035] The word line driver 120 is thus configured to output word line signals WWL1 - WWL4 on word lines WWL1 - WWL4 that are configured to, in part, cause each memory cell 112 to couple the included memory device to a corresponding one of the bit lines WBL1 - WBL4 .

[0036] In a read operation, Figure 1 In the illustrated embodiment, the word line driver 120 is configured to output a word line signal RWL1-RWL4, also referred to as a word line read signal RWL1-RWL4 in some embodiments, on a corresponding one of the word lines RWL1-RWL4, for example, corresponding to the row address Xaddr, including one of a high or low logic level, in response to one or more control signals CTRL. Each memory cell 112 coupled to one of the word lines RWL1-RWL4 is configured to couple the memory device to a corresponding one of the bit lines RBL1-RBL4 in response to the word line signal RWL1-RWL4 having one of a high or low logic level. In some embodiments, each memory cell 112 is configured to couple the memory device to a corresponding one of the bit lines RBL1-RBL4 only in response to the corresponding word line signal RWL1-RWL4.

[0037] In some embodiments, for example, in a read operation in those embodiments where each memory cell 112 is a four-terminal device, the word line driver 120 is configured to output a word line read signal RWL1-RWL4 on a corresponding one of the word lines WWL1-WWL4 in response to one or more control signals CTRL, and each memory cell 122 coupled to one of the word lines WWL1-WWL4 is configured to couple the memory device to a corresponding one of the bit lines WBL1-WBL4 in response to the word line signal RWL1-RWL4 having one of a high or low logic level.

[0038] The R / W interface 130, also referred to as the local I / O circuit 130 in some embodiments, is an electronic circuit configured to output selection signals YSEL1-YSEL4 (also referred to as write selection signals YSE1-YSEL4 and write selection lines YSE1-YEL4 in some embodiments) on selection lines YSEL1-YSEL4 in response to one or more control signals CTRL received from the control circuit 140 on the control signal bus CTRL and / or from one or more circuits (not shown) outside the memory circuit 100.

[0039] In a write operation, the R / W interface 130 is configured to output a selection signal YSEL1-YSEL4 on a corresponding one of the selection lines YSEL1-YSEL4, for example, corresponding to the column address Yaddr, including one of a high or low logic level, in response to one or more control signals CTRL. Each memory cell 112 coupled to one of the selection lines YSEL1-YSEL4 is configured to couple the memory device to a corresponding one of the bit lines WBL1-WBL4 in response to the selection signal YSEL1-YSEL4 having one of a high or low logic level, and also in response to the corresponding word line signal WWL1-WWL4 as described above.

[0040] R / W interface 130 is thus configured to output select signals YSEL1-YSEL4 on select lines YSEL1-YSEL4 that are configured to, in part, cause each memory cell 112 to couple the included memory device to a corresponding one of bit lines WBL1-WBL4.

[0041] In a write operation, the R / W interface 130 is also configured to output a bit line signal WBL1-WBL4 (also referred to as one or more programming voltages in some embodiments) on a corresponding one of the bit lines WBL1-WBL4, for example corresponding to the column address Yaddr, including one of a high or low logic level or one or more other voltage levels, in response to one or more of the control signals CTRL, or to program the corresponding memory cell 112 to a state corresponding to a high or low logic level.

[0042] In a read operation, the R / W interface 130 is also configured to output a bit line signal RBL1-RBR4 (also referred to as one or more read voltages or bias voltages in some embodiments) on a corresponding one of the bit lines RBL1-RBL4, for example corresponding to the column address Yaddr, including one of a high or low logic level or one or more other voltage levels, in response to one or more of the control signals CTRL, or to bias the corresponding memory cell 112 to a level corresponding to a read operation (e.g., a current sensing operation) of the R / W interface 130.

[0043] In some embodiments, for example, in read operations in those embodiments where each memory cell 112 is a four-terminal device, the R / W interface 130 is configured to output a bit line signal RBL1-RBL4 on a corresponding one of the bit lines WBL1-WBL4 in response to one or more control signals CTRL, and each memory cell 122 is thereby biased to one of a high or low logic level, or one or more other voltage levels received from a corresponding one of the bit lines WBL1-WLL4. In some embodiments, the fourth terminal of each memory cell 112 is coupled to a signal line ( Figure 1 ), such as a source line, which is configured to have a reference voltage level such as ground and / or is coupled to a signal detection circuit of the R / W interface 130.

[0044] exist Figure 1 In the illustrated embodiment, in which the memory circuit 100 is configured as a DRAM circuit, including a memory cell 112 configured as a DRAM cell, the R / W interface 130 includes a refresh and latch circuit, a column decoder (e.g., a multiplexer), and a read / write circuit. The refresh and latch circuit is configured to perform a refresh operation by, for example, periodically reading, latching, and rewriting data to the memory cell 112, the column decoder is configured to output a selection signal YSEL1-YSEL4 in response to an address Yaddr and activate the bit lines WBL1-WBL4 and / or RBL1-RBL4, and the read / write circuit is configured to output data to and read data from the memory cell 112 selected according to the selection signal YSE1-YSEL4 and the activated bit lines WBL1-WBL4 and / or RBL1-RBL4, respectively, in response to one or more control signals CTRL.

[0045] In some embodiments, the R / W interface 130 includes one or more signal detection circuits (not shown), such as sense amplifiers, and is thereby configured to perform one or more read operations based on one or more signals received on one or a combination of the bit lines RBL1-RBL4 and / or WBL1-WBL4, such as measuring one or more currents, voltages, or voltage differences, wherein a programmed logic high level or a logic low level of the selected memory cell 112 is detected.

[0046] In some embodiments, the one or more signal detection circuits are configured to determine the programming state of the selected memory cell 112 based on the first threshold voltage level being greater than or less than the second threshold voltage level. In some embodiments, the one or more signal detection circuits are configured to determine the programming state of the selected memory cell 112 based on one or more currents (e.g., channel currents) corresponding to one or more values ​​of the bit line signals RBL1-RBL4 and stored at a storage node of a corresponding memory device (e.g., as described below with reference to Figure 3A and Figure 3B The programming state of the selected memory cell 112 is determined by the voltage level on the storage node SN) of the memory device 310N or 310P in question.

[0047] According to the embodiments discussed herein, the control circuit 140 is an electronic circuit configured to control the operation of the memory circuit 100 by one or more control signals CTRL generated on a control signal bus CTRLB and received by the word line driver 120 and the R / W interface 130. In various embodiments, the control circuit 140 includes a hardware processor 142 and a non-transitory computer-readable storage medium 144. Among other things, the storage medium 144 is encoded with a computer program code, i.e., a set of executable instructions. The execution of the instructions by the hardware processor 142 represents (at least in part) a memory circuit operation tool, which implements, for example, the following description of Figure 7 A portion or all of method 700 (hereinafter referred to as the process and / or method) is discussed.

[0048] The processor 142 is electrically coupled to the non-transitory computer-readable storage medium 144, the I / O interface, and the network (details not shown) via the bus. The network interface is connected to the network (not shown) so that the processor 142 and the non-transitory computer-readable storage medium 144 can be connected to external elements through the network. The processor 142 is configured to execute computer program code encoded in the non-transitory computer-readable storage medium 144 so that the control circuit 140 and the memory circuit 100 can be used to perform part or all of the process and / or method. In one or more embodiments, the processor 142 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0049] In one or more embodiments, the non-transitory computer-readable storage medium 144 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium 144 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the non-transitory computer-readable storage medium 144 includes compact disk read-only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disk (DVD).

[0050] In one or more embodiments, the non-transitory computer-readable storage medium 144 stores computer program code configured to cause the control circuit 140 to generate control signals that can be used to perform some or all of the processes and / or methods. In one or more embodiments, the non-transitory computer-readable storage medium 144 also stores information that facilitates the performance of some or all of the processes and / or methods. In one or more embodiments, the non-transitory computer-readable storage medium 144 stores one or more data sets, such as a plurality of data patterns, which will be discussed below with reference to the described processes and / or methods.

[0051] Figure 2A and Figure 2B 2 is a schematic diagram of each memory cell 200P and 200N according to some embodiments. Each of the memory cells 200P and 200N can be used as described above with respect to Figure 1 The memory unit 112 is discussed.

[0052] Figure 2A and Figure 2B Each of the 1000 MHz and 1000 MHz signals includes a word line / signal WWL corresponding to one of the word lines / signals WWL1-WL4, a select line / signal YSEL corresponding to one of the select lines / signals YSEL1-YSEL4, and a bit line / signal WBL corresponding to one of the bit lines / signals WBL1-WBL4, each of which is referred to above. Figure 1 Discussed.

[0053] Each of the memory cells 200P and 200N includes a transistor W1 including an S / D terminal coupled to a selection line YSEL, a gate coupled to a word line WWL, and an S / D terminal coupled to a storage node SNW, and a transistor W0 including an S / D terminal coupled to a bit line WBL, a gate coupled to the storage node SNW, and an S / D terminal connected to the memory device 210. Figure 2A and Figure 2B As shown, the memory cell 200P includes each of transistors W1 and W0, each of which includes a p-type transistor, and the memory cell 200N includes each of transistors W1 and W0, each of which includes an n-type transistor.

[0054] Depending on the context, the S / D terminals may be referred to individually or collectively as source or drain.

[0055] A storage node (e.g., storage node SNW) is an IC structure that includes one or more conductive elements, such as metal line segments, configured to be selectively coupled to or decoupled from other structural elements through one or more switching devices (e.g., transistors, such as transistor W1). In some embodiments, the metal segments of the storage node are included in one or more transistors as one or more S / D terminals and / or one or more gates. In some embodiments, the storage node includes one or more through-hole structures located between and electrically connecting the multiple metal segments.

[0056] In some embodiments, the metal segments and via structures (if included) of the storage nodes are back-end-of-line (BEOL) components located in the IC interconnect structure. In some embodiments, the storage nodes are Figure 4 The storage node STN of the IC device 400 is discussed.

[0057] In operation, when decoupled from other structural elements by one or more switching devices, the storage node is electrically isolated by the dielectric material layer and closed channel of the one or more switching devices, so that a sufficiently small leakage current and a sufficiently large capacitance (e.g., parasitic capacitance) cause the charge on the storage node to remain substantially unchanged during a retention period. The retention period has a minimum duration based on the storage node configuration and charge level, and is long enough to allow the circuit (e.g., memory circuit 100) to perform multiple read and / or write operations while the charge is substantially retained on the storage node.

[0058] Thus, the charge retained on the storage node SNW can bias the gate of the transistor W0 so that the transistor W0 of the non-selected given memory cell 200P or 200N can be turned off during the retention period when one or more write operations are performed on one or more other (selected) memory cells, as described below with respect to Figure 6A-6F discussed.

[0059] exist Figure 2A and Figure 2B In the illustrated embodiment, the storage node SNW holding a charge corresponding to a high logic level corresponds to turning off the p-type transistor W0 of the memory circuit 200P during the retention period, while the storage node SNW holding a charge corresponding to a low logic level corresponds to turning off the n-type transistor W0 of the memory circuit 200N during the retention period.

[0060] As the minimum duration of the retention period increases, the number of read and / or write operations that can be performed on other memory cells also increases. In some embodiments, a storage node (e.g., storage node SNW) has a minimum duration from 100 milliseconds (ms) to 10 seconds. In some embodiments, a storage node has a minimum duration from 500 ms to 5 seconds.

[0061] Memory device 210 is an electrical, electromechanical, electromagnetic, or other device configured to store data bits represented by logic states. In some embodiments, the logic states correspond to voltage levels of charges stored in memory device 210. In some embodiments, the logic states correspond to physical properties of a portion or all of memory device 210, such as resistance or magnetic orientation.

[0062] In some embodiments, the memory device 210 includes a static random access memory (SRAM) device, a DRAM device, an embedded DRAM (eDRAM) device, a gain cell device, a resistive random access memory (RRAM) device, a magnetoresistive random access memory (MRAM) device, a ferroelectric random access memory (FeRAM) device, a NOR (NOR) or NAND (NAND) flash device, a conductive bridging random access memory (CBRAM) device, an NVM device, a 3D NVM device, or other memory device types capable of storing bit data.

[0063] The memory circuit 100 includes memory cells 200N or 200P, each memory cell including transistors W1 and W0, a storage node SNW, and a memory device 210, so as to be configured to selectively couple each memory device 210 to a corresponding bit line WBL1-WBL4 in response to a corresponding combination of word line signals WWL1-WWL4 and select signals YSEL1-YSEL4. Thus, the memory device 210 of the selected memory cell 200N or 200P is coupled to the corresponding bit line WBL1-WBL4, thereby avoiding a half-select disturb condition on the memory device 210 of the non-selected storage element 200N or 200B.

[0064] By avoiding the half-select disturb condition, power consumption during a write operation in the memory circuit 100 is reduced, for example, by selecting memory cells using only word line signals, compared to methods that rewrite data to address the half-select disturb condition caused by coupling a non-selected memory device to a bit line.

[0065] Figure 3A-3C is a schematic diagram of a non-limiting example of a memory cell 200N or 200P according to some embodiments. Figure 3A-3C Each of the word lines includes a word line / signal WWL, a select line / signal YSEL and a bit line / signal WBL, which are described above with respect to Figure 2A and Figure 2B A discussion was held. Figure 3A and Figure 3B Each of the 100 further includes a word line / signal RWL corresponding to one of the word lines / signals RWL1-RWL4 and a bit line / signal RBL corresponding to one of the bit lines / signals RBL1-RBL4, both of which are described above with respect to Figure 1 A discussion was held. Figure 3C Also included are the signal lines / signals SL discussed below.

[0066] Figure 3A depicts a memory cell 200N including a memory device 310N that may be used as the memory device 210, Figure 3B depicts a memory cell 200P including a memory device 310P that may be used as the memory device 210, Figure 3C A memory cell 200N including a memory device 310R serving as the memory device 210 is depicted.

[0067] Each of the memory devices 310N and 310P includes transistors R1 and R0. Transistor R1 includes an S / D terminal coupled to a bit line RBL, a gate coupled to a word line RWL, and an S / D terminal coupled to an S / D terminal of transistor R0. Transistor R0 includes a gate coupled to a storage node SN and an S / D terminal coupled to a power distribution path, and storage node SN also includes an S / D terminal of transistor W0. Figure 3A and Figure 3B As shown, the memory device 310N includes each of the transistors R1 and R0 including an n-type transistor and a power distribution path including a ground path, while the memory device 310P includes each of the transistors R1 and R0 including a p-type transistor and a power distribution path including a power supply distribution path.

[0068] Each of the memory devices 310N and 310P is thus configured as a gain cell device, in which the charge retained on the storage node SN can represent a logic state based on being greater than or less than the threshold voltage of the transistor R0.

[0069] In operation, the storage node SN of the memory device 310N retaining a charge corresponding to a high logic level represents a first logic state corresponding to the transistor R0 being turned on, and the storage node SN of the memory device 310N retaining a charge corresponding to a low logic level represents a second logic state corresponding to the transistor R0 being turned off. The storage node SN of the memory device 310P retaining a charge corresponding to a low logic level represents a first logic state corresponding to the transistor R0 being turned on, and the storage node SN of the memory device 310P retaining a charge corresponding to a high logic level represents a second logic state corresponding to the transistor R0 being turned off.

[0070] The memory device 310R includes a RRAM device RM coupled between the S / D terminal of the transistor W0 and the signal line SL. The RRAM device RM is a two-terminal device that can be programmed to at least two resistance levels corresponding to the first and second logic states by, for example, one or more differential voltages applied to the two terminals. In some embodiments, the RRAM device includes the following reference Figure 5 A variable resistance device 500 is discussed.

[0071] The signal line SL is an electrical path coupled to a voltage source (not shown), ground, the word line driver 120, and / or the R / W interface 130, so as to be configured to apply a signal SL to and / or receive a signal SL from a terminal of the RRAM device RM. In some embodiments, the signal line / signal SL is one of the above-mentioned word lines / signals RWL1-RWL4 or one of the bit lines / signals RBL1-RBL4.

[0072] exist Figure 3A In the embodiment shown, memory device 310R is included in memory cell 200N. In some embodiments, memory device 310R is included in memory cell 200P.

[0073] like Figure 3A-3C As shown, each memory device 310N, 310P and 310R included in the corresponding memory cell 200N or 200P is configured to be coupled to the bit line WBL in response to signals WWL and YSEL, so that the memory circuit (e.g., memory circuit 100) of the memory cell 200N or 200P including the memory device 310N, 310P or 310R can achieve the benefits discussed above with respect to the memory circuit 100 and the memory cells 200P and 200P.

[0074] Figure 4 is a cross-sectional view of an IC device 400 according to some embodiments. The IC device 400 is a BEOL device located in an interconnect structure of an IC, such as the memory circuit 100 described above.

[0075] Figure 4 An IC device 400 is depicted, which includes transistors T1 and T2 and a storage node STN, and X and Z directions. IC device 400 may be used in the configuration of memory cell 200N or 200P, where examples of transistors T1 and T2 and storage node STN may be used as described above with respect to Figure 2A-Figure 3C In some embodiments, the IC device 400 may be used in the configuration of the memory cell 200N or 200P, where the examples of the transistors T1 and T2 and the storage node STN may also be used as described above with respect to Figure 3A and Figure 3BThe respective transistors R0 and W0 and the storage node SN are discussed.

[0076] The transistor T1 includes S / D structures SD1 and SD2, a gate structure G1, an oxide layer OX1, and a channel layer CH1. The transistor T2 includes S / D structures SD3 and SD4, a gate structure G2, an oxide layer OX2, and a channel layer CH2. The storage node STN includes a gate G1, an S / D structure SD4, and a through-hole structure V located between the gate G1 and the S / D structure SD4 and electrically connecting the gate G1 and the S / D structure SD4.

[0077] Apart from Figure 4 In addition to the features shown in , IC device 400 also includes features that are not included for illustration purposes, such as one or more dielectric layers, such as including silicon dioxide (SiO2), between transistors T1 and T2 and around via structure V. For illustration purposes, front-end-of-line (FEOL) features located below IC device 400 are not depicted.

[0078] Figure 4 The relative positioning and dimensions of the features depicted in the drawings are non-limiting examples provided for purposes of illustration. Figure 4 Relative positioning and dimensions other than those shown are also within the scope of the present disclosure.

[0079] exist Figure 4 In the illustrated embodiment, the S / D structures SD1 and SD2 and the gate G1 are metal segments located in a first metal layer of the interconnect structure, and the S / D structures SD3 and SD4 and the gate G2 are metal segments located in a second metal layer of the interconnect structure and adjacent to the first metal layer. In some embodiments, the second layer is not adjacent to the first layer, so that one or more metal layers are located between the first and second metal layers. In some embodiments, the via structure V includes a single via structure, more than one via structure, and / or one or more metal segments in one or more metal layers between the first and second metal layers. The metal segments and via structures include one or more of copper (Cu), silver (Ag), tungsten (W), titanium (Ti), nickel (Ni), tin (Sn), aluminum (Al), or another metal or material suitable for providing a low resistance electrical path.

[0080] The oxide layers OX1 and OX2 (also referred to as gate oxide layers in some embodiments) include one or more insulating materials, such as SiO2, silicon nitride (Si3N4) and / or one or more other suitable materials, such as a low-k material having a k value less than 3.8 or a high-k material having a k value greater than 3.8 or 7.0, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5) or titanium oxide (TiO2), suitable for providing high resistance between IC structural elements, i.e., a resistance level above a predetermined threshold corresponding to one or more tolerance levels affecting resistance-based circuit performance.

[0081] The channel layers CH1 and CH2 include one or more semiconductor materials, such as polysilicon, oxide materials, such as indium oxide (In2O3), indium tungsten oxide (IWO), and / or one or more dopants, such as boron (B), phosphorus (P), arsenic (As), gallium (Ga), or other suitable materials, which are configured to provide a conductive channel between the corresponding S / D structures SD1 and SD2 or SD3 and SD4 in response to the charge retained on the corresponding gate G1 or G2.

[0082] Through the above configuration, the IC device 400 can be included in the memory cells 200N and 200P, so that the benefits described above with respect to the memory circuit 100 can be achieved.

[0083] Figure 5 FIG. 5 is a cross-sectional view of an IC device 500 according to some embodiments. The IC device 500 (also referred to as a variable resistor device 500 in some embodiments) may be used as described above with respect to Figure 3C The RRAM device RM discussed.

[0084] IC device 500 is a microelectronic device that includes a resistive layer L1 extending in the X and Y directions (not shown) between electrodes E1 and E2 along the Z direction. In some embodiments, IC device 500 includes one or more additional features, such as conductive elements, for clarity. Figure 5 Not shown in FIG.

[0085] In a programming operation, a sufficiently large voltage difference across the resistive layer L1 based on the voltages V1 and V2 applied to the respective electrodes E1 and E2 induces the formation of the fuse F1, thereby providing a current path that reduces the resistance level of the resistive layer L1 compared to the level corresponding to the resistive layer L1 not including the fuse F1. In a reading operation, the difference between the voltages V1 and V2 is small enough to avoid the formation of the fuse, thereby inducing a current that can be measured by the circuit, such as described above with respect to Figure 1-3C The R / W interface 130 is discussed.

[0086] The resistance layer L1 is one or more layers of dielectric material configured to receive a voltage difference. In various embodiments, the resistance layer L1 includes one or more oxides of tungsten (W), tantalum (Ta), titanium (Ti), nickel (Ni), cobalt (Co), hafnium (Hf), ruthenium (Ru), zirconium (Zr), zinc (Zn), iron (Fe), tin (Sn), aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), or another suitable element, including a composite material such as silicon, or another material capable of having a high resistance state (HRS) or a low resistance state (LRS) based on the presence or absence of the fuse F1.

[0087] exist Figure 5 In the illustrated embodiment, the resistive layer L1 includes a single fuse F1, thereby including a single current path through which current flows in operation. In various embodiments, the resistive layer L1 includes one or more fuses (not shown) in addition to the fuse F1, thereby including multiple current paths through which current flows in operation.

[0088] In various embodiments, the resistance value of the resistance layer L1 in the LRS ranges from 1 kiloohm (kΩ) to 4 kΩ, and / or in the HRS ranges from 15 kΩ to 30 kΩ. In various embodiments, the resistance layer L1 has a first resistance value range in the LRS and a second resistance value range in the HRS, and the difference between the maximum value of the first range and the minimum value of the second range is greater than the maximum value of the first range multiplied by 0.05 (greater than the maximum value of the first range by at least 5%).

[0089] By being included above in relation to Figure 1-3C In the discussed memory circuit 100 , the IC device 500 is used to achieve the benefits discussed above with respect to the memory circuit 100 .

[0090] Figure 6A-6F Non-limiting examples of operating parameters of memory circuit 100 according to some embodiments are depicted. Figure 6A-6F The examples depicted in each of the embodiments correspond to a memory circuit 100 including a memory cell 200N including the memory cell 200N described above with respect to Figure 1-3C Memory device 310N discussed. Operating parameters corresponding to memory circuit 100 configured in other ways, such as including memory cell 200P and / or memory device 310P or 310R, are within the scope of the present disclosure.

[0091] For the selected memory cell 200N, Fig. 6A Indicates standby mode, Figure 6B Indicates a write operation. Figure 6C Indicates a read operation. Fig.6D Indicates a refresh operation. Fig. 6E Depicted with Figure 6A-6D Each corresponding signal RWL, WWL, YSEL and WBL in Fig. 6F A write operation including multiple instances of the R / W interface 130 and non-selected memory cells 200N in the array 110 is depicted.

[0092] exist Fig. 6A and Fig. 6E In the illustrated standby mode, each of the word line signals RWL and WWL, the select signal YSEL, and the bit line signal WBL has a low logic level, and the bit line signal RBL is not controlled with respect to the selected memory cell 200N. In response, each of the transistors R1, W1, and W0 is turned off, the storage node SNW is decoupled from the select line YSEL, and retains a (previously applied) charge corresponding to a low logic level, and the storage node SN is decoupled from the bit line WBL, and retains a (previously programmed) charge corresponding to a high or low logic level (not shown).

[0093] exist Figure 6B and Fig. 6E In the write mode shown, the word line signal RWL has a low logic level, each of the word line voltage signal WWL and the selection signal YSEL has a high logic level, and the bit line signal WBL has a high or low logic level corresponding to the write data. The bit line signal RBL is not controlled with respect to the selected memory cell 200N. In response, the transistor R1 is turned off, each of the transistors W1 and W0 is turned on, the storage node SNW is coupled to the selection line YSEL and receives a charge corresponding to a high logic level, and the storage node SN is coupled to the bit line WBL and receives a charge corresponding to a high or low logic level (not shown) of the write data.

[0094] exist Figure 6C and Fig. 6E In the read mode shown, the word line signal RWL has a high logic level, each of the word line voltage signal WWL and the selection signal YSEL has a low logic level, and the bit line signal WBL is not controlled with respect to the selected memory cell 200N. In response, the transistor R1 is turned on, each of the transistors W1 and W0 is turned off, the storage node SNW is decoupled from the selection line YSEL and retains a charge corresponding to a low logic level (previously applied), the storage node SN is decoupled from the bit line WBL and retains a charge corresponding to a high or low logic level (not shown) of the written data, and the bit line signal RBL has a high or low voltage logic level corresponding to the previously written data based on the charge retained on the storage node SN.

[0095] exist Fig.6D and Fig. 6EIn the refresh mode shown, each of the word line signals RWL and WWL and the selection signal YSEL has a high logic level. In response, each of the transistors R1, W1 and W0 is turned on, the storage node SNW is coupled to the selection line YSEL and receives a charge corresponding to the high logic level, each of the bit line signals RBL and WBL has a high or low logic level corresponding to the previously written data based on the charge retained on the storage node SN, and the storage node SN is coupled to the bit line WBL and receives a charge corresponding to the previously written data.

[0096] like Fig. 6F As shown (lines / signals are not labeled for clarity), the write pattern for the selected memory cell 200N (labeled) includes Figure 6B and Fig. 6E The second (non-selected) memory cell 200N instance located in the same row as the selected memory cell 200N also receives the word line signal WWL having a high logic level. In response to the corresponding selection signal YSEL having a low logic level, the transistor W0 of the non-selected memory cell 200N is turned off, and the storage node SN is decoupled from the bit line WBL, so that the charge retained on the storage node SN is not disturbed in response to the word line signal WWL having a high logic level.

[0097] Figure 6A-6F A non-limiting illustration of the operation of the memory circuit 100 is thus provided, wherein the memory device of the non-selected memory cell 200N or 200P is not disturbed in response to the word line signal WWL having a logic level configured to cause data to be written into the selected memory cell 200N or 200P located in the same row as the non-selected memory cell 200N or 200P.

[0098] In some embodiments, the memory circuit 100 is otherwise configured so that the memory device of the non-selected memory cell 200N or 200P is not disturbed in response to the word line signal WWL having a logic level configured to cause data to be written to the selected memory cell 200N or 200P located in the same row as the non-selected memory cell 200N or 200P, for example, based on receiving the word line signal having the same logic level as the selected memory cell 200N or 200P. Figure 6A-6F , or based on a non-selected memory cell 200N or 200P including a memory device 310R including a terminal not coupled to a bit line WBL, in response to a word line signal WWL having a logic level configured to cause data to be written to the selected memory cell 200N or 200P.

[0099] Figure 7700 is a flow chart of a method 700 for operating a memory circuit according to some embodiments. The method 700 may be used in a memory circuit, for example, including the method described above with respect to Figure 1-6F The memory circuit 100 of the memory cell 200N or 200P example is discussed. In some embodiments, the operations of the method 700 are a subset of the operations of a method of operating a CIM or NMC circuit.

[0100] Figure 7 The order in which the operations of method 700 are described is for illustration only; the operations of method 700 may be performed in the same order as described in Figure 7 In some embodiments, Figure 7 Perform the following operations before, between, during, and / or after the operations shown: Figure 7 Operations other than those shown in .

[0101] At operation 710, in some embodiments, a first memory cell is provided by a memory circuit (eg, as described above with respect to Figure 1-6F The memory circuit 100 discussed above is operated in the standby mode. In some embodiments, operating the first memory cell in the standby mode includes operating the memory cell 200N or 200P, as described above with respect to Figure 2A-Figure 6F described.

[0102] In some embodiments, performing the standby operation includes applying a charge to a storage node between an S / D terminal of a first transistor of a first memory cell and a gate of a second transistor, the charge being configured to turn off the second transistor and decouple a memory device in the first memory cell from a first bit line of a memory circuit.

[0103] In some embodiments, operating the first memory unit in the standby mode includes performing the operations described above with respect to Fig. 6A and Fig. 6E The standby operation described.

[0104] In operation 720, a data bit is written to the first memory cell using a word line signal and a select signal, for example, using the above description of Figure 2A-Figure 6F The word line signal WWL and the select signal YSEL in question write a data bit to the memory cell 200N or 200P.

[0105] Writing a data bit to a first memory cell includes a memory circuit outputting a word line signal having a first logic level to a gate of a first transistor of the first memory cell, the first transistor including a first S / D terminal coupled to a first select line in addition to a second S / D terminal coupled to a storage node of the first memory cell, outputting a first select signal having a first logic level to the first select line, receiving a first charge from the first transistor, the first charge corresponding to the first logic level of the first select signal at the storage node and at a gate of a second transistor of the first memory cell, coupling a memory device of the first memory cell to a first bit line using the second transistor in response to receiving the first charge, and outputting the data bit to the first bit line.

[0106] In some embodiments, writing the data bit to the first memory cell comprises performing the Figure 6B and Fig. 6E The write operation described.

[0107] In some embodiments, coupling the memory device of the first memory cell to the first bit line using the second transistor includes coupling one of the memory devices 310N, 310P, or 310R to the bit line WBL, as described above with respect to Figure 3A-3C described.

[0108] In some embodiments, writing a data bit to a first memory cell includes: outputting a word line signal having a first logic level to a gate of a first transistor of a second memory cell, the first transistor including a first S / D terminal coupled to a second select line and a second S / D terminal coupled to a storage node of the second memory cell, outputting a second select signal having a second logic level to the second select line, receiving a second charge from the first transistor of the second memory cell, the second charge corresponding to the second logic level of the second select signal at the storage node of the second memory cell and at a gate of a second transistor of the second memory cell coupled to the storage node of the second memory cell, and in response to receiving the second charge, decoupling the memory device of the second memory cell from a second bit line using the second transistor of the second memory cell.

[0109] In some embodiments, writing the data bit to the first memory cell comprises performing the Fig. 6F of write operations.

[0110] At operation 730, in some embodiments, a data bit is read from the first memory cell. In some embodiments, reading the data bit from the first memory cell includes reading the data bit from memory cell 200N or 200P, as described above with respect to Figure 2A-Figure 6F discussed.

[0111] In some embodiments, reading a data bit from a first memory cell comprises performing the Figure 6C and Fig. 6E of the read operation.

[0112] At operation 740, in some embodiments, a refresh operation is performed on the first memory cell. In some embodiments, performing a refresh operation on the first memory cell includes performing a refresh operation on the memory cell 200N or 200P, as described above with respect to Figure 2A-Figure 6F discussed.

[0113] In some embodiments, performing a refresh operation on the first memory cell includes performing the Fig.6D and Fig. 6E Refresh operation.

[0114] By performing some or all of the operations of method 700, the memory circuit is able to selectively couple the memory device to the corresponding bit line in response to a combination of word line and select signals, thereby avoiding half-select disturbance conditions on non-selected memory cells, thereby achieving the benefits discussed above with respect to the memory circuit 100 and the memory cells 200N and 200P.

[0115] Figure 8 8 is a flow chart of a method 800 for manufacturing a memory circuit according to some embodiments. The method 800 may be operable to form a memory circuit including the above Figure 1-6F The memory circuit 100 of the memory cell 200N or 200P is discussed.

[0116] In some embodiments, the operations of method 800 are as follows: Figure 8 In some embodiments, the operations of method 800 are performed in the order shown. Figure 8 In some embodiments, one or more additional operations are performed before, during, between, and / or after the operations of method 800.

[0117] In some embodiments, one or more operations of method 800 are a subset of operations of a method of forming an IC and / or IC package that includes one or more memory arrays, such as a CIM or NMC IC.

[0118] At operation 810, a plurality of FEOL devices are constructed on a semiconductor substrate. Constructing the plurality of FEOL devices includes forming one or more devices according to the IC design, for example, transistors including S / D structures in active regions of the semiconductor substrate, gate structures on and / or in the active regions, and electrical connections between devices.

[0119] Constructing the plurality of FEOL devices includes performing a first plurality of fabrication operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations, suitable for constructing resistive layers, magnetic layers, or other material layers, dielectric layers, and / or gate structures adjacent to the S / D structures, and overlying or otherwise approaching active regions of the semiconductor substrate.

[0120] At operation 820, a memory cell array is constructed in an interconnect structure, each memory cell includes a first transistor and a second transistor, the first transistor includes an S / D terminal coupled to a storage node, the second transistor is coupled between the memory device and a bit line and includes a gate coupled to the storage node. Constructing the memory cell array includes constructing the above-mentioned Figure 1-6F The memory circuit 100 in question has an array 110 of memory cells 200N or 200P.

[0121] In some embodiments, constructing a memory cell array includes constructing a memory cell array including the Figure 4 The memory cell of the storage node STN is discussed.

[0122] In some embodiments, constructing a memory cell array includes constructing a memory cell array including a gain cell or an RRAM memory device (e.g., as described above with respect to Figure 3A-Figure 5 Memory cells of the memory device 310N, 310P, or 310R) discussed.

[0123] In some embodiments, constructing the memory cell array includes performing one or more BEOL operations, including performing a second plurality of manufacturing operations, such as one or more of lithography, diffusion, deposition, etching, planarization, or other operations, suitable for constructing metal segments, oxide layers and channel layers, resistive layers or other material layers, dielectric layers, and / or gate structures adjacent to the S / D structures, and overlying or otherwise approaching a plurality of FEOL devices.

[0124] At operation 830, in some embodiments, electrical connections are formed to the memory cell array. Forming the electrical connections includes performing one or more etching and deposition processes by which one or more metal lines are configured according to one or more masks. Performing the deposition process includes depositing one or more conductive materials, such as Cu, Ag, W, Ti, Ni, Sn, Al, or another metal or suitable material, such as polysilicon.

[0125] In some embodiments, according to the above Figure 1-6F For the discussed embodiments, forming electrical connections includes forming one or more of word lines WWL1 - WWL4 , word lines RWL1 - RWL4 , select lines YSEL1 - YSEL4 , bit lines WBL1 - WBL4 , or bit lines RBL1 - RBL4 .

[0126] By performing some or all of the operations of method 800, an IC device is manufactured that includes a memory circuit that includes memory cells capable of selectively coupling the memory device to corresponding bit lines in response to a combination of word lines and select signals, thereby avoiding half-select disturbance conditions on non-selected memory cells, thereby achieving the above-mentioned benefits regarding memory circuit 100 and memory cells 200N and 200P.

[0127] In some embodiments, the IC device includes a first transistor, a second transistor, a first memory device, and a first storage node, the first transistor including a first S / D terminal coupled to a first selection line, a second S / D terminal, and a gate coupled to a first word line, the second transistor including a first S / D terminal coupled to a first bit line, a second S / D terminal, and a gate, the first memory device is coupled to the second S / D terminal of the second transistor, and the first storage node includes the second S / D terminal of the first transistor and the gate of the second transistor. In some embodiments, the first S / D terminal and the second S / D terminal of each of the first transistor and the second transistor and each of the gates include a metal segment of an interconnect structure. In some embodiments, the first storage node also includes a through-hole structure located between the second S / D terminal of the first transistor and the gate of the second transistor, and electrically connecting the second S / D terminal of the first transistor to the gate of the second transistor. In some embodiments, the first memory device includes a third transistor and a fourth transistor, the third transistor including a first S / D terminal coupled to a second bit line, a second S / D terminal, and a gate coupled to a second word line, the fourth transistor including a first S / D terminal coupled to a second S / D terminal of the third transistor, a second S / D terminal coupled to a power distribution path, and a gate coupled to the second S / D terminal of the second transistor, and the second storage node of the IC device includes the second S / D terminal of the second transistor and the gate of the fourth transistor. In some embodiments, each of the first to fourth transistors includes an n-type transistor, and the power distribution path includes a ground path. In some embodiments, each of the first to fourth transistors includes a p-type transistor, and the power distribution path includes a power supply distribution path. In some embodiments, each of the first to fourth transistors includes a first S / D terminal, a second S / D terminal, and a gate includes a metal segment of an interconnect structure. In some embodiments, the IC device includes a third transistor, a fourth transistor, a second memory device, and a second storage node, the third transistor including a first S / D terminal coupled to a second selection line, a second S / D terminal, and a gate coupled to a first word line, the fourth transistor including a first S / D terminal coupled to a second bit line, a second S / D terminal, and a gate, the second memory device is coupled to the second S / D terminal of the fourth transistor, and the second storage node includes the second S / D terminal of the third transistor and the gate of the fourth transistor. In some embodiments, the IC device includes a third transistor, a fourth transistor, a second memory device, and a second storage node, the third transistor including a first S / D terminal coupled to a first selection line, a second S / D terminal, and a gate coupled to a second word line, the fourth transistor including a first S / D terminal coupled to a first bit line, a second S / D terminal, and a gate, the second memory device is coupled to the second S / D terminal of the fourth transistor, and the second storage node includes the second S / D terminal of the third transistor and the gate of the fourth transistor.In some embodiments, the first memory device includes a RRAM device including a first terminal coupled to the second S / D terminal of the second transistor and a second terminal coupled to the signal line.

[0128] In some embodiments, a memory circuit includes an array of memory cells arranged in rows and columns, a row decoder coupled to a plurality of first word lines corresponding to the rows of memory cells, and an R / W interface coupled to a plurality of selection bit lines and a first bit line corresponding to the columns of memory cells, wherein each memory cell of the array includes a first transistor, a second transistor, a memory device, and a first storage node, the first transistor including a first S / D terminal coupled to a corresponding selection line among a plurality of selection lines, a second S / D terminal, and a gate, the second transistor including a first bit line coupled to a corresponding first bit line among a plurality of first bit lines, a second S / D terminal, and a gate, the memory device, and a second S / D terminal coupled to the second transistor; the first storage node includes the second S / D terminal of the first transistor and the gate of the second transistor. In some embodiments, the row decoder is further coupled to a plurality of second word lines corresponding to the rows of memory cells, the R / W interface is further coupled to a plurality of second bit lines corresponding to the columns of memory cells, the memory device of each memory cell of the array includes a third transistor and a fourth transistor, the third transistor including a first S / D terminal coupled to a corresponding second bit line of the plurality of second bit lines, a second S / D terminal, and a gate coupled to a corresponding second word line of the plurality of second word lines, the fourth transistor including a first S / D terminal coupled to a second S / D terminal of the third transistor, a second S / D terminal coupled to a power distribution path of the memory circuit, and a gate coupled to the second S / D terminal of the second transistor, the second storage node of each memory cell of the array including the corresponding second S / D terminal of the second transistor and the gate of the fourth transistor. In some embodiments, each memory cell of the array includes each of the first to fourth transistors, the first to fourth transistors include n-type transistors, and the power distribution path includes a ground path. In some embodiments, each memory cell of the array includes each of the first to fourth transistors, the first to fourth transistors include p-type transistors, and the power distribution path includes a power supply distribution path. In some embodiments, the memory circuit includes an interconnect structure including a first storage node of each memory cell of the array. In some embodiments, the R / W interface is further coupled to a plurality of signal lines corresponding to columns of memory cells, the memory device of each memory cell of the array comprising an RRAM device comprising a first terminal coupled to a second S / D terminal of the second transistor and a second terminal coupled to a corresponding signal line of the plurality of signal lines. In some embodiments, the R / W interface comprises a column decoder configured to output a plurality of select signals to the plurality of select lines in response to a received address.

[0129] In some embodiments, a method of operating a memory circuit includes writing a data bit to a first memory cell by the following steps: outputting a word line signal having a first logic level to a gate of a first transistor of the first memory cell, the first transistor including a first source / drain (S / D) terminal coupled to a first selection line and a second S / D terminal coupled to a storage node of the first memory cell; outputting a first selection signal having a first logic level to the first selection line; receiving a first charge from the first transistor, the first charge corresponding to the first logic level of the first selection signal at the storage node and at a gate of a second transistor of the first memory cell coupled to the storage node; in response to receiving the first charge, coupling a memory device of the first memory cell to a first bit line using a second transistor; and outputting the data bit to the first bit line. In some embodiments, writing a data bit to a first memory cell further comprises: outputting a word line signal having a first logic level to a gate of a first transistor of a second memory cell, the first transistor comprising a first S / D terminal coupled to a second select line and a second S / D terminal coupled to a storage node of the second memory cell; outputting a second select signal having a second logic level to the second select line; receiving a second charge from the first transistor of the second memory cell, the second charge corresponding to the second logic level of the second select signal at the storage node of the second memory cell and at a gate of a second transistor of the second memory cell coupled to the storage node of the second memory cell; and in response to receiving the second charge, decoupling a memory device of the second memory cell from a second bit line using a second transistor of the second memory cell. In some embodiments, coupling the memory device of the memory cell to the first bit line using the second transistor comprises coupling a storage node of a gain cell device to the first bit line using the second transistor.

[0130] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, comprising: A first transistor comprising: a first source / drain terminal coupled to a first select line; a second source / drain terminal; and a gate coupled to the first word line; The second transistor comprises: a first source / drain terminal coupled to a first bit line; a second source / drain terminal; and Gate; a first memory device coupled to the second source / drain terminal of the second transistor; and A first storage node includes the second source / drain terminal of the first transistor and the gate of the second transistor.

2. The integrated circuit device according to claim 1, wherein: Each of the first and second source / drain terminals and the gates of each of the first and second transistors includes a metal segment of an interconnect structure.

3. The integrated circuit device according to claim 2, wherein: The first storage node also includes: A through-hole structure is located between the second source / drain terminal of the first transistor and the gate of the second transistor, and electrically connects the second source / drain terminal of the first transistor and the gate of the second transistor.

4. The integrated circuit device according to claim 1, wherein: The first memory device comprises: A third transistor includes: a first source / drain terminal coupled to a second bit line; a second source / drain terminal; and a gate coupled to a second word line; and A fourth transistor comprising: a first source / drain terminal coupled to the second source / drain terminal of the third transistor; a second source / drain terminal coupled to the power distribution path; and a gate coupled to the second source / drain terminal of the second transistor, and A second storage node of the integrated circuit device includes the second source / drain terminal of the second transistor and the gate of the fourth transistor.

5. The integrated circuit device according to claim 4, wherein: Each of the first to fourth transistors includes an n-type transistor, and The power distribution path includes a ground path.

6. The integrated circuit device according to claim 1, further comprising: A third transistor includes: a first source / drain terminal coupled to a second select line; a second source / drain terminal; and a gate coupled to the first word line; A fourth transistor comprising: a first source / drain terminal coupled to a second bit line; a second source / drain terminal; and Gate; a second memory device coupled to the second source / drain terminal of the fourth transistor; and A second storage node includes the second source / drain terminal of the third transistor and the gate of the fourth transistor.

7. A memory circuit comprising: an array of memory cells, arranged in rows and columns; a row decoder coupled to a plurality of first word lines corresponding to the rows of memory cells; as well as a read / write interface coupled to a plurality of select bit lines and a plurality of first bit lines corresponding to the columns of the memory cells, Wherein, each memory cell of the array comprises: A first transistor comprising: a first source / drain terminal coupled to a corresponding select line of the plurality of select lines; a second source / drain terminal; and a gate coupled to a corresponding first word line of the plurality of first word lines; The second transistor comprises: a first source / drain terminal coupled to a corresponding first bit line of the plurality of first bit lines; a second source / drain terminal; and Gate; a memory device coupled to the second source / drain terminal of the second transistor; and A first storage node includes the second source / drain terminal of the first transistor and the gate of the second transistor.

8. The memory circuit according to claim 7, wherein: The row decoder is also coupled to a plurality of second word lines corresponding to the row of memory cells, The read / write interface is also coupled to a plurality of second bit lines corresponding to the columns of memory cells, The memory device of each memory cell of the array comprises: A third transistor includes: a first source / drain terminal coupled to a corresponding second bit line of the plurality of second bit lines; a second source / drain terminal; and a gate coupled to a corresponding second word line of the plurality of second word lines; and A fourth transistor comprising: a first source / drain terminal coupled to the second source / drain terminal of the third transistor; a second source / drain terminal coupled to a power distribution path of the memory circuit; and a gate coupled to the second source / drain terminal of the second transistor, and The second storage node of each memory cell of the array includes the corresponding second source / drain terminal of the second transistor and the gate of the fourth transistor.

9. A method of operating a memory circuit, the method comprising: The data bit is written to the first memory cell by the following steps: outputting a word line signal having a first logic level to a gate of a first transistor of the first memory cell, the first transistor including a first source / drain terminal coupled to a first select line and a second source / drain terminal coupled to a storage node of the first memory cell; outputting a first selection signal having the first logic level to the first selection line; receiving a first charge from the first transistor, the first charge corresponding to the first logic level of the first select signal at the storage node and at a gate of a second transistor of the first memory cell coupled to the storage node; in response to receiving the first charge, coupling a memory device of the first memory cell to a first bit line using the second transistor; as well as The data bit is output to the first bit line.

10. The method according to claim 9, wherein: Writing the data bit into the first memory cell further comprises: outputting the word line signal having the first logic level to a gate of a first transistor of a second memory cell, the first transistor including a first source / drain terminal coupled to a second select line and a second source / drain terminal coupled to a storage node of the second memory cell; outputting a second selection signal having a second logic level to the second selection line; receiving a second charge from the first transistor of the second memory cell, the second charge corresponding to the second logic level of the second select signal at the storage node of the second memory cell and at the gate of a second transistor of the second memory cell coupled to the storage node of the second memory cell; and In response to receiving the second charge, a memory device of the second memory cell is decoupled from a second bit line using the second transistor of the second memory cell.

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