Memory device

Abstract

A memory device is provided. The memory device includes: a first die; a second die electrically connected to the first die; a plurality of interconnects forming a signal transmission path between the first die and the second die; a plurality of flip-flops disposed in the first die, the plurality of flip-flops being electrically connected to the plurality of interconnects; and a test circuit disposed in the second die and electrically connected to the plurality of interconnects. A test circuit is configured to perform a test operation on the plurality of interconnects using the plurality of triggers.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0154817 filed on November 9, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a memory device, and more particularly, to a memory device including a plurality of dies. Background Art

[0003] Memory devices are used to store data and can be classified as volatile memory devices and non-volatile memory devices. Flash memory devices, a type of non-volatile memory device, can be used in mobile phones, digital cameras, mobile computing devices, stationary computing devices, or other devices.

[0004] As information and communication devices become more multifunctional, there is an increasing demand for memory devices with a variety of performance characteristics. Therefore, the demand for memory devices including different dies is increasing. In this case, an interconnection may be formed to electrically connect the different dies. When a defect occurs in such an interconnection, it may have a significant impact on the performance of the entire memory device. Summary of the invention

[0005] Example embodiments provide a memory device capable of effectively detecting a defective interconnection among interconnections forming a signal transmission path between different dies.

[0006] According to one aspect of an example embodiment, a memory device includes: a first die; a second die electrically connected to the first die; a plurality of interconnects forming a signal transmission path between the first die and the second die; a plurality of triggers disposed in the first die, the plurality of triggers electrically connected to the plurality of interconnects; and a test circuit disposed in the second die and electrically connected to the plurality of interconnects. The test circuit is configured to perform a test operation on the plurality of interconnects using the plurality of triggers.

[0007] According to one aspect of an example embodiment, a memory device includes: a first die; a second die; a plurality of through silicon vias extending through the second die and forming a signal transmission path to the first die; a plurality of triggers disposed in the first die, the plurality of triggers being electrically connected to the plurality of through silicon vias; and a test circuit disposed in the second die and electrically connected to the plurality of through silicon vias. The test circuit is configured to detect whether the plurality of through silicon vias are defective using the plurality of triggers.

[0008] According to one aspect of an example embodiment, a memory device includes: an interposer; a first die on the interposer; a second die on the interposer and spaced apart from the first die in a horizontal direction; a plurality of interconnects in the interposer forming a signal transmission path between the first die and the second die; a plurality of triggers in the first die electrically connected to the plurality of interconnects; and a test circuit in the second die electrically connected to the plurality of interconnects. The test circuit is configured to detect whether the plurality of interconnects are defective using the plurality of triggers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0010] Figure 1 is a diagram illustrating a memory device according to example embodiments.

[0011] Figure 2 is a block diagram illustrating a memory device according to example embodiments.

[0012] FIG. 3A to FIG. 3D It is shown Figure 2 FIG. 1 is a diagram of an example of a test operation of a memory device.

[0013] Figure 4 is a block diagram illustrating a memory device according to example embodiments.

[0014] Figure 5A It is shown Figure 4 A diagram of an example of operation of a memory device in a test mode, and Figure 5B It is shown Figure 4 A diagram of an example of operation of a memory device in a normal mode.

[0015] Figure 6 is a block diagram illustrating a memory device according to example embodiments.

[0016] 7A to 7C It is shown Figure 6 Schematic diagram of a repair operation of a memory device.

[0017] Figure 8 is a block diagram illustrating a memory device according to example embodiments.

[0018] 9A to 9C It is shown Figure 8 A diagram of the operation of a memory device.

[0019] Fig.10 is a block diagram illustrating a memory device according to example embodiments.

[0020] Fig.11 2 is a diagram illustrating conditions for identifying a defective through silicon via among second to eighth through silicon vias.

[0021] Fig.12 is a block diagram illustrating a memory device according to example embodiments.

[0022] Fig.13 2 is a diagram illustrating conditions for identifying a defective through silicon via among second to eighth through silicon vias.

[0023] Fig.14 is a block diagram illustrating a memory device according to example embodiments.

[0024] Fig.15 is a block diagram illustrating a memory device according to example embodiments.

[0025] Fig.16 is a block diagram illustrating a memory device according to example embodiments.

[0026] Fig.17 is a block diagram illustrating a memory device according to example embodiments. DETAILED DESCRIPTION

[0027] Hereinafter, example embodiments will be described with reference to the accompanying drawings. Throughout the specification, the same components are represented by the same reference numerals, and their repeated descriptions are omitted. It will be understood that when an element or layer is referred to as being "on", "connected to" or "bonded to" another element or layer, it may be directly on, connected to or bonded to another element or layer, or one or more intermediate elements or layers may be present between them. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly bonded to" another element or layer, there are not one or more intermediate elements or layers between them. The embodiments described herein are example embodiments, and therefore, the present disclosure is not limited thereto, and may be implemented in various other forms. Each example embodiment provided in the following description does not exclude being associated with one or more features of another example or another example embodiment also provided herein, or being associated with one or more features of another example or another example embodiment not provided herein but consistent with the present disclosure.

[0028] Figure 1 is a diagram illustrating a memory device 1000 according to example embodiments.

[0029] The memory device 1000 may include interconnects that electrically connect different dies to each other, and the memory device 1000 may detect whether one or more of the interconnects are defective. In this case, the memory device 1000 may constitute a virtual memory circuit, and may detect whether one or more of the interconnects are defective by a test operation performed on the virtual memory circuit. Therefore, the memory device 1000 may effectively detect whether the interconnect is defective without any overhead.

[0030] Will refer to Figure 1 A detailed description is provided. The memory device 1000 may include a first die 1100, a second die 1200, and interconnections 211 to 21n.

[0031] At least one semiconductor device may be provided on each of the first die 1100 and the second die 1200. For example, a flash memory, a dynamic RAM (DRAM), a resistive RAM (ReRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM) and a large number of memory elements may be provided on the first die 1100, and a circuit element such as a decoder and a control logic may be provided on the second die 1200. For example, a photoelectric conversion element such as a photodiode may be provided on the first die 1100, and a circuit element such as an analog-to-digital converter (ADC) may be provided on the second die 1200. However, this is only an example, and the semiconductor elements provided on the first die 1100 and the second die 1200 are not limited thereto.

[0032] The first die 1100 and the second die 1200 may be disposed in various ways and may be electrically connected to each other. To this end, the memory device 1000 may include interconnections 211 to 21n.

[0033] In one example embodiment, the first die 1100 and the second die 1200 may be stacked vertically. For example, each of the first die 1100 and the second die 1200 may be a vertically stacked memory die of a three-dimensional (3D) stacked memory. For example, each of the first die 1100 and the second die 1200 may be a vertically stacked system-in-package (SiP) logic die. For example, the first die 1100 may be a memory die, and the second die 1200 may be a logic die.

[0034] In this case, the interconnects 211 to 21n may electrically connect the vertically stacked first die 1100 and the second die 1200 to each other. For example, each of the interconnects 211 to 21n may be a through silicon via (or referred to as a through silicon via, hereinafter referred to as a "TSV"). In this case, the through silicon via TSV may be formed in the first die 1100, in the second die 1200, or in both the first die 1100 and the second die 1200. For example, each of the interconnects 211 to 21n may be a bump or a microbump disposed between the first die 1100 and the second die 1200. Alternatively, for example, each of the interconnects 211 to 21n may be a combination of a through silicon via TSV and a bump, a combination of a through silicon via TSV and a microbump, or a combination of a through silicon via TSV, a bump, and a microbump.

[0035] In an example embodiment, the first die 1100 and the second die 1200 may be arranged in a horizontal direction. For example, the first die 1100 and the second die 1200 may be implemented as a chiplet (or a small chip, a microchip). For example, the first die 1100 may be a logic die that performs a first function, and the second die 1200 may be a logic die that performs a second function, and the first die 1100 and the second die 1200 may be electrically connected through interconnects 211 to 21n. In this case, each of the interconnects 211 to 21n may be implemented as a through silicon via TSV.

[0036] In an example embodiment, each of the first die 1100 and the second die 1200 may be disposed on an interposer (or interposer, interposer). For example, the first die 1100 may be a memory die disposed on the interposer, the second die 1200 may be a logic die disposed on the interposer, and the first die 1100 and the second die 1200 may be electrically connected through interconnects 211 to 21n. In this case, each of the interconnects 211 to 21n may be a metal line disposed in the interposer. However, this is only an example, and each of the interconnects 211 to 21n may be a microbump disposed between the first die 1100 and the interposer or a microbump disposed between the second die 1200 and the interposer.

[0037] The memory device 1000 may perform a test operation to detect a defective interconnection among the interconnections 211 to 21n. In order to effectively perform a test operation on the interconnections 211 to 21n, the memory device 1000 may constitute a dummy memory circuit 1300, which includes the interconnections 211 to 21n. The dummy memory circuit 1300 may operate similarly to an internal memory (such as a static random access memory (SRAM)) of the memory device 1000. Therefore, a test operation on the internal memory may be equally applied to the dummy memory circuit 1300.

[0038] A more detailed description is now provided. Figure 1 As shown in , the first die 1100 may be implemented to include a plurality of flip-flops (F / F) 1111 to 111m. At least one interconnect may be connected to an input terminal of each flip-flop, and at least one interconnect may be connected to an output terminal of each flip-flop. The plurality of flip-flops 1111 to 111m and corresponding interconnects 211 to 21n may constitute a virtual memory circuit 1300.

[0039] Each of the plurality of flip-flops 1111 to 111m may correspond to, for example, a bit-cell of an SRAM. An interconnect connected to an input terminal of each flip-flop may correspond to an input port of the SRAM. An interconnect connected to an output terminal of each flip-flop may correspond to an output port of the SRAM. Therefore, the plurality of flip-flops 1111 to 111m and the corresponding interconnects 211 to 21n may operate similarly to an SRAM.

[0040] The second die 1200 may include a test circuit 1210 . For example, the test circuit 1210 of the second die 1200 may be used to check whether the SRAM operates normally. For example, the test logic used to test the SRAM in the test circuit 1210 may also be used to test the dummy memory circuit 1300 .

[0041] Typically, when a test operation is performed on an SRAM, a write operation, a read operation, and a comparison operation may be performed sequentially, wherein the write operation is used to input desired data into a bit cell, the read operation is used to read stored data from the bit cell, and the comparison operation is used to determine whether the data input into the bit cell and the data read from the bit cell are the same.

[0042] In a similar manner, in the test mode, the test circuit 1210 of the second die 1200 may perform a test operation on the dummy memory circuit 1300 through a data input operation, a data output operation, and a data comparison operation.

[0043] For example, during a data input operation in the test mode, the test circuit 1210 of the second die 1200 may provide an input signal to each flip-flop through an interconnect connected to an input terminal of each flip-flop. For example, the test circuit 1210 may provide an input signal to the first flip-flop 1111 through the first interconnect 211.

[0044] During the data output operation in the test mode, the test circuit 1210 of the second die 1200 can receive an output signal from each flip-flop through an interconnect connected to the output terminal of each flip-flop. For example, the test circuit 1210 can receive an output signal from the first flip-flop 1111 through the second interconnect 212.

[0045] During the data comparison operation in the test mode, the test circuit 1210 of the second die 1200 may compare the input signal and the output signal corresponding to each flip-flop, and determine whether the interconnect is defective based on the result of the comparison. For example, when the value of the input signal provided to the first flip-flop 1111 through the first interconnect 211 and the value of the output signal output from the first flip-flop 1111 through the second interconnect 212 are different from each other, the test circuit 1210 may determine that at least one of the first interconnect 211 and the second interconnect 212 is defective.

[0046] As described above, the memory device 1000 can perform a test operation on the interconnects 211 to 21n using the test logic used in the test operation for the internal memory (such as SRAM). Therefore, no additional logic circuit is required, so that the memory device 1000 can effectively perform a test operation on the interconnects 211 to 21n without any significant overhead.

[0047] Hereinafter, various examples of memory devices constituting a dummy memory circuit for detecting whether one or more interconnects are defective according to example embodiments will be described in more detail. Figures 2 to 11 An example is provided in which a trigger is formed on a first die Die1, an interconnection and a test circuit are formed on a second die Die2, and the first die Die1 and the second die Die2 are vertically stacked. In addition, an example is provided in which the interconnection is implemented using through silicon vias (TSVs) and the test circuit is implemented using memory built-in self-test (MBIST).

[0048] Figure 2 is a block diagram illustrating a memory device 1000A according to example embodiments. Figure 2 The memory device 1000A and Figure 1 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0049] Reference Figure 2 , the memory device 1000A may include a first die 1100A and a second die 1200A that are vertically stacked, and a dummy memory circuit 1300A may be formed across the first die 1100A and the second die 1200A.

[0050] The first die 1100A may include a plurality of triggers. Figure 2 As shown in , the first die 1100A may include first to third flip-flops (F / F1 ) 1111 to (F / F3 ) 1113 .

[0051] The second die 1200A may include a plurality of through silicon vias (TSVs) and an MBIST 1210. For example, the second die 1200A may be connected to first to seventh through silicon vias TSV1 to TSV7 and the MBIST 1210 connected thereto. According to example embodiments, the second die 1200A may further include an SRAM.

[0052] The first through silicon via 211 may receive the clock signal CLK from the MBIST 1210. The first through silicon via 211 may provide the clock signal CLK to the first to third flip-flops 1111 to 1113.

[0053] The second through silicon via 212 and the third through silicon via 213 may be electrically connected to the first trigger 1111 .

[0054] For example, the second through silicon via 212 may be connected to an input terminal of the first flip-flop 1111. A 0th data input signal DIN[0] from the MBIST 1210 may be provided to the first flip-flop 1111 through the second through silicon via 212. The third through silicon via 213 may be connected to an output terminal of the first flip-flop 1111. A 0th data output signal DOUT[0] from the first flip-flop 1111 may be provided to the MBIST 1210 through the third through silicon via 213.

[0055] Similarly, fourth and fifth TSVs 214 and 215 may be electrically connected to second flip-flop (F / F2 ) 1112 . First data input signal DIN[ 1 ] may be transmitted through fourth TSV 214 , and first data output signal DOUT[ 1 ] may be transmitted through fifth TSV 215 .

[0056] In addition, sixth and seventh TSVs 216 and 217 may be electrically connected to third flip-flop 1113. Second data input signal DIN[2] may be transmitted through sixth TSV 216, and second data output signal DOUT[2] may be transmitted through seventh TSV 217.

[0057] The dummy memory circuit 1300A may include first to third triggers 1111 to 1113 and first to seventh through silicon vias 211 to 217. MBIST 1210 may perform a test operation on the dummy memory circuit 1300A using a "test logic used in a test operation on an SRAM." Therefore, a defective through silicon via among the first to seventh through silicon vias 211 to 217 may be detected.

[0058] Figure 3A and Figure 3B It is shown Figure 2 FIG. 1 is a diagram of an example of a test operation of a memory device.

[0059] Figure 3A and Figure 3B It is shown Figure 2 100A. Specifically, Figure 3A is a timing diagram showing an example of a test operation when there is no defect in the through silicon vias 211 to 217, and Figure 3B is a diagram showing test results when no defects exist in the through silicon vias 211 to 217 .

[0060] Reference Figure 2 , Figure 3A and Figure 3B , a data input operation in the test mode may be performed between the first time t1 and the second time t2.

[0061] For example, a high-level 0th data input signal DIN[0] may be provided to the second TSV 212 between the first time t1 and the second time t2. The 0th data input signal DIN[0] may be provided to the input terminal of the first flip-flop 1111 through the second TSV 212.

[0062] A low-level first data input signal DIN[1] may be provided to the fourth through silicon via 214 between the first time t1 and the second time t2. The first data input signal DIN[1] may be provided to an input terminal of the second flip-flop 1112 via the fourth through silicon via 214.

[0063] A high-level second data input signal DIN[2] may be provided to the sixth through silicon via 216 between the first time t1 and the second time t2. The second data input signal DIN[2] may be provided to an input terminal of the third flip-flop 1113 via the sixth through silicon via 216.

[0064] At the second time t2 , the clock signal CLK may transition from a low level to a high level.

[0065] The data output operation and the data comparison operation in the test mode may be performed between the second time t2 and the third time t3.

[0066] For example, the first flip-flop 1111 may reflect the signal level at the input terminal to the output signal at the output terminal based on the rising edge of the clock signal CLK at the second time t2. The output signal of the first flip-flop 1111 may be transmitted to the MBIST 1210 as the 0th data output signal DOUT[0] via the third through silicon via 213 between the second time t2 and the third time t3.

[0067] When the second TSV 212 and the third TSV 213 are normal, a signal level of the 0th data input signal DIN[0] between the first time t1 and the second time t2 may be the same as a signal level of the 0th data output signal DOUT[0] between the second time t2 and the third time t3.

[0068] When at least one of the second through silicon via 212 and the third through silicon via 213 is defective, the signal level of the 0th data input signal DIN[0] may be distorted through the defective through silicon via. For example, when at least one of the second through silicon via 212 and the third through silicon via 213 is defective, the signal level of the 0th data input signal DIN[0] between the first time t1 and the second time t2 may be different from the signal level of the 0th data output signal DOUT[0] between the second time t2 and the third time t3.

[0069] MBIST 1210 may compare “the signal level of the 0th data input signal DIN[0] between the first time t1 and the second time t2” with “the signal level of the 0th data output signal DOUT[0] between the second time t2 and the third time t3”, and determine whether one or both of the second through silicon via 212 and the third through silicon via 213 are defective based on the comparison result.

[0070] For example, Figure 3A and Figure 3B As shown in , when the signal level of the 0th data input signal DIN[0] between the first time t1 and the second time t2 and the signal level of the 0th data output signal DOUT[0] between the second time t2 and the third time t3 are both high, MBIST 1210 can determine that the second silicon via 212 and the third silicon via 213 are normal.

[0071] Similarly, the second flip-flop 1112 can reflect the signal level at the input terminal to the output signal at the output terminal based on the rising edge of the clock signal CLK at the second time t2. The output signal of the second flip-flop 1112 can be transmitted to the MBIST1210 as the first data output signal DOUT[1] via the fifth silicon through via 215 between the second time t2 and the third time t3.

[0072] MBIST 1210 may compare “the signal level of the first data input signal DIN[1] between the first time t1 and the second time t2” with “the signal level of the first data output signal DOUT[1] between the second time t2 and the third time t3”, and determine whether one or both of the fourth through silicon via 214 and the fifth through silicon via 215 are defective based on the comparison result. For example, Figure 3A and Figure 3B As shown in , when the signal level of the first data input signal DIN[1] between the first time t1 and the second time t2 and the signal level of the first data output signal DOUT[1] between the second time t2 and the third time t3 are both low, MBIST 1210 can determine that the fourth silicon via 214 and the fifth silicon via 215 are normal.

[0073] Similarly, based on the rising edge of the clock signal CLK at the second time t2, the third flip-flop 1113 may reflect the signal level at the input terminal to the output signal at the output terminal, and the MBIST 1210 may determine whether one or both of the sixth through silicon via 216 and the seventh through silicon via 217 are defective. Figure 3A and Figure 3B As shown in , when the signal level of the second data input signal DIN[2] between the first time t1 and the second time t2 and the signal level of the second data output signal DOUT[2] between the second time t2 to the third time t3 are both high, MBIST 1210 can determine that the sixth silicon via 216 and the seventh silicon via 217 are normal.

[0074] The data input operation, the data output operation, and the data comparison operation in the test mode may be repeatedly performed between the third time t3 and the fifth time t5.

[0075] For example, the data input operation in the test mode may be performed between the third time t3 and the fourth time t4. In this case, the signal level of the data input signal may be set to be different from the signal level between the first time t1 and the second time t2. At the fourth time t4, the clock signal CLK may be changed from a low level to a high level. The data output operation and the data comparison operation in the test mode may be performed between the fourth time t4 and the fifth time t5.

[0076] The data input operation, data output operation, and data comparison operation in the test mode may be repeatedly performed between the fifth time t5 and the seventh time t7. For example, the data input operation in the test mode may be performed between the fifth time t5 and the sixth time t6. The data output operation and data comparison operation in the test mode may be performed between the sixth time t6 and the seventh time t7.

[0077] In addition, the data input operation, data output operation, and data comparison operation in the test mode may be repeatedly performed between the seventh time t7 and the ninth time t9. For example, the data input operation in the test mode may be performed between the seventh time t7 and the eighth time t8. The data output operation and data comparison operation in the test mode may be performed between the eighth time t8 and the ninth time t9.

[0078] As described above, when the signal level of the data input signal supplied to the “through silicon via connected to the input terminal of the flip-flop” is the same as the signal level of the data output signal output from the “through silicon via connected to the output terminal of the flip-flop”, it can be determined that the through silicon via is normal.

[0079] Figure 3C and Figure 3D It is shown Figure 2 FIG. 1 is a diagram showing another example of a test operation of the memory device 1000A. Figure 3C In the example, at least one of the second through silicon via 212 and the third through silicon via 213 is defective. Figure 3D In FIG. 1 , an example is provided in which the first through silicon via 211 is defective.

[0080] When a through silicon via is defective, a signal level of a signal provided through the through silicon via may be distorted.

[0081] For example, when a through silicon via connected to an input terminal of a trigger is defective, a signal level of a data input signal provided to the defective through silicon via may be distorted. Therefore, a signal level of a data input signal provided to the defective through silicon via and a signal level of a data output signal corresponding to the data input signal may be different from each other.

[0082] Similarly, when a through silicon via connected to an output terminal of a trigger is defective, or when both through silicon vias connected to an input terminal and an output terminal of the trigger are defective, a signal level of a data input signal and a signal level of a data output signal corresponding to the data input signal may be different from each other.

[0083] Now refer to Figure 2 and Figure 3C A detailed description is provided. When at least one of the second through silicon via 212 and the third through silicon via 213 is defective, the 0th data input signal DIN[0] may be distorted via the defective through silicon via. Therefore, the signal level of the 0th data input signal DIN[0] and the signal level of the 0th data output signal (DOUT[0]) may be different from each other.

[0084] For example, the signal level of the 0th data input signal DIN[0] is a high level between the first time t1 and the second time t2, but the signal level of the 0th data output signal DOUT[0] may be a low level between the second time t2 and the third time t3. In addition, the signal level of the 0th data input signal DIN[0] is a high level between the fifth time t5 and the sixth time t6, but the signal level of the 0th data output signal DOUT[0] may be a low level between the sixth time t6 and the seventh time t7.

[0085] In this case, the MBIST 1210 may determine that at least one of the second through silicon via 212 corresponding to the 0th data input signal DIN[0] and the third through silicon via 213 corresponding to the 0th data output signal DOUT[0] is defective.

[0086] In addition, for example, when the through silicon via through which the clock signal CLK passes is defective, the clock signal CLK provided to each flip-flop may be distorted. In this case, all flip-flops operate incorrectly, so that the data input signal and the corresponding data output signal may not match each other in many cases. Alternatively, in this case, all flip-flops operate incorrectly, so that the data input signal and the corresponding data output signal may randomly not match each other.

[0087] Now refer to Figure 2 and Figure 3D A detailed description is provided. When the first through silicon via 211 is defective, the clock signal CLK may be distorted via the defective first through silicon via 211, and the first to third flip-flops 1111 to 1113 may operate based on the distorted clock signal. Figure 3D As shown in , errors may occur in all through silicon vias TSV2 to TSV7 corresponding to the first to third flip-flops 1111 to 1113. In this case, the MBIST 1210 may determine that the first through silicon via 211 corresponding to the clock signal CLK is defective.

[0088] As mentioned above Figures 2 to 3D As described above, the memory device 1000A can detect whether one or more of the through silicon vias are defective by "using the test logic used when testing the SRAM". In this case, no additional logic circuit is required, so that the memory device 1000A can effectively perform the test operation on the through silicon vias without any additional overhead.

[0089] In addition, the memory device 1000A can perform a test operation on the through silicon via by adjusting the cycle of the clock signal and the cycle of the data input signal. Since the cycle of the clock signal and the cycle of the data input signal can be set to be short, the memory device 1000A can perform a test operation on the through silicon via at a high speed.

[0090] Figure 4 is a block diagram illustrating a memory device 1000B according to example embodiments. Figure 4 The memory device 1000B and Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0091] For ease of description, an example will be provided in which the first die 1100B and the second die 1200B respectively include a first logic circuit 1130 and a second logic circuit 1230. When the memory device 1000B operates in a normal mode (such as a read operation, a write operation, a calculation operation, or a data processing operation), the first logic circuit 1130 of the first die 1100B and the second logic circuit 1230 of the second die 1200B may be electrically connected to each other.

[0092] The memory device 1000B may support a switching operation between a test mode and a normal mode, and thus may selectively operate in the test mode and the normal mode. To this end, the memory device 1000B may further include a mode multiplexer.

[0093] Reference Figure 4 , the memory device 1000B may include a first die 1100B and a second die 1200B.

[0094] The first die 1100B may include first to third flip-flops (F / F1 ) 1111 to (F / F3 ) 1113 . In addition, the first die 1100B may include a first logic circuit 1130 and first to third mode multiplexers 1121 to 1123 .

[0095] The second die 1200B may include first to seventh through silicon vias 211 to 217 and an MBIST 1210. In addition, the second die 1200B may include a second logic circuit 1230 and fourth to sixth mode multiplexers 1221 to 1223.

[0096] A virtual memory circuit 1300B may be formed across the first die 1100B and the second die 1200B. The virtual memory circuit 1300B may include first to third flip-flops 1111 to 1113 and first to seventh through silicon vias 211 to 217. According to example embodiments, the virtual memory circuit 1300B may include first to third mode multiplexers 1121 to 1123 and fourth to sixth mode multiplexers 1221 to 1223.

[0097] In an example embodiment, the memory device 1000B may support a test mode and a normal mode. The first to third mode multiplexers 1121 to 1123 and the fourth to sixth mode multiplexers 1221 to 1223 of the memory device 1000B may perform a switching operation between the test mode and the normal mode.

[0098] In the test mode, the MBIST 1210 of the second die 1200B may be electrically connected to the dummy memory circuit 1300B through the fourth to sixth mode multiplexers 1221 to 1223. Therefore, detection may be made as to whether one or more of the first to seventh TSVs 211 to 217 are defective.

[0099] In the normal mode, the first logic circuit 1130 of the first die 1100B may be electrically connected to the second logic circuit 1230 of the second die 1200B through the first to third mode multiplexers 1121 to 1123 and the fourth to sixth mode multiplexers 1221 to 1223. Thus, an operation of the memory device 1000B in the normal mode (such as a read operation, a write operation, a calculation operation, or a data processing operation) may be performed.

[0100] As described above, switching operations between the test mode and the normal mode can be supported, and thus the memory device 1000B can detect not only defects in the through silicon vias during the memory manufacturing process, but also defects caused by "deterioration or damage of the through silicon vias caused by the use of the through silicon vias".

[0101] Figure 5A It is shown Figure 4 is a diagram of an example of operation of a memory device 1000B in a test mode, and Figure 5B It is shown Figure 4 1 is a diagram of an example of operation of a memory device 1000B in a normal mode.

[0102] Reference Figure 5A , in the test mode, the test mode signal TM may be set to "1". Therefore, the fourth mode multiplexer 1221 to the sixth mode multiplexer 1223 of the second die 1200B may each electrically connect the MBIST 1210 to the through silicon via. In addition, the first mode multiplexer 1121 to the third mode multiplexer 1123 of the first die 1100B may each electrically connect the trigger to the through silicon via. Therefore, the MBIST 1210 may be electrically connected to the virtual memory circuit 1300B in the test mode.

[0103] A test operation may be performed on the dummy memory circuit 1300B to detect whether one or more of the first through silicon via 211 to the seventh through silicon via 217 is defective.

[0104] Reference Figure 5B , in the normal mode, the test mode signal TM may be set to "0". Therefore, the fourth mode multiplexer 1221 to the sixth mode multiplexer 1223 of the second die 1200B may each electrically connect the second logic circuit 1230 to the through silicon via. In addition, the first mode multiplexer 1121 to the third mode multiplexer 1123 of the first die 1100B may each electrically connect the first logic circuit 1130 to the through silicon via. Therefore, in the normal mode, the first logic circuit 1130 of the first die 1100B and the second logic circuit 1230 of the second die 1200B may be electrically connected to each other through the first through silicon via 211 to the seventh through silicon via 217.

[0105] The memory device 1000B may perform an operation (such as a read operation, a write operation, a calculation operation, or a data processing operation) in a normal mode.

[0106] As described above, the memory device 1000B can support a switching operation between a test mode and a normal mode.

[0107] Figure 6 is a block diagram illustrating a memory device 1000C according to example embodiments. Figure 6 The memory device 1000C is Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0108] For convenience of description, an example will be provided in which the memory device 1000C includes two redundant through silicon vias 221 (RTSV1) and 222 (RTSV2).

[0109] The memory device 1000C may perform a repair operation on a defective through silicon via. To this end, the memory device 1000C may include a redundant through silicon via and a shift circuit.

[0110] Now refer to Figure 6 A detailed description is provided. The memory device 1000C may include a first die 1100C and a second die 1200C.

[0111] The first die 1100C may include first to third flip-flops (F / F1 ) 1111 to (F / F3 ) 1113 . Furthermore, the first die 1100C may include a first shift circuit 1140 and a second shift circuit 1150 .

[0112] The first shift circuit 1140 may include first to third shift multiplexers 1141 to 1143 .

[0113] An input terminal of the first shift multiplexer 1141 may be connected to the second through silicon via 212 and the fourth through silicon via 214, and an output terminal of the first shift multiplexer 1141 may be connected to an input terminal of the first flip-flop 1111. The first shift multiplexer 1141 may electrically connect the second through silicon via 212 or the fourth through silicon via 214 to the input terminal of the first flip-flop 1111 according to the 0th flag signal FLA[0].

[0114] An input terminal of the second shift multiplexer 1142 may be connected to the fourth through silicon via 214 and the sixth through silicon via 216, and an output terminal of the second shift multiplexer 1142 may be connected to an input terminal of the second flip-flop 1112. The second shift multiplexer 1142 may electrically connect the fourth through silicon via 214 or the sixth through silicon via 216 to the input terminal of the second flip-flop 1112 according to the first flag signal FLA[1].

[0115] An input terminal of the third shift multiplexer 1143 may be connected to the sixth through silicon via 216 and the first redundant through silicon via 221, and an output terminal of the third shift multiplexer 1143 may be connected to an input terminal of the third flip-flop 1113. The third shift multiplexer 1143 may electrically connect the sixth through silicon via 216 or the first redundant through silicon via 221 to the input terminal of the third flip-flop 1113 according to the second flag signal FLA[2].

[0116] The second shift circuit 1150 may include a fourth shift multiplexer 1151 and a fifth shift multiplexer 1152 .

[0117] An input terminal of the fourth shift multiplexer 1151 may be connected to an output terminal of the first flip-flop 1111 and an output terminal of the second flip-flop 1112, and an output terminal of the fourth shift multiplexer 1151 may be connected to the fifth through silicon via 215. The fourth shift multiplexer 1151 may electrically connect the output terminal of the first flip-flop 1111 or the output terminal of the second flip-flop 1112 to the fifth through silicon via 215 according to the 0th flag signal FLA[0].

[0118] An input terminal of the fifth shift multiplexer 1152 may be connected to an output terminal of the second flip-flop 1112 and an output terminal of the third flip-flop 1113, and an output terminal of the fifth shift multiplexer 1152 may be connected to the seventh through silicon via 217. The fifth shift multiplexer 1152 may electrically connect the output terminal of the second flip-flop 1112 or the output terminal of the third flip-flop 1113 to the seventh through silicon via 217 according to the first flag signal FLA[1].

[0119] The second die 1200C may include first to seventh TSVs 211 to 217 and an MBIST 1210 . In addition, the second die 1200C may include first and second redundant TSVs 221 and 222 , a third shift circuit 1240 , and a fourth shift circuit 1250 .

[0120] The third shift circuit 1240 may include a sixth shift multiplexer 1241 and a seventh shift multiplexer 1242 .

[0121] An input terminal of the sixth shift multiplexer 1241 may receive the 0th data input signal DIN[0] and the first data input signal DIN[1], and an output terminal of the sixth shift multiplexer 1241 may be connected to the fourth through silicon via 214. The sixth shift multiplexer 1241 may transmit the 0th data input signal DIN[0] or the first data input signal DIN[1] to the fourth through silicon via 214[0] according to the 0th flag signal FLA[0].

[0122] An input terminal of the seventh shift multiplexer 1242 may receive the first data input signal DIN[1] and the second data input signal DIN[2], and an output terminal of the seventh shift multiplexer 1242 may be connected to the sixth through silicon via 216. The seventh shift multiplexer 1242 may transmit the first data input signal DIN[1] or the second data input signal DIN[2] to the sixth through silicon via 216 according to the first flag signal FLA[1].

[0123] The fourth shift circuit 1250 may include eighth to tenth shift multiplexers 1251 to 1253 .

[0124] Input terminals of the eighth shift multiplexer 1251 may be connected to the third TSV 213 and the fifth TSV 215. The eighth shift multiplexer 1251 may output one of the signals transmitted through the third TSV 213 and the fifth TSV 215 as the 0th data output signal DOUT[0] according to the 0th flag signal FLA[0].

[0125] An input terminal of the ninth shift multiplexer 1252 may be connected to the fifth TSV 215 and the seventh TSV 217. The ninth shift multiplexer 1252 may output one of the signals transmitted through the fifth TSV 215 and the seventh TSV 217 as a first data output signal DOUT[1] according to the first flag signal FLA[1].

[0126] An input terminal of the tenth shift multiplexer 1253 may be connected to the seventh TSV 217 and the second redundant TSV 222. The tenth shift multiplexer 1253 may output one of the signals transmitted through the seventh TSV 217 and the second redundant TSV 222 as a second data output signal DOUT[2] according to the second flag signal FLA[2].

[0127] A dummy memory circuit 1300C may be formed across the first die 1100C and the second die 1200C. The dummy memory circuit 1300C may include first to third flip-flops 1111 to 1113, first to seventh through silicon vias 211 to 217, and first to second redundant through silicon vias 221 to 222. According to example embodiments, the dummy memory circuit 1300C may include first to fourth shift circuits 1140, 1150, 1240, and 1250.

[0128] According to example embodiments, the memory device 1000C may perform a repair operation on a defective through silicon via. For example, when one of the first through silicon via 211 to the seventh through silicon via 217 is determined to be defective, the memory device 1000C may replace the defective through silicon via with a redundant through silicon via. For example, the memory device 1000C may identify a defective through silicon via and avoid the defective through silicon via with a redundant through silicon via.

[0129] The first redundant TSV 221 may be provided to perform a repair operation on a defective TSV among upward TSVs. The upward TSV may refer to a TSV for transmitting a signal from the second die 1200C to the first die 1100C.

[0130] For example, Figure 6 As shown in , each of the second through silicon via 212, the fourth through silicon via 214, and the sixth through silicon via 216 may receive a data input signal and may correspond to an upward through silicon via. When one of the second through silicon via 212, the fourth through silicon via 214, and the sixth through silicon via 216 is defective, the first redundant through silicon via 221 may replace the defective through silicon via. For example, the memory device 1000C may identify a defective through silicon via and utilize the first redundant through silicon via 221 to avoid the defective through silicon via.

[0131] The second redundant TSV 222 may be provided to perform a repair operation on a defective TSV among downward TSVs. The downward TSV may refer to a TSV for transmitting a signal from the first die 1100C to the second die 1200C.

[0132] For example, Figure 6As shown in , each of the third through silicon via 213, the fifth through silicon via 215, and the seventh through silicon via 217 may receive a data output signal and may correspond to a downward through silicon via. When one of the third through silicon via 213, the fifth through silicon via 215, and the seventh through silicon via 217 is defective, the second redundant through silicon via 222 may replace the defective through silicon via. For example, the memory device 1000C may identify a defective through silicon via and utilize the second redundant through silicon via 222 to avoid the defective through silicon via.

[0133] The first to fourth shift circuits 1140 , 1150 , 1240 , and 1250 may operate according to the flag signal FLA[2:0] and may select a redundant through silicon via (rather than a defective through silicon via).

[0134] For example, Figure 6 As shown in FIG. 1 , the first shift circuit 1140 and the third shift circuit 1240 may be electrically connected to the upward TSVs 212, 214, and 216 and the first redundant TSV 221. When one of the upward TSVs 212, 214, and 216 is defective, the first shift circuit 1140 and the third shift circuit 1240 may block a signal transmission path through the defective TSV and generate a signal transmission path through the first redundant TSV 221.

[0135] In addition, for example, the second shift circuit 1150 and the fourth shift circuit 1250 may be electrically connected to the downward through silicon vias 213, 215, 217 and the second redundant through silicon via 222. When one of the downward through silicon vias 213, 215, and 217 is defective, the second shift circuit 1150 and the fourth shift circuit 1250 may block a signal transmission path through the defective through silicon via and generate a signal transmission path through the second redundant through silicon via 222.

[0136] As described above, the memory device 1000C may support a repair operation on a defective through silicon via.

[0137] Furthermore, according to example embodiments, the second die 1200C may further include a repair information storage medium 1220. The repair information storage medium 1220 may store information on a flag signal FLA[2:0] used in a repair operation.

[0138] The repair information storage medium 1220 may be implemented as a nonvolatile memory such as a one-time programmable (OTP) memory, an electric fuse, a flash memory, etc. Therefore, information on the flag signal FLA[2:0] used in the repair operation may be continuously maintained. As a result, even when the memory device 1000C is powered off and then powered on again, the memory device 1000C does not need to perform the operation of detecting a defective through silicon via and the repair operation again, and the memory device 1000C may operate stably.

[0139] 7A to 7C It is shown Figure 6 Schematic diagram of a repair operation of a memory device 1000C. Fig. 7A This shows that when there are no defects in the TSV Figure 6 000C is a diagram of an example of the operation of the memory device 1000C. Figure 7B is a graph showing that when a defect occurs in at least one of the second through silicon via 212 and the third through silicon via 213 Figure 6 1000C is a diagram of an example of a repair operation of a memory device 1000C. Figure 7C is a graph showing that when a defect occurs in at least one of the fourth through silicon via 214 and the fifth through silicon via 215 Figure 6 1000C is a diagram of an example of a repair operation of a memory device 1000C.

[0140] For ease of description, refer to Figure 2 and FIG. 3A to FIG. 3D Similar to the description, an example will be provided in which when it is determined that at least one TSV connected to the input and output terminals of the trigger is defective, all TSVs connected to the input and output terminals of the trigger are replaced with redundant TSVs.

[0141] Reference Fig. 7A , providing an example where the second through silicon via 212 to the seventh through silicon via 217 are all normal. In this case, the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be selected as "0", "0", and "0", respectively.

[0142] In this case, if Fig. 7A As shown in , the first to third shift multiplexers 1141 to 1143, the fourth shift multiplexer 1151, the fifth shift multiplexer 1152, the sixth shift multiplexer 1241, the seventh shift multiplexer 1242 and the eighth to tenth shift multiplexers 1251 to 1253 can form a signal transmission path according to the flag signal "0".

[0143] For example, the first shift multiplexer 1141 may connect the second through silicon via 212 to the input terminal of the first flip-flop 1111 according to the 0th flag signal FLA[0] having a value of “0”. Therefore, the 0th data input signal DIN[0] may be provided to the input terminal of the first flip-flop 1111. In addition, the eighth shift multiplexer 1251 may output “the signal of the third through silicon via 213 connected to the output terminal of the first flip-flop 1111” as the 0th data output signal DOUT[0] according to the 0th flag signal FLA[0] having a value of “0”. As a result, the input terminal and the output terminal of the first flip-flop 1111 may be electrically connected to the second through silicon via 212 and the third through silicon via 213, respectively.

[0144] Similarly, when the values ​​of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] are “0”, “0”, and “0”, respectively, the input terminal and the output terminal of the second flip-flop 1112 may be electrically connected to the fourth through silicon via 214 and the fifth through silicon via 215, respectively. In addition, the input terminal and the output terminal of the third flip-flop 1113 may be electrically connected to the sixth through silicon via 216 and the seventh through silicon via 217, respectively.

[0145] The values ​​"0", "0", and "0" of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be stored in the repair information storage medium 1220. Therefore, even when the memory device 1000C is powered off and then powered on, the memory device 1000C may be stably operated through a normal through silicon via.

[0146] Reference Figure 7B , providing an example where at least one of the second through silicon via 212 and the third through silicon via 213 is defective. In this case, the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be selected as "1", "1", and "1", respectively. Therefore, the signal transmission path passing through the second through silicon via 212 and the third through silicon via 213 may be blocked, and the signal transmission path passing through the first redundant through silicon via 221 and the second redundant through silicon via 222 may be formed.

[0147] For example, the first shift multiplexer 1141 and the sixth shift multiplexer 1241 may be electrically connected through the fourth through silicon via 214 according to the 0th flag signal FLA[0] having a value of "1". Therefore, the 0th data input signal DIN[0] may be transmitted to the input terminal of the first flip-flop 1111 via the fourth through silicon via 214. For example, the signal transmission path through the second through silicon via 212 may be blocked, and the 0th data input signal DIN[0] may be transmitted to the input terminal of the first flip-flop 1111 through the signal transmission path including the fourth through silicon via 214.

[0148] In addition, the fourth shift multiplexer 1151 and the eighth shift multiplexer 1251 may be electrically connected through the fifth through silicon via 215 according to the 0th flag signal FLA[0] having a value of "1". Therefore, the output signal of the first flip-flop 1111 may be output as the 0th data output signal DOUT[0] via the fifth through silicon via 215. For example, the signal transmission path through the third through silicon via 213 may be blocked, and the 0th data output signal DOUT[0] may be output through the signal transmission path including the fifth through silicon via 215.

[0149] As a result, the signal transmission path through which the 0th data input signal DIN[0] and the 0th data output signal DOUT[0] are transmitted can be shifted, and the input terminal and the output terminal of the first trigger 1111 can be electrically connected to the fourth silicon via 214 and the fifth silicon via 215, respectively.

[0150] Similarly, when the values ​​of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] are “1”, “1”, and “1”, respectively, the signal transmission path through which the first data input signal DIN[1] and the first data output signal DOUT[1] are transmitted may be shifted, and the input terminal and the output terminal of the second flip-flop 1112 may be electrically connected to the sixth through silicon via 216 and the seventh through silicon via 217, respectively. In addition, the signal transmission path through which the second data input signal DIN[2] and the second data output signal DOUT[2] are transmitted may be shifted, and the input terminal and the output terminal of the third flip-flop 1113 may be electrically connected to the first redundant through silicon via 221 and the second redundant through silicon via 222, respectively.

[0151] As described above, a signal transmission path through which a data input signal and a data output signal are transmitted may be shifted, and thus a repair operation may be performed on a defective through silicon via.

[0152] The values ​​“1”, “1”, and “1” of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be stored in the repair information storage medium 1220. Therefore, even when the memory device 1000C is powered off and then powered on, the memory device 1000C may be stably operated through the first redundant through silicon via 221 and the second redundant through silicon via 222 instead of the defective through silicon vias 212 and 213.

[0153] Reference Figure 7C, providing an example where at least one of the fourth and fifth through silicon vias 214 and 215 is defective. In this case, the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be selected as "0", "1", and "1", respectively. Therefore, the signal transmission path passing through the fourth through silicon via 214 and the fifth through silicon via 215 may be blocked, and the signal transmission path passing through the first redundant through silicon via 221 and the second redundant through silicon via 222 may be formed.

[0154] For example, when the values ​​of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] are respectively "0", "1", and "1", the signal transmission path through which the 0th data input signal DIN[0] and the 0th data output signal DOUT[0] are transmitted can maintain the same Fig. 7A However, the signal transmission path through which the first data input signal DIN[1] and the first data output signal DOUT[1] are transmitted may be shifted, and the input terminal and the output terminal of the second flip-flop 1112 may be electrically connected to the sixth through silicon via 216 and the seventh through silicon via 217, respectively. In addition, the signal transmission path through which the second data input signal DIN[2] and the second data output signal DOUT[2] are transmitted may be shifted, and the input terminal and the output terminal of the third flip-flop 1113 may be electrically connected to the first redundant through silicon via 221 and the second redundant through silicon via 222, respectively.

[0155] The values ​​“0”, “1”, and “1” of the 0th flag signal FLA[0], the first flag signal FLA[1], and the second flag signal FLA[2] may be stored in the repair information storage medium 1220. Therefore, even when the memory device 1000C is powered off and then powered on, the memory device 1000C may be stably operated through the first and second redundant through silicon vias 221 and 222 instead of the defective through silicon vias 214 and 215.

[0156] Although not shown, similarly, when at least one of the sixth through silicon via 216 and the seventh through silicon via 217 is defective, the signal transmission path through which the second data input signal DIN[2] and the second data output signal DOUT[2] are transmitted may be shifted, and the input terminal and the output terminal of the third trigger 1113 may be electrically connected to the first redundant through silicon via 221 and the second redundant through silicon via 222, respectively.

[0157] As reference Figures 6 to 7CAs described, the memory device 1000C according to the example embodiment may support a repair operation for a defective through silicon via. For example, the memory device 1000C according to the example embodiment may shift a signal transmission path through which a data input signal and a data output signal are transmitted to perform a repair operation for a defective through silicon via.

[0158] exist Figures 6 to 7C In the present invention, a description has been provided for an example in which, when it is determined that at least one through silicon via connected to the input terminal and the output terminal of the trigger is defective, all through silicon vias connected to the input terminal and the output terminal of the trigger are replaced with redundant through silicon vias. However, this is only an example, and it should be understood that example embodiments are not limited thereto.

[0159] According to an exemplary embodiment, as will be referred to below Figures 8 to 12 As described, the memory device according to the example embodiment can accurately identify the defective TSV. In this case, the memory device according to the example embodiment can also perform a repair operation on the identified defective TSV by setting the “value of the flag signal provided to the shift multiplexer” in various ways.

[0160] Figure 8 is a block diagram illustrating a memory device 1000D according to example embodiments. Figure 8 The memory device 1000D and Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0161] For ease of description, an example will be provided in which the decoding circuits 1160 and 1170 are formed on the first die 1100D. However, this is merely an example, and example embodiments are not limited thereto. For example, in an example embodiment, the decoding circuits 1160 and 1170 may be formed on the second die 1200D.

[0162] The memory device 1000D according to example embodiments may accurately identify a defective through silicon via among a plurality of through silicon vias. To this end, the memory device 1000D may further include a decoding circuit.

[0163] Reference Figure 8 , for example, the memory device 1000D may include a first die 1100D and a second die 1200D.

[0164] The first die 1100D may include first to fourth flip-flops (F / F1 ) 1111 to (F / F4 ) 1114 . The first die 1100D may also include a first decoding circuit 1160 and a second decoding circuit 1170 .

[0165] The first decoding circuit 1160 may include a first decoding multiplexer 1161 and a second decoding multiplexer 1162 .

[0166] An input terminal of the first decoding multiplexer 1161 may be connected to the second through silicon via 212 and the fourth through silicon via 214, and an output terminal of the first decoding multiplexer 1161 may be connected to an input terminal of the first flip-flop 1111. The first decoding multiplexer 1161 may electrically connect one of the second through silicon via 212 and the fourth through silicon via 214 to the input terminal of the first flip-flop 1111 according to the address signal ADDR.

[0167] An input terminal of the second decoding multiplexer 1162 may be connected to the second through silicon via 212 and the fourth through silicon via 214, and an output terminal of the second decoding multiplexer 1162 may be connected to an input terminal of the second flip-flop 1112. The second decoding multiplexer 1162 may electrically connect one of the second through silicon via 212 and the fourth through silicon via 214 to the input terminal of the second flip-flop 1112 according to the address signal ADDR.

[0168] The second decoding circuit 1170 may include a third decoding multiplexer 1171 and a fourth decoding multiplexer 1172 .

[0169] An input terminal of the third decoding multiplexer 1171 may be connected to the sixth through silicon via 216 and the eighth through silicon via 218, and an output terminal of the third decoding multiplexer 1171 may be connected to an input terminal of the third flip-flop 1113. The third decoding multiplexer 1171 may electrically connect one of the sixth through silicon via 216 and the eighth through silicon via 218 to the input terminal of the third flip-flop 1113 according to the address signal ADDR.

[0170] An input terminal of the fourth decoding multiplexer 1172 may be connected to the sixth through silicon via 216 and the eighth through silicon via 218, and an output terminal of the fourth decoding multiplexer 1172 may be connected to an input terminal of the fourth flip-flop 1114. The fourth decoding multiplexer 1172 may electrically connect one of the sixth through silicon via 216 and the eighth through silicon via 218 to the input terminal of the fourth flip-flop 1114 according to the address signal ADDR.

[0171] The second die 1200D may include first to ninth TSVs 211 to 219 and an MBIST 1210 .

[0172] The virtual memory circuit 1300D may be formed across the first die 1100D and the second die 1200D. The virtual memory circuit 1300D may include first to fourth flip-flops 1111 to 1114 and first to ninth through silicon vias 211 to 219. In addition, according to example embodiments, the virtual memory circuit 1300C may include first and second decoding circuits 1160 and 1170.

[0173] In one example embodiment, the memory device 1000D may perform a switching operation to accurately detect a defective through silicon via, the switching operation changing the through silicon via connected to the input terminal of each trigger. For example, when it is determined that at least one of two through silicon vias corresponding to a specific trigger is defective, the memory device 1000D may electrically connect a normal through silicon via to a trigger corresponding to the through silicon via that needs to be inspected for defects. Therefore, the defective through silicon via may be accurately detected.

[0174] 9A to 9C It is shown Figure 8 Schematic diagram of the operation of the memory device 1000D. Fig. 9A An example of a signal transmission path of the memory device 1000D when the address ADDR is "0" is shown. Fig. 9B An example of a signal transmission path of the memory device 1000D when the address ADDR is "1" is shown. Fig. 9C An example of conditions for identifying a defective through silicon via among the second through silicon vias to the ninth through silicon vias is shown.

[0175] For ease of description, operations related to the second to fifth through silicon vias 212 to 215 among the first to ninth through silicon vias 211 to 219 will be mainly described below.

[0176] Reference Fig. 9A , the address ADDR can be set to "0".

[0177] In this case, the first decoding multiplexer 1161 may connect the second through silicon via 212 to the input terminal of the first flip-flop 1111 according to the address signal ADDR having a value of “0”. Therefore, the 0th data input signal DIN[0] may be provided to the input terminal of the first flip-flop 1111.

[0178] Furthermore, the second decoding multiplexer 1162 connects the fourth through silicon via 214 to the input terminal of the second flip-flop 1112 in response to the address signal ADDR having a value of “0.” Thus, the first data input signal DIN[1] may be provided to the input terminal of the second flip-flop 1112 .

[0179] For ease of description, Figure 2 and Figure 3C Similarly, an example is provided in which at least one of the second through silicon via 212 and the third through silicon via 213 is defective and the fourth through silicon via 214 and the fifth through silicon via 215 are normal.

[0180] In this case, when a test operation is performed on the virtual memory circuit 1300D, the 0th data output signal DOUT[0] may be a fail, and the 1st data output signal DOUT[1] may be a pass. For example, based on the test result that the 0th data output signal DOUT[0] is a fail in a state where the address ADDR is "0", the MBIST 1210 may first determine that at least one of the second through silicon via 212 and the third through silicon via 213 is defective. In an example embodiment, the MBIST 1210 may perform an additional test operation after determining that at least one of the second through silicon via 212 and the third through silicon via 213 is defective.

[0181] Reference Fig. 9B , the address ADDR may be changed from "0" to "1" to accurately detect a defective TSV among the second TSV 212 and the third TSV 213. This results in the formation of a signal transmission path in which a TSV to be inspected for defects and a normal TSV are electrically connected to each other. MBIST 1210 may perform an additional test operation in a state in which the address ADDR is "1". A defective TSV among the second TSV 212 and the third TSV 213 may be accurately detected by the additional test operation.

[0182] A more detailed description is now provided. MBIST 1210 may first change the address ADDR from "0" to "1".

[0183] The first decoding multiplexer 1161 may connect the fourth through silicon via 214 to the input terminal of the first flip-flop 1111 according to the address signal ADDR having a value of “1”. Therefore, the fourth through silicon via 214 may be connected to the input terminal of the first flip-flop 1111. For example, the fourth through silicon via 214 that has been determined to be normal may be connected to the input terminal of the first flip-flop 1111, and the third through silicon via 213 that needs to be inspected for defects may be connected to the output terminal of the first flip-flop 1111.

[0184] The second decoding multiplexer 1162 may connect the second through silicon via 212 to the input terminal of the second flip-flop 1112 according to the address signal ADDR having a value of “1”. Therefore, the second through silicon via 212 may be connected to the input terminal of the second flip-flop 1112. For example, the second through silicon via 212 that needs to be inspected for defects may be connected to the input terminal of the second flip-flop 1112, and the fifth through silicon via 215 that has been determined to be normal may be connected to the output terminal of the second flip-flop 1112.

[0185] MBIST 1210 may perform additional test operations to accurately detect defective TSVs among the second TSVs 212 and the third TSVs 213 .

[0186] When the third TSV 213 is defective, the 0th data output signal DOUT[0] output from the third TSV 213 may be a fail. For example, the fourth TSV 214 is normal, so that when the third TSV 213 is defective, the 0th data output signal DOUT[0] output from the third TSV 213 may indicate a fault. Conversely, when the third TSV 213 is normal, the 0th data output signal DOUT[0] output from the third TSV 213 may be a pass.

[0187] When the second through silicon via 212 is defective, the first data output signal DOUT[1] output from the fifth through silicon via 215 may be a fail. For example, the fifth through silicon via 215 is normal, so that when the second through silicon via 212 is defective, the first data output signal DOUT[1] output through the second through silicon via 212 may be a fail. On the contrary, when the second through silicon via 212 is normal, the first data output signal DOUT[1] may be a pass.

[0188] The 0th data output signal DOUT[0] in the additional test operation may be an output signal corresponding to the first data input signal DIN[1], and the first data output signal DOUT[1] in the additional test operation may be an output signal corresponding to the 0th data input signal DIN[0].

[0189] In general, when the 0th data output signal DOUT[0] fails when the address ADDR is set to “0” and the first data output signal DOUT[1] fails when the address ADDR is set to “1”, the second through silicon via 212 may be determined to be defective.

[0190] Furthermore, when the 0th data output signal DOUT[0] is failed in a state where the address ADDR is set to “0” and the 0th data output signal DOUT[0] is failed in a state where the address ADDR is set to “1”, the third through silicon via 213 may be determined to be defective.

[0191] As described above, a signal transmission path may be formed to include TSVs that have been determined to be normal and TSVs that need to be inspected for defects, and an additional test operation may be performed. As a result, the memory device 1000D according to example embodiments may accurately detect defective TSVs.

[0192] Such a method of detecting defective through silicon vias may be similarly applied to other through silicon vias.

[0193] For example, refer to Fig. 9C, when the first data output signal DOUT[1] is failed in a state where the address ADDR is set to “0” and the 0th data output signal DOUT[0] is failed in a state where the address ADDR is set to “1”, the fourth through silicon via 214 may be determined to be defective.

[0194] Furthermore, when the first data output signal DOUT[1] is a fail if the address ADDR is set to “0” and the first data output signal DOUT[1] is a fail if the address ADDR is set to “1”, the fifth through silicon via 215 may be determined to be defective.

[0195] Similarly, in Fig. 9C Under the conditions shown in , defects of each of the sixth through silicon via 216 to the ninth through silicon via 219 can be accurately inspected.

[0196] exist Figure 8 , Fig. 9A and Fig. 9B In the embodiment, the decoding circuit 1160 and the decoding circuit 1170 have been described as being formed on the first die 1100D. However, this is merely an example, and example embodiments are not limited thereto. For example, according to example embodiments, the decoding circuit 1160 and the decoding circuit 1170 may be formed on the second die 1200D.

[0197] exist Figures 2 to 9C In the above description, a description has been provided for an example in which a single through silicon via corresponds to an input terminal or an output terminal of a single flip-flop. However, this is merely an example, and example embodiments are not limited thereto.

[0198] According to example embodiments, the number of upward through silicon vias may be greater than the number of downward through silicon vias. In this case, at least two through silicon vias may be connected to an input terminal of a single trigger.

[0199] Alternatively, according to example embodiments, the number of downward through silicon vias may be greater than the number of upward through silicon vias. In this case, at least two through silicon vias may be connected to the output terminal of a single trigger.

[0200] Even in such a situation, the memory device according to example embodiments can detect defective through silicon vias and perform a repair operation on the defective through silicon vias. This will be described below with reference to Figures 10 to 13 Describe in more detail.

[0201] Fig.10 is a block diagram illustrating a memory device 1000E according to example embodiments. Fig.10 The memory device 1000E is Figure 1 The memory device 1000 and Figure 8Therefore, the same or similar components will be represented by the same or similar reference numerals, and redundant descriptions will be omitted. Figure 8 Similarly, an example will be provided in which the first decoding circuit 1160 is formed on the first die 1100D.

[0202] In the memory device 1000E according to example embodiments, the number of downward through silicon vias may be greater than the number of upward through silicon vias. Therefore, at least two through silicon vias may be connected to the output terminal of a single trigger. Even in this case, the memory device 1000E may accurately detect defective through silicon vias.

[0203] Now refer to Fig.10 A more detailed description is provided. The memory device 1000E may include a first die 1100E and a second die 1200E.

[0204] The first die 1100E may include first to third flip-flops 1111 to 1113. In addition, the first die 1100E may include a first decoding circuit 1160. The first decoding circuit 1160 may include a first decoding multiplexer 1161 and a second decoding multiplexer 1162.

[0205] The second die 1200E may include first to eighth TSVs 211 to 218 and an MBIST 1210 .

[0206] The dummy memory circuit 1300E may be formed across the first die 1100E and the second die 1200E. The dummy memory circuit 1300E may include first to third flip-flops 1111 to 1113 and first to eighth through silicon vias 211 to 218. Furthermore, according to example embodiments, the dummy memory circuit 1300E may include a first decoding circuit 1160.

[0207] In an example embodiment, in the memory device 1000E, the number of downward through silicon vias may be greater than the number of upward through silicon vias. For example, a single through silicon via 216 may be electrically connected to an input terminal of the third trigger 1113, while two through silicon vias 217 and 218 may be electrically connected to an output terminal of the third trigger 1113. Even in this case, the memory device 1000E according to the example embodiment may accurately detect defective through silicon vias.

[0208] For example, when the second through silicon vias 212 to the fifth through silicon vias 215 need to be inspected, the memory device 1000E can electrically connect the normal through silicon vias to the through silicon vias that need to be inspected for defects using the first decoding circuit 1160. Therefore, defective through silicon vias among the second through silicon vias 212 to the fifth through silicon vias 215 can be accurately detected.

[0209] For example, in the case where the sixth through silicon vias 216 to the eighth through silicon vias 218 need to be inspected, the memory device 1000E may accurately detect defective through silicon vias based on the test results.

[0210] Fig.11 2 is a diagram illustrating conditions for identifying a defective through silicon via among second to eighth through silicon vias.

[0211] Conditions and references for determining whether one or more of the second through silicon via 212 to the fifth through silicon via 215 are defective Fig. 9B and Fig. 9C Therefore, the following description will be provided with respect to conditions for determining whether one or more of the sixth through silicon via 216 to the eighth through silicon via 218 are defective.

[0212] Reference Fig.10 and Fig.11 , the sixth through silicon via 216 may be connected to an input terminal of the third flip-flop 1113 , and the seventh through silicon via 217 and the eighth through silicon via 218 may be connected to an output terminal of the third flip-flop 1113 .

[0213] Therefore, when the sixth through silicon via 216 is defective, the second data input signal DIN[2] may be distorted through the sixth through silicon via 216, and thus the second data output signal DOUT[2] and the third data output signal DOUT[3] may also be distorted. As a result, regardless of whether the address ADDR is "0" or "1", when both the second data output signal DOUT[2] and the third data output signal DOUT[3] fail, the sixth through silicon via 216 may be determined to be defective.

[0214] In addition, when the seventh through silicon via 217 is defective, only the second data output signal DOUT[2] may be distorted. As a result, regardless of whether the address ADDR is "0" or "1", when the second data output signal DOUT[2] is a fail and the third data output signal DOUT[3] is a pass, the seventh through silicon via 217 may be determined to be defective.

[0215] In addition, when the eighth through silicon via 218 is defective, only the third data output signal DOUT[3] may be distorted. As a result, regardless of whether the address ADDR is "0" or "1", when the second data output signal DOUT[2] is a pass and the third data output signal DOUT[3] is a fail, the eighth through silicon via 218 may be determined to be defective.

[0216] As described above, in the memory device 1000E according to example embodiments, the number of downward TSVs may be greater than the number of upward TSVs. Even in this case, the memory device 1000E may accurately detect defective TSVs.

[0217] Fig.12 is a block diagram illustrating a memory device 1000F according to example embodiments. Fig.12 The memory device 1000F is Figure 1 The memory device 1000 and Fig.10 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted. For ease of description, an example will be provided in which the first decoding circuit 1160 and the third decoding circuit 1180 are formed on the first die 1100D.

[0218] In the memory device 1000E according to the example embodiment, the number of upward through silicon vias may be greater than the number of downward through silicon vias. Therefore, at least two through silicon vias may be connected to the input terminal of the trigger. Even in this case, the memory device 1000F may accurately detect defective through silicon vias.

[0219] Will refer to Fig.12 A more detailed description is provided. The memory device 1000F may include a first die 1100F and a second die 1200F.

[0220] The first die 1100F may include first to third flip-flops 1111 to 1113. In addition, the first die 1100F may include a first decoding circuit 1160 and a third decoding circuit 1180. The first decoding circuit 1160 may include a first decoding multiplexer 1161 and a second decoding multiplexer 1162, and the third decoding circuit 1180 may include a fifth decoding multiplexer 1181.

[0221] The second die 1200F may include first to eighth TSVs 211 to 218 and an MBIST 1210 .

[0222] The virtual memory circuit 1300F may be formed across the first die 1100F and the second die 1200F. The virtual memory circuit 1300F may include first to third flip-flops 1111 to 1113 and first to eighth through silicon vias 211 to 218. In addition, according to example embodiments, the virtual memory circuit 1300F may include first and third decoding circuits 1160 and 1180.

[0223] In one example embodiment, in the memory device 1000F, the number of upward through silicon vias may be greater than the number of downward through silicon vias. For example, two through silicon vias 216 and 218 may be electrically connected to the input terminal of the third trigger 1113, and a single through silicon via 217 may be electrically connected to the output terminal of the third trigger 1113. Even in this case, the memory device 1000F may accurately detect defective through silicon vias.

[0224] For example, when the second through silicon vias 212 to the fifth through silicon vias 215 need to be inspected, the memory device 1000F can electrically connect the normal through silicon vias to the through silicon vias that need to be inspected for defects using the first decoding circuit 1160. Therefore, defective through silicon vias among the second through silicon vias 212 to the fifth through silicon vias 215 can be accurately detected.

[0225] For example, when the sixth through silicon via 216 to the eighth through silicon via 218 need to be inspected, the memory device 1000F can electrically connect the normal through silicon vias to the through silicon vias that need to be inspected for defects using the third decoding circuit 1180. Therefore, the defective through silicon vias among the sixth through silicon via 216 to the eighth through silicon via 218 can be accurately detected.

[0226] Fig.13 2 is a diagram illustrating conditions for identifying a defective through silicon via among second to eighth through silicon vias.

[0227] Conditions and references for determining whether one or more of the sixth through silicon via 216 to the eighth through silicon via 218 are defective Fig. 9B and Fig. 9C The conditions described are the same. Therefore, the following description will be provided for the conditions for determining whether one or more of the sixth through silicon via 216 to the eighth through silicon via 218 are defective. During the execution of the test operation, the fifth decoding multiplexer 1181 may connect the sixth through silicon via 216 to the input terminal of the third trigger 1113 according to the address signal ADDR having a value of "0". The fifth decoding multiplexer 1181 may connect the eighth through silicon via 218 to the input terminal of the third trigger 1113 according to the address signal ADDR having a value of "1". For example, the sixth through silicon via 216 that needs to be inspected for defects may be connected to the input terminal of the third trigger 1113, and the seventh through silicon via 217 that has been determined to be normal may be connected to the output terminal of the third trigger 1113, so as to accurately detect defective through silicon vias among the sixth through silicon via 216 to the eighth through silicon via 218.

[0228] Reference Fig.12 and Fig.13 , the sixth through silicon via 216 and the eighth through silicon via 218 may be connected to the input terminal of the third flip-flop 1113 , and the seventh through silicon via 217 may be connected to the output terminal of the third flip-flop 1113 .

[0229] The test operation may be performed in a state where the address ADDR is set to “0”.

[0230] When the second data output signal DOUT[2] is a fail in a state where the address ADDR is set to “0”, at least one of the sixth through silicon via 216 and the seventh through silicon via 217 may be defective.

[0231] In this case, an additional test operation may be performed when the address ADDR is changed from "0" to "1". When the second data output signal DOUT[2] is a pass in a state where the address ADDR is set to "1", the sixth through silicon via 216 may be determined to be defective. When the second data output signal DOUT[2] is a fail in a state where the address ADDR is set to "1", the seventh through silicon via 217 may be determined to be defective.

[0232] When the second data output signal DOUT[2] is a pass in the case where the address ADDR is set to "0", the sixth through silicon via 216 and the seventh through silicon via 217 may be normal. In this case, an additional test operation may be performed in the state where the address ADDR changes from "0" to "1". When the second data output signal DOUT[2] is a fail in the state where the address ADDR is set to "1", the eighth through silicon via 218 may be determined to be defective.

[0233] As described above, in the memory device 1000F according to example embodiments, the number of upward TSVs may be greater than the number of downward TSVs. In this case, the memory device 1000F may accurately detect defective TSVs.

[0234] Fig.14 is a block diagram illustrating a memory device 1000G according to example embodiments. Fig.14 The memory device 1000G with Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0235] In the foregoing description, memory device 1000 and memory devices 1000A to 1000F have been described as including two dies. However, it should be understood that this is merely an example, and example embodiments are not limited thereto. The memory device according to example embodiments may also be applied to a case where three or more dies are stacked in a vertical direction or arranged in a horizontal direction.

[0236] For example, the memory device 1000G may include first to third dies Die 1 to Die 3 1100G, 1200G, and 1400G. The second die 1200G may include a plurality of through silicon vias 211_1 to 217_1 for electrically connecting the first die 1100G and the second die 1200G, and the third die 1400G may include a plurality of through silicon vias 211_2 to 217_2 for electrically connecting the second die 1200G and the third die 1400G.

[0237] In this case, the memory device 1000G may configure the virtual memory circuit 1300G to detect a defective through silicon via among the plurality of through silicon vias 211_1 to 217_1 and 211_2 to 217_2. For example, the first die 1100G may be implemented to include a plurality of triggers 1111 to 1113, and the third die 1400G may be implemented to include the MBIST 1210, and the virtual memory circuit 1300G may be configured across the first die 1100G, the second die 1200G, and the third die 1400G. Therefore, a defective through silicon via among the plurality of through silicon vias 211_1 to 217_1 and the plurality of through silicon vias 211_2 to 217_2 may be detected without any additional overhead.

[0238] Fig.15 is a block diagram illustrating a memory device 1000H according to example embodiments. Fig.15 The memory device 1000H is Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0239] exist Figures 2 to 14 middle, Figure 1 The interconnection is described as a through silicon via. However, this is merely an example, and example embodiments are not limited thereto.

[0240] For example, Fig.15 As shown in , the memory device 1000H may include a first die 1100H and a second die 1200H, and the bump BP may be disposed between the first die 1100H and the second die 1200H. In this case, Figure 1 The interconnection member may correspond to the bump. Optionally, Figure 1 The interconnects may correspond to bumps and through silicon vias. Figure 1 The interconnection may correspond to “any medium forming a signal transmission path electrically connecting the first die 1100H and the second die 1200H.” As described above, the memory device 1000H may detect a defective interconnection among interconnections formed in various ways without any additional overhead.

[0241] Fig.16 is a block diagram illustrating a memory device 1000I according to example embodiments. Fig.16 The memory device 1000I is Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0242] exist Figures 2 to 15 In the present invention, the through silicon via has been described as being formed in the second die. However, this is only an example, and example embodiments are not limited thereto.

[0243] For example, Fig.16 As shown in FIG, a plurality of through silicon vias 211 to 217 may be formed in the first die 1000I together with the flip-flops 1111 to 1113. In this case, the memory device 1000I may detect a defective through silicon via among the plurality of through silicon vias 211 to 217 without any additional overhead.

[0244] Fig.17 is a block diagram illustrating a memory device 1000J according to example embodiments. Fig.17 The memory device 1000J and Figure 1 The memory device 1000 and Figure 2 Therefore, the same or similar components will be denoted by the same or similar reference numerals, and redundant descriptions will be omitted.

[0245] exist Figures 2 to 16 In the embodiment of the present invention, the first die and the second die have been described as being stacked in a vertical direction. However, this is only an example, and example embodiments are not limited thereto.

[0246] For example, Fig.17 As shown in , the memory device 1000J may include a first die 1100J, a second die 1200J, and an interposer 1400J, and the first die 1100J and the second die 1200J may be disposed on the interposer 1400J. For example, the first die 1100 may be implemented to include a plurality of flip-flops (F / F). In this case, Figure 1 The interconnects 211 to 21n may correspond to metal wires or the like disposed inside the interposer 1400J. Alternatively, for example, Figure 1 The interconnects may be micro bumps disposed between the first die 1100J and the interposer 1400J, or micro bumps disposed between the second die 1200J and the interposer 1400J.

[0247] As described above, the first die 1100J and the second die 1200J may be disposed in a horizontal direction, and the memory device 1000J may detect a defective signal transmission path among signal transmission paths between the first die 1100J and the second die 1200J.

[0248] As set forth above, a memory device according to example embodiments may effectively detect a defective interconnection among interconnections forming a signal transmission path between different dies.

[0249] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: First bare film; a second die electrically connected to the first die; a plurality of interconnects forming a signal transmission path between the first die and the second die; a plurality of flip-flops disposed in the first die, the plurality of flip-flops being electrically connected to the plurality of interconnects; as well as a test circuit disposed in the second die and electrically connected to the plurality of interconnects, and The test circuit is configured to perform a test operation on the plurality of interconnections using the plurality of triggers.

2. The memory device of claim 1, wherein: The plurality of interconnects include first to third interconnects, wherein the plurality of triggers include a first trigger electrically connected to the first interconnect to the third interconnect, The test circuit is further configured to: provide a clock signal to the first flip-flop through a first interconnect, provide a data input signal to the first flip-flop through a second interconnect, and receive a data output signal from the first flip-flop through a third interconnect.

3. The memory device of claim 2, wherein: The test circuit is further configured to determine whether at least one of the second interconnect and the third interconnect is defective based on a comparison result of the data input signal and the data output signal.

4. The memory device of claim 2, wherein: The test circuit is further configured to determine that at least one of the second interconnection and the third interconnection is defective based on a value of the data input signal and a value of the data output signal being different from each other.

5. The memory device of claim 1, wherein: The plurality of interconnects include first to fifth interconnects, The plurality of triggers include a first trigger and a second trigger, the first trigger and the second trigger are electrically connected to the first interconnection to the fifth interconnection, wherein the first trigger and the second trigger are configured to receive a clock signal through a first interconnection member, wherein the first trigger has an input terminal selectively connected to the second interconnect or the fourth interconnect and an output terminal connected to the third interconnect, and The second trigger has an input terminal selectively connected to the second interconnection or the fourth interconnection and an output terminal connected to the fifth interconnection.

6. The memory device of claim 5, wherein: The test circuit is further configured to control the input terminal of the first trigger to be connected to the second interconnection during the first test operation, and to control the input terminal of the second trigger to be connected to the fourth interconnection.

7. The memory device according to claim 6, wherein: The test circuit is further configured to: control a second test operation to be performed based on at least one of the second interconnect and the third interconnect being determined to be defective by the first test operation, and The test circuit is further configured to: control the input terminal of the first trigger to be connected to the fourth interconnection during the second test operation, and control the input terminal of the second trigger to be connected to the second interconnection.

8. The memory device of claim 5, further comprising: a first decoding multiplexer configured to electrically connect the second interconnect or the fourth interconnect to an input terminal of the first flip-flop; as well as The second decoding multiplexer is configured to electrically connect the second interconnection or the fourth interconnection to the input terminal of the second flip-flop.

9. The memory device of claim 8, wherein: The plurality of interconnects further include sixth to eighth interconnects, Wherein, the plurality of triggers further includes a third trigger, wherein the third flip-flop is configured to receive a clock signal through the first interconnect, and Among them, the input terminal of the third trigger is connected to the sixth interconnection, and the output terminal of the third trigger is commonly connected to the seventh interconnection and the eighth interconnection.

10. The memory device of claim 8, wherein: The plurality of interconnects further include sixth to eighth interconnects, Wherein, the plurality of triggers include a third trigger, wherein the third flip-flop is configured to receive a clock signal through the first interconnect, and Among them, the third trigger has an input terminal selectively connected to the sixth interconnection or the eighth interconnection and an output terminal connected to the seventh interconnection.

11. The memory device of claim 10, further comprising: The third decoding multiplexer is configured to electrically connect the sixth interconnection or the eighth interconnection to the input terminal of the third flip-flop.

12. The memory device of claim 3, further comprising: A first redundant interconnect and a second redundant interconnect form a signal transmission path between the first die and the second die, The test circuit is further configured to: based on determining that at least one of the second interconnect and the third interconnect is defective, perform a repair operation on the at least one of the second interconnect and the third interconnect using the first redundant interconnect and the second redundant interconnect.

13. The memory device of claim 12, wherein: The plurality of interconnects further include fourth to seventh interconnects, The plurality of triggers further include: a second trigger and a third trigger, electrically connected to the fourth interconnection member to the seventh interconnection member, wherein each of the second flip-flop and the third flip-flop is configured to receive a clock signal through the first interconnection, wherein the first trigger has an input terminal selectively connected to the second interconnection or the fourth interconnection and an output terminal selectively connected to the third interconnection or the fifth interconnection, wherein the second trigger has an input terminal selectively connected to the fourth interconnection or the sixth interconnection and an output terminal selectively connected to the fifth interconnection or the seventh interconnection, and The third trigger has an input terminal selectively connected to the sixth interconnect or the first redundant interconnect and an output terminal selectively connected to the seventh interconnect or the second redundant interconnect.

14. The memory device of claim 13, further comprising: a first shift multiplexer configured to electrically connect the second interconnect or the fourth interconnect to an input terminal of the first flip-flop; a second shift multiplexer configured to electrically connect the fourth interconnect or the sixth interconnect to an input terminal of the second flip-flop; a third shift multiplexer configured to electrically connect the sixth interconnect or the first redundant interconnect to an input terminal of the third flip-flop; a fourth shift multiplexer configured to electrically connect an output terminal of the first flip-flop or an output terminal of the second flip-flop to a fifth interconnect; as well as A fifth shift multiplexer is configured to electrically connect an output terminal of the second flip-flop or an output terminal of the third flip-flop to a seventh interconnection.

15. The memory device of claim 14, further comprising: a sixth shift multiplexer configured to receive a 0th data input signal and a first data input signal from the test circuit and transmit the 0th test input signal or the first test input signal to a fourth interconnect; a seventh shift multiplexer configured to receive the first data input signal and the second data input signal from the test circuit and transmit the first test input signal or the second test input signal to the sixth interconnect; an eighth shift multiplexer configured to electrically connect the third interconnection or the fifth interconnection to the test circuit and transmit the 0th data output signal to the test circuit; a ninth shift multiplexer configured to electrically connect the fifth interconnect or the seventh interconnect to the test circuit and transmit the first data output signal to the test circuit; as well as A tenth shift multiplexer is configured to electrically connect the seventh interconnect or the second redundant interconnect to the test circuit and transmit the second data output signal to the test circuit.

16. The memory device of claim 1, wherein: Each of the plurality of interconnects is a through silicon via.

17. The memory device of claim 1, wherein: The plurality of interconnects are disposed on the first die or the second die.

18. The memory device of claim 1, further comprising: An interposer includes a first die, a second die, and the plurality of interconnects.

19. A memory device comprising: First bare film; The second die; a plurality of through silicon vias extending through the second die and forming a signal transmission path to the first die; as well as a plurality of triggers disposed in the first die, the plurality of triggers being electrically connected to the plurality of through silicon vias; a test circuit disposed in the second die and electrically connected to the plurality of through silicon vias, The test circuit is configured to detect whether the plurality of through silicon vias are defective using the plurality of triggers.

20. A memory device comprising: Intermediary; The first die, on the interposer; a second die on the interposer and spaced apart from the first die in a horizontal direction; a plurality of interconnects, in the interposer, the plurality of interconnects forming a signal transmission path between the first die and the second die; a plurality of flip-flops, in the first die, the plurality of flip-flops being electrically connected to the plurality of interconnects; as well as a test circuit, in the second die, the test circuit being electrically connected to the plurality of interconnects, The test circuit is configured to detect whether the plurality of interconnections are defective using the plurality of triggers.

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