A method for detecting silicon dislocation defects on top of SOI wafer

Abstract

The present invention relates to the technical field of semiconductor manufacturing, and relates to a method for detecting silicon dislocation defects on the top of an SOI wafer. The method comprises the following steps: providing an SOI silicon wafer to be tested, measuring the initial thickness H0 of a top silicon layer for use in determining subsequent processing parameters; placing the SOI silicon wafer in an etching solution, and causing a dislocation defect region to preferentially corrode through to produce micropores penetrating a buried oxide layer when the thickness H0 is reduced to a set value during the etching process of the top silicon layer; placing the etched SOI silicon wafer in hydrofluoric acid for treatment to expand the dislocation defect perforation region to a visible range, observing the expanded dislocation perforation region through an optical microscope, and counting the number of dislocation defects within multiple fields of view; calculating the dislocation defect density based on the number of defects and the field of view area of ​​the microscope, and evaluating the sample quality. The method adopts chemical etching combined with optical microscope detection, has low equipment cost, controllable detection consumables cost, significantly reduces detection costs, and is suitable for online quality detection of large quantities of SOI silicon wafers.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, in particular to a method for detecting silicon dislocation defects on the top of an SOI wafer. Background Art

[0002] SOI (Silicon on Insulator) technology is a semiconductor manufacturing technique that introduces a silicon oxide insulating layer between the silicon wafer and the substrate. Compared to traditional bulk silicon processes, SOI wafers offer advantages such as reduced parasitic capacitance, low leakage, low power consumption, high-temperature resistance, and radiation resistance. They are widely used in high-performance integrated circuits, RF chips, and power devices. The core advantage of SOI wafers lies in their ability to effectively suppress short-channel effects, improve device performance, and reduce power consumption, making them a crucial foundational material for advanced microelectronics manufacturing processes.

[0003] However, during the SOI wafer manufacturing process, the top silicon layer is prone to dislocation defects due to process steps such as material growth, oxidation, and annealing. Dislocation defects are linear defects caused by lattice misalignment. They can cause local stress concentration, leading to uneven electrical properties and affecting device reliability, lifespan, and performance. For example, during SOI wafer manufacturing, dislocation defects can lead to increased leakage current, decreased breakdown voltage, and reduced device mobility. Therefore, accurately detecting and controlling the dislocation defect density in the top silicon layer of SOI wafers has become a key step in improving product quality and optimizing the manufacturing process.

[0004] Currently, the detection of silicon dislocation defects on the top of SOI wafers mainly relies on the following technologies:

[0005] Transmission electron microscopy (TEM): This technique uses a high-energy electron beam to penetrate samples, enabling nanoscale dislocation defect detection and direct observation of crystal structure defects. However, TEM testing is expensive, sample preparation is complex, and the sample detection range is limited, making large-scale screening difficult.

[0006] Cathodoluminescence (CL) characterization technology: This technique uses an electron beam to excite a material to produce fluorescence, analyzing the optical characteristic changes caused by defects. It has high sensitivity, but its detection equipment is expensive, the operation is complex, and it has high requirements for the sample surface condition.

[0007] X-ray topography (XRT) technology uses X-rays to illuminate silicon wafers and analyze crystal defects through diffraction imaging. Although this method can perform non-destructive testing on large samples, its limited spatial resolution makes it difficult to accurately locate tiny defects.

[0008] Raman spectroscopy: This method uses optical lasers to analyze changes in lattice stress, indirectly revealing the presence of dislocation defects. This method is suitable for rapid screening, but it has difficulty distinguishing between different types of crystal defects.

[0009] Laser confocal microscopy: Combining optical microscopy with laser scanning, it enables non-contact surface defect analysis and is suitable for testing large-area samples, but its ability to detect buried defects is relatively weak.

[0010] While these detection methods can, to a certain extent, analyze defects in SOI wafers, the high price of the equipment and the long detection cycles limit their application in large-scale production. Existing methods typically require single-point or localized detection, making it difficult to quickly assess the defect density of the entire silicon wafer. They primarily rely on surface detection, making it difficult to identify deep defects. Conventional methods often struggle to accurately detect areas with deeper dislocation defects, impacting the reliability of the final assessment. Summary of the Invention

[0011] To this end, the present invention aims to provide a method for detecting silicon dislocation defects on the top of SOI wafers. This method utilizes chemical etching technology, controls process parameters such as the type, concentration, and temperature of the etching solution, and combines real-time thickness monitoring and defect expansion processing to achieve efficient and accurate detection of silicon dislocation defects on the top of SOI wafers. This method effectively distinguishes the etching rates of dislocation defect regions from those of normal lattice regions, prioritizing etching through defective regions. This method then allows for observation and statistical analysis using an optical microscope, providing a low-cost, highly efficient solution for detecting dislocation defect density. This solution addresses the high detection cost, low efficiency, and inability to perform large-scale statistical analysis in existing technologies.

[0012] To achieve the above object, the present invention provides the following technical solutions:

[0013] A method for detecting silicon dislocation defects on the top of an SOI wafer comprises the following steps:

[0014] Step S1: providing an SOI silicon wafer to be tested and measuring the initial thickness H0 of the top silicon layer for determining subsequent processing parameters;

[0015] Step S2: placing the SOI silicon wafer in an etching solution. When the thickness H0 of the top silicon layer is reduced to a set value during the etching process, the difference in etching rates between the dislocation defect region and the defect-free region is utilized to preferentially corrode the dislocation defect region to form micropores penetrating the buried oxide layer.

[0016] Step S3, placing the etched SOI silicon wafer in hydrofluoric acid for treatment to expand the dislocation defect perforation area to a visible range;

[0017] Step S4, observing the expanded dislocation perforation area through an optical microscope, and counting the number of dislocation defects in multiple fields of view;

[0018] Step S5: Calculate the dislocation defect density based on the number of defects and the microscope field area, and evaluate the sample quality.

[0019] The present invention is further configured as follows: Step 2 specifically includes the following steps:

[0020] S21, the parameters include the type of etching solution, concentration C and temperature T, and the etching solution type is selected from alkaline etching solution or oxidizing etching solution according to the material characteristics of the top silicon layer;

[0021] S22. Place the SOI silicon wafer in an etching solution and use a thickness monitor to measure the thickness H(t) of the top silicon layer in real time. The thickness is etched over time t according to the following mathematical model:

[0022] Where H0 is the initial thickness of the top silicon layer; is the corrosion rate of the defect area, defined as: ; Where k is the reaction rate constant of the corrosive solution; is the corrosion activation energy; R is the gas constant, and T is the temperature of the corrosive solution.

[0023] S23, when the thickness of the top silicon layer is reduced to the set value H Target When the corrosion rate difference between the dislocation defect area and the defect-free area is used, the corrosion rate V defect = .V normal

[0024] in is the rate enhancement factor, which ranges from 2 to 4;

[0025] S24. Based on the real-time thickness monitoring data, the concentration and temperature of the etching solution are dynamically adjusted to keep the etching rate within the set target range. The adjustment methods include:

[0026] If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the corrosive solution by 3%-5% and the temperature by 10℃-15℃.

[0027] If the actual corrosion rate V c When the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃;

[0028] S25, when the corrosion reaches the end condition, that is, the top silicon thickness is reduced to the set value H Target Finally, the etching process is terminated and the SOI silicon wafer is cleaned to remove residual corrosion products and ensure that the top silicon layer surface is clean.

[0029] The present invention is further configured as follows: the alkaline corrosive liquid is TMAH, and the concentration is 10%-40%; the oxidizing corrosive liquid is potassium permanganate solution, and the concentration is 10%-40%.

[0030] The present invention is further configured as follows: the concentration of the hydrofluoric acid solution in step S3 is controlled at 10%-20%, and the processing time is 60-120 seconds.

[0031] The present invention is further configured as follows: the microscope field area A is calculated according to the following formula:

[0032] Wherein, the diameter of the field of view d is the estimated number of fields of view of the microscope D 显微镜 And the magnification M is calculated: .

[0033] The present invention is further configured as follows: the defect density The calculation formula is: ,

[0034] in is the average number of defects under multiple microscope fields of view, and A is the area of ​​the microscope field of view.

[0035] The present invention is further configured to: evaluate the quality of the sample according to the calculated dislocation defect density, and the quality grade classification standards are as follows:

[0036] Superior quality: dislocation defect density is less than 100 / mm²;

[0037] Good product: dislocation defect density is 100-300 pieces / mm²;

[0038] Defective product: dislocation defect density is greater than 300 / mm².

[0039] Compared with the shortcomings of the prior art, the beneficial effects of the present invention are:

[0040] The present invention adopts chemical corrosion combined with optical microscope detection, has low equipment cost, controllable cost of detection consumables, greatly reduces detection costs, and is suitable for online quality detection of large quantities of SOI silicon wafers.

[0041] The difference in corrosion rate between defective and non-defective areas is utilized to ensure that defective areas are corroded first. Combined with hydrofluoric acid expansion treatment, the defect locations are fully exposed to avoid missed detection and ensure the accuracy and consistency of defect density assessment. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a process flow chart of the present invention;

[0043] Figure 2 Schematic diagram of silicon dislocation defect on the top of SOI wafer;

[0044] Figure 3 Schematic diagram after top silicon etching;

[0045] Figure 4This is a schematic diagram after hydrofluoric acid immersion;

[0046] Figure 5 These are images taken with an optical microscope at 50x and 500x magnifications. DETAILED DESCRIPTION

[0047] Reference Figure 1-Figure 5 The present invention further describes a method for detecting dislocation defects in top silicon of an SOI wafer. The SOI wafer comprises a top silicon layer 1, a buried oxide layer 2, and a substrate silicon layer 3. Generally, the thickness of the top silicon layer 1 can range from tens of nanometers to several microns, depending on device requirements. The detection method includes the following steps:

[0048] Step 1: Provide the SOI silicon wafer to be tested. Use high-precision testing instruments such as ellipsometer, reflectometer or X-ray reflectometer to measure the thickness of the top silicon layer. Measure the initial thickness H0 of the top silicon layer and use it as the corrosion target H0. Target And the basis for corrosion rate control. After recording H0, we can proceed to the next stage of corrosion process design.

[0049] Step 2: By removing a certain thickness of the top silicon layer in the etching solution, the dislocation defect area is preferentially corroded through the buried oxide layer to form micropores, which facilitates the subsequent visualization and statistics of defects.

[0050] Etching solution type and parameter setting: If the top silicon layer material is conventional (100) silicon or (111) silicon, alkaline etching solution TMAH (tetramethylammonium hydroxide) can be used with a concentration range of 10%–40%. If higher selectivity or stronger oxidizing ability is required, oxidizing etching solution potassium permanganate solution can also be used with a concentration range of 10%–40%.

[0051] In the actual process, the specific etching solution needs to be selected based on comprehensive considerations such as equipment conditions, requirements for the surface roughness of the top silicon layer, etching uniformity, and environmental factors.

[0052] Corrosive solution concentration C: Initially set in the range of 10%–40%. The specific value can be determined based on experience or small-scale tests.

[0053] Etching solution temperature T: Generally controlled within the range of 60–90°C. The higher the temperature, the faster the corrosion rate; the lower the temperature, the slower the corrosion rate, but the surface smoothness may be better.

[0054] For defect-free areas, the corrosion rate It can be expressed as follows:

[0055]

[0056] Where H0 is the initial thickness of the top silicon layer; k is the reaction rate constant of the etching solution; is the corrosion activation energy; R is the gas constant, and T is the temperature of the corrosive solution.

[0057] Place the SOI silicon wafer in an etching solution of set temperature and concentration to begin etching. Through online thickness monitoring (e.g., using laser interferometry, ellipsometry online monitoring, etc.), obtain a curve of the current top silicon layer thickness H(t) versus time.

[0058] The thickness variation of the defect-free area can be approximately expressed as:

[0059] In actual operation, the corrosion rate should be closely monitored to ensure that the corrosion proceeds stably within the target range.

[0060] Determine the thickness of the top silicon layer that needs to be removed based on process requirements or preliminary experiments, and obtain the target thickness H Target , when H(t) is detected to be reduced to H Target When the corrosion rate reaches 0.05, it can be considered that the predetermined corrosion endpoint has been reached.

[0061] Utilizing dislocation defect areas to accelerate corrosion: When dislocations or other crystal defects exist in the top silicon, lattice stress concentration or lattice distortion will make the area more sensitive to the corrosive solution, and the corrosion rate will be greater than that of the defect-free area.

[0062] Assume that the corrosion rate of the dislocation defect area is V defect , then V defect = .V normal ,in is the rate enhancement factor, which ranges from 2 to 4.

[0063] When the remaining thickness of the top silicon layer gradually becomes thinner, the dislocations will be preferentially "opened" due to the higher corrosion rate, forming micropores that penetrate the buried oxide layer; this provides conditions for the subsequent hydrofluoric acid solution to further etch / expand the buried oxide layer and micropores.

[0064] Dynamically adjust the concentration and temperature of the etching solution: In order to achieve the desired corrosion depth within a reasonable time while taking into account the quality of the corrosion surface, a target corrosion rate range needs to be determined in advance. , real-time monitoring rate V c If it exceeds this range, the concentration and temperature of the corrosive liquid must be adjusted in time.

[0065] If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the corrosive solution by 3%-5% and the temperature by 10℃-15℃.

[0066] If the actual corrosion rate V cWhen the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃;

[0067] When the measured value of the top silicon layer thickness H(t) = H Target When the corrosion rate remains stable, it is considered that the corrosion endpoint has been reached; at this time, microporous structures have been formed at most dislocation defects, and subsequent pore expansion treatment can be carried out using HF (hydrofluoric acid) solution.

[0068] Remove the SOI wafer from the etching solution and clean it thoroughly (using ultrapure water combined with ultrasonic or rotary washing);

[0069] The purpose is to remove corrosion products and residual corrosion liquid to avoid their impact on subsequent HF hole expansion and microscopic observation.

[0070] Step 3: Place the etched SOI wafer in hydrofluoric acid. The concentration of the hydrofluoric acid solution should be controlled between 10% and 20%, and the treatment time should be 60-120 seconds. Adjust the treatment time appropriately based on the size of the micropores and the required clarity. Excessive treatment time may cause the micropores to expand excessively, making counting more difficult.

[0071] HF can selectively etch silicon dioxide (buried oxide layer) and the oxide layer on the silicon surface, further expanding the micropores horizontally or vertically;

[0072] This creates a clear "through hole" in the dislocation region, making it easier to identify with the naked eye or under a microscope. After hole enlargement, rinse thoroughly with ultrapure water again. After rinsing, dry it with nitrogen or allow it to air dry in a clean environment to ensure that there are no water stains or ion residues on the surface, ensuring quality for microscopic observation.

[0073] Step 4. Select a metallographic microscope or inverted microscope with a magnification of 50–200 times (select the appropriate magnification based on the pore size and defect density);

[0074] The size of the field of view (field of view diameter d) must be clearly quantified in order to calculate the defect density.

[0075] Select multiple fields of view (e.g., 5–10) on the same SOI wafer to prevent the discreteness of local samples from affecting the overall judgment; record the number of holes (defects) in each field of view, and obtain the defect counts N1, N2, ..., Ni of multiple fields of view, and take the average value. As the number of statistical defects.

[0076] The microscope field area A is calculated according to the following formula: , where the field diameter d is the estimated number of microscope fields D 显微镜 And the magnification M is calculated:

[0077] Step 5: Calculate the dislocation defect density based on the number of defects and the microscope field of view area, and evaluate the sample quality.

[0078] The average number of defects across multiple fields of view and single field of view area A, defect density The calculation formula is: ,

[0079] The sample quality is evaluated based on the calculated dislocation defect density. The quality grade classification standards are as follows:

[0080] Superior quality: dislocation defect density is less than 100 / mm²;

[0081] Good product: dislocation defect density is 100-300 pieces / mm²;

[0082] Defective product: dislocation defect density is greater than 300 / mm².

[0083] For SOI silicon wafers that require high reliability and high performance devices, the lower the dislocation defect density, the better the stability of the manufactured devices;

[0084] If the defect density is too high, device performance and life will be significantly affected, requiring further process optimization or supplier replacement.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for detecting silicon dislocation defects on the top of an SOI wafer, characterized in that: The steps include: Step S1: providing an SOI silicon wafer to be tested and measuring the initial thickness H0 of the top silicon layer for determining subsequent processing parameters; Step S2: placing the SOI silicon wafer in an etching solution. When the thickness H0 of the top silicon layer is reduced to a set value during the etching process, the difference in etching rates between the dislocation defect region and the defect-free region is utilized to preferentially corrode the dislocation defect region to form micropores penetrating the buried oxide layer. Step S3, placing the etched SOI silicon wafer in hydrofluoric acid for treatment to expand the dislocation defect perforation area to a visible range; Step S4, observing the expanded dislocation perforation area through an optical microscope, and counting the number of dislocation defects in multiple fields of view; Step S5: calculating the dislocation defect density based on the number of defects and the microscope field area, and evaluating the sample quality; The step S2 specifically includes the following steps: S21, the parameters include the type of etching solution, concentration C and temperature T, and the etching solution type is selected from alkaline etching solution or oxidizing etching solution according to the material characteristics of the top silicon layer; S22. Place the SOI silicon wafer in an etching solution and use a thickness monitor to measure the thickness H(t) of the top silicon layer in real time. The thickness is etched over time t according to the following mathematical model: ; in, is the initial thickness of the top silicon layer; is the corrosion rate of the defect-free area, defined as: ; Where k is the reaction rate constant of the corrosive solution; is the corrosion activation energy; R is the gas constant, T is the temperature of the corrosive solution; S23, when the thickness of the top silicon layer is reduced to the set value H Target When the corrosion rate difference between the dislocation defect area and the defect-free area is used, the corrosion rate of the dislocation defect area is increased. ; in is the rate enhancement factor, which ranges from 2 to 4; S24. Based on the real-time thickness monitoring data, the concentration and temperature of the etching solution are dynamically adjusted to keep the etching rate within the set target range. The adjustment methods include: If the actual corrosion rate V c When the rate is lower than the target rate, increase the concentration of the etching solution by 3%-5% and the temperature by 10℃-15℃; If the actual corrosion rate V c When the rate is higher than the target rate, reduce the concentration of the corrosive solution by 3%-5% and lower the temperature by 10℃-15℃; S25, when the corrosion reaches the end condition, that is, the top silicon thickness is reduced to the set value H Target Finally, the etching process is terminated and the SOI silicon wafer is cleaned to remove residual corrosion products and ensure that the top silicon layer surface is clean.

2. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 1, wherein: The alkaline corrosive solution is TMAH, and the concentration is 10%-40%; the oxidizing corrosive solution is potassium permanganate solution, and the concentration is 10%-40%.

3. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 2, wherein: In step S3, the concentration of the hydrofluoric acid solution is controlled at 10%-20%, and the treatment time is 60-120 seconds.

4. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 2, wherein: The microscope field area A is calculated according to the following formula: ; Wherein, the diameter of the field of view d is the estimated number of fields of view of the microscope D 显微镜 And the magnification M is calculated: .

5. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 4, wherein: The defect density The calculation formula is: , in is the average number of defects under multiple microscope fields of view, and A is the area of ​​the microscope field of view.

6. The method for detecting silicon dislocation defects on the top of an SOI wafer according to claim 5, wherein: The sample quality is evaluated based on the calculated dislocation defect density. The quality grade classification standards are as follows: Superior quality: dislocation defect density is less than 100 / mm²; Good product: dislocation defect density is 100-300 pieces / mm²; Defective product: dislocation defect density is greater than 300 / mm².

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