Shallow trench isolation structure, preparation method thereof and semiconductor device

Abstract

The invention provides a shallow trench isolation structure, a preparation method thereof and a semiconductor device. According to the preparation method of the shallow trench isolation structure, a nitriding process or a deposition process is adopted to form a composite structure formed by stacking a first nitriding layer, a protective layer and a second nitriding layer on the side wall and the bottom wall of a trench, so that material modification of the protective layer is realized; furthermore, the difference value between the thermal expansion coefficient of the STI filling isolation layer and the thermal expansion coefficient of silicon in the substrate is reduced, so that stress generated by thermal mismatch can be buffered after cooling; in other words, the stress effect problem generated by STI thermal mismatch is effectively relieved, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a shallow trench isolation structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] Shallow trench isolation (STI) has the advantages of good isolation performance and flat surface shape, and is suitable for a variety of chip structures. In particular, in CMOS technology, STI is usually used as lateral isolation between transistors.

[0003] See also Figures 1 to 3 In the conventional STI preparation process, an oxide layer 101 and a nitride layer 102 are generally formed on a substrate 100 in sequence. Then, a patterned photoresist layer is used as a mask to etch the nitride layer 102, and the patterned nitride layer 102 after etching is used as a hard mask layer to sequentially etch the oxide layer 101 and the substrate 100 to form a trench T. Subsequently, an oxide liner 103 is formed on the exposed surface of the trench T and the nitride layer 102 to serve as a buffer protection layer for subsequent filling of the isolation material 104. Finally, silicon dioxide is filled into the trench T as the isolation material 104, and then chemical mechanical polishing and rapid thermal oxidation are sequentially performed to form a trench T. Figure 3 STI shown.

[0004] However, the entire manufacturing process, from forming the oxide liner 103 to the rapid thermal oxidation process, is a high-temperature process. The thermal expansion coefficient of the silicon dioxide filled in the trench T is different from the thermal expansion coefficient of the silicon in the substrate 100. Figure 4 and Figure 5 As shown, when the temperature decreases, the contraction speed of silicon in the substrate 100 is greater than the contraction speed of silicon dioxide, which will cause STI to generate compressive stress F, thereby squeezing the channel, source S and drain D in the active area AA of the MOS tube, and even affecting the gate structure G, and easily causing the electrical parameters of the MOS tube to change, especially the saturation current (Idsat) and threshold voltage (Vt) of the MOS tube. This effect is called the LOD effect, or the STI stress effect. And as the critical dimensions of semiconductors become smaller and smaller, how to control the mechanical compressive stress of STI on the active area of ​​the device has become one of the main challenges in the preparation of semiconductor devices. Therefore, a new preparation method is urgently needed to alleviate the STI stress effect. Summary of the invention

[0005] The object of the present invention is to provide a shallow trench isolation structure and a preparation method thereof, and a semiconductor device, so as to solve at least one of the problems of how to alleviate the STI stress effect and how to improve the performance of the semiconductor device.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a shallow trench isolation structure, comprising:

[0007] Providing a substrate, wherein a plurality of grooves are formed in the substrate;

[0008] forming a protective layer, wherein the protective layer at least covers the sidewalls and the bottom wall of the groove;

[0009] Performing a nitride oxidation process to form a first nitride layer at the interface between the protective layer and the substrate;

[0010] Performing a nitridation process to form a second nitride layer on the surface of the protective layer;

[0011] An isolation layer is formed, wherein the isolation layer covers a surface of the second nitride layer and fills the trench.

[0012] Optionally, in the method for preparing the shallow trench isolation structure, the process of performing the nitridation process includes:

[0013] At least introducing a reaction gas into the groove, so that the reaction gas penetrates the protective layer and reacts with the surface of the substrate, and forms the first nitride layer at the interface between the protective layer and the substrate;

[0014] Wherein, the reaction gas includes N2O, NO and O2.

[0015] Optionally, in the method for preparing the shallow trench isolation structure, the nitridation process includes a decoupled plasma nitridation process; and the decoupled plasma nitridation process includes:

[0016] performing a plasma nitridation process; and,

[0017] An annealing process is performed to form the second nitride layer on the surface of the protection layer.

[0018] Optionally, in the method for preparing the shallow trench isolation structure, the radio frequency waveform used in the process of performing the plasma nitridation process is a continuous wave.

[0019] Optionally, in the method for preparing the shallow trench isolation structure, the material of the first nitride layer and the second nitride layer both includes SiO x N y , x and y are positive integers, and x≤3, y≤3; and the material of the protective layer includes silicon dioxide.

[0020] Based on the same concept, the present invention also provides a method for preparing a shallow trench isolation structure, comprising:

[0021] Providing a substrate, wherein a plurality of grooves are formed in the substrate;

[0022] forming a first nitride layer, wherein the first nitride layer at least covers the sidewalls and the bottom wall of the trench;

[0023] forming a protective layer, wherein the protective layer covers a surface of the first nitride layer;

[0024] forming a second nitride layer, wherein the second nitride layer covers a surface of the protective layer;

[0025] An isolation layer is formed, wherein the isolation layer covers a surface of the second nitride layer and fills the trench.

[0026] Optionally, in the method for preparing the shallow trench isolation structure, the process of forming the first nitride layer and the second nitride layer includes a chemical vapor deposition process or an ISSG process.

[0027] Optionally, in the method for preparing the shallow trench isolation structure, the material of the first nitride layer and the second nitride layer both includes SiO x N y , x and y are positive integers, and x≤3, y≤3; and the material of the protective layer includes silicon dioxide.

[0028] Based on the same concept, the present invention also provides a shallow trench isolation structure, which is prepared by the preparation method of the shallow trench isolation structure; and the shallow trench isolation structure comprises:

[0029] A substrate having a plurality of grooves formed therein;

[0030] A first nitride layer, wherein the first nitride layer covers the sidewalls and bottom wall of the trench;

[0031] a protective layer, wherein the protective layer covers a surface of the first nitride layer;

[0032] a second nitride layer, wherein the second nitride layer covers a surface of the protective layer;

[0033] An isolation layer covers a surface of the second nitride layer and fills the trench.

[0034] Based on the same concept, the present invention also provides a semiconductor device including the shallow trench isolation structure.

[0035] In summary, the present invention provides a shallow trench isolation structure and a preparation method thereof, and a semiconductor device. Compared with the prior art, the preparation method of the shallow trench isolation structure is to form a composite structure in which a first nitride layer, a protective layer, and a second nitride layer are stacked on the sidewall and bottom wall of the trench using a nitridation process or a deposition process, so as to achieve material modification of the protective layer, thereby reducing the difference between the thermal expansion coefficient of the STI and the thermal expansion coefficient of silicon in the substrate, so that the stress generated by the thermal mismatch can be buffered after cooling; that is, the stress effect problem caused by the STI thermal mismatch is effectively alleviated, and it is beneficial to improve the performance of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0037] Figures 1 to 3 It is a schematic diagram of a semiconductor structure during the STI preparation process in the prior art.

[0038] Figures 4-5 It is a schematic diagram of a MOS tube subjected to STI compressive stress in the prior art.

[0039] Figure 6 The present invention is a flowchart of a method for preparing a shallow trench isolation structure according to an embodiment of the present invention.

[0040] Figure 7 Schematic diagram of a structure in which a groove is formed in a substrate in an embodiment of the present invention.

[0041] Figure 8 It is a schematic diagram of a structure in which a protective layer is formed in an embodiment of the present invention.

[0042] Fig. 9 It is a structural schematic diagram of performing a nitridation process to form a first nitride layer in an embodiment of the present invention.

[0043] Fig.10 In the embodiment of the present invention Fig. 9 Schematic diagram of the enlarged local structure of the middle P region.

[0044] Fig.11 FIG. 4 is an atomic structure diagram of a first nitride layer formed by performing a nitridation process in an embodiment of the present invention.

[0045] Fig.12 It is a structural schematic diagram of performing a nitridation process to form a second nitride layer in an embodiment of the present invention.

[0046] Fig.13 In the embodiment of the present invention Fig.12 Schematic diagram of the enlarged local structure of the middle Q region.

[0047] Fig.14Schematic diagram of the structure of the isolation layer filling the trench in an embodiment of the present invention.

[0048] Fig.15 Schematic diagram of the structure of the shallow trench isolation structure in an embodiment of the present invention.

[0049] Fig.16 It is a flow chart of another method for preparing a shallow trench isolation structure in an embodiment of the present invention.

[0050] Fig.17 It is a schematic diagram of a semiconductor structure after a first nitride layer, a protective layer and a second nitride layer are sequentially formed in an embodiment of the present invention.

[0051] Fig.18 It is a schematic diagram of a semiconductor structure in which an isolation layer is used to fill a trench in an embodiment of the present invention.

[0052] Fig.19 It is a schematic diagram of the structure of a MOS tube in an embodiment of the present invention.

[0053] And, in the attached drawings:

[0054] 100-substrate; 101-oxide layer; 102-nitride layer; 103-oxide liner; 104-isolation material;

[0055] 200 - substrate; 201 - gate oxide layer; 202 - hard mask layer; 203 - protective layer; 204 - first nitride layer; 205 - second nitride layer; 206 - isolation layer;

[0056] T-trench; AA-active area; S-source; D-drain; G-gate structure; F-compressive stress; M-interface. DETAILED DESCRIPTION

[0057] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third" and the like in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship between the various components, elements, steps, etc. And, the X-axis direction, Y-axis direction and Z-axis direction referred to in the specification and drawings of this application are three directions perpendicular to each other in three-dimensional space.

[0058] See also Figure 6This embodiment provides a method for preparing a shallow trench isolation structure, comprising:

[0059] Step 1 S10: providing a substrate, wherein a plurality of grooves are formed in the substrate;

[0060] Step 2 S11: forming a protective layer, wherein the protective layer at least covers the sidewalls and the bottom wall of the trench;

[0061] Step three S12: performing a nitridation process to form a first nitride layer at the interface between the protective layer and the substrate;

[0062] Step 4 S13: performing a nitridation process to form a second nitride layer on the surface of the protective layer;

[0063] Step five S14: forming an isolation layer, wherein the isolation layer covers the surface of the second nitride layer and fills the trench.

[0064] Based on this, the preparation method of the shallow trench isolation structure provided in this embodiment is to use a nitridation process or a deposition process to form a composite structure in which a first nitride layer, a protective layer and a second nitride layer are stacked on the side wall and bottom wall of the trench, so as to reduce the difference between the thermal expansion coefficient of the shallow trench isolation structure and the thermal expansion coefficient of silicon in the substrate, so that the stress caused by the thermal mismatch can be buffered after cooling; that is, the stress effect problem caused by the STI thermal mismatch is effectively alleviated, and it is beneficial to improve the performance of semiconductor devices.

[0065] The following is combined with Figures 6 to 19 The preparation method of the shallow trench isolation structure provided in this embodiment is specifically described.

[0066] Step 1 S10: Please refer to Figure 7 , a substrate 200 is provided, and a plurality of trenches T are formed in the substrate 200 .

[0067] The substrate 200 provides an operating platform for subsequent preparation processes, and can be any substrate for carrying semiconductor integrated circuit components known to those skilled in the art, and can be a bare chip, a wafer processed by an epitaxial growth process, or a circuit layer with devices formed thereon. Optionally, the substrate 200 includes a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate.

[0068] It should be noted that the preparation method of the shallow trench isolation structure provided in this embodiment can be applied to the preparation of a variety of semiconductor devices, and this embodiment does not specifically limit this. Exemplarily, the preparation method of the shallow trench isolation structure is applicable to the preparation of MOS tubes. Therefore, before forming the trench T, the surface of the substrate 200 is first planarized to improve the overall quality and performance of the device. Then, the substrate 200 is cleaned and dried. Secondly, a gate oxide layer 201 is formed on the surface of the substrate 200. The material of the gate oxide layer 201 includes but is not limited to silicon dioxide, which is used to protect the substrate 200 and serve as an electrical isolation structure between the substrate 200 and the gate structure G formed subsequently, so as to protect and control the current. Subsequently, a hard mask layer 202 is formed on the surface of the gate oxide layer 201 to serve as a mask structure for subsequent etching. Finally, a patterned photoresist layer is formed on the hard mask layer 202, and the hard mask layer 202 is etched using the patterned photoresist layer as an etching barrier to transfer the pattern on the patterned photoresist layer to the hard mask layer 202, thereby forming a patterned hard mask layer 202. Optionally, the material of the hard mask layer 202 includes, but is not limited to, silicon nitride.

[0069] After forming the patterned hard mask layer 202, the gate oxide layer 201 and the substrate 200 are sequentially etched using the patterned hard mask layer 202 as an etching mask to form a plurality of trenches T. Figure 7 As shown, the trench T sequentially penetrates the hard mask layer 202 and the gate oxide layer 201 , and extends into the substrate 200 .

[0070] Step 2 S11: Please refer to Figure 8 , forming a protection layer 203, wherein the protection layer 203 at least covers the sidewalls and the bottom wall of the trench T.

[0071] Optionally, an in situ steam generation (ISSG) process is used to form a thin protective layer 203. The protective layer 203 covers the sidewalls and bottom wall of the trench T, and covers the top surface of the hard mask layer 202. The material of the protective layer 203 includes but is not limited to silicon dioxide. Since silicon dioxide is relatively hard, the protective layer 203 can not only form the boundary of the trench T, but also play a role of buffer protection when the trench T is subsequently filled.

[0072] Step 3 S12: Please refer to Figure 8 to Figure 11 , a nitride oxidation process is performed to form a first nitride layer 204 at an interface M between the protective layer 203 and the substrate 200 .

[0073] See also Fig. 9In the process of performing the nitridation process, the semiconductor structure is first placed in a reaction chamber, and a reaction gas is injected toward the protective layer 203, and in particular, the reaction gas needs to be introduced into the groove T, and the reaction gas includes but is not limited to N2O, NO and O2. The reaction gas molecules have strong molecular activity in a high temperature reaction environment, and are easy to penetrate the molecular gap of the protective layer 203 to contact and react with the substrate 200. Fig.10 and Fig.11 As shown, the nitriding gases such as N2O and NO in the reaction gas react with the silicon material in the substrate 200 to undergo a nitriding reaction; and the O2 in the reaction gas promotes the nitriding reaction during the nitriding reaction, and finally forms SiO at the interface M. x N y , as the first nitride layer 204. Wherein, x and y are positive integers, and x≤3, y≤3; for example, the material of the first nitride layer 204 is SiON.

[0074] It can be understood that since the thermal expansion coefficient of the substrate 200 is: αSi=2.6×10 -6 K -1 The thermal expansion coefficient of the protective layer 203 is αSiO2=0.5×10 -6 K -1 Therefore, after high-temperature preparation, the decrease in temperature will make Si shrink faster than SiO2, which will cause STI to produce compressive stress, thereby affecting device performance. The preparation method provided in this embodiment uses the nitridation process to modify the material at the interface M between the protective layer 203 and the substrate 200 into a first nitride layer 204, the material of which is, for example, SiON. The expansion coefficient of SiON is αSiON=2~3.1×10 -6 K -1 It can be seen that the composite material formed by combining the SiON material with the silicon dioxide material of the protection layer 203 can increase the thermal expansion coefficient of the dielectric material in the trench T, thereby reducing the difference in thermal expansion coefficient between the dielectric material in the trench T and the substrate 200, thereby alleviating the stress effect problem caused by STI thermal mismatch and facilitating the optimization of device performance.

[0075] Step 4 S13: Please refer to Fig.12 and Fig.13 , a nitridation process is performed to form a second nitride layer 205 on the surface of the protective layer 203.

[0076] In order to further reduce the difference in thermal expansion coefficient between the dielectric material in the trench T and the substrate 200, the preparation method provided in this embodiment further forms a second nitride layer 205. Optionally, a decoupled plasma nitridation process (DPN) is used as the nitridation process to modify the exposed surface of the protective layer 203 into SiO x N y , wherein x and y are positive integers, and x≤3, y≤3; for example, the material of the second nitride layer 205 is SiON.

[0077] Specifically, in the process of performing the decoupled plasma nitridation treatment process, a plasma nitridation process is first performed. That is, under high temperature and high pressure, the nitrogen molecules are ionized and excited into a plasma state, and are passed into the groove T so that the free nitrogen atoms are attached to the surface of the protective layer 203. However, the free nitrogen atoms in this process are not very stable and are easy to volatilize. Therefore, after performing the plasma nitridation process, a post-nitridation annealing process (Post Nitridation Anneal, PNA) is required to perform curing in time so that the nitrogen atoms are bonded to the silicon dioxide on the surface of the protective layer 203, thereby forming a stable SiO x N y That is, the second nitride layer 205. Among them, the ISSG process, the DPN process and the PNA process can be implemented on the same machine, and the operation is relatively convenient.

[0078] Based on this, Fig.13 As shown in the partial enlarged view, the sidewall and bottom wall of the trench T can form a sandwich structure composed of the first nitride layer 204, the protective layer 203 and the second nitride layer 205; that is, SiO x N y , SiO2 and SiO x N y Composite material. x N y The thermal expansion coefficient of is higher than that of SiO2, so the thermal expansion coefficient of the composite material is close to that of the substrate 200, which can effectively alleviate the compressive stress generated by STI after cooling, thereby avoiding affecting the electrical parameters of the device such as the saturation current and threshold voltage, and optimizing the device performance.

[0079] Optionally, the RF waveform used in the plasma nitridation process is a continuous wave. Compared with the existing 50% duty cycle pulse wave RF waveform, the continuous wave RF waveform can make the surface of the protective layer 203 more nitrogen-doped, and the formed second nitride layer 205 has a better depth and thickness.

[0080] Step 5 S14: Please refer to Fig.12 , Fig.14 and Fig.15 , forming an isolation layer 206 , wherein the isolation layer 206 covers the surface of the second nitride layer 205 and fills the trench T.

[0081] Optionally, a high-density plasma (HDP) deposition process is used to fill the trench T. The material of the isolation layer 206 includes but is not limited to silicon dioxide. After the isolation layer 206 is formed, Fig.15 As shown, a chemical mechanical polishing process is used to polish and remove the portion of the isolation layer 206 covering the top surface of the protection layer 203, and only the portion of the isolation layer 206 filling the trench T is retained. Thus, the preparation of the shallow trench isolation structure is completed.

[0082] Based on the same concept, this embodiment also provides another method for preparing a shallow trench isolation structure. Figure 7 , Figure 16 to Figure 18 , the preparation method of the shallow trench isolation structure comprises:

[0083] Step 1 S20: Please refer to Figure 7 , providing a substrate 200, wherein a plurality of trenches T are formed in the substrate 200;

[0084] Step 2 S21: Please refer to Fig.17 , forming a first nitride layer 204, wherein the first nitride layer 204 at least covers the sidewalls and the bottom wall of the trench T;

[0085] Step 3 S22: Please refer to Fig.17 , forming a protective layer 203, wherein the protective layer 203 covers the surface of the first nitride layer 204;

[0086] Step 4 S23: Please refer to Fig.17 , forming a second nitride layer 205, wherein the second nitride layer 205 covers the surface of the protective layer 203;

[0087] Step 5 S24: Please refer to Fig.18 , forming an isolation layer 206 , wherein the isolation layer 206 covers the surface of the second nitride layer 205 and fills the trench T.

[0088] It should be noted that the specific implementation process of step 1 S20 and step 5 S24 can refer to step 1 S10 and step 5 S14; and the specific implementation process of forming the protective layer 203 in step 3 S22 can also refer to the record of step 2 S11, which will not be repeated in this embodiment. However, the order and method of forming the first nitride layer 204, the protective layer 203 and the second nitride layer 205 in step 2 S21, step 3 S22 and step 4 S23 are different from those in step 2 S11, step 3 S12 and step 4 S13.

[0089] Specifically, the first nitride layer 204 is first formed by a deposition process, and the first nitride layer 204 covers the sidewalls and bottom wall of the trench T, and covers the exposed surfaces of the gate oxide layer 201 and the hard mask layer 202. Then, the protective layer 203 is formed. The protective layer 203 covers the surface of the first nitride layer 204. Finally, the second nitride layer 205 is formed by a deposition process. The second nitride layer 205 covers the exposed surface of the protective layer 203. In other words, the first nitride layer 204, the protective layer 203 and the second nitride layer 205 are formed in the trench T in sequence. Optionally, the process for forming the first nitride layer 204 and the second nitride layer 205 includes but is not limited to a chemical vapor deposition process or an ISSG process. And, for the unexplained part of the preparation process of step 1 S20 to step 5 S24, reference can be made to step 1 S10 to step 5 S14, and this embodiment will not be repeated here.

[0090] Based on the same concept, this embodiment also provides a shallow trench isolation structure. Fig.19 The shallow trench isolation structure is prepared by any of the above-mentioned shallow trench isolation structure preparation methods. Specifically, the shallow trench isolation structure includes: a substrate 200, a first nitride layer 204, a protective layer 203, a second nitride layer 205 and an isolation layer 206; wherein a plurality of trenches T are formed in the substrate 200; the first nitride layer 204 covers the sidewalls and bottom walls of the trenches T; the protective layer 203 covers the surface of the first nitride layer 204; the second nitride layer 205 covers the surface of the protective layer 203; and the isolation layer 206 covers the surface of the second nitride layer 205 and fills the trenches T.

[0091] Based on the same concept, this embodiment also provides a semiconductor device. Fig.19, the semiconductor device includes the above-mentioned shallow trench isolation structure. Exemplarily, the semiconductor device is a MOS tube, and various well regions, lightly doped drain structures, source S and drain D are formed in the active area AA surrounded by the shallow trench isolation structure; and a gate oxide layer 201 and a gate structure G are also formed on the surface of the substrate 200 corresponding to the active area AA.

[0092] In summary, the present embodiment provides a shallow trench isolation structure and a preparation method thereof, and a semiconductor device. The preparation method is to form a composite structure in which a first nitride layer 204, a protective layer 203, and a second nitride layer 205 are stacked on the sidewall and bottom wall of the trench T by a nitridation process or a deposition process, so as to modify the material of the protective layer 203, thereby reducing the difference between the thermal expansion coefficient of the STI and the thermal expansion coefficient of silicon in the substrate 200, so that the stress generated by the thermal mismatch can be buffered after the temperature is lowered; that is, the stress effect problem generated by the STI thermal mismatch is effectively alleviated, and it is beneficial to improve the performance of the semiconductor device.

[0093] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: include: Providing a substrate, wherein a plurality of grooves are formed in the substrate; forming a protective layer, wherein the protective layer at least covers the sidewalls and the bottom wall of the groove; Performing a nitride oxidation process to form a first nitride layer at the interface between the protective layer and the substrate; Performing a nitridation process to form a second nitride layer on the surface of the protective layer; An isolation layer is formed, wherein the isolation layer covers a surface of the second nitride layer and fills the trench.

2. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The process of performing the nitrogen oxidation process includes: At least introducing a reaction gas into the groove, so that the reaction gas penetrates the protective layer and reacts with the surface of the substrate, and forms the first nitride layer at the interface between the protective layer and the substrate; Wherein, the reaction gas includes N2O, NO and O2.

3. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The nitridation process includes a decoupled plasma nitridation process; and the decoupled plasma nitridation process includes: performing a plasma nitridation process; and, An annealing process is performed to form the second nitride layer on the surface of the protection layer.

4. The method for preparing a shallow trench isolation structure according to claim 3, characterized in that: The radio frequency waveform used in the process of performing the plasma nitridation process is a continuous wave.

5. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The materials of the first nitride layer and the second nitride layer both include SiO x N y , x and y are positive integers, and x≤3, y≤3; and the material of the protective layer includes silicon dioxide.

6. A method for preparing a shallow trench isolation structure, characterized in that: include: Providing a substrate, wherein a plurality of grooves are formed in the substrate; forming a first nitride layer, wherein the first nitride layer at least covers the sidewalls and the bottom wall of the trench; forming a protective layer, wherein the protective layer covers a surface of the first nitride layer; forming a second nitride layer, wherein the second nitride layer covers a surface of the protective layer; An isolation layer is formed, wherein the isolation layer covers a surface of the second nitride layer and fills the trench.

7. The method for preparing a shallow trench isolation structure according to claim 6, characterized in that: The process of forming the first nitride layer and the second nitride layer includes a chemical vapor deposition process or an ISSG process.

8. The method for preparing a shallow trench isolation structure according to claim 6, characterized in that: The materials of the first nitride layer and the second nitride layer both include SiO x N y , x and y are positive integers, and x≤3, y≤3; and the material of the protective layer includes silicon dioxide.

9. A shallow trench isolation structure, characterized in that: The shallow trench isolation structure is prepared by the method for preparing the shallow trench isolation structure according to any one of claims 1 to 5, or is prepared by the method for preparing the shallow trench isolation structure according to any one of claims 6 to 8; and the shallow trench isolation structure comprises: A substrate having a plurality of grooves formed therein; A first nitride layer, wherein the first nitride layer covers the sidewalls and bottom wall of the trench; a protective layer, wherein the protective layer covers a surface of the first nitride layer; a second nitride layer, wherein the second nitride layer covers a surface of the protective layer; An isolation layer covers a surface of the second nitride layer and fills the trench.

10. A semiconductor device, characterized in that: It includes the shallow trench isolation structure as claimed in claim 9.

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