Semiconductor structure and manufacturing method thereof
By oxidizing and removing the patterned mask layer during the semiconductor manufacturing process, the problem that common cleaning liquid cannot effectively remove the mask layer is solved, and the effect of reducing production costs and improving the productivity and reliability of semiconductor structures is achieved.
Patent Information
- Application Number
- CN202510159276.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-05-13
AI Technical Summary
In the back-end process of semiconductor manufacturing, the commonly used cleaning solution does not contain H2O2 water, and cannot effectively remove the mask layer, resulting in uneven growth of subsequent deposition barrier layers and seed layers, drape phenomena and metal voids, which lead to an increase in defects and an inability to improve productivity.
After etching the interlayer dielectric material layer in the patterned mask layer, the oxidation treatment is performed to convert it into an oxide mask layer, and then the oxide mask layer is removed using common cleaning liquid, the need for using expensive equipment is avoided.
This method not only reduces production costs, but also allows the mask layer to be removed more thoroughly and evenly, reduces the occurrence of overhang phenomenon and metal voids, and improves the productivity and reliability of semiconductor structures.
Smart Images
Figure CN119993911A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductor manufacturing process, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] In the back-end of line (BEOL) process of semiconductor manufacturing, wet stripping after metal etching is one of the key steps. Common cleaning solutions do not contain H 2 O 2 Water (aqueous solution of hydrogen peroxide) cannot effectively remove the mask layer, resulting in uneven growth of the groove opening and sidewalls during the subsequent deposition of the barrier layer and seed layer, overhangs, premature sealing, and the formation of a mushroom-shaped structure, which deteriorates the metal filling capacity and causes metal voids, thereby increasing defects and failing to effectively improve the semiconductor production yield.
[0003] Currently, the only solution in the industry is to use the H 2 O 2 However, this solution has obvious limitations: on the one hand, the cleaning fluid cost of the EKC580 machine is relatively high; on the other hand, users need to purchase an additional EKC580 machine, which increases the equipment investment cost.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the invention
[0005] Based on this, the embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can significantly reduce production costs while improving the production yield and reliability of the semiconductor structure.
[0006] According to some embodiments, the present application provides, on one hand, a method for manufacturing a semiconductor structure, comprising:
[0007] Providing a substrate, and forming an interlayer dielectric material layer on a surface of the substrate;
[0008] forming a patterned mask layer on a side of the interlayer dielectric material layer away from the substrate;
[0009] After etching the interlayer dielectric material layer using the patterned mask layer as a mask, the patterned mask layer is oxidized to transform the patterned mask layer into an oxide mask layer;
[0010] The oxide mask layer is removed.
[0011] In some embodiments, the oxidation treatment of the patterned mask layer includes:
[0012] A heat treatment is performed in a gas environment containing oxygen or ozone to transform the patterned mask layer into the oxide mask layer.
[0013] In some embodiments, when the patterned mask layer is heat-treated in a gas environment containing ozone, the reaction temperature ranges from 100° C. to 200° C.
[0014] In some embodiments, when the patterned mask layer is heat-treated in a gas environment containing ozone, the reaction temperature is 100° C.
[0015] In some embodiments, forming a patterned mask layer on a side of the interlayer dielectric material layer away from the substrate includes:
[0016] The patterned mask layer is formed by depositing a nitride material on a side of the interlayer dielectric material layer away from the substrate.
[0017] In some embodiments, the nitride material includes titanium nitride.
[0018] In some embodiments, removing the oxide mask layer includes:
[0019] The oxide mask layer is removed by using a cleaning solution containing hydrofluoric acid.
[0020] In some embodiments, forming an interlayer dielectric material layer on the surface of the substrate includes:
[0021] A low dielectric constant material layer and an ultra-low dielectric constant material layer are sequentially formed on the surface of the substrate.
[0022] In some embodiments, before forming the patterned mask layer on a side of the interlayer dielectric material layer away from the substrate, the manufacturing method further comprises: forming a protective material layer on a side of the interlayer dielectric material layer away from the substrate;
[0023] Wherein, the patterned mask layer is formed on a side of the protective material layer away from the interlayer dielectric material layer.
[0024] According to some embodiments, the present application further provides a semiconductor structure on the other hand, wherein the semiconductor structure is manufactured using the semiconductor structure manufacturing method provided in the aforementioned embodiment.
[0025] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.
[0026] The embodiments of the present application may or at least have the following advantages:
[0027] The present application adds a step of oxidizing the patterned mask layer after etching the interlayer dielectric material layer according to the patterned mask layer to convert it into an oxide mask layer, and then removes the oxide mask layer. Not only is the process simple and easy to implement, but the oxide mask layer obtained after oxidation can be removed using a common cleaning solution, without the need for users to specifically purchase expensive equipment (such as an EKC580 machine), thereby significantly reducing production costs.
[0028] The manufacturing method provided by the present application can remove the patterned mask layer more thoroughly and evenly without increasing the equipment investment cost, which helps to obtain a barrier layer and / or seed layer with better morphology in the subsequent process, etc., reduces the overhang phenomenon and the situation of premature sealing of the top of the opening, thereby avoiding the deterioration of the metal filling capacity and the appearance of metal voids. Therefore, the present application can also improve the production yield and reliability of semiconductor structures.
[0029] Other advantages, objectives and features of the present application will be described in the following description to some extent, and will be apparent to those skilled in the art based on the following examination and study, or can be taught from the practice of the present application to some extent. The objectives and other advantages of the present application can be achieved and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings.
[0031] Figure 1 A schematic diagram of a process for manufacturing a semiconductor structure in some embodiments of the present application;
[0032] Figure 2 A schematic diagram of a cross-sectional structure of a structure obtained after a patterned mask layer is formed in a method for manufacturing a semiconductor structure provided in some embodiments of the present application;
[0033] Figure 3 A schematic diagram of a cross-sectional structure of a structure obtained after an oxide mask layer is formed in a method for manufacturing a semiconductor structure provided in some embodiments of the present application;
[0034] Figure 4 A schematic diagram of the cross-sectional structure of a structure obtained after removing the oxide mask layer in a method for manufacturing a semiconductor structure provided in some embodiments of the present application.
[0035] Description of reference numerals:
[0036] 11. Interlayer dielectric material layer; 111. Low dielectric constant material layer; 112. Ultra-low dielectric constant material layer; 12. Protective material layer; 21. Patterned mask layer; 31. Oxide mask layer; 40. Conductive interconnect structure. DETAILED DESCRIPTION
[0037] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0039] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0040] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present disclosure in a schematic manner. Although the illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout type may also be more complicated.
[0041] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.
[0042] In the back-end of line (BEOL) process of semiconductor manufacturing, wet stripping after metal etching is one of the key steps. Taking 28nm and 40nm BEOL metal etching wet stripping as an example, when using common cleaning liquid for processing, the common cleaning liquid does not contain H2 O 2 Water (aqueous solution of hydrogen peroxide) cannot effectively remove the mask layer, resulting in uneven growth of the groove opening and sidewalls during the subsequent deposition of the barrier layer and seed layer, overhangs, premature sealing, and the formation of a mushroom-shaped structure, which deteriorates the metal filling capacity and causes metal voids, thereby increasing defects and failing to effectively improve the semiconductor production yield.
[0043] Currently, the only solution in the industry is to use the H 2 O 2 However, this solution has obvious limitations: on the one hand, the cleaning fluid cost of the EKC580 machine is relatively high, costing up to $8 per piece; on the other hand, users need to purchase an additional EKC580 machine, which increases the equipment investment cost. It is estimated that the cost of purchasing an EKC580 machine is about 70 million.
[0044] Based on this, the present application hopes to provide a solution that can solve the above technical problems, significantly reduce production costs, and improve the production yield and reliability of semiconductor structures. The details will be described in the subsequent embodiments.
[0045] According to some embodiments, the present application provides a method for manufacturing a semiconductor structure. Figure 1 The method for manufacturing the semiconductor structure may specifically include the following steps S100 to S400.
[0046] S100: providing a substrate, and forming an interlayer dielectric material layer on a surface of the substrate.
[0047] S200: forming a patterned mask layer on a side of the interlayer dielectric material layer away from the substrate.
[0048] S300: after etching the interlayer dielectric material layer using the patterned mask layer as a mask, oxidizing the patterned mask layer to transform the patterned mask layer into an oxide mask layer.
[0049] S400: removing the oxide mask layer.
[0050] The present application adds a step of oxidizing the patterned mask layer after etching the interlayer dielectric material layer according to the patterned mask layer to convert it into an oxide mask layer, and then removes the oxide mask layer. Not only is the process simple and easy to implement, but the oxide mask layer obtained after oxidation can be removed using a common cleaning solution, without the need for users to specifically purchase expensive equipment (such as an EKC580 machine), thereby significantly reducing production costs.
[0051] The manufacturing method provided by the present application can remove the patterned mask layer more thoroughly and evenly without increasing the equipment investment cost, which helps to obtain a barrier layer and / or seed layer with better morphology in the subsequent process, etc., reduces the overhang phenomenon and the situation of premature sealing of the top of the opening, thereby avoiding the deterioration of the metal filling capacity and the appearance of metal voids. Therefore, the present application can also improve the production yield and reliability of semiconductor structures.
[0052] The following combination Figures 2 to 4 The method for manufacturing the semiconductor structure provided in the embodiment of the present application is described in detail.
[0053] In step S100, a substrate is provided, and an interlayer dielectric material layer 11 is formed on the surface of the substrate. Figure 2 shown.
[0054] Please continue reading Figure 2 In some embodiments, the interlayer dielectric material layer 11 formed on the substrate surface may specifically include: a low dielectric constant material layer 111 and an ultra-low dielectric constant material layer 112 formed in sequence from the substrate surface.
[0055] For example, the constituent material of the low dielectric constant material layer 111 may include but is not limited to silicon carbon nitride (SiCN). Forming the low dielectric constant material layer 111 with a relatively low dielectric constant on the substrate surface can effectively reduce the capacitance effect of the semiconductor structure during signal transmission, thereby reducing signal transmission delay, and helping to improve the operating speed and performance of the semiconductor device.
[0056] The ultra-low dielectric constant material refers to an ultra-low dielectric constant material (Ultra-Low-K, referred to as ULK), the dielectric constant of which is lower than that of the low dielectric constant material layer 111. The constituent materials of the ultra-low dielectric constant material layer 112 may include but are not limited to organic silicon materials, such as porous silicon oxide (SiO 2 An ultra-low dielectric constant material layer 112 is also formed on the surface of the low dielectric constant material layer 111 away from the substrate, which further reduces the signal transmission delay of the semiconductor structure and improves the high-frequency performance of the semiconductor device.
[0057] As an example, the thickness range of the low dielectric constant material layer 111 may include For example The thickness range of the ultra-low dielectric constant material layer 112 may include For example etc.
[0058] Please continue reading Figure 2In some embodiments, before executing step S200, a protective material layer 12 can be formed on the side of the interlayer dielectric material layer 11 away from the substrate to prevent the interlayer dielectric material layer 11 from being damaged in subsequent process steps, especially during etching and cleaning, which helps to maintain the integrity and performance of the interlayer dielectric material layer 11.
[0059] As an example, the material constituting the protective material layer 12 may include but is not limited to TEOS (TetraethylOrthosilicate).
[0060] Exemplarily, the thickness range of the protective material layer 12 may include For example etc.
[0061] Please continue reading Figure 2 In step S200 , a patterned mask layer 21 is formed on a side of the interlayer dielectric material layer 11 away from the substrate.
[0062] In some embodiments, a nitride material may be deposited on the side of the interlayer dielectric material layer 11 away from the substrate to form a patterned mask layer 21. The nitride material may include but is not limited to titanium nitride (TiN), silicon nitride (SiN), and the like.
[0063] Nitride materials, such as titanium nitride, have high chemical stability and physical hardness. The patterned mask layer 21 formed by depositing the nitride material can maintain a stable structure during the etching process of the interlayer dielectric material layer 11, and is not easily corroded or deformed, which helps to prevent the interlayer dielectric material layer 11 from being over-etched or damaged, thereby ensuring the etching accuracy and uniformity, and ensuring the manufacturing quality of the semiconductor structure.
[0064] In addition, forming the patterned mask layer 21 by depositing a nitride material can also facilitate the subsequent transformation of the patterned mask layer 21 into an oxide mask layer, thereby ensuring efficient oxidation treatment, which will be described in detail later.
[0065] It should be noted that in the example where the protective material layer 12 is formed on the side of the interlayer dielectric material layer 11 away from the substrate, Figure 2 As shown, the patterned mask layer 21 may be formed on a side of the protection material layer 12 away from the interlayer dielectric material layer 11 .
[0066] Please combine Figure 2 and Figure 3 It is understood that in step S300 , after the interlayer dielectric material layer 11 is etched using the patterned mask layer 21 as a mask, the patterned mask layer 21 is oxidized to transform the patterned mask layer 21 into an oxide mask layer 31 .
[0067] For step S300, Figure 3 As shown, in some embodiments, in the presence of oxygen (O 2 ) or ozone (O 3 ) is subjected to heat treatment in a gas environment to transform the patterned mask layer 21 into an oxide mask layer 31.
[0068] When the patterned mask layer 21 is heat-treated in a gas environment containing ozone, since ozone has a strong oxidizing property, compared with traditional high-temperature oxidation treatment, the use of ozone for oxidation treatment can quickly oxidize the patterned mask layer 21 into an oxide mask layer 31 at a relatively low temperature, thereby reducing the risk of thermal damage to other materials and / or devices in the semiconductor structure caused by the oxidation process, and helping to protect the performance and reliability of the semiconductor structure.
[0069] In addition, the use of ozone for oxidation treatment has good process compatibility and can be seamlessly integrated with existing semiconductor manufacturing processes and equipment. There is no need to purchase additional dedicated equipment or make large-scale process adjustments, and therefore there is no need to increase equipment investment costs.
[0070] Taking the patterned mask layer 21 formed by deposition of titanium nitride material as an example, the titanium nitride material can effectively react with ozone during the oxidation process to form a stable titanium oxide (TiO 2 ) mask layer. The chemical formula of the reaction between titanium nitride material and ozone is as follows:
[0071] TiN+O 3 =TiO 2 +NO.
[0072] Considering that ozone is relatively unstable at room temperature and easily decomposes under heat, its decomposition temperature is about 300° C. As an example, when the patterned mask layer 21 is heat-treated in a gas environment containing ozone, the reaction temperature range may specifically include 100° C. to 200° C.
[0073] Controlling the reaction temperature between 100° C. and 200° C. can effectively prevent excessive decomposition of ozone during the heat treatment process, thereby ensuring that ozone has sufficient activity and stability during the oxidation treatment process in step S300 and improving the oxidation efficiency.
[0074] Moreover, compared with a higher temperature range, the reaction temperature of 100°C to 200°C is relatively low, which can avoid thermal damage to the substrate and / or other materials, protect the performance and reliability of the semiconductor structure from being affected, and improve the production yield of the semiconductor structure.
[0075] As an example, when the patterned mask layer 21 is heat-treated in a gas environment containing ozone, the reaction temperature range may be 100° C., 125° C., 150° C., 175° C., or 200° C., etc.
[0076] See also Figure 4 In step S400 , the oxide mask layer 31 is removed.
[0077] It can be understood that the oxide mask layer 31 can be removed using a common cleaning solution, without the need for the user to purchase expensive equipment (eg, an EKC580 machine).
[0078] In some embodiments, the oxide mask layer 31 may be removed using a cleaning solution containing hydrofluoric acid (HF).
[0079] Currently, mask removal usually requires the use of the H 2 O 2 Water. The conventional mask layer itself has a low reactivity to hydrofluoric acid and is difficult to be directly removed by hydrofluoric acid. However, since the patterned mask layer 21 is transformed into an oxide mask layer 31 in step S300, the reactivity of the oxide mask layer 31 with hydrofluoric acid is significantly improved, and thus it can be directly removed using a cleaning solution containing hydrofluoric acid (HF), without relying on the HF of the EKC580 machine. 2 O 2 water, significantly reducing production costs.
[0080] Taking the case where a patterned mask layer 21 is formed by depositing a titanium nitride material and then converted into a titanium oxide mask layer after oxidation treatment as an example, the titanium oxide mask layer has a high reactivity with hydrofluoric acid and can therefore be removed using a cleaning solution containing hydrofluoric acid (HF). The chemical formula for the reaction between the titanium oxide mask layer and hydrofluoric acid is as follows:
[0081] TiO 2 +6HF=H 2 [TiF 6 ]+2H 2 O.
[0082] The above reaction can be carried out at room temperature without additional heating or high temperature conditions. The process is simple and easy to implement, and the titanium oxide mask layer can be removed efficiently. The reaction product titanate (H 2 [TiF 6 ]) Stable in solution and easy to clean and handle.
[0083] It can be understood that the manufacturing method provided by the present application can form a precise groove or trench structure by etching the interlayer dielectric material layer 11 using the patterned mask layer 21 as a mask. Figure 4As shown, the formed grooves or trenches can be used to fill conductive materials, such as metal conductive materials (such as copper). The conductive materials are filled in the grooves or trenches to form conductive interconnect structures 40 for connecting different parts in the semiconductor device to achieve transmission of electrical signals.
[0084] As mentioned above, by using the manufacturing method provided by the present application, a barrier layer and / or seed layer with better morphology can be obtained, and the overhang phenomenon and premature sealing of the top of the opening can be reduced. Therefore, the uniform filling of the conductive material can be ensured, the generation of voids and defects can be reduced, thereby improving the reliability and stability of the conductive interconnection and ensuring good electrical contact and signal transmission in the semiconductor structure.
[0085] According to some embodiments, the present application also provides a semiconductor structure, which is manufactured by the manufacturing method of the semiconductor structure provided in the above embodiment. Therefore, the technical effects that can be achieved by the manufacturing method of the above semiconductor structure can also be achieved by the semiconductor structure, which will not be described in detail here.
[0086] In the description of this specification, the description with reference to the terms "some embodiments", "as an example", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0087] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0088] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, and forming an interlayer dielectric material layer on a surface of the substrate; forming a patterned mask layer on a side of the interlayer dielectric material layer away from the substrate; After etching the interlayer dielectric material layer using the patterned mask layer as a mask, the patterned mask layer is oxidized to transform the patterned mask layer into an oxide mask layer; The oxide mask layer is removed.
2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of performing oxidation treatment on the patterned mask layer comprises: A heat treatment is performed in a gas environment containing oxygen or ozone to transform the patterned mask layer into the oxide mask layer.
3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that: When the patterned mask layer is heat-treated in a gas environment containing ozone, the reaction temperature ranges from 100°C to 200°C.
4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that: When the patterned mask layer is heat treated in a gas environment containing ozone, the reaction temperature is 100°C.
5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The step of forming a patterned mask layer on a side of the interlayer dielectric material layer away from the substrate comprises: The patterned mask layer is formed by depositing a nitride material on a side of the interlayer dielectric material layer away from the substrate.
6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The nitride material includes titanium nitride.
7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: The removing of the oxide mask layer comprises: The oxide mask layer is removed by using a cleaning solution containing hydrofluoric acid.
8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The step of forming an interlayer dielectric material layer on the surface of the substrate comprises: A low dielectric constant material layer and an ultra-low dielectric constant material layer are sequentially formed on the surface of the substrate.
9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: Before forming the patterned mask layer on the side of the interlayer dielectric material layer away from the substrate, the manufacturing method further comprises: forming a protective material layer on the side of the interlayer dielectric material layer away from the substrate; Wherein, the patterned mask layer is formed on a side of the protective material layer away from the interlayer dielectric material layer.
10. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 9.