Constant-frequency DCDC circuit

Abstract

The invention provides a DCDC circuit with constant frequency, which is applied to the technical field of clock circuits, and comprises a clock circuit and a bias current circuit, the clock circuit is used for generating a clock signal with constant frequency for controlling the on or off of a power tube M1, and the bias current circuit is used for generating a bias current; the bias current circuit is used for providing bias current to dynamically adjust the substrate potential of a depletion type MOS tube in the clock circuit to realize temperature compensation; the clock circuit comprises an MOS (Metal Oxide Semiconductor) transistor PM12, an MOS transistor PM11, an MOS transistor NM11 and an MOS transistor NM12, a substrate of the MOS transistor PM12 is accessed to bias current Ip1 through a resistance network, and a substrate of the MOS transistor NM12 is accessed to bias current In1 through the resistance network; the bias current circuit comprises a current generation unit and a current mirror unit, the current generation unit generates a synthesis current I0 with a positive temperature coefficient, and the current mirror unit generates a bias current corresponding to the clock circuit based on the synthesis current I0 by using a current mirror structure.

Description

Technical Field

[0001] The invention belongs to the technical field of clock circuits, and in particular relates to a DCDC circuit with a constant frequency. Background Art

[0002] The frequency of the oscillator is the basis for the operation of the DCDC converter. When the oscillator has temperature drift, its output frequency will change with the temperature, which may cause the stability of the output voltage or current of the DCDC converter to decrease. Especially in situations where the output voltage or current needs to be accurately controlled, such as precision instruments, communication equipment, etc., the impact of temperature drift on system stability is particularly significant.

[0003] The control loop of a DCDC converter usually relies on the frequency of an oscillator to adjust the output voltage or current. If the frequency of the oscillator changes due to temperature drift, the performance of the control loop will also be affected, which may lead to problems such as slower system response speed and reduced regulation accuracy.

[0004] The frequency change of the oscillator may also affect the electromagnetic compatibility of the system. When the frequency changes, the electromagnetic radiation generated by the system will also change, which may increase the interference to other electronic devices or be interfered by other electronic devices.

[0005] like Figure 1 As shown, the threshold of the MOS tube in the traditional clock circuit is greatly affected by temperature, which causes the clock frequency output therefrom to have a positive temperature characteristic. When the temperature rises, the frequency changes accordingly, affecting the normal use of the DCDC circuit. Summary of the invention

[0006] In view of the above problems in the prior art, the purpose of the present invention is to provide a constant frequency DCDC circuit, which dynamically adjusts the substrate potential of the depletion-type MOS tube through a bias current with a positive temperature characteristic, realizes threshold voltage compensation, and improves the stability of circuit performance.

[0007] A constant frequency DCDC circuit comprises a clock module, wherein the clock module comprises a clock circuit and a bias current circuit, wherein the clock circuit is used to generate a clock signal with a constant frequency for controlling the opening or closing of a power tube M1, and the bias current circuit is used to provide a bias current with a positive temperature coefficient to the clock circuit, and the substrate potential of a depletion-type MOS tube in the clock circuit is dynamically adjusted by using the bias current to realize temperature compensation; the clock circuit comprises a MOS tube PM12, a MOS tube PM11, a MOS tube NM11 and a MOS tube NM12, wherein the MOS tube PM12 and the MOS tube NM12 are depletion-type MOS tubes, the substrate of the MOS tube PM12 is connected to the bias current I p1 through a resistor network, and the substrate of the MOS tube NM12 is connected to the bias current I n1; the gate of the MOS transistor PM11 and the gate of the MOS transistor NM11 are connected, the drain of the MOS transistor PM11 and the drain of the MOS transistor NM11 are connected, the source of the MOS transistor PM11 is connected to the drain of the MOS transistor PM12, the source and gate of the MOS transistor PM12 are connected, the source of the MOS transistor NM11 is connected to the drain of the MOS transistor NM12, and the source and gate of the MOS transistor NM12 are connected; the bias current circuit includes a current generating unit and a current mirror unit, the current generating unit is used to generate a synthetic current I0 with a positive temperature coefficient, and the current mirror unit generates a bias current corresponding to the clock circuit based on the synthetic current I0 by using a current mirror structure.

[0008] Preferably, the substrate of the MOS transistor PM12 is connected to the bias current I p1 through the resistor R11 , and the substrate of the MOS transistor NM12 is connected to the bias current I n1 through the resistor R12 .

[0009] Preferably, the clock circuit further includes a MOS transistor PM22, a MOS transistor PM21, a MOS transistor NM21 and a MOS transistor NM22 and a resistor R21 and a resistor R22; the MOS transistor PM22 and the MOS transistor NM22 are depletion-type MOS transistors, the substrate of the MOS transistor PM22 is connected to the bias current I p2 through the resistor R21, and the substrate of the MOS transistor NM22 is connected to the bias current I n2 through the resistor R22; the gate of the MOS transistor PM21 and the gate of the MOS transistor NM21 are connected and connected to the drains of the MOS transistors PM11 and NM11, the drain of the MOS transistor PM21 and the drain of the MOS transistor NM21 are connected, the source of the MOS transistor PM21 is connected to the drain of the MOS transistor PM22, the source of the MOS transistor PM22 is connected to the gate, the source of the MOS transistor NM21 is connected to the drain of the MOS transistor NM22, and the source of the MOS transistor NM22 is connected to the gate.

[0010] Preferably, the clock circuit further includes a MOS transistor PM32, a MOS transistor PM31, a MOS transistor NM31 and a MOS transistor NM32 and a resistor R31 and a resistor R32; the MOS transistor PM32 and the MOS transistor NM32 are depletion-type MOS transistors, the substrate of the MOS transistor PM32 is connected to the bias current I p3 through the resistor R31, and the substrate of the MOS transistor NM32 is connected to the bias current I n3 through the resistor R32; the gate of the MOS transistor PM31 and the gate of the MOS transistor NM31 are connected and connected to the drain of the MOS transistors PM21 and NM21, the drain of the MOS transistor PM31 and the drain of the MOS transistor NM31 are connected and connected to the gates of the MOS transistors PM11 and NM11, the source of the MOS transistor PM31 is connected to the drain of the MOS transistor PM32, the source of the MOS transistor PM32 is connected to the gate, the source of the MOS transistor NM31 is connected to the drain of the MOS transistor NM32, and the source of the MOS transistor NM32 is connected to the gate.

[0011] Preferably, the current generating unit includes a MOS tube PM41, a resistor R0, and a MOS tube NM41, wherein the source and gate of the MOS tube PM41 are connected to the power supply VDD, the sum of the drain current I2 output by the drain of the MOS tube PM41 and the current I1 generated by the power supply VDD through the resistor R0 forms a synthetic current I0 connected to the gate and drain of the MOS tube NM41, and the source of the MOS tube NM41 is grounded.

[0012] Preferably, the current mirror unit includes a MOS transistor PM42, a MOS transistor PM43, a MOS transistor NM42, and a MOS transistor NM43, the sources of the MOS transistor NM42 and the MOS transistor NM43 are grounded, the gates of the MOS transistors NM41, NM42, and NM43 are connected to each other and connected to a synthetic current I0, the drain of the MOS transistor NM43 generates a bias current I n1, the drain of the MOS transistor NM42 is connected to the gate and drain of the MOS transistor PM42, the gates of the MOS transistor PM42 and the MOS transistor PM43 are connected to each other, the drain of the MOS transistor PM43 generates a bias current I p1, and the source of the MOS transistor PM42 and the source of the MOS transistor PM43 are connected to a power supply VDD.

[0013] Preferably, the current mirror unit further includes a MOS transistor PM44 and a MOS transistor NM44, wherein the source of the MOS transistor PM44 is connected to the power supply VDD, the gate is connected to the gates of the MOS transistors PM42 and PM43, and the drain outputs a bias current I p2; the source of the MOS transistor NM44 is grounded, the gate is connected to the gates of the MOS transistors NM42 and NM43, and the drain outputs a bias current I n2.

[0014] Preferably, the current mirror unit further includes a MOS transistor PM45 and a MOS transistor NM45, wherein the source of the MOS transistor PM45 is connected to the power supply VDD, the gate is connected to the gates of the MOS transistors PM42, PM43 and PM44, and the drain outputs a bias current I p3; the source of the MOS transistor NM45 is grounded, the gate is connected to the gates of the MOS transistors NM42, NM43 and NM44, and the drain outputs a bias current I n3.

[0015] Preferably, the clock module is connected to the logic control module, and the pulse output end of the logic control module is connected to the power tube M1 for controlling the power tube M1 to be turned on or off; the source of the power tube M1 is connected to a diode D1 and an inductor L0 in parallel, the other end of the diode D1 is grounded, the other end of the inductor L0 is connected to a capacitor C0, and a resistor R1 and a resistor R2 connected in series, the other end of the capacitor C0 and the other end of the resistor R2 are grounded, and a feedback voltage Vfb is output between the resistor R1 and the resistor R2; the feedback voltage Vfb and the reference voltage Vref are connected to the input end of the amplifier, and the output signal of the amplifier is connected to the logic control module through a supplementary module to realize circuit feedback.

[0016] The beneficial effects of the present invention are as follows: the constant frequency DCDC circuit realizes dynamic temperature compensation of the threshold voltage of the MOS tube through a bias current circuit with a positive temperature characteristic; as the temperature rises, the positive temperature current I1 and the leakage current I2 increase; the synthetic current I0 formed by the two generates a corresponding bias current through a current mirror structure to realize dynamic adjustment of the substrate potential, compensate for the decrease in the threshold voltage of the depletion-type MOS tube at high temperature, effectively suppress the phenomenon of the threshold voltage drifting with temperature, ensure the performance stability of the MOS tube at different temperatures, thereby improving the stability of the entire circuit, and effectively improving the working performance of the circuit in a high temperature environment, and is particularly suitable for application scenarios such as industry, automotive electronics, and high-temperature sensors.

[0017] The MOS tube connected by a resistor and a reverse diode generates a positive temperature current, and the structure design is simple, without the need for additional complex circuits. At the same time, in the clock circuit, the substrate potential of the depletion-type MOS tube is adjusted through a resistor network, avoiding a highly complex temperature sensing circuit, and is easy to integrate and implement in practical applications.

[0018] The constant frequency DCDC circuit has the advantages of simple structure, significant compensation effect, fast temperature response, and output of multiple bias currents. It can be widely used in high-precision analog circuits, sensor circuits, and other electronic systems that require temperature stability, and has high practical value and promotion prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0020] Figure 1 It is the circuit diagram of a traditional clock circuit;

[0021] Figure 2 is a circuit diagram of the present invention;

[0022] Figure 3 is a circuit diagram of a clock circuit of the present invention;

[0023] Figure 4 is a circuit diagram of a bias current circuit of the present invention;

[0024] Figure 5 It is a working waveform diagram of the depletion-type MOS tube of the present invention. DETAILED DESCRIPTION

[0025] Embodiment 1

[0026] like Figure 2 As shown, a constant frequency DCDC circuit includes a clock module, the clock module includes a clock circuit and a bias current circuit, wherein the clock module is used to generate a clock signal with a constant frequency for controlling the power tube M1 to be turned on or off. The bias current circuit is used to provide a bias current with a positive temperature coefficient to the clock circuit, and the substrate potential of the depletion-type MOS tube in the clock circuit is dynamically adjusted by the bias current to achieve temperature compensation.

[0027] like Figure 3 As shown, the clock circuit includes MOS transistors PM12, PM11, NM11 and NM12 and resistors R11 and R12, wherein MOS transistors PM12 and NM12 are depletion-type MOS transistors, the substrate of MOS transistor PM12 is connected to bias current I p1 through resistor R11, and the substrate of MOS transistor NM12 is connected to bias current I n1 through resistor R12.

[0028] Specifically, the source of the MOS transistor PM12 is connected to the gate, the drain of the MOS transistor PM12 is connected to the source of the MOS transistor PM11, the gate of the MOS transistor PM11 is connected to the gate of the MOS transistor NM11, the drain of the MOS transistor PM11 is connected to the drain of the MOS transistor NM11, the source of the MOS transistor NM11 is connected to the drain of the MOS transistor NM12, and the gate of the MOS transistor NM12 is connected to the source.

[0029] It should be noted that the bias current I p1 and the bias current I n1 have positive temperature characteristics. As the temperature rises, the current increases accordingly. The dynamic compensation of the depletion-type MOS tube by the bias current enables the circuit to have better stability at different temperatures.

[0030] like Figure 5 As shown, since the MOS transistor PM12 is a P-type MOS transistor, the substrate potential Vsubp1 of the MOS transistor PM12 decreases as the temperature increases, and the bias current Ip1 generates a corresponding voltage drop that is positively correlated with the temperature after passing through the resistor R11. The voltage drop is applied to the substrate of the MOS transistor PM12 to compensate for the influence of the threshold voltage drop of the MOS transistor PM12 at high temperature.

[0031] Since the MOS tube NM12 is an N-type MOS tube, the substrate potential Vsubn1 of the MOS tube NM12 increases with the increase of temperature, and the bias current I n1 generates a corresponding voltage drop that is positively correlated with the temperature after passing through the resistor R12. The voltage drop is applied to the substrate of the MOS tube NM12. Through the synergistic effect of the influence of the bias current I p1 on the substrate voltage of the MOS tube PM12 and the influence of the bias current I n1 on the substrate voltage of the MOS tube NM12, the threshold voltage of the MOS tube NM12 can be effectively compensated, so that the threshold voltage of the MOS tube NM12 can remain stable when the temperature increases and does not change with the temperature.

[0032] like Figure 4 As shown, the bias current circuit includes a MOS transistor PM41, a resistor R0, a MOS transistor NM41, a MOS transistor PM42, a MOS transistor PM43, a MOS transistor NM42, and a MOS transistor NM43.

[0033] The source and gate of MOS transistor PM41, the source of MOS transistor PM42 and the source of MOS transistor PM43 are respectively connected to the power supply VDD, and the sum of the drain current I2 output by the drain of MOS transistor PM41 and the current I1 generated by the power supply VDD through the resistor R0 forms a synthetic current I0 which is connected to MOS transistor NM41.

[0034] The sources of the MOS tubes NM41, NM42 and NM43 are all grounded, the gates of the MOS tubes NM41, NM42 and NM43 are connected to each other and connected to the synthetic current I0, the drain and gate of the MOS tube NM41 are connected, the drain of the MOS tube NM42 is connected to the gate and drain of the MOS tube PM42, the drain of the MOS tube NM43 generates a bias current I n1, the gates of the MOS tubes PM42 and PM43 are connected to each other, and the drain of the MOS tube PM43 generates a bias current I p1.

[0035] Among them, the MOS transistor PM41 uses a reverse diode structure to generate a drain current I2 with a positive temperature characteristic, and the current I1 generated by the resistor R0 connected in series between the power supply and the MOS transistor NM41 also has a positive temperature characteristic. Therefore, the synthetic current I0 formed by the drain current I2 of the MOS transistor PM41 and the current I1 flowing through the resistor R0 has a positive temperature characteristic. The synthetic current I0 forms a bias current Ip1 and a bias current In1 through a current mirror structure, which are used to drive the clock circuit and provide a stable temperature compensation function.

[0036] Embodiment 2

[0037] like Figure 3 , Figure 4 As shown, the structure of this embodiment is basically the same as that of the first embodiment, except that: the clock circuit in this embodiment further includes MOS transistor PM22, MOS transistor PM21, MOS transistor NM21 and MOS transistor NM22 and resistors R21 and R22. Among them, MOS transistor PM22 and MOS transistor NM22 are depletion-type MOS transistors, the substrate of MOS transistor PM22 is connected to bias current I p2 through resistor R21, and the substrate of MOS transistor NM22 is connected to bias current I n2 through resistor R22.

[0038] The gate of MOS transistor PM21 and the gate of MOS transistor NM21 are connected and connected to the drains of MOS transistor PM11 and MOS transistor NM11, the drain of MOS transistor PM21 and the drain of MOS transistor NM21 are connected, the source of MOS transistor PM21 is connected to the drain of MOS transistor PM22, the source and gate of MOS transistor PM22 are connected, the source of MOS transistor NM21 is connected to the drain of MOS transistor NM22, and the source and gate of MOS transistor NM22 are connected.

[0039] Correspondingly, the current mirror unit further includes a MOS transistor PM44 and a MOS transistor NM44, wherein the source of the MOS transistor PM44 is connected to the power supply VDD, the gate of the MOS transistor PM44 is connected to the gates of the MOS transistors PM42 and PM43, and the drain of the MOS transistor PM44 outputs a bias current Ip2. The source of the MOS transistor NM44 is grounded, the gate is connected to the gates of the MOS transistors NM42 and NM43, and the drain outputs a bias current In2.

[0040] Embodiment 3

[0041] like Figure 3 , Figure 4As shown, the structure of this embodiment is basically the same as that of the second embodiment, except that: the clock circuit in this embodiment further includes MOS transistor PM32, MOS transistor PM31, MOS transistor NM31 and MOS transistor NM32 and resistors R31 and R32. Among them, MOS transistor PM32 and MOS transistor NM32 are depletion-type MOS transistors, the substrate of MOS transistor PM32 is connected to bias current I p3 through resistor R31, and the substrate of MOS transistor NM32 is connected to bias current I n3 through resistor R32.

[0042] The gate of the MOS transistor PM31 and the gate of the MOS transistor NM31 are connected and connected to the drains of the MOS transistors PM21 and NM21; the drain of the MOS transistor PM31 and the drain of the MOS transistor NM31 are connected and connected to the gates of the MOS transistors PM11 and NM11; the source of the MOS transistor PM31 is connected to the drain of the MOS transistor PM32; the source and gate of the MOS transistor PM32 are connected; the source of the MOS transistor NM31 is connected to the drain of the MOS transistor NM32; and the source and gate of the MOS transistor NM32 are connected.

[0043] Correspondingly, the current mirror unit further includes a MOS transistor PM45 and a MOS transistor NM45, wherein the source of the MOS transistor PM45 is connected to the power supply VDD, the gate of the MOS transistor PM45 is connected to the gates of the MOS transistors PM42, PM43, and PM44, and the drain of the MOS transistor PM45 outputs a bias current I p3. The source of the MOS transistor NM45 is grounded, the gate of the MOS transistor NM45 is connected to the gates of the MOS transistors NM42, NM43, and NM44, and the drain of the MOS transistor NM45 outputs a bias current I n3.

[0044] like Figure 3 As shown in FIG. 1 , the clock circuit forms a self-excited oscillation and generates a CLK signal. Figure 2 As shown, the clock module is connected to the logic control module, the pulse output end of the logic control module is connected to the power tube M1, and the logic control module controls the power tube M1 to turn on or off according to the clock signal with a constant frequency generated by the clock module.

[0045] Among them, the source of the power tube M1 is connected to a diode D1 and an inductor L0 in parallel, the other end of the diode D1 is grounded, the other end of the inductor L0 is connected to a capacitor C0, and a resistor R1 and a resistor R2 connected in series, the other end of the capacitor C0 and the other end of the resistor R2 are grounded, and a feedback voltage Vfb is output between the resistor R1 and the resistor R2.

[0046] The feedback voltage Vfb and the reference voltage Vref are connected to the input end of the amplifier, and the output signal of the amplifier is connected to the logic control module through the supplementary module to realize circuit feedback.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A constant frequency DCDC circuit, characterized in that: The clock module includes a clock circuit and a bias current circuit. The clock circuit is used to generate a clock signal with a constant frequency for controlling the power tube M1 to be turned on or off. The bias current circuit is used to provide a bias current with a positive temperature coefficient to the clock circuit. The bias current is used to dynamically adjust the substrate potential of the depletion-type MOS tube in the clock circuit to achieve temperature compensation. The clock circuit includes a MOS transistor PM12, a MOS transistor PM11, a MOS transistor NM11 and a MOS transistor NM12, wherein the MOS transistor PM12 and the MOS transistor NM12 are depletion-type MOS transistors, the substrate of the MOS transistor PM12 is connected to the bias current Ip1 through a resistor network, and the substrate of the MOS transistor NM12 is connected to the bias current In1 through a resistor network; The gate of the MOS transistor PM11 is connected to the gate of the MOS transistor NM11, the drain of the MOS transistor PM11 is connected to the drain of the MOS transistor NM11, the source of the MOS transistor PM11 is connected to the drain of the MOS transistor PM12, the source and gate of the MOS transistor PM12 are connected, the source of the MOS transistor NM11 is connected to the drain of the MOS transistor NM12, and the source and gate of the MOS transistor NM12 are connected; The bias current circuit includes a current generating unit and a current mirror unit. The current generating unit is used to generate a synthetic current I0 with a positive temperature coefficient. The current mirror unit generates a bias current corresponding to the clock circuit based on the synthetic current I0 using a current mirror structure.

2. The constant frequency DCDC circuit according to claim 1, characterized in that: The substrate of the MOS transistor PM12 is connected to the bias current Ip1 through the resistor R11, and the substrate of the MOS transistor NM12 is connected to the bias current In1 through the resistor R12.

3. The constant frequency DCDC circuit according to claim 1, characterized in that: The clock circuit further includes a MOS transistor PM22, a MOS transistor PM21, a MOS transistor NM21, a MOS transistor NM22, and a resistor R21, a resistor R22; The MOS transistor PM22 and the MOS transistor NM22 are depletion-type MOS transistors. The substrate of the MOS transistor PM22 is connected to the bias current Ip2 through the resistor R21, and the substrate of the MOS transistor NM22 is connected to the bias current In2 through the resistor R22. The gate of the MOS transistor PM21 and the gate of the MOS transistor NM21 are connected and connected to the drains of the MOS transistors PM11 and NM11, the drain of the MOS transistor PM21 and the drain of the MOS transistor NM21 are connected, the source of the MOS transistor PM21 is connected to the drain of the MOS transistor PM22, the source and gate of the MOS transistor PM22 are connected, the source of the MOS transistor NM21 is connected to the drain of the MOS transistor NM22, and the source and gate of the MOS transistor NM22 are connected.

4. The constant frequency DCDC circuit according to claim 3, characterized in that: The clock circuit also includes MOS transistor PM32, MOS transistor PM31, MOS transistor NM31 and MOS transistor NM32 and resistors R31 and R32; The MOS transistor PM32 and the MOS transistor NM32 are depletion-type MOS transistors. The substrate of the MOS transistor PM32 is connected to the bias current Ip3 through the resistor R31, and the substrate of the MOS transistor NM32 is connected to the bias current In3 through the resistor R32. The gate of the MOS transistor PM31 and the gate of the MOS transistor NM31 are connected and connected to the drains of the MOS transistors PM21 and NM21; the drain of the MOS transistor PM31 and the drain of the MOS transistor NM31 are connected and connected to the gates of the MOS transistors PM11 and NM11; the source of the MOS transistor PM31 is connected to the drain of the MOS transistor PM32; the source and gate of the MOS transistor PM32 are connected; the source of the MOS transistor NM31 is connected to the drain of the MOS transistor NM32; the source and gate of the MOS transistor NM32 are connected.

5. The constant frequency DCDC circuit according to claim 1, characterized in that: The current generating unit includes a MOS transistor PM41, a resistor R0, and a MOS transistor NM41. The source and gate of the MOS transistor PM41 are connected to the power supply VDD. The sum of the drain current I2 output by the drain of the MOS transistor PM41 and the current I1 generated by the power supply VDD through the resistor R0 forms a synthetic current I0 connected to the gate and drain of the MOS transistor NM41. The source of the MOS transistor NM41 is grounded.

6. The constant frequency DCDC circuit according to claim 5, characterized in that: The current mirror unit includes a MOS transistor PM42, a MOS transistor PM43, a MOS transistor NM42, and a MOS transistor NM43. The sources of the MOS transistors NM42 and NM43 are grounded. The gates of the MOS transistors NM41, NM42, and NM43 are connected to each other and connected to a synthetic current I0. The drain of the MOS transistor NM43 generates a bias current In1. The drain of the MOS transistor NM42 is connected to the gate and drain of the MOS transistor PM42. The gates of the MOS transistors PM42 and PM43 are connected to each other. The drain of the MOS transistor PM43 generates a bias current Ip1. The sources of the MOS transistor PM42 and PM43 are connected to a power supply VDD.

7. The constant frequency DCDC circuit according to claim 6, characterized in that: The current mirror unit further includes a MOS transistor PM44 and a MOS transistor NM44, wherein the source of the MOS transistor PM44 is connected to the power supply VDD, the gate is connected to the gates of the MOS transistor PM42 and the MOS transistor PM43, and the drain outputs a bias current Ip2; The source of the MOS transistor NM44 is grounded, the gate is connected to the gates of the MOS transistors NM42 and NM43, and the drain outputs the bias current In2.

8. The constant frequency DCDC circuit according to claim 7, characterized in that: The current mirror unit further includes a MOS transistor PM45 and a MOS transistor NM45, wherein the source of the MOS transistor PM45 is connected to the power supply VDD, the gate is connected to the gates of the MOS transistors PM42, PM43 and PM44, and the drain outputs a bias current Ip3; The source of the MOS transistor NM45 is grounded, the gate is connected to the gates of the MOS transistors NM42 , NM43 , and NM44 , and the drain outputs a bias current In3 .

9. The constant frequency DCDC circuit according to any one of claims 1 to 8, characterized in that: The clock module is connected to the logic control module, and the pulse output end of the logic control module is connected to the power tube M1 to control the power tube M1 to be turned on or off; The source of the power tube M1 is connected to a diode D1 and an inductor L0 in parallel, the other end of the diode D1 is grounded, the other end of the inductor L0 is connected to a capacitor C0, and a resistor R1 and a resistor R2 connected in series, the other end of the capacitor C0 and the other end of the resistor R2 are grounded, and a feedback voltage Vfb is output between the resistor R1 and the resistor R2; The feedback voltage Vfb and the reference voltage Vref are connected to the input end of the amplifier, and the output signal of the amplifier is connected to the logic control module through the supplementary module to realize circuit feedback.

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