High-precision low-frequency clock generation circuit based on frequency divider
Through the high-precision low-frequency clock generation circuit based on the frequency divider, the frequency divider and frequency selection circuit are used to generate high-precision low-frequency clock signals, which solves the problem of low-precision low-frequency clock signals in the prior art, and realizes the low-frequency clock signal output with adjustable frequency and high reliability.
Patent Information
- Application Number
- CN202411802005.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-05-13
Smart Images
Figure CN119995587A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of clocks, and in particular to a high-precision low-frequency clock generating circuit based on a frequency divider. Background Art
[0002] With the development of domestic aviation technology, more and more designs have put forward the demand for high-precision low-frequency clocks. The clock sources on the market now have relatively high frequencies, generally greater than 1MHz, while the low-frequency clocks require a frequency less than or equal to 1KHz. In addition, the commonly used low-frequency clocks on the market are mostly sinusoidal waveform clocks with low precision, which do not meet the design requirements. Summary of the invention
[0003] In view of this, the present application provides a high-precision low-frequency clock generation circuit based on a frequency divider, which solves the problems in the prior art and improves the accuracy and reliability of the generated low-frequency clock signal.
[0004] The present application provides a high-precision low-frequency clock generation circuit based on a frequency divider, which adopts the following technical solution:
[0005] A high-precision low-frequency clock generation circuit based on a frequency divider, comprising:
[0006] Clock, as a clock source outputs a pulse signal;
[0007] The frequency divider receives the pulse signal output by the clock, counts the number of pulses and converts them into binary signal output;
[0008] The frequency selection circuit receives the binary signal output by the frequency divider, and selects the corresponding binary value. When the actual binary value is consistent with the preset binary value, the output level of the frequency selection circuit is reversed to obtain a square wave signal of the required frequency.
[0009] Optionally, the pulse signal frequency f output by the clock is a MHz, where a is 1-10.
[0010] Optionally, the frequency divider is a counter with at least ten bits, and a CLK input terminal of the counter receives a pulse signal of the clock.
[0011] Optionally, the frequency selection circuit includes a logic gate and a JK flip-flop, the input end of the logic gate is connected to the output end of the frequency divider, and the output end of the logic gate generates a high level every time the counter accumulates n-1 pulses. When the next clock cycle arrives, the frequency divider is reset, and the output generates a falling edge, so that a falling edge is generated for every n high-speed clock pulses;
[0012] The J and K pins of the JK flip-flop are pulled up to a high level. Whenever a falling edge is detected at the input, the level of the output Q is flipped, thereby obtaining the required square wave signal.
[0013] Optionally, the high-precision low-frequency clock generating circuit also includes a signal conditioning circuit, which receives a square wave signal output by the frequency selection circuit, and the signal conditioning circuit amplifies the square wave signal circuit to drive a back-end application circuit.
[0014] Optionally, the signal conditioning circuit is a push-pull output circuit, which includes a PMOS and an NMOS. When the input of the push-pull circuit is 1, the PMOS is turned on, the NMOS is turned off, and the output of the push-pull output circuit is connected to VDD; when the input of the push-pull circuit is 0, the PMOS is turned off, the NMOS is turned on, and the output of the push-pull output circuit is connected to VSS.
[0015] In summary, this application includes the following beneficial technical effects:
[0016] The advantage of the low-frequency clock generation circuit of the present application is that it uses simple electronic devices, which can adapt to more complex operating environments and has higher reliability compared to complex electronic devices. The advantage of the low-frequency clock generation circuit of the present application is that the frequency of the low-frequency clock is adjustable and has high precision due to the frequency division function of the frequency divider, and the frequency can be flexibly adjusted according to different project requirements to meet product requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0018] Figure 1 4 is a principle block diagram of a high-precision low-frequency clock generating circuit in an embodiment of the present application. DETAILED DESCRIPTION
[0019] The embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0020] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.
[0021] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.
[0022] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The illustrations only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.
[0023] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.
[0024] An embodiment of the present application provides a high-precision low-frequency clock generation circuit based on a frequency divider.
[0025] A high-precision low-frequency clock generation circuit based on a frequency divider, comprising:
[0026] A high-frequency clock is used as a clock source to output a pulse signal, and the frequency f of the pulse signal output by the clock is a MHz, where a is 1-10.
[0027] The frequency divider receives the pulse signal output by the clock, counts the number of pulses and converts them into a binary signal for output. The frequency divider is a counter with at least ten bits, and the CLK input terminal of the counter receives the pulse signal of the clock.
[0028] The frequency selection circuit receives the binary signal output by the frequency divider, and the frequency selection circuit selects the corresponding binary value. When the actual binary value is consistent with the preset binary value, the frequency selection circuit outputs a level flip, and obtains a square wave signal of the required frequency. The frequency selection circuit includes a logic gate and a JK trigger. The input end of the logic gate is connected to the output end of the frequency divider. Whenever the counter accumulates n-1 pulses, the output end of the logic gate generates a high level. When the next clock cycle arrives, the frequency divider is reset, and the output generates a falling edge, so that a falling edge is generated for every n high-speed clock pulses; the J pin and the K pin of the JK trigger are pulled up to a high level. Whenever a falling edge is detected at the input end, the level of the output end Q is flipped once, so as to obtain the required square wave signal.
[0029] The signal conditioning circuit receives the square wave signal output by the frequency selection circuit, and the signal conditioning circuit amplifies the square wave signal circuit to drive the back-end application circuit. The signal conditioning circuit is a push-pull output circuit, and the push-pull output circuit includes a PMOS and an NMOS. When the input end of the push-pull circuit is 1, the PMOS is turned on, the NMOS is turned off, and the output end of the push-pull output circuit is connected to VDD; when the input end of the push-pull circuit is 0, the PMOS is turned off, the NMOS is turned on, and the output end of the push-pull output circuit is connected to VSS.
[0030] like Figure 1 As shown, the embodiment of the present application takes a 1MHz high-frequency clock source and a 1KHz required clock as an example to explain in detail the technical solution of the present application.
[0031] Select a general high-frequency clock source with an output frequency of 1MHz, which emits a stable square wave clock. Select a counter with at least ten digits, connect the 1MHz clock to the CLK input of the counter, and set the counter to count up.
[0032] The logic gate selects a multi-input AND gate circuit, and the input end is connected to the D1, D2, D5, D6, D7, D8, and D9 data output ports of the counter / frequency divider. Every time the counter accumulates 499 pulses, the output of the AND gate circuit will generate a high level. When the next clock cycle arrives, the counter is reset and the output generates a falling edge. Thus, a falling edge is generated every 500 high-speed clock pulses, that is, a falling edge is generated every 0.5ms.
[0033] The general JK flip-flop pulls the J and K pins of the JK flip-flop to a high level, so that it has the function of output state flipping. Whenever a falling edge is detected at the input end, the level of the output end Q flips once, 0→1 or 1→0, and flips once every 0.5ms, thereby obtaining a square wave signal with a period of 1ms (frequency of 1KHz) and a duty cycle of 50%. The pulse clock output signal is shown in Table 1.
[0034] Table 1 Schematic diagram of pulse clock output signal
[0035] CLK J K Q Q* x x x x Q Falling edge 0 0 0 0 Falling edge 0 0 1 1 Falling edge 1 0 0 1 Falling edge 1 0 1 1 Falling edge 0 1 0 0 Falling edge 0 1 1 0 Falling edge 1 1 0 1 Falling edge 1 1 1 0
[0036] The square wave signal generated by the JK trigger generally has a low driving capability and is not enough to drive the back-end application circuit. Therefore, a push-pull output circuit needs to be added as a signal conditioning circuit. The push-pull output circuit is composed of a PMOS and an NMOS. When the input of the push-pull output circuit is 1, the PMOS is turned on and the NMOS is turned off. The output of the push-pull output circuit is directly connected to VDD, which can provide a larger output current. When the input of the push-pull output circuit is 0, the PMOS is turned off and the NMOS is turned on. The output of the push-pull output circuit is directly connected to VSS, which can tolerate a larger sink current.
[0037] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A high-precision low-frequency clock generation circuit based on a frequency divider, characterized in that: include: Clock, as a clock source outputs a pulse signal; The frequency divider receives the pulse signal output by the clock, counts the number of pulses and converts them into binary signal output; The frequency selection circuit receives the binary signal output by the frequency divider, and selects the corresponding binary value. When the actual binary value is consistent with the preset binary value, the output level of the frequency selection circuit is reversed to obtain a square wave signal of the required frequency.
2. The high-precision low-frequency clock generation circuit based on a frequency divider according to claim 1, characterized in that: The pulse signal frequency f output by the clock is a MHz, where a is 1-10.
3. The high-precision low-frequency clock generation circuit based on a frequency divider according to claim 1, characterized in that: The frequency divider is a counter with at least ten bits, and a CLK input terminal of the counter receives a pulse signal of the clock.
4. The high-precision low-frequency clock generation circuit based on a frequency divider according to claim 1, characterized in that: The frequency selection circuit includes a logic gate and a JK flip-flop, the input end of the logic gate is connected to the output end of the frequency divider, and the output end of the logic gate generates a high level every time the counter accumulates n-1 pulses. When the next clock cycle arrives, the frequency divider is reset and the output generates a falling edge, so that a falling edge is generated for every n high-speed clock pulses; The J and K pins of the JK flip-flop are pulled up to a high level. Whenever a falling edge is detected at the input, the level of the output Q is flipped, thereby obtaining the required square wave signal.
5. The high-precision low-frequency clock generating circuit based on a frequency divider according to claim 1, characterized in that: The high-precision low-frequency clock generation circuit also includes a signal conditioning circuit, which receives the square wave signal output by the frequency selection circuit and amplifies the square wave signal circuit to drive the back-end application circuit.
6. The high-precision low-frequency clock generation circuit based on a frequency divider according to claim 5, characterized in that: The signal conditioning circuit is a push-pull output circuit, which includes a PMOS and an NMOS. When the input end of the push-pull circuit is 1, the PMOS is turned on, the NMOS is turned off, and the output end of the push-pull output circuit is connected to VDD; when the input end of the push-pull circuit is 0, the PMOS is turned off, the NMOS is turned on, and the output end of the push-pull output circuit is connected to VSS.