Output phase shifting unit for decimal frequency synthesizer

Abstract

The invention provides an output phase shifting unit for a decimal frequency synthesizer, and belongs to the technical field of integrated circuits. The invention relates to a decimal frequency division signal generator which comprises a resettable Delta-Sigma modulator and a counter, the resettable Delta-Sigma modulator is used for generating a control sequence for controlling decimal frequency division, the counter is used for controlling the reset moment of the resettable Delta-Sigma modulator and generating a reset signal, and the resettable Delta-Sigma modulator and the counter share the same clock signal. The method comprises the following steps of: resetting a resettable Delta-Sigma modulator at the beginning of phase adjustment, and meanwhile, loading a corresponding count value into a counter and starting counting; and when the counting value is full, a signal is generated, and the resettable Delta-Sigma modulator is reset again after receiving the signal, so that the output sequence of the Delta-Sigma modulator is translated, and the function of phase shift of the output signal under the condition that the frequency dividing ratio is not changed is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an output phase shift unit for a fractional frequency synthesizer. Background Art

[0002] With the booming development of the communication market, the requirements for wireless communication technology are also increasing. Personal wireless communication systems, wireless local area networks, satellite navigation systems, and satellite television have shown a trend of rapid growth. At the same time, wireless communication technology is also widely used in high-end technical fields such as space technology and electronic countermeasures. Among them, technologies such as digital phased array beamforming, high-speed serial-to-parallel conversion, and multi-channel clock systems have also been widely used. Among these technologies, the phase synchronization of multiple local oscillator signals is the key to determining their performance, so requirements are put forward for the phase shift function of the output signal of the frequency synthesizer.

[0003] Traditional fractional frequency synthesizer output phase shift units are mainly divided into two types:

[0004] One is analog, which relies on the delay characteristics of devices or circuits to shift the signal phase. However, this output phase shift unit has low accuracy, high power consumption, and is difficult to cover a 360° phase shift range;

[0005] The other is a digital method, which converts the digital control signal into an analog time delay by adding a digital-to-time converter. However, the design of this output phase shift unit is relatively complex and requires a compromise between accuracy and linearity. Summary of the invention

[0006] In view of this, the present invention proposes an output phase shift unit for a fractional frequency synthesizer. The present invention effectively achieves higher phase shift accuracy and good linearity of the fractional frequency synthesizer with only a small amount of additional circuit added.

[0007] The technical solution adopted by the present invention is:

[0008] An output phase shift unit for a fractional frequency synthesizer comprises a resettable Delta-Sigma modulator and a counter, wherein the resettable Delta-Sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset moment of the resettable Delta-Sigma modulator and generate a reset signal;

[0009] The count value is input to the input terminal of the counter, the overflow signal output terminal is connected to the reset port of the resettable Delta-Sigma modulator, and the clock signal port is connected to the clock signal;

[0010] The FRAC input port of the resettable Delta-Sigma modulator inputs the numerator value of the fractional frequency division ratio, the MOD port inputs the denominator value of the fractional frequency division ratio, the output port outputs the control sequence, the clock signal port is connected to the clock signal, the reset port is connected to the overflow signal output port of the counter, and the external reset signal is connected;

[0011] The resettable Delta-Sigma modulator and the counter share the same clock signal.

[0012] Further, the resettable Delta-Sigma modulator is a MASH 1-1-1 structure, including a Sigma-Delta modulator and a noise shaping circuit, and the Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series;

[0013] The carry signal of the third-stage first-order Sigma-Delta modulator is connected to the first input port of the first three-input accumulator. At the same time, the carry signal is inverted and connected to the second input port of the first three-input accumulator after passing through a delay device.

[0014] The carry signal of the second-stage first-order Sigma-Delta modulator is connected to the third input port of the first three-input accumulator after passing through a delay device;

[0015] The accumulated result output by the first three-input accumulator is connected to the first input terminal of the second three-input accumulator. Meanwhile, the accumulated result is connected to the second input terminal of the second three-input accumulator after being inverted through a delay device.

[0016] The carry signal of the first-stage first-order Sigma-Delta modulator is input into the third input terminal of the second three-input accumulator after passing through two delays;

[0017] The accumulated result output by the second three-input accumulator is the control sequence.

[0018] Further, when the fractional frequency division starts, the numerator value and the denominator value of the fractional frequency division ratio are input through the FRAC port and the MOD port of the resettable Delta-Sigma modulator;

[0019] At the beginning of phase adjustment, the resettable Delta-Sigma modulator is reset by an external reset signal, and at the same time, the counter is loaded with the corresponding count value through the input terminal and starts counting;

[0020] When the count value is full, the counter generates a signal and outputs it to the resettable Delta-Sigma modulator through the overflow signal output terminal. After receiving the signal, the resettable Delta-Sigma modulator resets the Delta-Sigma modulator again, thereby realizing the translation of the control sequence without changing the fractional division ratio.

[0021] Furthermore, the relationship between the shift phase of the control sequence and the counter count value is:

[0022]

[0023] in, is the shift phase, which is reflected by the phase difference of the control sequence; k0 is the count value input to the counter; FRAC is the fractional frequency numerator input to the FRAC port of the resettable Delta-Sigma modulator, and MOD is the fractional frequency denominator input to the MOD port of the resettable Delta-Sigma modulator.

[0024] The beneficial effects of the present invention are:

[0025] 1. The present invention resets the Delta-Sigma modulator twice successively at the beginning of phase shift and at the time when the count value is full, thereby effectively achieving higher phase shift accuracy and good linearity of the fractional frequency synthesizer with only a small amount of additional circuit added.

[0026] 2. The present invention uses a counter timing reset method to reset the Delta-Sigma modulator that is currently widely used, so that the new sequence is shifted compared to the original sequence, and the new sequence is the same as the original sequence, that is, the decimal value remains unchanged.

[0027] 3. The present invention can calculate the count value according to the relationship between the phase and the reset time and load it into the counter, reset the Delta-Sigma modulator and start counting at the start time of phase adjustment, and reset the Delta-Sigma modulator again after the count value is full, thereby accurately changing the output phase of the Delta-Sigma modulator.

[0028] 4. The present invention can be used for a signal generator, wherein the signal source can be provided by a memory, a hard disk, an operating system and a host computer software, and the user can set the required signal frequency and phase, and the corresponding data will be input into a frequency synthesizer chip to generate a signal of the required frequency and phase.

[0029] In summary, the present invention uses a resettable Delta-Sigma modulator to generate a sequence for controlling the frequency division ratio, and uses a counter to control the reset time to achieve sequence translation. The present invention achieves high phase shift accuracy and good linearity without changing the frequency division ratio, while avoiding the use of complex radio frequency circuits and digital time conversion circuits, effectively saving the cost of frequency synthesizer chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The diagram is a schematic diagram of the principle of an output phase shift unit for a fractional frequency synthesizer according to an embodiment of the present invention.

[0031] Figure 2 yes Figure 1 Schematic diagram of the resettable Delta-Sigma modulator.

[0032] Figure 3 It is a sequence translation flow chart in an embodiment of the present invention.

[0033] Figure 4 It is a flow chart of counting value calculation in an embodiment of the present invention.

[0034] FIG5(a) and FIG5(b) are comparison diagrams of sequence shift results in an embodiment of the present invention, wherein FIG5(a) is the output result of a third-order Sigma-Delta modulator, and FIG5(b) is the output result after sequence shift.

[0035] Figure 6 4 is a diagram showing the phase shift result of the output signal in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the technical scheme of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be pointed out that the implementation described is only a part of the embodiments of the present invention, not all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] An output phase shift unit for a fractional frequency synthesizer comprises a resettable Delta-Sigma modulator and a counter, wherein the resettable Delta-Sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset moment of the resettable Delta-Sigma modulator and generate a reset signal;

[0038] The count value is input to the input terminal of the counter, the overflow signal output terminal is connected to the reset port of the resettable Delta-Sigma modulator, and the clock signal port is connected to the clock signal;

[0039] The FRAC input port of the resettable Delta-Sigma modulator inputs the numerator value of the fractional frequency division ratio, the MOD port inputs the denominator value of the fractional frequency division ratio, the output port outputs the control sequence, the clock signal port is connected to the clock signal, the reset port is connected to the overflow signal output port of the counter, and the external reset signal is connected;

[0040] The resettable Delta-Sigma modulator and the counter share the same clock signal.

[0041] The resettable Delta-Sigma modulator is a MASH 1-1-1 structure, including a Sigma-Delta modulator and a noise shaping circuit. The Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series.

[0042] The carry signal of the third-stage first-order Sigma-Delta modulator is connected to the first input port of the first three-input accumulator. At the same time, the carry signal is inverted and connected to the second input port of the first three-input accumulator after passing through a delay device.

[0043] The carry signal of the second-stage first-order Sigma-Delta modulator is connected to the third input port of the first three-input accumulator after passing through a delay device;

[0044] The accumulated result output by the first three-input accumulator is connected to the first input terminal of the second three-input accumulator. Meanwhile, the accumulated result is connected to the second input terminal of the second three-input accumulator after being inverted through a delay device.

[0045] The carry signal of the first-stage first-order Sigma-Delta modulator is input into the third input terminal of the second three-input accumulator after passing through two delays;

[0046] The accumulated result output by the second three-input accumulator is the control sequence.

[0047] At the beginning of the fractional division, the numerator value and the denominator value of the fractional division ratio are input through the FRAC port and the MOD port of the resettable Delta-Sigma modulator.

[0048] The relationship between the moving phase of the control sequence translation and the counter count value is:

[0049]

[0050] in, is the shift phase, which is reflected by the phase difference of the control sequence; k0 is the count value input to the counter; FRAC is the fractional frequency numerator input to the FRAC port of the resettable Delta-Sigma modulator, and MOD is the fractional frequency denominator input to the MOD port of the resettable Delta-Sigma modulator.

[0051] The count value is calculated based on the above relationship. When the phase adjustment starts, the resettable Delta-Sigma modulator is reset by the external reset signal. At the same time, the counter is loaded with the calculated count value through the input terminal and starts counting.

[0052] When the count value is full, the counter generates a signal and outputs it to the resettable Delta-Sigma modulator through the overflow signal output terminal. After receiving the signal, the resettable Delta-Sigma modulator resets the Delta-Sigma modulator again, thereby realizing the translation of the control sequence without changing the fractional division ratio.

[0053] It can be seen that the output phase shift unit solves the problem of high-precision and high-linearity phase shift of the output signal by adding only a small amount of additional circuits.

[0054] Here is a more specific example:

[0055] Figure 1 This is the schematic diagram of the fractional frequency synthesizer output phase shift unit. Figure 1 The connection relationship between the counter 101 and the Delta-Sigma modulator 102 is mainly described. The counter 101 input terminal k0 inputs the count value, and the output terminal is connected to the reset terminal RST of the Delta-Sigma modulator 102. The Delta-Sigma modulator 102 input terminals MOD and FRAC input the fractional frequency division ratio, and the output terminal MC outputs the generated sequence. The two modules share a clock, which is usually connected to the feedback frequency division signal.

[0056] Figure 2 The schematic diagram of the Delta-Sigma modulator is shown in Figure 1. It uses a MASH 1-1-1 structure, including three first-order Sigma-Delta modulators and a noise shaping circuit. The three first-order Sigma-Delta modulators are connected in series, and the carry is input to the noise shaping circuit, which outputs the generated control sequence.

[0057] Figure 3 This is a sequence translation flowchart. The specific steps are as follows:

[0058] Step 301, when the phase shift starts, calculate and load the count value;

[0059] Step 302, resetting the Delta-Sigma modulator to start outputting the sequence from the beginning;

[0060] Step 303, the counter starts counting and outputs a signal when the count value is full;

[0061] Step 304, when the Delta-Sigma modulator receives the signal, it is immediately reset again, the sequence output remains unchanged and therefore the fractional frequency division ratio remains unchanged, and the new sequence is offset relative to the original sequence, thereby realizing the fractional frequency synthesizer output phase shift function.

[0062] Figure 4 This is the count value calculation flow chart, the specific steps are as follows:

[0063] Step 401, reading the phase value to be moved;

[0064] Step 402, read the current fractional frequency value;

[0065] Step 403, according to the formula Calculate the required count value, where is the phase value of the shift, k0 is the count value, FRAC is the fractional frequency numerator, and MOD is the fractional frequency denominator;

[0066] Step 404, loading the obtained count value into the counter.

[0067] Figure 5(a) and Figure 5(b) compare the results of sequence shifting. Figure 5(a) shows the output result of the normal third-order Sigma-Delta modulator, and Figure 5(b) shows the output result after sequence shifting. As can be seen from the figure, after the second reset, the output sequence of the Sigma-Delta modulator is equivalent to being shifted, which can realize the function of shifting the output result of the fractional frequency synthesizer.

[0068] Figure 6 The output signal phase shift result diagram is shown in Figure 2. The original phase signal and the phase-shifted signal are compared. As can be seen from the result diagram, the two signals differ by 135°. This method realizes the output phase shift function of the fractional frequency synthesizer.

[0069] In summary, the present invention obtains the count value according to the formula, uses the counter to control the reset time of the Delta-Sigma modulator, resets the Delta-Sigma modulator twice at the beginning and end of counting, and realizes the output sequence shift of the Delta-Sigma modulator.

[0070] The present invention can achieve a 360° phase shift range without changing the fractional frequency division ratio, has good phase shift accuracy and linearity, and reduces the impact on loop performance. The present invention is not affected by process, voltage, and temperature, and only adds a small amount of additional circuits and power consumption while achieving higher phase shift accuracy, effectively saving the cost of the frequency synthesizer chip.

Claims

1. An output phase shift unit for a fractional frequency synthesizer, characterized in that: It includes a resettable Delta-Sigma modulator and a counter, wherein the resettable Delta-Sigma modulator is used to generate a control sequence for controlling fractional frequency division, and the counter is used to control the reset time of the resettable Delta-Sigma modulator and generate a reset signal; The count value is input to the input terminal of the counter, the overflow signal output terminal is connected to the reset port of the resettable Delta-Sigma modulator, and the clock signal port is connected to the clock signal; The FRAC input port of the resettable Delta-Sigma modulator inputs the numerator value of the fractional frequency division ratio, the MOD port inputs the denominator value of the fractional frequency division ratio, the output port outputs the control sequence, the clock signal port is connected to the clock signal, the reset port is connected to the overflow signal output port of the counter, and the external reset signal is connected; The resettable Delta-Sigma modulator and the counter share the same clock signal.

2. The output phase shift unit for a fractional frequency synthesizer according to claim 1, characterized in that: The resettable Delta-Sigma modulator is a MASH 1-1-1 structure, including a Sigma-Delta modulator and a noise shaping circuit, wherein the Sigma-Delta modulator is composed of three first-order Sigma-Delta modulators connected in series; The carry signal of the third-stage first-order Sigma-Delta modulator is connected to the first input port of the first three-input accumulator. At the same time, the carry signal is inverted and connected to the second input port of the first three-input accumulator after passing through a delay device. The carry signal of the second-stage first-order Sigma-Delta modulator is connected to the third input port of the first three-input accumulator after passing through a delay device; The accumulated result output by the first three-input accumulator is connected to the first input terminal of the second three-input accumulator. Meanwhile, the accumulated result is connected to the second input terminal of the second three-input accumulator after being inverted through a delay device. The carry signal of the first-stage first-order Sigma-Delta modulator is input into the third input terminal of the second three-input accumulator after passing through two delays; The accumulated result output by the second three-input accumulator is the control sequence.

3. The output phase shift unit for a fractional frequency synthesizer according to claim 1, characterized in that: At the beginning of fractional frequency division, the numerator value and denominator value of the fractional frequency division ratio are input through the FRAC port and MOD port of the resettable Delta-Sigma modulator; At the beginning of phase adjustment, the resettable Delta-Sigma modulator is reset by an external reset signal, and at the same time, the counter is loaded with the corresponding count value through the input terminal and starts counting; When the count value is full, the counter generates a signal and outputs it to the resettable Delta-Sigma modulator through the overflow signal output terminal. After receiving the signal, the resettable Delta-Sigma modulator resets the Delta-Sigma modulator again, thereby realizing the translation of the control sequence without changing the fractional division ratio.

4. The output phase shift unit for a fractional frequency synthesizer according to claim 1, characterized in that: The relationship between the moving phase of the control sequence translation and the counter count value is: in, It is the shift phase, which is reflected by the phase difference of the control sequence; k0 is the count value input to the counter; FRAC is the fractional frequency numerator input to the FRAC port of the resettable Delta-Sigma modulator, and MOD is the fractional frequency denominator input to the MOD port of the resettable Delta-Sigma modulator.

Images