Event-driven analog-to-digital converter

Abstract

The invention discloses an event-driven analog-to-digital converter, and the converter comprises a signal folding module which is used for folding an input signal and outputting a folded signal; the first comparison control circuit is used for comparing the folded signal with a threshold common-mode voltage, generating a first comparison result and generating a signal direction conversion event pulse according to the first comparison result; the multi-level comparison module is connected with the signal folding module and the first comparison control circuit and is used for selecting the upper threshold voltage or the lower threshold voltage according to the first comparison result and comparing the upper threshold voltage or the lower threshold voltage with the folding signal to generate a second comparison result; the second logic control circuit is used for generating a sampling mark event pulse according to the second comparison result; the folding logic control circuit is connected with the first comparison control circuit and the second logic control circuit and is used for generating a sampling event pulse and feeding back the sampling event pulse to the signal folding module; and the lifting counter module is connected with the first comparison control circuit and the second logic control circuit and is used for generating an amplitude code.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an event-driven analog-to-digital converter. Background Art

[0002] In recent years, MEMS gas sensors have been widely used in industrial production, environmental testing, health care and other fields. In order to convert the electrical data of the gas sensor into a digital signal that is easy to process by the digital signal processing system, the analog-to-digital converter is applied to the gas sensor system. When the gas sensor senses abnormal gas, the output voltage of the gas sensor will change and output a small analog signal. This change is collected by the analog-to-digital converter and converted into a digital signal with sufficient speed and accuracy. Finally, it is sent to the back-end processing part of the sensor system to identify the type of odor and predict the corresponding concentration.

[0003] In the prior art, two traditional Nyquist sampling analog-to-digital converters, namely, successive approximation analog-to-digital converters and Σ-Δ (Sigma-Delta) analog-to-digital converters, are usually used to sample analog signals at a fixed sampling frequency, and then perform analog-to-digital conversion processing. However, unlike the continuously changing output signals of other sensors, the output information of gas sensors is relatively sparse, and it maintains a constant state most of the time. For example, in the entire detection cycle, the output signal of the gas sensor has basically no amplitude change for more than 95% of the time, and only in some very short time windows will the sensor output a high-frequency, large-amplitude changing signal. This signal characteristic causes a large amount of power consumption of the analog-to-digital converter using uniform sampling to be wasted on voltage nodes without valid information, resulting in low energy efficiency of the converter, and signals that change in a very short time may not be effectively monitored. Summary of the invention

[0004] The present invention provides an event-driven analog-to-digital converter to solve the technical problems that a large amount of power consumption of the existing analog-to-digital converter is wasted on voltage nodes without valid information during sampling, resulting in low energy efficiency of the converter and signals that change in a very short time may not be effectively monitored.

[0005] In order to solve the above technical problems, the present invention provides an event-driven analog-to-digital converter, comprising:

[0006] A signal folding module, including a switched capacitor circuit, for folding an input signal and outputting a folded signal;

[0007] a first comparison control circuit connected to the output end of the signal folding module, configured to compare the folding signal with a threshold common mode voltage to generate a first comparison result, and generate a signal direction conversion event pulse according to the first comparison result;

[0008] a multi-level comparison module, connected to the output end of the signal folding module and the first comparison control circuit, and configured to select an upper threshold voltage or a lower threshold voltage to compare with the folding signal according to the first comparison result to generate a second comparison result;

[0009] A second logic control circuit is connected to the output end of the multi-level comparison module and is used to generate a sampling mark event pulse according to the second comparison result;

[0010] a folding logic control circuit, connected to the first comparison control circuit and the second logic control circuit, configured to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse, and feed the sampling event pulse back to the signal folding module;

[0011] an up-down counter module, connected to the first comparison control circuit, and also connected to the first comparison control circuit and the second logic control circuit through an OR gate, for generating an amplitude code according to the signal direction conversion event pulse and the sampling mark event pulse;

[0012] The threshold common mode voltage is an average of the upper threshold voltage and the lower threshold voltage.

[0013] Compared with the prior art, the event-driven analog-to-digital converter of the present invention utilizes a signal folding module to fold the input signal, the first comparison control circuit compares the folding signal with the threshold common mode voltage to generate a first comparison result, and generates a signal direction conversion event pulse according to the first comparison result, the multi-level comparison module selects an upper threshold voltage or a lower threshold voltage according to the first comparison result to compare with the folding signal to generate a second comparison result, and then utilizes a second logic control circuit to generate a sampling mark event pulse according to the second comparison result, and utilizes a folding logic control circuit to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse, and the sampling event pulse is fed back to The signal folding module performs signal folding according to the sampling event pulse, and generates an amplitude code according to the sampling mark event pulse and the signal direction conversion event pulse through the up-down counter module; it can be seen that the event-driven analog-to-digital converter of the present invention samples only when the amplitude of the input signal changes significantly, which greatly reduces the energy loss of useless sampling points to the overall system, and when the input signal changes very quickly, the sampling rate of the event-driven analog-to-digital converter of the present invention will be adaptively increased, and when the input signal does not change, the sampling rate will be adaptively reduced, that is, the sampling rate can be automatically adjusted according to the input signal change rate, thereby greatly improving the energy efficiency ratio of the analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0015] Figure 1 It is a schematic circuit block diagram of an event-driven analog-to-digital converter in one embodiment of the present invention.

[0016] Figure 2 yes Figure 1 The specific circuit diagram of the first logic control circuit and the second logic control circuit in the event-driven analog-to-digital converter is shown.

[0017] Figure 3 yes Figure 1 The specific circuit diagram of the multiplexer in the event-driven analog-to-digital converter is shown.

[0018] Figure 4 yes Figure 1 The specific circuit diagram of the folding logic control circuit in the event-driven analog-to-digital converter is shown.

[0019] Figure 5 yes Figure 1 The specific circuit diagram of the switched capacitor circuit in the event-driven analog-to-digital converter is shown.

[0020] Figure 6 yes Figure 1 The specific circuit diagram of the up-down counter module in the event-driven analog-to-digital converter is shown.

[0021] Figure 7 yes Figure 6 The specific circuit diagram of the up-down counter in the up-down counter module shown.

[0022] Figure 8 It is a specific circuit diagram of a pulse generator in an event-driven analog-to-digital converter of the present invention.

[0023] Fig. 9 It is a waveform diagram of the event-driven analog-to-digital converter of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] Reference Figures 1 to 8 , Figures 1 to 8 A specific embodiment of the event-driven analog-to-digital converter of the present invention is shown. In the embodiment shown in the accompanying drawings, the event-driven analog-to-digital converter includes a signal folding module 10, a first comparison control circuit 20, a multi-level comparison module 30, a second logic control circuit 40, a folding logic control circuit 50 and an up-down counter module 60, wherein the signal folding module 10 includes a switch capacitor circuit for folding the input signal VIN and outputting a folding signal VON; the first comparison control circuit 20 is connected to the output end of the signal folding module 10, and is used to compare the folding signal VON with the threshold common mode voltage VM to generate a first comparison result, and generate a signal direction conversion event pulse according to the first comparison result; the multi-level comparison module 30 is connected to the output end of the signal folding module 10 and the first comparison control circuit 20, and is used to select an upper threshold voltage VH or a lower threshold voltage VL to be connected to the folding signal according to the first comparison result. VON is compared to generate a second comparison result; the second logic control circuit 40 is connected to the output end of the multi-level comparison module 30, and is used to generate a sampling mark event pulse CC according to the second comparison result; the folding logic control circuit 50 is connected to the first comparison control circuit 20 and the second logic control circuit 40, and is used to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse CC, and feed the sampling event pulse back to the signal folding module 10; the up-down counter module 60 is connected to the first comparison control circuit 20, and is also connected to the first comparison control circuit 20 and the second logic control circuit 40 through an OR gate OR1, and is used to generate an amplitude code according to the sampling mark event pulse CC and the signal direction conversion event pulse; wherein the threshold common mode voltage VM is the average of the upper threshold voltage VH and the lower threshold voltage VL.

[0026] Based on the above design, the first comparison control circuit 20 and the multi-level comparison module 30 and the second logic control circuit 40 of the present invention are used to monitor the change of the input signal VIN and determine whether a sampling event occurs. The up-down counter module 60 of the present invention can generate an amplitude code according to the sampling mark event pulse CC and the signal direction conversion event pulse to quantify the amplitude of the sampling point. The signal folding module 10 can perform signal folding according to the sampling event pulse, and only sample when the amplitude of the input signal VIN changes significantly, which greatly reduces the energy loss of useless sampling points to the overall system. When the input signal VIN changes very quickly, the sampling rate of the event-driven analog-to-digital converter of the present invention will be adaptively increased, and when the input signal VIN does not change, the sampling rate will be adaptively reduced, that is, the sampling rate can be automatically adjusted according to the change rate of the input signal VIN, thereby greatly improving the energy efficiency ratio of the analog-to-digital converter.

[0027] Continue to refer to Figure 1 and Figure 2 In some embodiments, the first comparison control circuit 20 includes a first comparison module and a first logic control circuit 22, the first comparison module includes a first comparator U21, the non-inverting input terminal of the first comparator U21 is connected to the output terminal of the signal folding module 10, the inverting input terminal of the first comparator U21 receives the threshold common mode voltage VM, and is used to compare the folding signal VON with the threshold common mode voltage VM to generate a first comparison result; the first logic control circuit 22 is connected to the output terminal of the first comparator U21, and includes a first NOT gate NOT1 and a second NOT gate NOT2, the input terminal of the first NOT gate NOT1 is connected to the output terminal of the first comparator U21, and the output terminal of the first NOT gate NOT1 is connected to the output terminal of the first comparator U21 through a pulse generator. The generator is connected to an input end of the OR gate OR1, that is, the output signal UDP is sent to the OR gate OR1, and the OR gate OR1 receives UDP and CC and outputs the signal CHANGE, and the input end of the second NOT gate NOT2 is connected to the output end of the first NOT gate NOT1, and the output end of the second NOT gate NOT2 and the output end of the first NOT gate NOT1 are respectively connected to the multi-level comparison module 30 through a buffer, and the UD signal (used to indicate whether the folding signal VON output by the signal folding module 10 is above or below the threshold common mode voltage VM) and the UDB signal are respectively output to the multi-level comparison module 30, and the output end of the second NOT gate NOT2 is also connected to the up-down counter module 60, that is, the UD signal is output to the up-down counter module 60. It can be understood that in this embodiment, the sampling mark event pulse includes the UD signal, the UDB signal and the UDP signal, and the three signals are independent of each other.

[0028] Combination Figure 3 In some embodiments, the multi-level comparison module 30 includes a multiplexer MUX and a second comparator U32, wherein the enable control terminal of the multiplexer MUX is connected to the output terminal of the first comparison control circuit 20, the output terminal of the signal folding module 10, the upper threshold voltage VH or the lower threshold voltage VL are respectively connected to an input terminal of the multiplexer MUX, and the two output terminals of the multiplexer MUX are respectively connected to the non-inverting input terminal and the inverting input terminal of the second comparator U32, and the output terminal of the second comparator U32 serves as the output terminal of the multi-level comparison module 30 to output the second comparison result. Specifically, as Figure 3As shown, the multiplexer MUX includes switch tubes S7, S8, S9 and S10, the control ends of the switch tubes S7 and S9 are connected to the output end of the first NOT gate NOT1, the control ends of the switch tubes S8 and S10 are connected to the output end of the second NOT gate NOT2, and the input ends of the switch tubes S8 and S9 are connected to the output end of the signal folding module 10, the input ends of the switch tubes S7 and S10 are respectively connected to the lower threshold voltage VL and the upper threshold voltage VH, the output ends of the switch tubes S7 and S9 are connected to the inverting input end of the second comparator U32, and the output ends of the switch tubes S8 and S10 are connected to the non-inverting input end of the second comparator U32. Based on the above design, the multiplexer MUX sends the required signal to both ends of the second comparator U32. When the output signal (RCO signal) of the first comparator U21 is at a high level, it indicates that the signal VON is higher than VM. At this time, the multiplexer MUX sends VH to the non-inverting input terminal of the second comparator U32 and sends VON to the inverting input terminal of the second comparator U32. When the RCO signal is at a low level, it indicates that the signal VON is lower than VM. At this time, the multiplexer MUX sends VON to the non-inverting input terminal of the second comparator U32 and sends VL to the inverting input terminal of the second comparator U32. Overall, since VON is between VH and VL most of the time, the second comparator U32 outputs logic 1 most of the time, and only when VON crosses VH or VL will it briefly output logic 0.

[0029] Continue to refer to Figure 2 In some embodiments, the second logic control circuit 40 includes a CMOS transmission gate TG1, an NMOS tube S0, a T trigger TFF1, a pulse generator and a first trigger. The input end of the CMOS transmission gate TG1 is connected to the output end of the multi-level comparison module 30. The output end of the CMOS transmission gate TG1 and the drain of the NMOS tube S0 are connected to the clock input pin of the T trigger TFF1 through a NOT gate NOT0. The source of the NMOS tube S0 is grounded. The inverting output pin of the T trigger TFF1 is connected to the pulse generator. The output end of the pulse generator serves as the second logic control circuit 40. The output end outputs the sampling mark event pulse CC and is connected to the input pin of the first trigger, the inverting output pin of the first trigger is connected to the lower control end of the CMOS transmission gate TG1, and the positive output pin of the first trigger is connected to the upper control end of the CMOS transmission gate TG1 and the gate of the NMOS tube S0, so as to close the NMOS tube S0 and open the CMOS transmission gate TG1 when the sampling mark event pulse CC is at a low level, and open the NMOS tube S0 and close the CMOS transmission gate TG1 when the sampling mark event pulse CC is at a high level, thereby latching the T trigger TFF1.

[0030] Specifically, in this embodiment, the first comparator U21 and the second comparator U32 preferably use hysteresis comparators, the first trigger is preferably an SR trigger SR1, and the second logic control circuit 40 also includes a NAND gate NAND0, the output end of the OR gate OR1 is connected to an input end of the NAND gate NAND0 after passing through a delay unit and a seventh NOT gate NOT7 in sequence, the other input end of the NAND gate NAND0 receives a reset signal, and its output end is connected to the R input pin of the SR trigger SR1, and the S input pin of the SR trigger SR1 is connected to the output end of the pulse generator. Figure 8 As shown, the pulse generators used in this embodiment are all composed of an XOR gate XOR and a delay unit.

[0031] Continue to refer to Figure 1 and Figure 4 In some embodiments, the folding logic control circuit 50 includes a D flip-flop D1, a first NAND gate NAND1, a second NAND gate NAND2, a third NOT gate NOT3, a fourth NOT gate NOT4, a first AND gate AND1, a second AND gate AND2, a third AND gate AND3 and a fourth AND gate AND4, wherein a clock input pin of the D flip-flop D1 is connected to the output end of the second logic control circuit 40, a D input pin and a QB output pin thereof are connected to an input pin of the first NAND gate NAND1, a Q output pin of the D flip-flop D1 is connected to an input pin of the second NAND gate NAND2, another input pin of the second NAND gate NAND2 and the first NAND gate NAND1 are respectively connected to the output ends of the first NAND gate NAND1 and the second NAND gate NAND2 through a delay unit, and are respectively connected to the third NOT gate NOT3 and the fourth NOT gate NOT4. The output end of the third NOT gate NOT3 is connected to an input end of the first AND gate AND1 and the second AND gate AND2 respectively, the output end of the fourth NOT gate NOT4 is connected to an input end of the third AND gate AND3 and the fourth AND gate AND4 respectively, the other input ends of the first AND gate AND1 and the third AND gate AND3 are connected to the output end of the second NOT gate NOT2, the other input ends of the second AND gate AND2 and the fourth AND gate AND4 are connected to the output end of the first NOT gate NOT1, and the output ends of the first AND gate AND1, the second AND gate AND2, the third AND gate AND3 and the fourth AND gate AND4 are respectively connected to the control end of a switch tube of the switch capacitor circuit, so that the switch capacitor circuit folds the input signal VIN according to the sampling event pulses from the first AND gate AND1, the second AND gate AND2, the third AND gate AND3 and the fourth AND gate AND4.

[0032] Combination Figure 5In some embodiments, the switch capacitor circuit includes a first capacitor string C1, a second capacitor string C2, a third capacitor string C3, a first switch tube S1, a second switch tube S2, a third switch tube S3, a fourth switch tube S4, a fifth switch tube S5 and a sixth switch tube S6, wherein the control ends of the first switch tube S1, the second switch tube S2, the third switch tube S3 and the fourth switch tube S4 are respectively connected to the output ends of the second AND gate AND2, the first AND gate AND1, the fourth AND gate AND4 and the third AND gate AND3, the input ends of the first switch tube S1 and the third switch tube S3 both receive the upper threshold voltage VH, and the input ends of the second switch tube S2 and the fourth switch tube S4 both receive the The lower threshold voltage VL is set, and the output ends of the first switch tube S1 and the second switch tube S2 are both connected to the midpoint of the third capacitor string C3, the output ends of the third switch tube S3 and the fourth switch tube S4 are both connected to the midpoint of the first capacitor string C1, the midpoint of the second capacitor string C2 is connected to the midpoints of the first capacitor string C1 and the third capacitor string C3 through the fifth switch tube S5 and the sixth switch tube S6, and the control ends of the fifth switch tube S5 and the sixth switch tube S6 are respectively connected to the output ends of the third NOT gate NOT3 and the fourth NOT gate NOT4, and both ends of the first capacitor string C1, the second capacitor string C2, and the third capacitor string C3 are all connected between the input signal VIN and the ground. In this embodiment, the second capacitor string C2 is responsible for tracking the input signal VIN, and the adjacent first capacitor string C1 and third capacitor string C3 are responsible for voltage shifting of the input signal VIN, with a shift size of 1LSB, that is, a voltage shift of 1LSB is performed on the second capacitor string C2. When the VIN signal is between VM and VH, the upper plate voltage of the capacitor at the bottom of the capacitor string used for the shift operation will be pre-charged by VL, and when the VIN signal is between VM and VL, the upper plate voltage of the capacitor at the bottom of the capacitor string used for the shift operation will be pre-charged by VH.

[0033] Based on the above design, when the input signal VIN exceeds VH or VL, the second comparator U32 will be triggered to make the second logic control circuit 40 generate a CC pulse. When the input signal VIN is higher than VM, the first comparator U21 will output a logic level of 1. When the input signal VIN is lower than VM, the first comparator U21 will output a logic level of 0. Specifically, when the second logic control circuit 40 generates a CC pulse, if UD is 1, indicating that the input signal VIN has exceeded VH upward, then the signal folding module 10 will adjust the voltage of the input signal VIN downward by 1LSB. If UD is 0, indicating that the input signal VIN has exceeded VL downward, then the signal folding module 10 will adjust the voltage of the input signal VIN upward by 1LSB. The signal folding module 10 will fold the input signal VIN into a window with a width of 2LSB.

[0034] Reference Fig. 9 , Fig. 9 Schematic diagram of waveform of event-driven analog-to-digital converter of the present invention. When the folding logic control circuit 50 starts working, RESET resets the D flip-flop D1, Q=0, QB=1. Then P1=1, P2=0, P2H=0, P2L=0; when UD=1, P1H=0, P1L=1; (the third capacitor string C3 is pre-charged by VL), and when UD=0, P1H=1, P1L=0 (the third capacitor string C3 is pre-charged by VH).

[0035] When UD=1 and a CC pulse arrives, the D flip-flop D1 is connected in the manner of Q(n+1)=QB(n), so the new Q=1, QB=0, causing P1 to become 0 first and then P2 to become 1. At this time, P1H=0, P1L=0, P2H=0, P2L=1. That is, when UD=1 and a CC pulse arrives, it indicates that VON has passed VH and needs to be folded down (shifted down). The third capacitor string C3 was previously pre-charged by VL, so P1, P1H, and P1L are opened, and P2 is closed, so that the input signal VIN goes down 1LSB. At the same time, because UD is still 1 at this time and VON is still in the upper LSB, P2L=1 is required, and VL is used to pre-charge the first capacitor string C1 to prepare for the next shift down). It should be noted here that P1H and P1L are both controlled by P1. When P1 becomes 0 first, it will inevitably cause P1H and P1L to become 0. It is necessary to ensure that this operation is faster than the closure of P2 (increasing the delay of the delay unit), otherwise VL will be directly connected to VON.

[0036] When UD=1, and the next CC pulse arrives, the D flip-flop D1 is connected in the way of Q(n+1)=QB(n), so the new Q=0, QB=1, causing P2 to change to 0 first, and then P1 to change to 1. At this time, P1H=0, P1L=1, P2H=0, P2L=0. That is, when UD=1, and the next CC pulse arrives, it indicates that VON has passed VH and needs to shift down. At this time, the first capacitor string C1 has been pre-charged by VL, so P2, P2H, P2L are opened, and P1 is closed, so that the input signal VIN goes down 1LSB. At the same time, because UD is still 1 at this time and VON is still in the upper LSB, P1L=1 is required, and VL is used to pre-charge the third capacitor string C3 to prepare for the next shift down. It should be noted here that the delay of the delay unit should be reasonably designed so that P2H=0, P2L=0 are fully set before P1=1.

[0037] When no CC pulse is generated, that is, no crossover event of VON with VH and VL occurs, but UD changes from 1 to 0, at this time, since the previous D flip-flop D1 state will not be updated by CC, P1 = 1, P2 = 0, resulting in P1H = 1, P1L = 0, P2H = 0, P2L = 0. (At this time, UD changes from 1 to 0, that is, VON is going down, so at this time, the third capacitor string C3 pre-charged with VL should be switched to pre-charged with VH).

[0038] When UD=0 and a CC pulse arrives, it means that VON has hit VL. Since the connection of D flip-flop D1 is Q(n+1)=QB(n), the new Q=1, QB=0, causing P1 to change to 0 first and P2 to change to 1. At this time, P1H=0, P1L=0, P2H=1, P2L=0. That is, when UD=0 and a CC pulse arrives, it means that VON has crossed VL and needs to be folded up (shift up). The third capacitor was pre-charged by VH before, so P1, P1H, P1L are opened, and P2 is closed, so that the input signal VIN goes up 1LSB. At the same time, because UD is still 0 at this time and VON is in the lower LSB, P2H=1 is required, and VH is used to pre-charge the first capacitor string C1 to prepare for the next shiftup).

[0039] When UD=0, and the next CC pulse arrives, it means that VON has hit VL. Since the connection of D flip-flop D1 is Q(n+1)=QB(n), the new Q=0, QB=1, causing P2 to change to 0 first, and then P1 to change to 1. At this time, P1H=1, P1L=0, P2H=0, P2L=0. That is, when UD=0, and a CC pulse arrives, it means that VON has crossed VL and needs to shift up. The first capacitor string C1 was pre-charged by VH before, so P2, P2H, P2L are opened, and P1 is closed, so that the input signal VIN goes up 1LSB. At the same time, because UD is still 0 at this time and VON is in the lower LSB, P1H=1 is required, and VH is used to pre-charge the right branch to prepare for the next shiftup.

[0040] Combination Figure 6In some embodiments, the up-down counter module 60 includes an up-down counter COUNTER and a logic gate circuit, wherein the logic gate circuit includes a fifth NOT gate NOT5, a sixth NOT gate NOT6, a multi-input NOR gate NOR1, a multi-input AND gate AND0, a third NAND gate NAND3, a fourth NAND gate NAND4, a fifth NAND gate NAND5 and a first NOR gate NOR2, the input ends of the fifth NOT gate NOT5 and the sixth NOT gate NOT6 are respectively connected to the output ends of the second NOT gate NOT2 and the OR gate OR1, the two input ends of the third NAND gate NAND3 are respectively connected to the output ends of the second NOT gate NOT2 and the multi-input AND gate AND0, and the two input ends of the fourth NAND gate NAND4 are respectively connected to the fifth NOT gate NOT5 And the output end of the multi-input NAND gate NOR1, the output ends of the third NAND gate NAND3 and the fourth NAND gate NAND4 are respectively connected to the two input ends of the fifth NAND gate NAND5, the output end of the fifth NAND gate NAND5 and the output end of the sixth NOT gate NOT6 are respectively connected to the two input ends of the first NOR gate NOR2, the output end of the first NOR gate NOR2 and the output end of the second NOT gate NOT2 are respectively connected to the CHANGE counting pin and the UD signal input pin of the up-down counter COUNTER, the output pin of the up-down counter COUNTER serves as the output end of the up-down counter module 60, for outputting the amplitude code, and is connected to the input ends of the multi-input NOR gate NOR1 and the multi-input AND gate AND0.

[0041] In this embodiment, the up / down counter COUNTER is a 6-bit up / down counter, the multi-input NOR gate NOR1 is a 6-bit input NOR gate, the multi-input AND gate AND0 is a 6-bit input AND gate, and the register is a 6-bit DFF register. Figure 7 As shown, the 6-bit up-down counter COUNTER includes 6 TFFs, 5 binary selectors C and logic gates. The outputs of the 6 TFFs constitute the 6-bit data of the 6-bit up-down counter COUNTER. The T signal of the first-level TFF is set to 1, and the determination of the T signals of the next five levels of TFFs depends on the status of the outputs of the previous levels.

[0042] It can be understood that the six-bit input NOR gate NOR1 and the six-bit input AND gate AND0 can monitor under-overflow and over-overflow, then, when the up-down counter COUNTER is full, that is, all 6-bit outputs are 1, O_F=1, when the up-down counter COUNTER is empty, that is, all 6-bit outputs are 0, U_F=1; when O_F=1 and UD=1 (indicating that the input signal VIN is still rising), the CHANGE pin of the 6-bit up-down counter COUNTER constituted by TFF is set to 0, and no changes occur (that is, no longer counting up); when U_F=1 and UD_B=1 (UD=0, indicating that the input signal VIN is still falling), the CHANGE pin of the 6-bit up-down counter COUNTER constituted by TFF is set to 0, and no changes occur (that is, no longer counting down).

[0043] When the up / down counter COUNTER starts working, it is reset first, that is, the RST input terminals of the 6 TFFs are all set to 0. At this time, the Q output of each TFF is 0 and the QB output is 1. Table 1 shows the output of each TFF in the 6-bit up / down counter COUNTER under 14 consecutive CHANGE signals. The UD signal is 1 at the first 7 CHANGE signal rising edges, and the UD signal is 0 at the next seven CHANGE signal rising edges. There are only 7 CHANGE signal rising edges in a specific signal direction. In this example, only the first 3 bits of the up / down counter COUNTER are observed. It can be understood that the flip of TFF depends on the T generated by the arrival of the last CHANGE signal rising edge, rather than the T generated after the arrival of the current CHANGE signal rising edge.

[0044]

[0045]

[0046] Table 1

[0047] As can be seen from the above table, after the up-down counter COUNTER is reset, each bit of the output will be set to 0. At the rising edge of the first 7 CHANGE signals when UD=1, the first three bits of data gradually change from 000 to 111, and at the rising edge of the last 7 CHANGE signals when UD=0, the first three bits of data gradually change from 111 to 000, that is, when the rising edge of the CHANGE signal arrives, the up-down counter COUNTER will count up or down successively according to the instructions of UD, that is, the up-down counter COUNTER is changed by the direction of the UD signal.

[0048] Furthermore, in order to uniformly output the 6-bit data when the output signal of the up-down counter COUNTER is completely stable, the up-down counter module 60 also includes a 6-bit register DFF1, the input pin of the register DFF1 is connected to the output pin of the up-down counter COUNTER, the output pin of the register DFF1 serves as the output end of the up-down counter module 60, and is used to output the amplitude code, and the enable pin of the register DFF1 is connected to the output end of the OR gate OR1 through a delay unit, and the CHANGE signal is output to the enable pin of the register DFF1 through the delay unit as the clock trigger signal EN of the 6-bit DFF register DFF1 to ensure that the output of the 6-bit TFF can be completely stable within the delay time, and the CHANGE signal is connected to the NAND gate NAND0 in the second logic control circuit 40 after passing through the delay unit and the seventh NOT gate NOT7, so that the ACK signal can be output for new bit sampling monitoring after the local data processing of the second logic control circuit 40 is completed.

[0049] It can be understood that the specific working process of the first logic control circuit 22 and the second logic control circuit 40 of the present invention is as follows: RESET is set to 0, the T trigger TFF1 outputs: Q=0, QB=1, and when the time is sufficient, CC3 becomes 0. Since RESET=0, rdy=1 is caused. In summary, S=0, R=1 of the SR trigger SR1, so hld=0, hldb=1, causing the NMOS tube S0 (high level conduction) to be turned off, and the CMOS transmission gate TG1 to be turned on, and the CCO signal (the output signal of the second comparator U32) can be transmitted. At the same time, the T end of TFF1 is set to 1, indicating that when the rising edge of CLK changes, the TFF1 output will flip, when VON is between VH and VL, CCO outputs 1, and when VON crosses VH or VL, the CCO output becomes 0.

[0050] After the reset is completed, RESET is set to 1. If ACK=1 (ACK can be indicated as the flag bit indicating that the current data output by the up-down counter COUNTER is completely stable), rdy=0. For TFF1, the circuit reset is completed and it can start working normally. For SR1, rdy becomes 0, which will not affect its output result, so it will not affect the working status of TG1 and S0 tubes.

[0051] When the CCO signal flips from 1 to 0, the TG1 output flips from 1 to 0. After passing through the NOT gate NOT0, the input of the clock input pin of TFF1 flips from 0 to 1, so the output Q of TFF1 flips from 0 to 1, and QB flips from 1 to 0. After the flip signal of QB output passes through the pulse generator, CC3 will have a short high level. On the one hand, this high level is output as the CC signal through the buffer buffer. On the other hand, the short high level of CC3 will make the S output of SR1 change to 1 briefly, causing the output Q of SR1 to change to 1 and QB to change to 0, that is, hld=1, hldb=0 (and this state After CC3 becomes 0, the output of SSR1 will not change), causing TG1 to be turned off, and the output CCO of the second comparator U32 cannot affect the subsequent circuit of TG1. At the same time, the input of the NOT gate NOT0 is pulled to 0. At this time, the clock input pin of TFF1 is equivalent to being locked. Until SR1's R is set to 1 again (for example, the RESET signal of the NAND gate NAND0 input pin is set to 0, or the ACK signal is received (indicating that the previous state of the entire ADC has been completely processed and is ready to accept new inputs)), the clock input pin of TFF1 will accept a new flip signal.

[0052] In summary, the event-driven analog-to-digital converter of the present invention utilizes a signal folding module to fold the input signal, the first comparison control circuit compares the folding signal with the threshold common-mode voltage to generate a first comparison result, and generates a signal direction conversion event pulse according to the first comparison result, the multi-level comparison module selects an upper threshold voltage or a lower threshold voltage according to the first comparison result to compare with the folding signal to generate a second comparison result, and then utilizes a second logic control circuit to generate a sampling mark event pulse according to the second comparison result, and utilizes a folding logic control circuit to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse, and feeds the sampling event pulse back to the signal The signal folding module is provided so that the signal folding module performs signal folding according to the sampling event pulse, and generates an amplitude code according to the sampling mark event pulse and the signal direction conversion event pulse through the up-down counter module; it can be seen that the event-driven analog-to-digital converter of the present invention performs sampling only when the amplitude of the input signal changes significantly, which greatly reduces the energy loss of the useless sampling points to the overall system, and when the input signal changes very quickly, the sampling rate of the event-driven analog-to-digital converter of the present invention will be adaptively increased, and when the input signal does not change, the sampling rate will be adaptively reduced, that is, the sampling rate can be automatically adjusted according to the input signal change rate, thereby greatly improving the energy efficiency ratio of the analog-to-digital converter.

[0053] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. An event-driven analog-to-digital converter, characterized in that: include: A signal folding module, including a switched capacitor circuit, for folding an input signal and outputting a folded signal; a first comparison control circuit connected to the output end of the signal folding module, configured to compare the folding signal with a threshold common mode voltage to generate a first comparison result, and generate a signal direction conversion event pulse according to the first comparison result; a multi-level comparison module, connected to the output end of the signal folding module and the first comparison control circuit, and configured to select an upper threshold voltage or a lower threshold voltage to compare with the folding signal according to the first comparison result to generate a second comparison result; A second logic control circuit is connected to the output end of the multi-level comparison module and is used to generate a sampling mark event pulse according to the second comparison result; a folding logic control circuit, connected to the first comparison control circuit and the second logic control circuit, configured to generate a sampling event pulse according to the signal direction conversion event pulse and the sampling mark event pulse, and feed the sampling event pulse back to the signal folding module; An up-down counter module is connected to the first comparison control circuit and is also connected to the first comparison control circuit and the second logic control circuit through an OR gate, and is used to generate an amplitude code; The threshold common mode voltage is an average of the upper threshold voltage and the lower threshold voltage.

2. The event-driven analog-to-digital converter according to claim 1, wherein: The multi-level comparison module includes a multiplexer and a second comparator, wherein the enable control end of the multiplexer is connected to the output end of the first comparison control circuit, the output end, the upper threshold voltage or the lower threshold voltage of the signal folding module are respectively connected to an input end of the multiplexer, and the two output ends of the multiplexer are respectively connected to the in-phase input end and the inverting input end of the second comparator, and the output end of the second comparator serves as the output end of the multi-level comparison module to output the second comparison result.

3. The event-driven analog-to-digital converter according to claim 1 or 2, characterized in that: The second logic control circuit includes a CMOS transmission gate, an NMOS tube, a T trigger, a pulse generator and a first trigger. The input end of the CMOS transmission gate is connected to the output end of the multi-level comparison module. The output end of the CMOS transmission gate and the drain of the NMOS tube are connected to the clock input pin of the T trigger through a NOT gate. The source of the NMOS tube is grounded. The inverting output pin of the T trigger is connected to the pulse generator. The output end of the pulse generator serves as the output end of the second logic control circuit, outputs the sampling mark event pulse, and is connected to the input pin of the first trigger. The inverting output pin of the first trigger is connected to the lower control end of the CMOS transmission gate. The positive output pin of the first trigger is connected to the upper control end of the CMOS transmission gate and the gate of the NMOS tube, so as to close the NMOS tube and open the CMOS transmission gate when the sampling mark event pulse is at a low level, and to open the NMOS tube and close the CMOS transmission gate when the sampling mark event pulse is at a high level, thereby latching the T trigger.

4. The event-driven analog-to-digital converter according to claim 3, characterized in that: The first trigger is an SR trigger, and the second logic control circuit also includes a NAND gate. The output end of the OR gate is connected to an input end of the NAND gate after passing through a delay unit and a seventh NAND gate in sequence. The other input end of the NAND gate receives a reset signal, and its output end is connected to the R input pin of the SR trigger, and the S input pin of the SR trigger is connected to the output end of the pulse generator.

5. The event-driven analog-to-digital converter according to claim 1, wherein: The first comparison control circuit comprises: A first comparison module, connected to the output end of the signal folding module, for comparing the folding signal with a threshold common mode voltage to generate a first comparison result; The first logic control circuit is connected to the output end of the first comparison module, and includes a first NOT gate and a second NOT gate. The input end of the first NOT gate is connected to the output end of the first comparison module, the output end of the first NOT gate is connected to an input end of the OR gate through a pulse generator, and the input end of the second NOT gate is connected to the output end of the first NOT gate. The output end of the second NOT gate and the output end of the first NOT gate are respectively connected to the multi-level comparison module through a buffer, and the output end of the second NOT gate is also connected to the up-down counter module.

6. The event-driven analog-to-digital converter according to claim 5, characterized in that: The folding logic control circuit includes a D flip-flop, a first NAND gate, a second NAND gate, a third NAND gate, a fourth NAND gate, a first AND gate, a second AND gate, a third AND gate and a fourth AND gate, wherein a clock input pin of the D flip-flop is connected to an output end of the second logic control circuit, a D input pin and a QB output pin thereof are connected to an input pin of the first NAND gate, a Q output pin of the D flip-flop is connected to an input pin of the second NAND gate, another input pin of the second NAND gate and the first NAND gate are respectively connected to the output ends of the first NAND gate and the second NAND gate through a delay unit, and are respectively connected to the input ends of the third NAND gate and the fourth NAND gate. , the output end of the third NOT gate is respectively connected to an input end of the first AND gate and the second AND gate, the output end of the fourth NOT gate is respectively connected to an input end of the third AND gate and the fourth AND gate, the other input ends of the first AND gate and the third AND gate are connected to the output end of the second NOT gate, the other input ends of the second AND gate and the fourth AND gate are connected to the output end of the first NOT gate, and the output ends of the first AND gate, the second AND gate, the third AND gate and the fourth AND gate are respectively connected to the control end of a switch tube of the switch capacitor circuit, so that the switch capacitor circuit folds the input signal according to the sampling event pulses from the first AND gate, the second AND gate, the third AND gate and the fourth AND gate.

7. The event-driven analog-to-digital converter according to claim 6, wherein: The switch capacitor circuit includes a first capacitor string, a second capacitor string, a third capacitor string, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a sixth switch tube, wherein the control ends of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are respectively connected to the output ends of the second AND gate, the first AND gate, the fourth AND gate and the third AND gate, the input ends of the first switch tube and the third switch tube both receive the upper threshold voltage, the input ends of the second switch tube and the fourth switch tube both receive the lower threshold voltage, and the output ends of the first switch tube and the second switch tube are both connected to the midpoint of the third capacitor string, the output ends of the third switch tube and the fourth switch tube are both connected to the midpoint of the first capacitor string, the midpoint of the second capacitor string is connected to the midpoints of the first capacitor string and the third capacitor string through the fifth switch tube and the sixth switch tube, and the control ends of the fifth switch tube and the sixth switch tube are respectively connected to the output ends of the third NOT gate and the fourth NOT gate, and both ends of the first capacitor string, the second capacitor string and the third capacitor string are connected between the input signal and the ground.

8. The event-driven analog-to-digital converter according to claim 5, wherein: The up-down counter module includes an up-down counter and a logic gate circuit. The logic gate circuit includes a fifth NOT gate, a sixth NOT gate, a multi-input NOR gate, a multi-input AND gate, a third NAND gate, a fourth NAND gate, a fifth NAND gate and a first NOR gate. The input ends of the fifth NOT gate and the sixth NOT gate are respectively connected to the output ends of the second NOT gate and the OR gate. The two input ends of the third NAND gate are respectively connected to the output ends of the second NOT gate and the multi-input AND gate. The two input ends of the fourth NAND gate are respectively connected to the output ends of the fifth NOT gate and the multi-input NOR gate. The output ends of the third NAND gate and the fourth NAND gate are respectively connected to the two input ends of the fifth NAND gate. The output end of the fifth NAND gate and the output end of the sixth NAND gate are respectively connected to the two input ends of the first NOR gate. The output end of the first NOR gate and the output end of the second NAND gate are respectively connected to the counting pin and the signal input pin of the up-down counter. The output pin of the up-down counter serves as the output end of the up-down counter module, is used to output the amplitude code, and is connected to the input ends of the multi-input NOR gate and the multi-input AND gate.

9. The event-driven analog-to-digital converter according to claim 8, characterized in that: The up-down counter module also includes a register, an input pin of the register is connected to an output pin of the up-down counter, the output pin of the register serves as an output end of the up-down counter module for outputting an amplitude code, and an enable pin of the register is connected to the output end of the OR gate via a delay unit.

10. The event-driven analog-to-digital converter according to claim 9, characterized in that: The up-down counter is a 6-bit up-down counter, the multi-input NOR gate is a 6-bit input NOR gate, the multi-input AND gate is a 6-bit input AND gate, and the register is a 6-bit DFF register.

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