Bandwidth adjustment method, device and equipment for OTN (Optical Transport Network) system
By introducing chain cache channel configuration and channel cache waterline adjustment mechanism in OTN system, the problem of poor bandwidth adjustment technology flexibility and reliability in OTN system is solved, and efficient and reliable bandwidth adjustment is achieved, reducing costs and improving resource utilization.
Patent Information
- Application Number
- CN202411221480.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-05-13
AI Technical Summary
The bandwidth adjustment technology of existing OTN systems is poor in flexibility and reliability, resulting in increased costs and poor anti-jitter capability when applied in high-capacity lines.
By introducing chain cache channel configuration and channel cache waterline adjustment mechanism in the OTN system, the chain cache channel configuration and configuration adjustment information are calculated, and the channel cache waterline is controlled to be within the preset range of the medium waterline to ensure the smooth transition of channel service rate during bandwidth adjustment.
It realizes efficient, reliable and low cost of bandwidth adjustment in OTN systems, ensuring the integrity of channel data during the adjustment process and efficient utilization of resources.
Smart Images
Figure CN119996204A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of optical communication technology, and in particular to a bandwidth adjustment method, device and equipment for an OTN system. Background Art
[0002] At present, OTN (Optical Transport Network) is the core technology of the transport network, which is characterized by large service capacity and flexible scheduling. However, with the development of OTN technology, the bearer network is not only required to carry fixed-rate services, but also has an increasing demand for adjusting the rate of low-order (LO) services and the time slot adjustment of high-order (HO) services in the bearer network. Therefore, lossless bandwidth adjustment technology has emerged and is increasingly widely used in OTN networks.
[0003] In the related art, bandwidth adjustment technology uses a fixed-depth cache in the channel cache design for carrying services, ignoring the cost, flexibility and reliability of the design, resulting in poor anti-jitter capability and inflexibility in actual application. If each channel needs to cache LO services of multiple bandwidths, a large amount of cache resources will be consumed, especially in high-capacity lines, which greatly increases the cost. Therefore, there is an urgent need for a high-efficiency, high-reliability and low-cost bandwidth adjustment technology to support services of different rates. Summary of the invention
[0004] The present application provides a bandwidth adjustment method, device and equipment for an OTN system, which can solve the technical problems of poor flexibility and reliability of bandwidth adjustment technology in the prior art.
[0005] In a first aspect, an embodiment of the present application provides a bandwidth adjustment method for an OTN system, the method comprising:
[0006] When each site receives a bandwidth adjustment instruction, it calculates the chain cache channel configuration and configures the adjustment information; the chain cache channel configuration includes the channel switching watermark; when the adjustment information of the site is the same as that of the upstream site, it sends an adjustment confirmation message to the downstream site;
[0007] After the first site detects the adjustment confirmation information of other sites, all sites transmit the channel switching command to the downstream sites in turn. After receiving the command, each site switches to the corresponding chain cache channel configuration;
[0008] After all site channel switching is completed, the first site adjusts the bandwidth and transmits bandwidth adjustment instruction signals to downstream sites one by one, so that other sites can adjust their bandwidth; when any site adjusts the bandwidth, the channel cache waterline is controlled to be within a preset range centered on the middle waterline.
[0009] In combination with the first aspect, in one implementation, after receiving the command, each site switches to a corresponding chained cache channel configuration when a switching condition is met;
[0010] The above switching conditions include a write-side channel configuration switching condition and a read-side channel configuration switching condition;
[0011] The above write-side channel configuration switching conditions are: the above channel switching command is valid, the channel cache watermark is not greater than the above channel switching watermark, and the write-side channel is written to the 0 pointer;
[0012] The switching conditions of the read side channel configuration are: the channel switching command is valid, the channel cache watermark is not greater than the channel switching watermark, and the read side channel reads to the 0 pointer.
[0013] In combination with the first aspect, in one implementation, the above-mentioned switching to the corresponding chained cache channel configuration when the switching condition is met specifically includes:
[0014] First, when the write-side channel configuration switching condition is met, the write-side channel configuration switching is triggered, and then when the read-side channel configuration switching condition is met, the read-side channel configuration switching is triggered.
[0015] In combination with the first aspect, in one implementation, after the end station switches to the corresponding chain cache channel configuration when the switching condition is met, the method further includes:
[0016] Feedback the channel switching completion instruction to the upstream site one by one; wherein, when each site feeds back the channel switching completion instruction to the upstream, the hardware generates an interrupt signal to report to the local upper management system.
[0017] In conjunction with the first aspect, in one implementation, before the first site adjusts the bandwidth, the method further includes:
[0018] Sending bandwidth adjustment instruction information to downstream sites one by one;
[0019] After receiving the bandwidth adjustment indication information, the last station sends a feedback signal to the first station in a transparent transmission manner. The feedback signal is used to feedback that all stations are ready.
[0020] In combination with the first aspect, in one implementation, the chained cache channel configuration further includes the number of time slots m; and when calculating the chained cache channel configuration, it also includes:
[0021] The chain cache channel configuration information is saved to a standby configuration table, and corresponding cache resources are allocated to the standby configuration table; if n chain RAM blocks can be allocated to each time slot, the cache resources are m×n chain RAM blocks.
[0022] In conjunction with the first aspect, in one implementation, the chained cache channel configuration further includes a channel cache high watermark and a channel cache low watermark;
[0023] The control channel cache waterline is located within the preset range centered on the middle waterline, including:
[0024] When the channel cache waterline is greater than the above-mentioned channel cache high waterline, pull up the cache waterline high state, and adjust the waterline downward until the channel cache waterline reaches the middle waterline;
[0025] When the channel cache waterline is lower than the above-mentioned channel cache low waterline, the cache waterline is pulled up to the low state, and the waterline is adjusted up until the channel cache waterline reaches the middle waterline.
[0026] In combination with the first aspect, in one implementation, the chained cache channel configuration further includes a chained cache depth allocated to a new service after bandwidth adjustment;
[0027] The above channel cache high watermark and the above channel switching watermark are both 3 / 4 of the above chain cache depth;
[0028] The channel cache low watermark is 1 / 4 of the chain cache depth.
[0029] In a second aspect, an embodiment of the present application provides a bandwidth adjustment device for an OTN system, which is arranged in each site, and the device includes:
[0030] A channel chain cache module, which is used to configure adjustment information when receiving a bandwidth adjustment instruction, and when the adjustment information of the current site is the same as that of the upstream site, send adjustment confirmation information to the downstream site; and after receiving a channel switching command, transmit the channel switching command to the downstream site; it is also used to adjust the bandwidth, and after the bandwidth is adjusted, transmit a bandwidth adjustment indication signal to the downstream site;
[0031] A channel configuration calculation module, which is used to calculate the chain cache channel configuration when receiving the bandwidth adjustment instruction; the chain cache channel configuration includes a channel switching watermark;
[0032] A frame positioning module, which is used to switch to the corresponding chain cache channel configuration after receiving a channel switching command;
[0033] The speed measurement module is used to control the channel cache waterline to be within a preset range centered on the middle waterline when adjusting the bandwidth.
[0034] In a third aspect, an embodiment of the present application provides a bandwidth adjustment device for an OTN system, the device comprising a processor, a memory, and a bandwidth adjustment program stored in the memory and executable by the processor, wherein when the bandwidth adjustment program is executed by the processor, the steps of the bandwidth adjustment method are implemented.
[0035] The beneficial effects brought by the technical solution provided by the embodiments of the present application include:
[0036] The bandwidth adjustment method, device and equipment of the present application, when each site receives a bandwidth adjustment instruction, calculates the chain cache channel configuration and configures the adjustment information; the above-mentioned chain cache channel configuration includes a channel switching watermark; when the adjustment information of the current site is the same as that of the upstream site, the adjustment confirmation information is sent to the downstream site; after the first site detects the adjustment confirmation information of other sites, all sites transmit the channel switching command to the downstream site in turn, and after receiving the command, each site switches to the corresponding chain cache channel configuration; after all sites have completed the channel switching, the first site adjusts the bandwidth and transmits the bandwidth adjustment indication signal to the downstream site one by one, so that the other sites adjust the bandwidth; when any site adjusts the bandwidth, the channel cache watermark is controlled to be within a preset range centered on the middle watermark; through an effective channel configuration switching process and a channel cache watermark adjustment mechanism, it is ensured that the channel service rate is smoothly transitioned during the entire bandwidth adjustment process, and the channel data will not be lost, thereby solving the technical problems of poor flexibility and reliability of the existing bandwidth adjustment technology. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1 A schematic diagram of a flow chart of an embodiment of a bandwidth adjustment method of the present application;
[0038] Figure 2 (1) to (4) are schematic diagrams of switching to the corresponding chain cache channel configuration in step S2;
[0039] Figure 3 A schematic diagram of channel configuration switching of this application;
[0040] Figure 4 This is a functional module diagram of an embodiment of a bandwidth adjustment device of the present application;
[0041] Figure 5 This is a schematic diagram of the channel chain cache address calculation for this application;
[0042] Figure 6 This is a schematic diagram of the hardware structure of the bandwidth adjustment device involved in the embodiment of the present application. DETAILED DESCRIPTION
[0043] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.
[0045] In a first aspect, an embodiment of the present application provides a bandwidth adjustment method for an OTN system.
[0046] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of the first embodiment of the bandwidth adjustment method for the OTN system of the present application. Figure 1 As shown, the bandwidth adjustment method for the OTN system includes:
[0047] S1. When each site receives a bandwidth adjustment instruction, it calculates the chain cache channel configuration and configures the adjustment information; the chain cache channel configuration includes the channel switching waterline; when the adjustment information of this site is the same as that of the upstream site, it sends an adjustment confirmation message to the downstream site;
[0048] S2. After the first site detects the adjustment confirmation information of other sites, all sites transmit the channel switching command to the downstream sites in turn. After receiving the command, each site switches to the corresponding chain cache channel configuration;
[0049] S3. After all site channels are switched, the first site adjusts the bandwidth and transmits bandwidth adjustment instruction signals to downstream sites one by one, so that other sites can adjust their bandwidths. When any site adjusts its bandwidth, the channel cache waterline is controlled to be within a preset range centered on the middle waterline.
[0050] The bandwidth adjustment method of the present application calculates the chain cache channel configuration and configures the adjustment information when each site receives the bandwidth adjustment instruction, and the above-mentioned chain cache channel configuration includes the channel switching waterline; when the adjustment information of the current site is the same as that of the upstream site, the adjustment confirmation information is sent to the downstream site; after the first site detects the adjustment confirmation information of other sites, all sites transmit the channel switching command to the downstream site in turn, and after receiving the command, each site switches to the corresponding chain cache channel configuration; after all sites have completed the channel switching, the first site adjusts the bandwidth and transmits the bandwidth adjustment indication signal to the downstream site one by one, so that other sites adjust the bandwidth; when any site adjusts the bandwidth, the channel cache waterline is controlled to be within a preset range centered on the middle waterline; through the effective channel configuration switching process and the channel cache waterline adjustment mechanism, it is ensured that the channel service rate is smoothly transitioned during the entire bandwidth adjustment process, and the channel data will not be lost, which solves the technical problem of poor flexibility and reliability of the bandwidth adjustment technology in the related technology.
[0051] Furthermore, in one embodiment, the chained cache channel configuration further includes the number of time slots m; and when calculating the chained cache channel configuration, it also includes:
[0052] The chain cache channel configuration information is saved to a standby configuration table, and corresponding cache resources are allocated to the standby configuration table; if n chain random access memory RAM blocks can be allocated to each time slot, the cache resources are m×n chain RAM blocks.
[0053] In this embodiment, by dynamically refreshing the channel configuration table and allocating corresponding cache resources according to the bandwidth adjustment information, it is possible to dynamically allocate channel cache resources that match the channel bandwidth adjustment requirements, thereby greatly improving resource utilization.
[0054] In this embodiment, after each station enters the link connection size adjustment mode, it is necessary to configure the channel number that needs to adjust the bandwidth and the ADD / REMOVE adjustment information to the overhead configuration, and at the same time, configure the above-calculated related channel configuration information to the standby configuration table. After the above-mentioned overhead and channel configuration are configured, at the position where the OMFP is indicated in the next HO multiframe header, the configured overhead is filled into the overhead bit byte corresponding to the frame and sent to the downstream. At this time, the channel can be configured to enter the adjustment mode and adjust the channel cache waterline.
[0055] On the basis of the above embodiment, in this embodiment, in the above step S2, after receiving the command, each site switches to the corresponding chain cache channel configuration when the switching condition is met.
[0056] The above switching conditions include a write-side channel configuration switching condition and a read-side channel configuration switching condition.
[0057] The above write-side channel configuration switching conditions are: the above channel switching command is valid, the channel cache watermark is not greater than the above channel switching watermark, and the write-side channel is written to the 0 pointer.
[0058] The switching conditions of the read side channel configuration are: the channel switching command is valid, the channel cache watermark is not greater than the channel switching watermark, and the read side channel reads to the 0 pointer.
[0059] Among them, the change of cache depth during channel switching causes the loss of high addresses. If the read and write operations are at high address positions at this time, read and write errors and data loss will occur. Therefore, the read and write channels must be satisfied to the 0 pointer.
[0060] In this embodiment, the channel switching command, the channel switching waterline and the channel cache read and write side pointer positions are used to control the orderly channel switching on both sides. The switching timing is controllable, the switching method is efficient and reliable, and the data flow of the entire channel switching process is guaranteed to be normal.
[0061] Further, in one embodiment, the above switching to the corresponding chained cache channel configuration when the switching condition is met specifically includes:
[0062] First, when the write-side channel configuration switching condition is met, the write-side channel configuration switching is triggered, and then when the read-side channel configuration switching condition is met, the read-side channel configuration switching is triggered.
[0063] In this embodiment, when the write side pointer reaches position 0, the write side configuration is switched first, and then when the read side pointer reaches position 0, the read side channel configuration is switched, further ensuring that data is not lost when the channel is switched.
[0064] like Figure 2As shown, taking the bandwidth adjustment mode from high bandwidth to low bandwidth as an example, the cache depth allocated to the current service is depth. After switching to the new service, the cache depth is allocated to half of the original depth / 2. The shaded part in the figure represents the part of the data stored in the cache. When the local upper-layer management system UPI sends the channel switching command chsw_en, step (1) in the figure shows that the current channel cache watermark counter is higher than the channel switching watermark chsw_lvl, which does not meet the channel switching condition. Therefore, the chain cache outputs ram_high, and after the watermark is lowered through control, it enters the state of step (2) in the figure. At this time, the current channel cache watermark counter is lower than the channel switching watermark chsw_lvl, but the write pointer is higher than the position of depth / 2-1. If the channel write side configuration is switched at this time, that is, the effective range of the write pointer is 0 to depth / 2-1, the current pointer position exceeds the effective range, which will cause write data loss and does not meet the requirements of lossless bandwidth adjustment. Therefore, this embodiment uses the 0 pointer position as a necessary condition for switching control. When the write pointer is written to the position of 0, the write side channel configuration switch is triggered, that is, the state of step (3) in the figure. After the write configuration is switched, when the read pointer reads to position 0 for the first time, as shown in the state of step (4) in the figure, the read side channel configuration is triggered to switch. This method of switching channels by waterline control and at the 0 pointer position is highly reliable and effectively avoids data loss caused by channel switching and uncertainty in the read and write positions of the channel cache after switching.
[0065] Further, in one embodiment, after the end station switches to the corresponding chained cache channel configuration when the switching condition is met, the method further includes:
[0066] Feedback the channel switching completion instruction to the upstream site one by one; wherein, when each site feeds back the channel switching completion instruction to the upstream, the hardware generates an interrupt signal to report to the local upper management system.
[0067] In this embodiment, an interrupt signal is generated by hardware and reported to the local upper-layer management system, indicating that the current link connection size adjustment process has ended.
[0068] Furthermore, in one embodiment, before the head site adjusts the bandwidth, the following steps are also included:
[0069] First, bandwidth adjustment indication information is sent to downstream sites one by one;
[0070] When the first site detects that the channel switching operations of all sites have been completed, the sender sends bandwidth adjustment indication information to the downstream site, indicating that the site has entered the BWR (Bandwidth Request, bandwidth adjustment) mode, and the receiver and sender are ready to support the LO service bandwidth size adjustment operation. Other sites follow this process to pass the bandwidth adjustment indication information to the end site in turn.
[0071] Then, after the last site receives the bandwidth adjustment indication information, the size adjustment operations of all sites on the OTN line are ready. The last site sends a feedback signal to the first site in a transparent transmission manner. The feedback signal is used to feedback that all sites are ready.
[0072] Furthermore, in one embodiment, the above-mentioned chain cache channel configuration also includes a channel cache high watermark and a channel cache low watermark.
[0073] When any site adjusts bandwidth, the control channel cache watermark is within a preset range centered on the middle watermark, including:
[0074] When the channel cache waterline is greater than the above-mentioned channel cache high waterline, pull up the cache waterline to the high state, and adjust the waterline down until the channel cache waterline reaches the middle waterline; when the channel cache waterline is less than the above-mentioned channel cache low waterline, pull up the cache waterline to the low state, and adjust the waterline up until the channel cache waterline reaches the middle waterline.
[0075] In this embodiment, the preset range is the range from the channel cache low watermark to the channel cache high watermark. By adjusting the channel cache watermark in real time, the anti-jitter capability is improved, and there is no need to use too much cache resources to absorb data jitter, thereby saving a lot of resources. At the same time, the adjustment mechanism ensures that the channel cache watermark remains near the middle watermark during the entire bandwidth adjustment process, making the adjustment process more stable and reliable.
[0076] Furthermore, in this embodiment, the above chain cache channel configuration also includes a chain cache depth allocated to new services after bandwidth adjustment.
[0077] The above-mentioned channel cache high watermark and the above-mentioned channel switching watermark are both 3 / 4 of the above-mentioned chain cache depth; the above-mentioned channel cache low watermark is 1 / 4 of the above-mentioned chain cache depth.
[0078] like Figure 3 As shown, when the platform issues a bandwidth adjustment instruction to a channel, each site detects the instruction and starts channel configuration switching, and steps A and B are performed simultaneously in parallel, wherein step A specifically includes:
[0079] A1. Determine which configuration table the current channel service is working in. If the working table is table A, select table B as the backup configuration table for calculation and refresh, enter LCR (Link Connection Resize) mode, configure the adjustment information to the overhead, and fill the allocated overhead into the overhead bit byte corresponding to the frame at the position of the next HO multiframe header OMFP and send it to the downstream;
[0080] A2. When the adjustment information sent by the peer site is received and it is determined to be consistent with the adjustment information of the bandwidth of the local site, the NORM information is configured in the overhead configuration and the channel switching stage is entered. The local UPI sends a channel switching command chsw_en, which is effective, and the channel enters the switching state;
[0081] A3. At the position of the next HO multiframe header OMFP, fill the NORM overhead configuration into the transmission frame and send it to the downstream site. At the same time, start adjusting the channel cache watermark until it is below the channel switching watermark chsw_lvl;
[0082] A4. Switch other service-related configurations at the position of the next HO multiframe header OMFP, configure IDLE overhead, exit LCR mode, and then fill in IDLE overhead for all adjusted branches at the position of the next HO multiframe header OMFP, and end.
[0083] The above step B comprises:
[0084] B1. Calculate the chain cache channel configuration and configure it to the standby configuration table, and configure the channel to enter the adjustment mode;
[0085] B2. When steps A1 and A2 are completed and the switching conditions are met, the channel configuration is switched;
[0086] B3. When it is determined that the current channel is working in the newly refreshed B table, it indicates that the channel switching is successful, the channel switching command chsw_en is turned off, the channel exits the adjustment mode, and ends.
[0087] Specifically, the bandwidth adjustment method of this embodiment includes:
[0088] Step 1: The network management platform sends bandwidth increase or decrease instructions to each site upstream and downstream of the OTN network line according to the bandwidth adjustment requirements. After receiving the bandwidth adjustment instructions from the network management platform, each site starts the link connection size adjustment process. The local UPI of each site calculates the number of time slots occupied by the LO service after the bandwidth adjustment and the chain cache channel configuration such as the channel rate adaptation cache according to the bandwidth adjustment instructions sent.
[0089] Among them, the above-mentioned chain cache channel configuration includes channel chain cache depth (ch_depth), channel chain cache start read watermark (start_lvl), channel cache high watermark and channel cache low watermark (hs_lvl and ls_lvl), channel switching watermark (chsw_lvl), channel chain cache RAM (Random Access Memory) block number configuration (ch_blk) and channel chain cache RAM block number storage address configuration (ch_pt), etc. These calculated channel configurations are saved in the backup configuration table, namely the backup register configuration and table entry configuration, to prepare for the channel configuration switching in bandwidth adjustment.
[0090] Step 2: The transmitting end of each site on the line inserts ADD / REMOVE adjustment information to the receiving end of the downstream site through the ODUk frame. At the same time, the receiving end of the site detects the ODUk frame sent from the upstream, extracts the adjustment information, including the channel and time slot, through the extraction module, and compares the received extracted time slot adjustment information with the time slot configuration to be adjusted at the local end. If the two are consistent, the comparison passes, and the local UPI sends adjustment confirmation information in the ODUk frame output by the transmitting end of the site, indicating that the bandwidth adjustment information of the site is consistent with that of the opposite site, and is ready to switch the time slot and channel configuration to the standby configuration table corresponding to the new time slot.
[0091] Step 3: After the receiving end of the first site detects the confirmation information in the received ODUk frame, it sends a control instruction through the local UPI to notify the sending end of the site to send a channel switching command through the ODUk branch at the next ODUk multiframe boundary. At the same time, the local UPI of this site sends a channel switching command chsw_en to switch the time slot and channel configuration of this site to the configuration table corresponding to the new time slot calculated in step 1.
[0092] Among them, after receiving the command, each site switches to the corresponding chain cache channel configuration when the switching conditions are met, that is, when the chsw_en command is valid and the real-time watermark value counter of the channel cache is less than or equal to the channel switching watermark chsw_lvl, the channel read side and write side respectively generate their own channel switching pulses at their respective read and write 0 pointers, triggering their respective channel-related configurations to switch to the channel cache configuration table corresponding to the new service.
[0093] When configuring the channel switching watermark chsw_lvl and the high and low state watermarks hs_lvl and ls_lvl of the current work table of the channel, hs_lvl and ls_lvl can be configured as 3 / 4 and 1 / 4 times the chain cache depth value allocated to the new service after the bandwidth adjustment, and chsw_lvl is set to the channel cache high watermark hs_lvl corresponding to the new service.
[0094] When the bandwidth adjustment method is from low-bandwidth service to high-bandwidth service, the channel cache capacity corresponding to the new service is greater than the channel cache capacity of the old service, so the real-time channel cache waterline counter originally meets the condition of being less than or equal to the channel switching waterline chsw_lvl. Therefore, when the local UPI sends chsw_en, the write side first writes to the 0 pointer and triggers the write side channel configuration switch, and then the read side reads to the 0 pointer and triggers the read side channel configuration switch. At the same time, the chain cache outputs the channel low waterline status indication ram_low, and controls the channel cache read operation to slow down according to the status indication, so that after the channel cache waterline gradually rises to the middle waterline, the chain cache will pull up the ram_low state.
[0095] When the bandwidth adjustment mode is adjusted from high-bandwidth service to low-bandwidth service, the channel cache capacity corresponding to the new service is smaller than the channel cache capacity of the old service, and the real-time channel cache watermark counter may be higher than the channel switching watermark chsw_lvl. At this time, if the channel configuration is switched, some cached data will be lost, causing service interruption. In order to achieve reliable lossless bandwidth adjustment, the high and low watermarks of the current working table of the channel will be configured to the high and low watermark configurations corresponding to the new service. If the current channel cache watermark is higher than the high watermark configuration value, the cache watermark high state indication ram_high will be output to control the speed of the channel cache read operation according to the state indication, so that the cache watermark gradually decreases below the channel switching watermark chsw_lvl, and then the write side and the read side each trigger a switching pulse at the 0 pointer to switch the channel.
[0096] After the receiving end of other sites detects the channel switching command through the ODUk branch, they send the channel switching command in the same way and perform the channel switching operation at the same time, switching to the service configuration corresponding to the new time slot.
[0097] Step 4: After the last station receives the channel switching command at the receiving end and completes the channel switching configuration, it sends the channel switching completion instruction to the upstream station one by one at the next ODUk multiframe boundary position of the transmitting end, and the hardware generates an interrupt signal to report the local UPI, indicating that the current LCR adjustment process has ended. Each upstream station executes this step in sequence until the first station receives the channel switching completion instruction from the downstream station, and the hardware generates an interrupt signal to report the local UPI, indicating that all stations have completed the channel switching.
[0098] Step 5: When the receiving end of the first node detects that the channel switching operation of all sites has been completed through the ODUk branch information, the sending end sends bandwidth adjustment indication information to the downstream site, indicating that the site has entered the BWR mode and both the receiving end and the sending end are ready to support the LO service bandwidth size adjustment operation. Other sites follow this process and pass the bandwidth adjustment indication information downstream to the last site in turn.
[0099] Step 6: When the receiving end of the last site receives the bandwidth adjustment indication information through the corresponding branch time slot of the ODUk frame, the size adjustment operation of all sites on the OTN line is ready. The sending end of this site sends a feedback signal through the ODUk frame branch. The feedback signal is transmitted to the first site through all intermediate sites in a transparent transmission manner.
[0100] Step 7: When the receiving end of the first site receives the feedback signal from the last site through the ODUk branch time slot, the system hardware generates an interrupt signal to report to the network management platform that all sites on the current OTN line are ready for bandwidth adjustment operations. At this time, the sending end of the first site starts to perform the LO service bandwidth size adjustment operation.
[0101] Since bandwidth adjustment needs to be performed gradually and slowly, if the LO service is adjusted too quickly, it may cause large channel data jitter and data non-uniformity, causing large fluctuations in the channel cache waterline for bandwidth adjustment, and even overflow or underflow, resulting in data loss. In this embodiment, through the waterline adjustment function, during the LO service bandwidth size adjustment process, when the channel cache waterline fluctuates within a certain range, the channel cache waterline high state indication ram_high and low state indication ram_low can be used to adjust the speed of the cache read operation in real time, thereby controlling the channel cache waterline near the middle waterline.
[0102] When the real-time channel cache waterline counter is greater than the channel cache high waterline hs_lvl, the cache ram_high is pulled up, triggering the speed measurement module to adjust the waterline down until the channel cache middle waterline; similarly, when the cache real-time waterline counter is less than the low state starting waterline value ls_lvl, the cache ram_low is pulled up, triggering the speed measurement module to adjust the waterline up until the channel cache middle waterline.
[0103] When the LO service bandwidth size adjustment operation of the first site is completed, a bandwidth adjustment BWR indication signal is sent to the downstream site through the ODUk frame branch time slot to tell the downstream site to start the LO service bandwidth size adjustment operation. The downstream site performs bandwidth adjustment in sequence according to this process until the end site.
[0104] Step 8: When the terminal site receives the bandwidth size adjustment instruction through the ODUk frame branch time slot and performs the bandwidth adjustment operation, the transmitting end sends a bandwidth size adjustment completion indication to the head site. The indication signal is transmitted to the head site through transparent transmission. The head site receives the indication signal, indicating that the entire OTN line has completed the BWR process and exits the BWR mode. At this time, the head site and the terminal site report the completion signal of the entire bandwidth adjustment process to the upper layer platform.
[0105] The method of this embodiment mainly involves lossless bandwidth adjustment and service switching of an optical transport network. According to the lossless bandwidth adjustment protocol, two processes of increasing and decreasing the LO service rate of the OTN network are supported. To improve the utilization rate of cache resources, when the bandwidth increases, the channel cache needs to be expanded, and when the bandwidth decreases, the channel cache capacity needs to be reduced. Regardless of whether the bandwidth increases or decreases, by dynamically allocating chain caches and dynamically adjusting the channel cache waterline, it is ensured that when the LO service has normal jitter during the bandwidth adjustment process, the channel waterline is always near the relatively safe and stable middle waterline. By an effective channel configuration switching method and a channel cache waterline adjustment mechanism, it is ensured that the channel service rate transitions smoothly during the entire bandwidth adjustment process, and channel data is not lost. At the same time, the designed cache resources are saved and resource utilization is improved.
[0106] In a second aspect, an embodiment of the present application further provides a bandwidth adjustment device for an OTN system.
[0107] The bandwidth adjustment device of this embodiment is arranged in each site, and includes a channel chain buffer module, a channel configuration calculation module, a frame positioning module and a speed measurement module.
[0108] The channel chain cache module is used to configure adjustment information when receiving a bandwidth adjustment instruction, and when the adjustment information of the current site is the same as that of the upstream site, send adjustment confirmation information to the downstream site; and after receiving a channel switching command, transmit the channel switching command to the downstream site; it is also used to adjust the bandwidth, and after the bandwidth is adjusted, transmit a bandwidth adjustment indication signal to the downstream site;
[0109] The channel configuration calculation module is used to calculate the chain cache channel configuration when receiving the bandwidth adjustment instruction; the chain cache channel configuration includes the channel switching waterline;
[0110] The frame positioning module is used to switch to the corresponding chain buffer channel configuration after receiving the channel switching command;
[0111] When the speed measurement module is used to adjust the bandwidth, the buffer waterline of the control channel is located within a preset range centered on the middle waterline.
[0112] In one embodiment, if Figure 4 As shown, the bandwidth adjustment device further includes an envelope characterization module and a read-write control module.
[0113] The above-mentioned envelope characterization module is used to output a fixed number of envelopes in a certain time window by counting according to the business standard rate. The output envelope meets the business standard rate and is relatively uniform.
[0114] The above-mentioned read-write control module is used to generate a read control signal of the channel chain cache according to the frame indication signal output by the frame positioning module, control the read operation of the channel chain cache, and the write control signal is generated by the input data envelope in_vld and the channel number in_chid of the LO service. The write control signal of the above-mentioned read-write control module controls the write operation.
[0115] In this embodiment, the channel chain cache is composed of multiple chain RAM blocks. When each site receives a bandwidth adjustment command, whether it is adjusted to high-speed service or low-speed service, the channel configuration table is dynamically refreshed according to the bandwidth adjustment information to allocate corresponding cache resources. The channel chain cache module can also output the waterline high and low state indications ram_high and ram_low according to the current chain cache waterline state and the cache high and low waterline configuration for waterline adjustment.
[0116] The channel configuration calculation module calculates the channel chain cache depth (ch_depth), the channel chain cache start read watermark (start_lvl), the channel cache high watermark and the channel cache low watermark (hs_lvl and ls_lvl), the channel switching watermark (chsw_lvl), the channel chain cache RAM block number configuration (ch_blk) and the channel chain cache RAM block number storage address configuration (ch_pt) according to the bandwidth adjustment requirements. Among them, the high and low watermark configurations hs_lvl and ls_lvl can be configured as 3 / 4 and 1 / 4 of the channel cache depth respectively, which are used to generate the high and low states of the chain cache watermark, that is, when the watermark is higher than the high watermark, the ram_high state is pulled up, and when the watermark is lower than the low watermark, the ram_low state is pulled up. When the watermark is adjusted to the middle watermark, the high and low states of the watermark are pulled down. The channel switching watermark chsw_lvl is generally configured as the high watermark value, which is used to control the timing of channel configuration switching during bandwidth adjustment.
[0117] The frame positioning module counts the frame length according to the envelope output by the envelope characterization module, and outputs the corresponding frame header FP, row header ROWP, multi-frame header OMFP, overhead position indication OH_IND and net position indication PL_IND, etc., which are used for channel data read and write control, chain cache channel and other service configuration switching.
[0118] The speed measurement module outputs corresponding feedback to the read-write control module according to the high and low states of the channel chain cache waterline, so that the read enable signal it outputs increases or decreases, thereby controlling the reading speed of the channel cache data and making the channel cache waterline stable near the middle waterline.
[0119] Among them, the channel chain cache read and write address calculation method is as follows:
[0120] The chain cache is composed of a certain number of chain RAM blocks. Each RAM block has the same bit width and depth and has an independent number. Assuming that the depth of a RAM block is d, each time slot can be allocated n chain RAM blocks. If the LO service bandwidth is adjusted to occupy m time slots, the channel can flexibly allocate any idle m×n block RAMs as cache resources, and can also be changed during operation according to the uniformity and jitter of the LO service and application requirements. Compared with fixed channel cache resources, its advantages are obvious. Among them, the configuration table entry ch_blk stores the block number of the channel chain cache. All RAM block numbers allocated to the same channel have continuous storage addresses in the table entry ch_blk to facilitate address addressing of read operations. The table entry ch_pt stores the storage address corresponding to the first RAM block number stored in the table entry ch_blk of the channel.
[0121] Attach Figure 5 For example, channel X is allocated three RAM blocks, numbered a, b and c, where a is the first RAM block number of the channel, stored in any three consecutive address positions of the table entry ch_blk, and the storage address of RAM block a is Y. The address value Y is stored in the address X of the table entry ch_pt, that is, the channel number of the channel. In this way, the storage value Y is first read according to the address X of the channel number X in the table entry ch_pt, and then the RAM block number a in the table entry ch_blk is read from the Y address, that is, the first RAM block number of the channel. The read and write start block address a*d of the channel cache can be calculated from the number a, and the reading and writing starts from the starting blk number a. At this time, the blk counter blk_cnt is 1. On the other hand, the read and write operation counts are accumulated and calculated by the serial adder.
[0122] Taking read as an example, the count range of the read operation count value rd_cnt is 1 to d. The count rd_cnt is the read offset address of the channel chain cache RAM block. The block address plus the offset address is the read address signal of the channel chain cache. At this time, the absolute address range of the channel read operation is a*d to (a+1)*d. When rd_cnt is equal to d, the read address of the configuration table item ch_blk is increased by 1, and the next RAM block number b is read to calculate the current new block address b*d. At the same time, the count blk_cnt is increased by 1 and rd_cnt starts counting again. At this time, the absolute address range is b*d to (b+1)*d. When rd_cnt counts to d again, the current blk_cnt is 3, the new block address is c*d, and rd_cnt counts again from 1 to d. At this time, the absolute address range is c*d to (c+1)*d. When counting reaches d again, the conditions of blk_cnt=3 and rd_cnt=d are met, and the first blk number a of the channel can be automatically found through the above method through the channel number X, table configuration ch_pt and ch_blk, and reading and writing can be restarted, and reading and writing can be performed in a loop according to the above address calculation method.
[0123] In this embodiment, the depth of the channel chain cache and the chain cache block position are dynamically allocated according to the OTN line bandwidth adjustment requirement, which can maximize the use of design cache resources, save costs, and make applications more flexible.
[0124] Furthermore, in one embodiment, the frame alignment module is further configured to switch to a corresponding chained cache channel configuration when a switching condition is met after receiving a channel switching command.
[0125] The switching conditions include a write-side channel configuration switching condition and a read-side channel configuration switching condition.
[0126] The above write-side channel configuration switching conditions are: the above channel switching command is valid, the channel cache watermark is not greater than the above channel switching watermark, and the write-side channel is written to the 0 pointer;
[0127] The switching conditions of the read side channel configuration are: the channel switching command is valid, the channel cache watermark is not greater than the channel switching watermark, and the read side channel reads to the 0 pointer.
[0128] Furthermore, in one embodiment, the channel chain cache module is also used to feed back a channel switching completion instruction to the upstream site after switching to the corresponding chain cache channel configuration. When feeding back the channel switching completion instruction to the upstream, the hardware generates an interrupt signal to report to the local upper management system.
[0129] Furthermore, in one embodiment, the channel chain buffer module is further configured to send bandwidth adjustment indication information to a downstream site when the channel chain buffer module is located at a site other than the last site.
[0130] The channel chain buffer module is also used to send a feedback signal to the first station through transparent transmission after receiving the bandwidth adjustment indication information when it is located at the last station.
[0131] Furthermore, in one embodiment, the speed measurement module is also used for:
[0132] When the channel cache waterline is greater than the above-mentioned channel cache high waterline, pull up the cache waterline high state, and adjust the waterline downward until the channel cache waterline reaches the middle waterline;
[0133] When the channel cache waterline is lower than the above-mentioned channel cache low waterline, the cache waterline is pulled up to the low state, and the waterline is adjusted up until the channel cache waterline reaches the middle waterline.
[0134] The above chain cache channel configuration also includes the chain cache depth of the new service allocation after the bandwidth adjustment;
[0135] The above channel cache high watermark and the above channel switching watermark are both 3 / 4 of the above chain cache depth;
[0136] The channel cache low watermark is 1 / 4 of the chain cache depth.
[0137] The functional implementation of each module in the bandwidth adjustment device for the OTN system corresponds to each step in the bandwidth adjustment method for the OTN system, and the functions and implementation processes thereof are not described one by one here.
[0138] In a third aspect, an embodiment of the present application provides a bandwidth adjustment device for an OTN system. The bandwidth adjustment device for an OTN system may be a device having a data processing function, such as an OTN device.
[0139] Reference Figure 6 , Figure 6 The hardware structure diagram of the bandwidth adjustment device for the OTN system involved in the embodiment of the present application is shown in FIG. In the embodiment of the present application, the bandwidth adjustment device for the OTN system may include a processor, a memory, a communication interface, and a communication bus.
[0140] The communication bus may be of any type and is used to interconnect the processor, the memory, and the communication interface.
[0141] The communication interface includes input / output (I / O) interface, physical interface and logical interface, etc., which are used to realize the interconnection of devices inside the bandwidth adjustment device for the OTN system, and the interface used to realize the interconnection between the bandwidth adjustment device for the OTN system and other devices (such as other computing devices or user equipment). The physical interface can be an Ethernet interface, a fiber interface, an ATM interface, etc.; the user equipment can be a display (Display), a keyboard (Keyboard), etc.
[0142] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.
[0143] The processor may be a general-purpose processor, and the general-purpose processor may call the bandwidth adjustment program for the OTN system stored in the memory, and execute the bandwidth adjustment method for the OTN system provided in the embodiment of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the bandwidth adjustment program for the OTN system is called may refer to the various embodiments of the bandwidth adjustment method for the OTN system of the present application, and will not be repeated here.
[0144] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation on the present application, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.
[0145] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments.
[0146] The terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices. The terms "first", "second" and "third" are used to distinguish different objects, etc., and do not represent a sequence, nor do they limit "first", "second" and "third" to different types.
[0147] In the description of the embodiments of the present application, "exemplary", "for example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary", "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary", "for example" or "for example" is intended to present related concepts in a specific way.
[0148] In the description of the embodiments of the present application, unless otherwise specified, “ / ” means or, for example, A / B can mean A or B; the “and / or” in the text is merely a description of the association relationship of associated objects, indicating that three relationships may exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, “multiple” refers to two or more than two.
[0149] In some processes described in the embodiments of the present application, multiple operations or steps that appear in a specific order are included, but it should be understood that these operations or steps may not be executed in the order in which they appear in the embodiments of the present application or in parallel, and the sequence number of the operation is only used to distinguish the different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed in sequence or in parallel, and these operations or steps may be combined.
[0150] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD) as described above, and includes a number of instructions for a terminal device to execute the methods described in each embodiment of the present application.
[0151] The above are only preferred embodiments of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.
Claims
1. A bandwidth adjustment method for an OTN system, characterized in that: The method comprises: When each site receives a bandwidth adjustment instruction, it calculates the chain cache channel configuration and configures the adjustment information; the chain cache channel configuration includes the channel switching watermark; when the adjustment information of the site is the same as that of the upstream site, it sends adjustment confirmation information to the downstream site; After the first site detects the adjustment confirmation information of other sites, all sites transmit the channel switching command to the downstream sites in turn. After receiving the command, each site switches to the corresponding chain cache channel configuration; After all site channel switching is completed, the first site adjusts the bandwidth and transmits bandwidth adjustment instruction signals to downstream sites one by one, so that other sites can adjust their bandwidth; when any site adjusts the bandwidth, the channel cache waterline is controlled to be within a preset range centered on the middle waterline.
2. The bandwidth adjustment method for an OTN system according to claim 1, characterized in that: After receiving the command, each site switches to the corresponding chain cache channel configuration when the switching conditions are met; The switching condition includes a write-side channel configuration switching condition and a read-side channel configuration switching condition; The write-side channel configuration switching condition is: the channel switching command is valid, the channel cache watermark is not greater than the channel switching watermark, and the write-side channel is written to the 0 pointer; The read side channel configuration switching condition is: the channel switching command is valid, the channel cache watermark is not greater than the channel switching watermark, and the read side channel reads to the 0 pointer.
3. The bandwidth adjustment method for an OTN system according to claim 2, characterized in that: The switching to the corresponding chained cache channel configuration when the switching condition is met specifically includes: First, when the write-side channel configuration switching condition is met, the write-side channel configuration switching is triggered, and then when the read-side channel configuration switching condition is met, the read-side channel configuration switching is triggered.
4. The bandwidth adjustment method for an OTN system according to claim 2, characterized in that: After the end station switches to the corresponding chain cache channel configuration when the switching condition is met, it also includes: Feedback the channel switching completion instruction to the upstream site one by one; wherein, when each site feeds back the channel switching completion instruction to the upstream, the hardware generates an interrupt signal to report to the local upper management system.
5. The bandwidth adjustment method for an OTN system according to claim 1, characterized in that: Before the first site adjusts the bandwidth, it also includes: Send bandwidth adjustment instruction information to downstream sites one by one; After receiving the bandwidth adjustment indication information, the end station sends a feedback signal to the head station in a transparent transmission manner, and the feedback signal is used to feedback that all stations are ready.
6. The bandwidth adjustment method for an OTN system according to claim 1, characterized in that: The chained cache channel configuration also includes the number of time slots m; when calculating the chained cache channel configuration, it also includes: The chained cache channel configuration information is saved to a standby configuration table, and corresponding cache resources are allocated to the standby configuration table; if n chained RAM blocks can be allocated to each time slot, the cache resources are m×n chained RAM blocks.
7. The bandwidth adjustment method for an OTN system according to claim 1, characterized in that: The chained cache channel configuration also includes a channel cache high watermark and a channel cache low watermark; The control channel cache waterline is located within a preset range centered on the middle waterline, including: When the channel cache waterline is greater than the channel cache high waterline, pull up the cache waterline high state, and adjust the waterline downward until the channel cache waterline reaches the middle waterline; When the channel cache waterline is lower than the channel cache low waterline, the cache waterline is pulled up to the low state, and the waterline is adjusted up until the channel cache waterline reaches the middle waterline.
8. The bandwidth adjustment method for an OTN system according to claim 7, characterized in that: The chain cache channel configuration also includes the chain cache depth of the new service allocation after the bandwidth adjustment; The channel cache high watermark and the channel switching watermark are both 3 / 4 of the chain cache depth; The channel cache low watermark is 1 / 4 of the chain cache depth.
9. A bandwidth adjustment device for an OTN system, arranged in each site, characterized in that: The device comprises: A channel chain cache module, which is used to configure adjustment information when receiving a bandwidth adjustment instruction, and when the adjustment information of the current site is the same as that of the upstream site, send adjustment confirmation information to the downstream site; and after receiving a channel switching command, transmit the channel switching command to the downstream site; it is also used to adjust the bandwidth, and after the bandwidth is adjusted, transmit a bandwidth adjustment indication signal to the downstream site; A channel configuration calculation module, which is used to calculate the chain cache channel configuration when receiving the bandwidth adjustment instruction; the chain cache channel configuration includes a channel switching watermark; A frame positioning module, which is used to switch to the corresponding chain cache channel configuration after receiving a channel switching command; The speed measurement module is used to control the channel cache waterline to be within a preset range centered on the middle waterline when adjusting the bandwidth.
10. A bandwidth adjustment device for an OTN system, characterized in that: The device comprises a processor, a memory, and a bandwidth adjustment program stored in the memory and executable by the processor, wherein when the bandwidth adjustment program is executed by the processor, the steps of the bandwidth adjustment method according to any one of claims 1 to 8 are implemented.