Endoscope image display system and method, electronic apparatus, and storage medium

Abstract

The invention relates to the technical field of data transmission, and discloses an endoscope image display system and method, electronic equipment and a storage medium, and the method comprises the steps: collecting an optical signal in the use process of an endoscope, and transmitting the optical signal based on a first target transmission protocol; receiving the optical signal, converting the optical signal into image data, and preprocessing the image data; in response to the preprocessed image data, under the condition that a plurality of continuous synchronizing signals of the image data are in the same state, packaging the plurality of continuous synchronizing signals to form a synchronizing signal group, and transmitting the image data based on the synchronizing signal group; image data is received and displayed in a display unit. According to the invention, the plurality of continuous synchronizing signals are packaged to form the synchronizing signal group, and the plurality of rows of data are transmitted according to the synchronizing signal group, so that the possibility of abnormal image display caused by interference or errors of a single synchronizing signal is reduced, the continuity of image data transmission is maintained, and the stability and the display effect of image display are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to an endoscope image display system, method, electronic equipment and storage medium. Background Art

[0002] In the related field programmable gate array (FPGA) inter-chip video transmission technology, low voltage differential signaling (LVDS) transmission is widely used. However, during the LVDS transmission process, the image displayed on the receiving end may be abnormal, such as repeated images, pixel misalignment and other technical problems of unstable image display, thus affecting the display effect of the image. Summary of the invention

[0003] In view of this, the present invention provides an endoscopic image display system, method, electronic device and storage medium to solve the technical problem of unstable endoscopic image display.

[0004] In a first aspect, the present invention provides an endoscope image display system, comprising:

[0005] An image sensor, a first field programmable gate array chip, a second field programmable gate array chip and a display unit;

[0006] The image sensor is used to collect optical signals during the use of the endoscope, and transmit the optical signals to the first field programmable gate array chip based on a first target transmission protocol;

[0007] The first field programmable gate array chip is used to receive the optical signal, convert the optical signal into image data, pre-process the image data, and transmit the pre-processed image data to the second field programmable gate array chip;

[0008] The second field programmable gate array chip is used to receive the preprocessed image data, and when multiple continuous synchronization signals of the image data are in the same state, the multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted to the display unit based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel valid signal;

[0009] The display unit is used to receive and display the image data.

[0010] Beneficial effects: During the use of the endoscope, the optical signal is collected by the image sensor, and the optical signal is transmitted to the first field programmable gate array chip through the first target transmission protocol, ensuring that the optical signal can be stably and orderly transmitted from the image sensor to the first FPGA chip. The optical signal from the image sensor is received by the first FPGA chip, and the optical signal is converted into image data; the image data is then preprocessed to improve the image quality, so as to facilitate better subsequent processing and display. The preprocessed image data will be transmitted to the second FPGA chip by the first FPGA chip. When receiving the preprocessed image data, the second FPGA chip will pay attention to the synchronization signal in the image data. When multiple continuous synchronization signals are detected to be in the same state, the multiple continuous synchronization signals will be packaged to form a synchronization signal group; so as to more effectively utilize the synchronization signal information and improve the efficiency and accuracy of image data transmission. After the synchronization signal group is formed, the second FPGA chip will transmit the image data to the display unit according to the synchronization signal group.

[0011] The display unit receives the image data transmitted from the second FPGA chip, and displays the corresponding pixel points on the display unit according to the color, brightness and other information of each pixel in the image data, thereby presenting a complete image, allowing the user to intuitively observe the image information of the object detected by the endoscope. The endoscope image display system provided by the present invention reduces the possibility of image display abnormality caused by interference or error of a single synchronization signal by packaging multiple continuous synchronization signals to form a synchronization signal group, and transmits multiple lines of data according to the synchronization signal group, which can stably transmit image data and maintain the continuity of image data transmission, thereby improving the stability and display effect of image display in the endoscope image display system.

[0012] In an optional implementation, the first field programmable gate array chip includes:

[0013] The first receiving module is used to receive the optical signal, convert the optical signal into a voltage signal and amplify the voltage signal; and perform digital-to-analog conversion on the amplified voltage signal to obtain the image data.

[0014] In an optional implementation, the first field programmable gate array chip further includes:

[0015] A first image processing module, configured to convert the current timing of the image data into a video graphics array timing;

[0016] The first image processing module is also used to preprocess image data whose current timing is the video graphics array timing, and the preprocessing includes analyzing and optimizing the image resolution, image refresh rate, image noise, image white balance, image brightness, and image red, green, and blue saturation of the image data.

[0017] In an optional implementation, the first field programmable gate array chip further includes: a first sending module, the first sending module including a first physical layer, a first data link layer and a first application layer;

[0018] The first physical layer is used to provide a first transmission channel based on a second target transmission protocol;

[0019] The first application layer is used to transmit the pre-processed image data to the first data link layer in sequence through the first transmission channel;

[0020] The first data link layer is used to encode the image data based on a preset encoding format, and transmit the encoded image data to the second field programmable gate array chip through the first transmission channel.

[0021] In an optional implementation, the second field programmable gate array chip includes: a second receiving module, the second receiving module includes a second physical layer, a second data link layer and a second application layer;

[0022] The second physical layer is used to provide a second transmission channel based on a second target transmission protocol;

[0023] The second data link layer is used to receive the encoded image data based on the second transmission channel, and decode the image data and transmit it to the second application layer;

[0024] The second application layer is used to transmit the decoded image data in sequence based on the second transmission channel.

[0025] In an optional implementation, the second field programmable gate array chip further includes:

[0026] A second image processing module is used to receive the decoded image data, detect whether a plurality of continuous synchronization signals of the image data are in the same state, and if so, pack the plurality of continuous synchronization signals into a synchronization signal group; and transmit the image data based on the synchronization signal group;

[0027] The second image processing module is further used to perform image processing on the image data transmitted based on the synchronization signal group, and the image processing includes image recognition, image feature extraction, image enhancement, image resolution adjustment and image filtering.

[0028] In an optional implementation, the second field programmable gate array chip further includes:

[0029] The second sending module is used to convert the image data after image processing into a target timing and then send it to the display unit.

[0030] In a second aspect, the present invention further provides an endoscopic image display method, comprising:

[0031] collecting optical signals during use of the endoscope, and transmitting the optical signals based on a first target transmission protocol;

[0032] receiving the optical signal and converting the optical signal into image data, and preprocessing the image data;

[0033] In response to the preprocessed image data, when multiple continuous synchronization signals of the image data are in the same state, multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel valid signal;

[0034] The image data is received and displayed on a display unit.

[0035] In a third aspect, the present invention further provides an electronic device, comprising: a memory, a processor, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus;

[0036] The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the endoscopic image display method as described above.

[0037] In a fourth aspect, the present invention further provides a computer-readable storage medium, wherein at least one executable instruction is stored in the storage medium. When the executable instruction is executed on the electronic device / endoscopic image display system, the electronic device / endoscopic image display system executes the endoscopic image display method as described above.

[0038] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to more clearly understand the technical means of the embodiment of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 is a structural schematic diagram of an endoscope image display system provided by an embodiment of the present invention;

[0041] Figure 2 It is a flowchart of an endoscope image display method provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a video graphics array timing of an image provided by an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of an encoding format of image data provided by an embodiment of the present invention;

[0044] Figure 5 It is a schematic diagram of the structure of an embodiment of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0046] like Figure 1 As shown, an embodiment of the present invention provides an endoscope image display system, including: an image sensor 100, a first field programmable gate array chip 200, a second field programmable gate array chip 300 and a display unit 400; the image sensor 100 is used to collect optical signals during the use of the endoscope, and transmit the optical signals to the first field programmable gate array chip 200 based on the first target transmission protocol; the first field programmable gate array chip 200 is used to receive the optical signal, convert the optical signal into image data, and pre-process the image data, and transmit the pre-processed image data to the second field programmable gate array chip 300; the second field programmable gate array chip 300 is used to receive the pre-processed image data, and when multiple continuous synchronization signals of the image data are in the same state, the multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted to the display unit 400 based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel effective signal; the display unit 400 is used to receive and display the image data.

[0047] In this embodiment, during the use of the endoscope, an optical signal is collected by the image sensor 100; wherein the optical signal may come from the light reflected from the surface of an object detected by the endoscope head. For example, in a gastrointestinal endoscopy in the medical field, the image sensor 100 will capture the light reflected by the tissue inside the gastrointestinal tract, thereby obtaining visual information of the corresponding part. After the image sensor 100 collects the optical signal, the optical signal is transmitted to the first FPGA chip 200 through the first target transmission protocol. In order to achieve efficient and accurate transmission, the first target transmission protocol may be a mobile industry processor interface (MIPI). The MIPI transmission protocol specifies the parameters such as the data format, transmission rate, and synchronization mode of the optical signal during the transmission process, ensuring that the optical signal can be transmitted from the image sensor 100 to the first FPGA chip 200 in a stable and orderly manner.

[0048] The first FPGA chip 200 receives the optical signal from the image sensor 100 and converts the optical signal into image data; the image data is then preprocessed to improve the image quality for better subsequent processing and display. The preprocessed image data will be transmitted to the second FPGA chip 300 by the first FPGA chip 200. When receiving the preprocessed image data, the second FPGA chip 300 will pay attention to the synchronization signal in the image data. When multiple continuous synchronization signals are detected to be in the same state, the multiple continuous synchronization signals will be packaged to form a synchronization signal group; so as to more effectively utilize the synchronization signal information and improve the efficiency and accuracy of image data transmission. After forming the synchronization signal group, the second FPGA chip 300 will transmit the image data to the display unit 400 according to the synchronization signal group.

[0049] The display unit 400 receives the image data transmitted by the second FPGA chip 300, and displays the corresponding pixel points on the display unit 400 according to the color, brightness and other information of each pixel in the image data, thereby presenting a complete image, allowing the user to intuitively observe the image information of the object detected by the endoscope. The display unit 400 can be a display device such as a liquid crystal display (LCD) and an organic light emitting diode display (OLED).

[0050] The endoscopic image display system provided by the present invention packages multiple continuous synchronization signals to form a synchronization signal group, and transmits multiple lines of data according to the synchronization signal group, thereby reducing the possibility of image display abnormalities caused by interference or errors in a single synchronization signal, and can stably transmit image data and maintain the continuity of image data transmission, thereby improving the stability and display effect of image display in the endoscopic image display system.

[0051] In one embodiment, the first field programmable gate array chip 200 includes: a first receiving module, used to receive an optical signal, convert the optical signal into a voltage signal and amplify the voltage signal; and perform digital-to-analog conversion on the amplified voltage signal to obtain image data.

[0052] In this embodiment, after the first receiving module receives the light signal transmitted by the image sensor 100, the first receiving module converts the received light signal into a voltage signal. Since the voltage signal obtained after the conversion is very weak, it is difficult to directly process and transmit effectively. Therefore, the first receiving module is required to amplify the voltage signal, and amplify the weak voltage signal according to a certain multiple so that its amplitude reaches the range required for subsequent processing, thereby improving the strength and processability of the signal. After processing the amplified voltage signal, the voltage signal is converted into image data in the form of a digital signal through digital-to-analog conversion. Digital-to-analog conversion converts a continuous analog voltage signal into a discrete digital signal according to a certain sampling frequency and quantization accuracy. Then the digital signal is organized in the form of a pixel matrix to form complete image data. The image data after digital-to-analog conversion can represent the color, brightness and other information of each pixel in the image, providing a basis for subsequent image display, processing and analysis.

[0053] In one embodiment, the first field programmable gate array chip 200 also includes: a first image processing module, used to convert the current timing of image data into a video graphics array timing; the first image processing module is also used to preprocess the image data whose current timing is the video graphics array timing, and the preprocessing includes analyzing and optimizing the image resolution, image refresh rate, image noise, image white balance, image brightness, and image red, green, and blue saturation of the image data.

[0054] In this embodiment, after the light signal is converted into image data, the image timing is still the timing of the image sensor 100 itself; due to different sensor specifications, their timing is also inconsistent. In order to maintain the consistency of image data transmission, the current timing of the image data needs to be converted into the video graphics array (VGA) timing. Specifically, according to the requirements of the VGA timing, the line synchronization signal (HS) and the frame synchronization signal (VS) can be regenerated, and the frequency and phase of the pixel clock can be adjusted to make the transmission of the image data match the line and frame structure of the VGA standard. Figure 3 As shown, Figure 3 The VGA timing of a 1080p image. Since there is blanking consumption between lines and frames, and this part consumes no time image data, but it still needs to be transmitted in timing; therefore, transmitting a 1080p picture requires transmitting image data of 2200×1125, in which the pixel value of the invalid area is 0.

[0055] After the timing conversion is completed, the image data with the current timing being the VGA timing is preprocessed to improve the image quality, remove noise, and enhance the features in the image, so as to facilitate the subsequent better processing and display of the image data. The preprocessing includes but is not limited to analyzing and optimizing the image resolution, image refresh rate, image noise, image white balance, image brightness, and image red, green, and blue saturation of the image data.

[0056] In one embodiment, the first field programmable gate array chip 200 also includes: a first sending module, the first sending module includes a first physical layer, a first data link layer and a first application layer; the first physical layer is used to provide a first transmission channel based on a second target transmission protocol; the first application layer is used to transmit the pre-processed image data to the first data link layer through the first transmission channel in sequence; the first data link layer is used to encode the image data based on a preset encoding format, and transmit the encoded image data to the second field programmable gate array chip 300 through the first transmission channel.

[0057] In this embodiment, the first sending module in the first field programmable gate array chip 200 includes a first physical layer, a first data link layer and a first application layer. A first transmission channel based on a second target transmission protocol is provided through the first physical layer, and the second target transmission protocol can be LVDS. The first application layer transmits the pre-processed image data through the first transmission channel and transmits the image data to the first data link layer in sequence from the upper left corner of the image, from left to right, from top to bottom. The first data link layer adopts 24-bit JEIDA encoding, and the encoding format of the image data is as follows: Figure 4 As shown, DE is the pixel valid signal. When the sending pixel is in the c and h areas, DE=1, otherwise it is 0; VS is the frame synchronization signal. When the sending pixel is in the f area, VS=1, otherwise it is 0; HS is the line synchronization signal. When the sending pixel is in the a area, HS=1, otherwise it is 0; R[7:0] is the red pixel data of the image; G[7:0] is the green pixel channel of the image; B[7:0] is the blue pixel channel of the image.

[0058] In one embodiment, the second field programmable gate array chip 300 includes: a second receiving module, the second receiving module includes a second physical layer, a second data link layer and a second application layer; the second physical layer is used to provide a second transmission channel based on a second target transmission protocol; the second data link layer is used to receive encoded image data based on the second transmission channel, and decode the image data and transmit it to the second application layer; the second application layer is used to transmit the decoded image data based on the second transmission channel and in sequence.

[0059] In this embodiment, the second receiving module of the second field programmable gate array chip 300 includes a second physical layer, a second data link layer and a second application layer. The second physical layer also creates a second transmission channel based on the LVDS transmission protocol to ensure that the image data can be correctly transmitted between the first field programmable gate array chip 200 and the second field programmable gate array chip 300. The second data link layer receives the encoded image data through the second transmission channel, and further decodes the image data to obtain 28-bit image data, so as to facilitate the subsequent further processing of the image data. The second data link layer transmits the decoded image data to the second application layer, and the second application layer then transmits the decoded image data to the second image processing module in sequence.

[0060] In one embodiment, the second field programmable gate array chip 300 also includes: a second image processing module, used to receive decoded image data, detect whether multiple continuous synchronization signals of the image data are in the same state, and if so, package the multiple continuous synchronization signals to form a synchronization signal group; transmit the image data based on the synchronization signal group; the second image processing module is also used to perform image processing on the image data transmitted based on the synchronization signal group, and the image processing includes image recognition, image feature extraction, image enhancement, image resolution adjustment and image filtering.

[0061] In this embodiment, after the second image processing module receives the decoded image data transmitted from the second application layer, it cannot determine whether the LVDS transmission channel is normal. Figure 3 The image 2200×1125 shown is represented by the coordinates (y, x); where y is the row coordinate and x is the column coordinate. The data bit width of each pixel in the image data is 28 bits {VS, HS, DE, XX, R[7:0], G[7:0], B[7:0]}, and XX is the don't care data. The coordinates of the first pixel in the upper left corner of the image are (0, 0), and its value is {1, 1, 0, XX, 0, 0, 0}. Assuming that the coordinates of a pixel in the image are (112, 1135), then according to Figure 3 It can be seen that (112, 1135) is in the effective display area, and the value of the pixel is {0, 0, 1, XX, R[7:0], G[7:0], B[7:0]}. If the DE of the pixel originally in the effective area changes from 1 to 0 due to an LVDS transmission error during the image data transmission process, such as the value of the pixel (112, 1135) changes to {0, 0, 0, XX, R[7:0], G[7:0], B[7:0]}, the second image processing module considers the pixel to be an invalid pixel, and an abnormality will occur when displaying the image.

[0062] In order to prevent display abnormalities, the second image processing module detects whether multiple continuous synchronization signals of the received image data are in the same state. If so, multiple continuous synchronization signals are packaged to form a synchronization signal group. For example, when VS is 1 for 10 clock cycles, 10 VS are packaged to form VS_post=1; when VS is 0 for 10 clock cycles, 10 VS are packaged to form VS_post=0; VS_post is used as a frame synchronization signal, and image data is transmitted according to VS_post. Similarly, the processing method of HS and DE signals is the same as that of VS signals. The processed pixel data is {VS_post, HS_post, DE_post, XX, R[7:0], G[7:0], B[7:0]}. The above processing method can maintain the continuity of image data, solve the problem of abnormal display of the back-end caused by a single bit error in LVDS transmission, and effectively utilize the synchronization signal group information to improve the efficiency and accuracy of image data transmission.

[0063] Furthermore, the second image processing module is also used to perform image processing on the image data transmitted based on the synchronization signal group; wherein the image processing includes but is not limited to image recognition, image feature extraction, image enhancement, image resolution adjustment and image filtering, etc., to improve the display effect of the image and facilitate subsequent processing and observation. For example, the image enhancement algorithm can highlight the details and edges of the image; the image filtering process can reduce the noise in the image; and the image resolution adjustment can adapt the image to the resolution requirements of different display units 400.

[0064] In one embodiment, the second field programmable gate array chip 300 further includes: a second sending module, configured to convert the image data after image processing into a target timing sequence and then send the converted image data to the display unit 400 .

[0065] In this embodiment, the image data after image processing needs to be sent to the display unit 400 for display according to a preset output format; wherein, the High Definition Multimedia Interface (HDMI) output format can be selected. The current timing of the processed image data is converted into the HDMI timing, and the image data can be sent to the display unit 400 through the HDMI interface. The HDMI interface uses differential signal transmission technology, which can effectively reduce electromagnetic interference and improve the quality and stability of signal transmission. The second field programmable gate array chip 300 encodes and modulates the converted image data and synchronization signal group according to the provisions of the HDMI protocol, and then transmits them to the receiving end of the display unit 400 through the HDMI cable. The receiving end of the display unit 400 decodes and demodulates the received signal, and correctly displays the image data on the display unit according to the synchronization signal group and the data output format, thereby presenting a high-quality image.

[0066] Second, as Figure 2 As shown, the present invention also provides an endoscope image display method, comprising the following steps:

[0067] Step S100, collecting optical signals during use of the endoscope, and transmitting the optical signals based on a first target transmission protocol;

[0068] Step S200, receiving a light signal and converting the light signal into image data, and preprocessing the image data;

[0069] Step S300, in response to the preprocessed image data, when multiple continuous synchronization signals of the image data are in the same state, the multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel valid signal;

[0070] Step S400 : receiving image data and displaying the image data in the display unit 400 .

[0071] In this embodiment, during the use of the endoscope, an optical signal is collected by the image sensor 100; wherein the optical signal may come from the light reflected from the surface of an object detected by the endoscope head. For example, in a gastrointestinal endoscopy in the medical field, the image sensor 100 will capture the light reflected by the tissue inside the gastrointestinal tract, thereby obtaining visual information of the corresponding part. After the image sensor 100 collects the optical signal, the optical signal is transmitted to the first FPGA chip 200 through the first target transmission protocol. In order to achieve efficient and accurate transmission, the first target transmission protocol may be a mobile industry processor interface (MIPI). The MIPI transmission protocol specifies the parameters such as the data format, transmission rate, and synchronization mode of the optical signal during the transmission process, ensuring that the optical signal can be transmitted from the image sensor 100 to the first FPGA chip 200 in a stable and orderly manner.

[0072] The first FPGA chip 200 receives the optical signal from the image sensor 100 and converts the optical signal into image data; the image data is then preprocessed to improve the image quality for better subsequent processing and display. The preprocessed image data will be transmitted to the second FPGA chip 300 by the first FPGA chip 200. When receiving the preprocessed image data, the second FPGA chip 300 will pay attention to the synchronization signal in the image data. When multiple continuous synchronization signals are detected to be in the same state, the multiple continuous synchronization signals will be packaged to form a synchronization signal group; so as to more effectively utilize the synchronization signal information and improve the efficiency and accuracy of image data transmission. After forming the synchronization signal group, the second FPGA chip 300 will transmit the image data to the display unit 400 according to the synchronization signal group.

[0073] The display unit 400 receives the image data transmitted by the second FPGA chip 300, and displays the corresponding pixel points on the display unit 400 according to the color, brightness and other information of each pixel in the image data, thereby presenting a complete image, allowing the user to intuitively observe the image information of the object detected by the endoscope. The display unit 400 can be a display device such as a liquid crystal display (LCD) and an organic light emitting diode display (OLED).

[0074] The endoscopic image display method provided by the present invention packages multiple continuous synchronization signals to form a synchronization signal group, and transmits multiple lines of data according to the synchronization signal group, thereby reducing the possibility of image display abnormalities caused by interference or errors in a single synchronization signal, and can stably transmit image data and maintain the continuity of image data transmission, thereby improving the stability and display effect of image display in the endoscopic image display system.

[0075] The method and system embodiments in the embodiments of the present application are based on the same application concept.

[0076] In a third aspect, the present invention also provides an electronic device, comprising: a memory, a processor, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the above-mentioned endoscopic image display method.

[0077] like Figure 5 As shown, the electronic device may include: a processor (processor) 502 , a communication interface (Communications Interface) 504 , a memory (memory) 506 , and a communication bus 508 .

[0078] The processor 502, the communication interface 504, and the memory 506 communicate with each other via a communication bus 508. The communication interface 504 is used to communicate with other devices such as a client or other server network elements. The processor 502 is used to execute a program 510, which can specifically execute the relevant steps in the above-mentioned embodiment of the method for displaying an endoscope image.

[0079] Specifically, the program 510 may include program code including computer-executable instructions.

[0080] The processor 502 may be a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the electronic device may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0081] The memory 506 is used to store the program 510. The memory 506 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0082] The program 510 can be specifically called by the processor 502 to enable the electronic device to execute the relevant steps in the above-mentioned embodiment of the method for displaying endoscopic images.

[0083] It can be understood by those skilled in the art that Figure 5 The structure shown is only for illustration and does not limit the structure of the above-mentioned device. Figure 5 More or fewer components as shown, or with Figure 5 Different configurations are shown.

[0084] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, in which at least one executable instruction is stored. When the executable instruction runs on the electronic device / endoscopic image display system, the electronic device / endoscopic image display system executes the above-mentioned endoscopic image display method.

[0085] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system or other device. In addition, the embodiments of the present invention are not directed to any particular programming language.

[0086] In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. Similarly, in order to simplify the present invention and help understand one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Wherein, the claims that follow the specific embodiment are hereby expressly incorporated into the specific embodiment, wherein each claim itself is a separate embodiment of the present invention.

[0087] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and / or processes or units are mutually exclusive.

[0088] It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be understood as limitations on the order of execution.

Claims

1. An endoscope image display system, characterized in that: include: An image sensor, a first field programmable gate array chip, a second field programmable gate array chip and a display unit; The image sensor is used to collect optical signals during the use of the endoscope, and transmit the optical signals to the first field programmable gate array chip based on a first target transmission protocol; The first field programmable gate array chip is used to receive the optical signal, convert the optical signal into image data, pre-process the image data, and transmit the pre-processed image data to the second field programmable gate array chip; The second field programmable gate array chip is used to receive the preprocessed image data, and when multiple continuous synchronization signals of the image data are in the same state, the multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted to the display unit based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel valid signal; The display unit is used to receive and display the image data.

2. The endoscopic image display system according to claim 1, characterized in that: The first field programmable gate array chip comprises: The first receiving module is used to receive the optical signal, convert the optical signal into a voltage signal and amplify the voltage signal; and perform digital-to-analog conversion on the amplified voltage signal to obtain the image data.

3. The endoscopic image display system according to claim 1, characterized in that: The first field programmable gate array chip also includes: A first image processing module, configured to convert the current timing of the image data into a video graphics array timing; The first image processing module is also used to preprocess image data whose current timing is the video graphics array timing, and the preprocessing includes analyzing and optimizing the image resolution, image refresh rate, image noise, image white balance, image brightness, and image red, green, and blue saturation of the image data.

4. The endoscopic image display system according to claim 3, characterized in that: The first field programmable gate array chip further includes: a first sending module, the first sending module including a first physical layer, a first data link layer and a first application layer; The first physical layer is used to provide a first transmission channel based on a second target transmission protocol; The first application layer is used to transmit the pre-processed image data to the first data link layer in sequence through the first transmission channel; The first data link layer is used to encode the image data based on a preset encoding format, and transmit the encoded image data to the second field programmable gate array chip through the first transmission channel.

5. The endoscope image display system according to claim 1, characterized in that: The second field programmable gate array chip includes: a second receiving module, the second receiving module includes a second physical layer, a second data link layer and a second application layer; The second physical layer is used to provide a second transmission channel based on a second target transmission protocol; The second data link layer is used to receive the encoded image data based on the second transmission channel, and decode the image data and transmit it to the second application layer; The second application layer is used to transmit the decoded image data in sequence based on the second transmission channel.

6. The endoscopic image display system according to claim 5, characterized in that: The second field programmable gate array chip also includes: A second image processing module is used to receive the decoded image data, detect whether a plurality of continuous synchronization signals of the image data are in the same state, and if so, pack the plurality of continuous synchronization signals into a synchronization signal group; and transmit the image data based on the synchronization signal group; The second image processing module is further used to perform image processing on the image data transmitted based on the synchronization signal group, and the image processing includes image recognition, image feature extraction, image enhancement, image resolution adjustment and image filtering.

7. The endoscopic image display system according to claim 6, characterized in that: The second field programmable gate array chip also includes: The second sending module is used to convert the image data after image processing into a target timing and then send it to the display unit.

8. An endoscopic image display method, characterized in that: include: collecting optical signals during use of the endoscope, and transmitting the optical signals based on a first target transmission protocol; receiving the optical signal and converting the optical signal into image data, and preprocessing the image data; In response to the preprocessed image data, when multiple continuous synchronization signals of the image data are in the same state, multiple continuous synchronization signals are packaged to form a synchronization signal group, and the image data is transmitted based on the synchronization signal group; the synchronization signal includes a field synchronization signal, a line synchronization signal and a pixel valid signal; The image data is received and displayed on a display unit.

9. An electronic device, characterized in that: include: A memory, a processor, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the endoscope image display method as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The storage medium stores at least one executable instruction, and when the executable instruction is executed on the electronic device / endoscopic image display system, the electronic device / endoscopic image display system executes the endoscopic image display method as described in claim 8.

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