Snapshot type infrared focal plane reading circuit and pixel merging method

Abstract

The invention discloses a snapshot type infrared focal plane reading circuit and a pixel merging method, and the method comprises the steps: enabling at least two pixels in a global pixel array to form a first merging unit, and enabling each pixel in the first merging unit to be provided with a first pixel merging switch; connecting an integral node of each pixel in the first merging unit to a first integral merging connection point through a first pixel merging switch; when the first pixel merging switch is in a first working mode, integral nodes of all pixels in the first merging unit are conducted with a first integral merging connection point, so that voltages at the integral nodes of all pixels in the first merging unit are the same; when the snapshot type infrared focal plane readout circuit reads the pixels in the first merging unit, only the readout signal of one pixel in the first merging unit is read, and other pixels in the first merging unit share the readout signal of one pixel. The dynamic range of the reading circuit can be enlarged, and the frame frequency is improved.

Description

Technical Field

[0001] The invention relates to the field of infrared thermal imaging, and in particular to a snapshot type infrared focal plane readout circuit and a pixel merging method. Background Art

[0002] Large array, small pixel infrared focal plane readout circuit is the development direction of the third generation of infrared detection technology. The pixel scale and spacing directly determine the detection distance and recognition ability. However, as the pixel scale increases and the size decreases, the frame rate of the readout circuit decreases and the dynamic range decreases. Through pixel merging technology, the detection distance, recognition ability, high frame rate, and large dynamic multiple modes can be switched according to the usage scenario.

[0003] There are two main methods for pixel merging in the existing infrared detection readout circuit: the first method is to use an image algorithm to perform weighted merging processing on the signal output by the readout circuit to increase the dynamic range of the image; the second method is to use odd and even row pixel integration capacitor multiplexing, when the odd row is exposed, the integration capacitor of the even row is reused to output the odd row sub-frame, and when the odd row is exposed, the integration capacitor of the even row is reused to output the even row sub-frame, and the sub-frames generated by the two exposures are merged to generate a complete frame information image.

[0004] Although the first pixel merging method mentioned above increases the dynamic range of the readout circuit, the amount of data output by the readout circuit remains unchanged and the frame rate of the detector cannot be increased. The second pixel merging method requires two exposures. Summary of the invention

[0005] In view of the technical defects and technical drawbacks in the prior art, the embodiments of the present invention provide a snapshot infrared focal plane readout circuit that overcomes the above problems or at least partially solves the above problems. The specific solution is as follows:

[0006] As a first aspect of the present invention, a snapshot infrared focal plane readout circuit is provided, comprising a plurality of pixels, each pixel having an integral node, at least two pixels forming a first merging unit, each pixel in the first merging unit having a first pixel merging switch, the integral node of each pixel in the first merging unit being connected to a first integral merging connection point through the first pixel merging switch of the corresponding pixel, the first pixel merging switch being used to connect the integral nodes of all pixels in the first merging unit to the first integral merging connection point in a first working mode, so that the voltages at the integral nodes of all pixels in the first merging unit are the same; when reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel.

[0007] Further, each of the picture elements includes a photodiode, an injection control circuit and a signal readout circuit;

[0008] The photodiode is connected to the integration node through an injection control circuit, and is used to inject the current generated at the photodiode into the integration node to change the voltage at the integration node;

[0009] The signal readout circuit is connected to the integration node and is used for outputting a corresponding readout signal according to the voltage at the integration node.

[0010] Further, the injection control circuit includes a first MOS tube, a second MOS tube, a third MOS tube and a capacitor, the first MOS tube is used as a feedback tube, the second MOS tube is used as an injection tube, and the third MOS tube is used as a reset tube; the signal readout circuit includes a fourth MOS tube and a fifth MOS tube, the fourth MOS tube is used as a follower tube, and the fifth MOS tube is used as a switch tube;

[0011] The positive electrode of the photodiode is connected to the SUBPV signal, and the negative electrode is connected to the drain of the first MOS tube M1; the gate of the first MOS tube is controlled by the feedback tube control signal FB_GPOL, and the source of the first MOS tube is connected to the positive power supply VDD; the source of the second MOS tube is connected to the drain of the first MOS tube, the drain is connected to the integration node, and the gate is controlled by the injection tube control signal GPOL; the source of the third MOS tube is connected to the reset voltage signal VREF, the drain is connected to the integration node, and the gate is controlled by the integration reset signal RST_INT; one end of the capacitor is connected to the integration node, and the other end is grounded; the gate of the fourth MOS tube is connected to the integration node, the source is connected to the positive power supply VDD, and the drain is connected to the source of the fifth MOS tube; the drain of the fifth MOS tube is connected to the PLX_OUT signal, and the gate is connected to the row selection valid signal.

[0012] Further, each pixel has a first pixel merging switch, and the global pixel array of M0×N0 is divided into multiple M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, and each M1×N1 pixel array serves as a first merging unit. There are multiple first integral merging connection points, and each first merging unit corresponds to a first integral merging connection point. The integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel;

[0013] Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

[0014] Furthermore, dividing the global pixel array into a plurality of M×N pixel arrays includes:

[0015] Divide the global pixel array into multiple 1×2 pixel arrays;

[0016] Alternatively, the global pixel array is divided into multiple 2×2 pixel arrays;

[0017] Alternatively, the global pixel array is divided into multiple 4×4 pixel arrays.

[0018] Furthermore, at least two first merging units constitute a second merging unit, each first merging unit in the second merging unit has a second pixel merging switch, the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point through the second pixel merging switch of the corresponding first merging unit, and the second pixel merging switch is used to connect the first integral merging connection points of all the first merging units in the second merging unit with the second integral merging connection point in the first working mode, so that the voltages at the first integral merging connection points of all the first merging units in the second merging unit are the same; when reading the pixels in each second merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel.

[0019] Further, the M2×N2 first merging unit array is divided into a plurality of M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array includes M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, there are a plurality of second integral merging connection points, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through the second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel;

[0020] Among them, M2 is an integer multiple of M3, and N2 is an integer multiple of N3.

[0021] As a second aspect of the present invention, a snapshot infrared focal plane readout circuit pixel merging method is provided, the method comprising:

[0022] At least two pixels in the global pixel array form a first merging unit, and each pixel in the first merging unit is configured with a first pixel merging switch;

[0023] Connecting the integration node of each pixel in the first merging unit to the first integration merging connection point through the first pixel merging switch of the corresponding pixel;

[0024] When the first pixel merging switch is in the first working mode, the integral nodes of all pixels in the first merging unit are connected to the first integral merging connection point, so that the voltages at the integral nodes of all pixels in the first merging unit are the same;

[0025] When reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels.

[0026] Furthermore, each pixel has a first pixel merging switch, and the method further includes:

[0027] The global pixel array of M0×N0 is divided into a plurality of M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, each M1×N1 pixel array serves as a first merging unit, there are a plurality of first integral merging connection points, each of the first merging units corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all the pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels;

[0028] Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

[0029] Further, the method also includes: dividing the M2×N2 first merging unit array into multiple M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array includes M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through the second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel;

[0030] Among them, M2 is an integer multiple of M3, and N2 is an integer multiple of N3.

[0031] The present invention has the following beneficial effects:

[0032] The present invention can reduce the number of times of reading out signals, and realize various pixel merging modes such as 1×2, 2×2, and 4×4 with 4×4 pixels as a unit. For example, when 2×2 pixels are merged, one pixel shares the integral capacitor of the other three pixels, the charge storage capacity is expanded four times, and the amount of read data is reduced four times; when 4×4 pixels are merged, one pixel shares the integral capacitor of the other fifteen pixels, the charge storage capacity is expanded sixteen times, and the amount of read data is reduced sixteen times. The pixel merging method of the infrared focal plane readout circuit of the present invention can increase the dynamic range of the readout circuit and improve the frame rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of a frame of a snapshot infrared focal plane readout circuit provided by an embodiment of the present invention;

[0034] Figure 2 A circuit framework diagram of a pixel provided by an embodiment of the present invention;

[0035] Figure 3 A circuit schematic diagram of a pixel provided by an embodiment of the present invention;

[0036] Figure 4 A schematic diagram of a second merging unit provided in an embodiment of the present invention

[0037] Figure 5 A flow chart of a pixel merging method for a snapshot infrared focal plane readout circuit provided by an embodiment of the present invention;

[0038] Figure 6 A 4×4 pixel merging structure diagram provided in an embodiment of the present invention;

[0039] Figure 7 A 4×4 pixel merging circuit diagram provided by an embodiment of the present invention;

[0040] Figure 8 A timing diagram of a readout circuit provided by an embodiment of the present invention;

[0041] Fig. 9 This is a graph of pixel circuit integration provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described target changes, the relative positional relationship may also change accordingly.

[0044] In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not all drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0045] Many specific details of the present disclosure are described below to provide a clearer understanding of the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may be implemented without following these specific details.

[0046] A snapshot infrared focal plane readout circuit provided by an embodiment of the present invention comprises a plurality of pixels, each pixel having an integral node, wherein at least two pixels constitute a first merging unit, each pixel in the first merging unit has a first pixel merging switch, the integral node of each pixel in the first merging unit is connected to a first integral merging connection point through the first pixel merging switch of the corresponding pixel, the first pixel merging switch is used to connect the integral nodes of all pixels in the first merging unit to the first integral merging connection point in a first working mode, so that the voltages at the integral nodes of all pixels in the first merging unit are the same, the charge storage capacity in the corresponding merging unit is also expanded by a corresponding multiple due to the number of pixels merged, and the amount of readout data is reduced by a corresponding multiple; when reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels.

[0047] It should be noted that before the snapshot infrared focal plane readout circuit works, it needs to first perform an integration stage and then a readout stage. During the integration stage, only the light-emitting diode and the corresponding circuit of one pixel in the first merging unit are turned on to inject the corresponding current into the integration node.

[0048] Generally, the plurality of pixels are arranged in an array, including M0 rows and N0 columns, that is, a global pixel array of M0×N0.

[0049] Figure 1 A schematic diagram of a snapshot infrared focal plane readout circuit provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, it is a case where four pixels form a first merging unit provided by an embodiment of the present invention. The integration nodes of the four pixels in the first merging unit are connected to the first integration merging connection point through the first pixel merging switch of the corresponding pixel. The first pixel merging switch is a switch circuit. The working mode of the first pixel merging switch includes an on mode (first working mode) and a off mode (second working mode). When the first pixel merging switch is in the on mode, the integration nodes of the four pixels in the first merging unit are all connected to the first integration merging connection point, so that the voltages at the integration nodes of the four pixels in the first merging unit are the same, and the snapshot infrared focal plane readout circuit outputs a corresponding readout signal through the voltage at the integration node. Since the voltages at the integration nodes of the four pixels are the same, the readout signals of the four pixels are also the same. By reading the readout signal of one pixel in the first merging unit, the readout signals of other pixels in the first merging unit can be obtained, thereby reducing the number of readout signals.

[0050] See also Figure 2 As shown, it is a circuit diagram of a pixel provided by an embodiment of the present invention. Optionally, each of the pixel comprises a photodiode, an injection control circuit and a signal readout circuit;

[0051] The photodiode is connected to the integration node through an injection control circuit, and is used to inject the current generated at the photodiode into the integration node to change the voltage at the integration node;

[0052] The signal readout circuit is connected to the integration node and is used for outputting a corresponding readout signal according to the voltage at the integration node.

[0053] See also Figure 3As shown, it is a circuit schematic diagram of a pixel provided by an embodiment of the present invention. Optionally, the injection control circuit includes a first MOS tube K1, a second MOS tube K2, a third MOS tube K3 and a capacitor C, the first MOS tube K1 is used as a feedback tube, the second MOS tube K2 is used as an injection tube, and the third MOS tube K3 is used as a reset tube; the signal readout circuit includes a fourth MOS tube K4 and a fifth MOS tube K5, the fourth MOS tube K4 is used as a follower tube, and the fifth MOS tube K5 is used as a readout tube;

[0054] The positive electrode of the photodiode is connected to the SUBPV signal, and the negative electrode is connected to the drain of the first MOS tube M1; the gate of the first MOS tube is controlled by the feedback tube control signal FB_GPOL, and the source of the first MOS tube is connected to the positive power supply VDD; the source of the second MOS tube is connected to the drain of the first MOS tube, the drain is connected to the integration node, and the gate is controlled by the injection tube control signal GPOL; the source of the third MOS tube is connected to the reset voltage signal VREF, the drain is connected to the integration node, and the gate is controlled by the integration reset signal RST_INT; one end of the capacitor is connected to the integration node, and the other end is grounded; the gate of the fourth MOS tube is connected to the integration node, the source is connected to the positive power supply VDD, and the drain is connected to the source of the fifth MOS tube; the drain of the fifth MOS tube is connected to the PLX_OUT signal (i.e., the output voltage signal), and the gate is connected to the row selection valid signal.

[0055] The first MOS tube K1 , the second MOS tube K2 , the fourth MOS tube K4 and the fifth MOS tube K5 are NMOS tubes, and the third MOS tube K3 is a PMOS tube.

[0056] Preferably, each pixel has a first pixel merging switch, and the global pixel includes M0 rows and N0 columns of pixels, that is, an M0×N0 global pixel array, and the M0×N0 global pixel array is divided into multiple M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, and each M1×N1 pixel array serves as a first merging unit. There are multiple first integral merging connection points, and each first merging unit corresponds to a first integral merging connection point. The integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel;

[0057] Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

[0058] In the implementation of the present invention, three main pixel merging schemes are provided, namely 1×2 pixel merging, 2×2 pixel merging and 4×4 pixel array;

[0059] In the 1×2 pixel merging mode: the global pixel array is divided into multiple 1×2 pixel arrays, that is, each 1×2 pixel array includes 2 pixels, each 1×2 pixel array serves as a first merging unit, there are multiple first integral merging connection points, each first merging unit corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel.

[0060] In the 2×2 pixel merging mode: the global pixel array is split into multiple 2×2 pixel arrays, that is, each 2×2 pixel array includes 4 pixels, each 2×2 pixel array serves as a first merging unit, there are multiple first integral merging connection points, each first merging unit corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel.

[0061] In the 4×4 pixel merging mode, the global pixel array is split into multiple 4×4 pixel arrays, that is, each 4×4 pixel array includes 16 pixels, each 4×4 pixel array serves as a first merging unit, there are multiple first integral merging connection points, each first merging unit corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when reading the pixels in each first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel.

[0062] Preferably, at least two first merging units constitute a second merging unit, each first merging unit in the second merging unit has a second pixel merging switch, the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point through the second pixel merging switch of the corresponding first merging unit, and the second pixel merging switch is used to connect the first integral merging connection points of all the first merging units in the second merging unit with the second integral merging connection point in the first working mode, so that the voltages at the first integral merging connection points of all the first merging units in the second merging unit are the same; when reading the pixels in each second merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel.

[0063] This embodiment is another merging mode provided by the present invention. This merging mode is based on the first merging mode, and the first merging unit is used as a small unit to be merged again to obtain a second merging unit. Figure 4 As shown, the four first merging units are merged again through the second pixel merging switch to obtain a second merging unit. When the second pixel merging switch is in the first working mode, the voltages at the four first integral merging connection points are made the same through the second integral merging connection point, and the voltage at the integral node of each pixel in the first merging unit is the same as the voltage at the corresponding first integral merging connection point, so that the voltages at the integral nodes of the 16 pixels are the same.

[0064] Preferably, the M2×N2 first merging unit array is divided into a plurality of M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array includes M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, there are a plurality of second integral merging connection points, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through the second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel;

[0065] Among them, M2 is an integer multiple of M3, N2 is an integer multiple of N3, for example, M2 and N2 are both 4, M1 and N1 are 2, M3 and N3 are also 2, that is, the M2×N2 first merging unit array includes 16 first merging units, each first merging unit includes 4 pixels, and the M3×N3 first merging unit array includes 4 first merging units, that is, the second merging unit includes 4 first merging units.

[0066] As shown in Figure 5, an embodiment of the present invention further provides a snapshot infrared focal plane readout circuit pixel merging method, the method comprising:

[0067] At least two pixels in the global pixel array form a first merging unit, and each pixel in the first merging unit is configured with a first pixel merging switch;

[0068] Connecting the integration node of each pixel in the first merging unit to the first integration merging connection point through the first pixel merging switch of the corresponding pixel;

[0069] When the first pixel merging switch is in the first working mode, the integral nodes of all pixels in the first merging unit are connected to the first integral merging connection point, so that the voltages at the integral nodes of all pixels in the first merging unit are the same;

[0070] When reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels.

[0071] Preferably, each pixel has a first pixel merging switch, and the method further comprises:

[0072] The global pixel array of M0×N0 is divided into a plurality of M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, each M1×N1 pixel array serves as a first merging unit, there are a plurality of first integral merging connection points, each of the first merging units corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all the pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels;

[0073] Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

[0074] In the above embodiment, the M0×N0 global pixel array is divided into a plurality of M1×N1 pixel arrays, and only one pixel readout signal needs to be read in each M1×N1 pixel array, thereby reducing the number of pixel readouts exponentially.

[0075] Preferably, the method further comprises: dividing the M2×N2 first merging unit array into a plurality of M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array comprises M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through a second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel;

[0076] Among them, M2 is an integer multiple of M3, and N2 is an integer multiple of N3

[0077] In the above embodiment, a plurality of first merging units are merged again into a second merging unit, thereby further reducing the number of times of pixel readout.

[0078] See also Figure 6 As shown, it is a 4×4 pixel merging structure diagram provided in an embodiment of the present invention. In this embodiment, the infrared focal plane readout circuit has a full-frame integration mode, a 2×2 pixel merging mode, and a 4×4 pixel merging mode. All three modes are snapshot exposures, and the readout circuit uses 4×4 pixels as a unit.

[0079] The exposure of 16 pixels in each unit is controlled by GPOL<0:2> and FB_GPOL<0:2>, where GPOL<0:2> and FB_GPOL<0:2> are reciprocal signals. <0> 、FB_GPOL <0> is the integral control signal of pixel 1, GPOL <1> 、FB_GPOL <1> is the integral control signal of pixel 2, 4, 5, 6, 7, 8, 10, 12, 13, 14, 15, 16, GPOL <2> 、FB_GPOL <2> is the integration control signal of pixels 3, 9, and 11. When integrating the full frame, 16 pixels are integrated uniformly and read out separately. In the 2×2 pixel merging mode, pixel 1 shares the integration capacitors of pixels 2, 5, and 6; pixel 3 shares the integration capacitors of pixels 4, 7, and 8; pixel 9 shares the integration capacitors of pixels 10, 13, and 14; pixel 11 shares the integration capacitors of pixels 12, 15, and 16; in the 4×4 pixel merging mode, pixel 1 shares the integration capacitors of pixels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16.

[0080] See also Figure 7 As shown, it is a 4×4 pixel merging circuit diagram provided by an embodiment of the present invention. In the embodiment of the present invention, the first pixel merging switch and the second pixel merging switch are both composed of two MOS tubes connected in parallel, one of which is an NMOS tube controlled by BIN2_N and BIN4_N signals, and the other is a PMOS tube controlled by BIN2_P and BIN4_P signals; the working mode of the first pixel merging switch is controlled by BIN2_P and BIN2_N signals, and the working mode of the second pixel merging switch is controlled by BIN4_P and BIN4_N signals. In this embodiment, the first integral merging connection point is also grounded through a MOS tube controlled by the BIN2_P signal, and the first integral merging connection point is also grounded through another MOS tube controlled by the BIN4_P signal:

[0081] In full-frame integration mode: BIN2_P is pulled high, BIN2_N is pulled low, BIN4_P is pulled high, BIN4_N is pulled low, the first and second pixel merging switches are turned off, the integration merging connection point is grounded to prevent crosstalk of the integration signal in the 16 pixels. When the pixel is reset, GPOL<0:2> is turned off, FB_GPOL<0:2> is turned on, and the feedback tube forms a path with the photodiode to provide compensation current for the photodiode. When the pixel integration starts, GPOL<0:2> is turned on, FB_GPOL<0:2> is turned off, and all 16 pixels start working. The injection tube enters subthreshold operation and the feedback tube is turned off.

[0082] In the 2×2 pixel merging mode, every 4 pixels are merged together to obtain the first merging unit, which includes a 2×2 pixel array: BIN2_P is pulled low, BIN2_N is pulled high, the 2×2 pixel merging mode is turned on, BIN4_P is pulled high, BIN4_N is pulled low, the second pixel merging switch is turned off, that is, the 4×4 pixel merging mode is turned off, and the integral merging connection point is grounded to prevent crosstalk of the integral signals of pixels 1, 3, 9, and 11. During the frame period, GPOL <1> Close, stop integration of pixels 2, 4, 5, 6, 7, 8, 10, 12, 13, 14, 15, 16, FB_GPOL <1> When it is turned on, the feedback tube provides compensation current for the photodiode to prevent the charge accumulation of the photodiodes of pixels 2, 4, 5, 6, 7, 8, 10, 12, 13, 14, 15, and 16 from causing charge leakage to affect pixels 1, 3, 9, and 11. When the pixel is reset, GPOL <0> GPOL <2> Close, FB_GPOL <0> 、FB_GPOL <2> When the integration starts: GPOL <0> Open, FB_GPOL <0> Close, control pixel 1 integration, GPOL <2> Turn on, control the integration of pixel 3, pixel 9, and pixel 11. The injection tube enters subthreshold operation, the feedback tube is closed, the charge storage capacity is expanded four times, and the readout data volume is reduced four times.

[0083] In the 4×4 pixel merging mode, four 2×2 pixel merging units (i.e., the first merging unit) are merged again through the second pixel merging switch, thereby realizing the merging of 16 pixels and obtaining the second merging unit: BIN2_P and BIN4_P are pulled low, BIN2_N and BIN4_N are pulled high, the second pixel merging switch is turned on, and the first working mode is entered, so that the 4×4 pixel merging mode is turned on. During the frame period, GPOL <1> GPOL <2> Close, pixel 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 stops integration, FB_GPOL <1> 、FB_GPOL <2> When it is turned on, the feedback tube provides compensation current for the photodiode to prevent the charge accumulation of the photodiodes of pixels 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, and 16 from causing charge leakage to affect pixel 1. When the pixel is reset, GPOL <0> Close, FB_GPOL <0> Turn on, the feedback tube provides compensation current for the photodiode, and the injection tube is turned off. When the integration starts: GPOL <0> Open, FB_GPOL <0> Close, control pixel 1 integration. Charge storage capacity is increased sixteen times, and the amount of readout data is reduced sixteen times.

[0084] See also Figure 8 As shown, it is a timing diagram of a readout circuit provided in an embodiment of the present invention. In this embodiment:

[0085] The timing signal of the infrared focal plane readout circuit is defined as:

[0086] INT is the frame cycle signal, which is valid at high level; GPOL<0:2> is the injection tube control signal, which is valid at high level; FB_GPOL<0:2> is the feedback tube control signal, which is valid at high level; RST_INT is the integral reset signal, which is valid at low level; DATAVALID is the frame readout valid mark signal

[0087] ROWSEL<0:M-1> is the row selection valid signal, which is valid at a high level; COLSEL<0:N-1> is the column selection valid signal, which is valid at a high level;

[0088] When the INT signal rises, RST_INT is pulled low, and the pixel begins to reset. To prevent the junction capacitance of the photodiode from redistributing charges with the integration capacitance, 10Tmc before RST_INT is pulled high, GPOL<0:2> is pulled high, FB_GPOL<0:2> is pulled low, the injection tube enters subthreshold operation, the feedback tube is turned off, and the junction capacitance of the photodiode is reset. The rising edge of RST_INT controls the pixel to start integration, and the falling edge of GPOL<0:2> ends the integration. Signal readout is performed after the current frame signal is integrated and before the next frame is integrated.

[0089] Full-frame mode: ROWSEL<0:M-1> is high and effective in turn to read out the pixel integration signal of the current frame row by row. After each row is read out, the next row is read out after a time Trd, until the signals of all pixels in the current frame are read out. During the effective period of each row, the column selection signal COLSEL<0:N-1> reads out each column signal in turn, and each signal read takes one main clock cycle Tmc.

[0090] 2×2 pixel merging mode: ROWSEL <0> , ROWSEL <2> , ROWSEL <4> .......ROWSEL <m-2>The pixel integration signal of the current frame is read out in sequence with high validity. After each row is read out, the next row is read out after a time Trd has passed, until the valid pixel integration signal of the current frame is read out. During the validity period of each row, the column selection signal COLSEL <0> 、COLSEL <2> 、COLSEL <4> .......COLSEL <n-2>The valid column signals are read out in sequence, and each signal read takes one main clock cycle Tmc.

[0091] 4×4 pixel merging mode: ROWSEL <0> , ROWSEL <4> , ROWSEL <8> .......ROWSEL <m-4>The pixel integration signal of the current frame is read out in sequence with high validity. After each row is read out, the next row is read out after a time Trd has passed, until the valid pixel integration signal of the current frame is read out. During the validity period of each row, the column selection signal COLSEL <0> 、COLSEL <4> 、COLSEL <8> .......COLSEL <n-4>The valid column signals are read out in sequence, and each signal read takes one main clock cycle Tmc.

[0092] According to the pixel integration formula,

[0093]

[0094] When the photocurrent remains unchanged, the integral curve area in the same integral time period is inversely proportional to the integral capacitance.

[0095]

[0096] As shown in FIG9 , the integral curve simulation results of the three modes show that the integral curve area of ​​the full-frame mode is four times the integral curve area of ​​the 2×2 pixel merging mode and sixteen times the integral curve area of ​​the 4×4 pixel merging mode, satisfying equation (2) and realizing the functions of the full-frame mode, the 2×2 pixel merging mode, and the 4×4 pixel merging mode.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A snapshot infrared focal plane readout circuit, comprising a plurality of pixels, each pixel having an integration node, characterized in that: At least two pixels form a first merging unit, each pixel in the first merging unit has a first pixel merging switch, the integral node of each pixel in the first merging unit is connected to the first integral merging connection point through the first pixel merging switch of the corresponding pixel, and the first pixel merging switch is used to connect the integral nodes of all pixels in the first merging unit to the first integral merging connection point in a first working mode, so that the voltages at the integral nodes of all pixels in the first merging unit are the same; when reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel.

2. The snapshot infrared focal plane readout circuit according to claim 1, characterized in that: Each of the picture elements includes a photodiode, an injection control circuit and a signal readout circuit; The photodiode is connected to the integration node through an injection control circuit, and is used to inject the current generated at the photodiode into the integration node to change the voltage at the integration node; The signal readout circuit is connected to the integration node and is used for outputting a corresponding readout signal according to the voltage at the integration node.

3. The snapshot infrared focal plane readout circuit according to claim 2, characterized in that: The injection control circuit includes a first MOS tube, a second MOS tube, a third MOS tube and a capacitor, the first MOS tube is used as a feedback tube, the second MOS tube is used as an injection tube, and the third MOS tube is used as a reset tube; the signal readout circuit includes a fourth MOS tube and a fifth MOS tube, the fourth MOS tube is used as a follower tube, and the fifth MOS tube is used as a switch tube; The positive electrode of the photodiode is connected to the SUBPV signal, and the negative electrode is connected to the drain of the first MOS tube M1; the gate of the first MOS tube is controlled by the feedback tube control signal FB_GPOL, and the source of the first MOS tube is connected to the positive power supply VDD; the source of the second MOS tube is connected to the drain of the first MOS tube, the drain is connected to the integration node, and the gate is controlled by the injection tube control signal GPOL; the source of the third MOS tube is connected to the reset voltage signal VREF, the drain is connected to the integration node, and the gate is controlled by the integration reset signal RST_INT; one end of the capacitor is connected to the integration node, and the other end is grounded; the gate of the fourth MOS tube is connected to the integration node, the source is connected to the positive power supply VDD, and the drain is connected to the source of the fifth MOS tube; The drain of the fifth MOS tube is connected to the PLX_OUT signal, and the gate is connected to the row selection valid signal.

4. The snapshot infrared focal plane readout circuit according to claim 1, characterized in that: Each pixel has a first pixel merging switch, and the global pixel array of M0×N0 is divided into multiple M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, and each M1×N1 pixel array serves as a first merging unit. There are multiple first integral merging connection points, and each first merging unit corresponds to a first integral merging connection point. The integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one pixel; Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

5. The snapshot infrared focal plane readout circuit according to claim 4, characterized in that: Dividing the global pixel array into multiple M×N pixel arrays includes: Divide the global pixel array into multiple 1×2 pixel arrays; Alternatively, the global pixel array is divided into multiple 2×2 pixel arrays; Alternatively, the global pixel array is divided into multiple 4×4 pixel arrays.

6. The snapshot infrared focal plane readout circuit according to claim 4, characterized in that: At least two first merging units constitute a second merging unit, each first merging unit in the second merging unit has a second pixel merging switch, the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point through the second pixel merging switch of the corresponding first merging unit, and the second pixel merging switch is used to connect the first integral merging connection points of all the first merging units in the second merging unit with the second integral merging connection point in a first working mode, so that the voltages at the first integral merging connection points of all the first merging units in the second merging unit are the same; when reading the pixels in each second merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel.

7. The snapshot infrared focal plane readout circuit according to any one of claim 6, characterized in that: The M2×N2 first merging unit array is divided into a plurality of M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array includes M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, there are a plurality of second integral merging connection points, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through the second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one of the pixels; Among them, M2 is an integer multiple of M3, and N2 is an integer multiple of N3.

8. A snapshot infrared focal plane readout circuit pixel merging method, characterized in that: The method comprises: At least two pixels in the global pixel array form a first merging unit, and each pixel in the first merging unit is configured with a first pixel merging switch; Connecting the integration node of each pixel in the first merging unit to the first integration merging connection point through the first pixel merging switch of the corresponding pixel; When the first pixel merging switch is in the first working mode, the integral nodes of all pixels in the first merging unit are connected to the first integral merging connection point, so that the voltages at the integral nodes of all pixels in the first merging unit are the same; When reading the pixels in the first merging unit, the snapshot infrared focal plane readout circuit only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels.

9. The pixel merging method of the snapshot infrared focal plane readout circuit according to claim 8, characterized in that: Each pixel has a first pixel merging switch, and the method further includes: The global pixel array of M0×N0 is divided into a plurality of M1×N1 pixel arrays, that is, each M1×N1 pixel array includes M1×N1 pixels, each M1×N1 pixel array serves as a first merging unit, there are a plurality of first integral merging connection points, each of the first merging units corresponds to a first integral merging connection point, and the integral node of each pixel in the first merging unit is connected to the first integral merging connection point corresponding to the first merging unit through the first pixel merging switch of the corresponding pixel, so that when the first pixel merging switch is in the first working mode, the voltages at the integral nodes of all the pixels in each first merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each first merging unit, it only reads the readout signal of one of the pixels in the first merging unit, and the other pixels in the first merging unit share the readout signal of the one of the pixels; Among them, M0 is an integer multiple of M1, and N0 is an integer multiple of N1.

10. The pixel merging method of the snapshot infrared focal plane readout circuit according to claim 9, characterized in that: The method further includes: dividing the M2×N2 first merging unit array into a plurality of M3×N3 first merging unit arrays, that is, each M3×N3 first merging unit array includes M3×N3 first merging units, each M3×N3 first merging unit array serves as a second merging unit, each second merging unit corresponds to a second integral merging connection point, and the first integral merging connection point of each first merging unit in the second merging unit is connected to the second integral merging connection point corresponding to the second merging unit through a second pixel merging switch corresponding to the first merging unit, so that when the second pixel merging switch is in the first working mode, the voltages at the first integral merging connection points of all the first merging units in each second merging unit are the same; when the snapshot infrared focal plane readout circuit reads the pixels in each second merging unit, it only reads the readout signal of one of the pixels in the second merging unit, and the other pixels in the second merging unit share the readout signal of the one pixel; Among them, M2 is an integer multiple of M3, and N2 is an integer multiple of N3.

Images