Reflective memory data exchange fault node identification and error correction system based on FPGA (Field Programmable Gate Array)

Abstract

The invention relates to a reflective memory data exchange fault node identification and error correction system based on an FPGA (Field Programmable Gate Array). The system comprises a set of FPGA software program; the FPGA software program comprises a GTX reflection memory data coding and decoding module, a looped network forwarding control module, a channel reset monitoring module, a delay error correction module and a packet number and packet length monitoring module, and is used for realizing the functions of core algorithm logic control, arbitrary channel receiving and forwarding of reflection memory data and the like. According to the invention, the fault node identification and error correction functions in the reflective memory looped network link can be realized through a software algorithm under the FPGA.

Description

Technical Field

[0001] The present invention belongs to the technical field of reflective memory network, and relates to a reflective memory data exchange fault node identification and error correction system, in particular to a reflective memory data exchange fault node identification and error correction system based on FPGA. Background Art

[0002] Reflective memory network is a real-time network that uses a replication and shared storage mechanism to achieve data transmission. Multiple modules on the same reflective memory network can share and access public storage space. It has low transmission delay and high transmission speed. It is mainly used in distributed real-time systems in fields such as navigation. Reflective memory network is generally composed of multiple reflective memory interface modules and reflective memory exchange modules. The reflective memory interface module is used to realize data transmission and protocol architecture construction between the reflective memory interface and the public storage space, and the reflective memory exchange module is used to realize data transmission and exchange networking between multiple reflective memory interface modules.

[0003] At present, there are relatively mature commercial modules for reflective memory networks in the domestic and foreign markets, but the reflective memory data exchange part is basically realized through dedicated interface chips developed by companies such as GE VMIC. Reflective memory data exchange technology is mainly used in reflective memory exchange modules to realize the interface implementation and exchange networking of multi-channel data. The dedicated interface chip implements complex control logic and channel error correction processing through a large number of logic gates, and integrates them into a chip for solidification. When using it, you only need to connect its hardware interface to realize the corresponding reflective memory data exchange function. However, there are currently no manufacturers of dedicated interface chips that realize related functions in China, and because its functions have been solidified, it is impossible to realize customized functions, and the flexibility of application is also greatly restricted.

[0004] The internal control of the reflective memory interface module is mainly implemented through FPGA, and FPGA has powerful logic control functions and extremely high flexibility. Therefore, implementing reflective memory data exchange technology through FPGA is an important way to achieve the system-level design of reflective memory network. Since there is no integrated reflective memory data exchange control module inside the FPGA, the identification and error correction of faulty nodes during the reflective memory data exchange process need to be implemented through software algorithms.

[0005] Under the current situation, higher requirements are put forward for independent design capabilities at both the system level and the module level. At present, the domestic independently designed reflective memory data exchange technology is still in a semi-blank stage and cannot meet the increasingly rich and flexible application requirements. Therefore, the realization of FPGA-based reflective memory data exchange fault node identification and error correction technology will provide more powerful support for the development of reflective memory network communication field, and it is also in line with the general trend of related technology development in the future.

[0006] Therefore, the present invention proposes a reflective memory data exchange fault node identification and error correction system based on FPGA. Summary of the invention

[0007] The purpose of the present invention is to overcome the shortcomings of the prior art and propose a reflective memory data exchange fault node identification and error correction system based on FPGA, which can realize the fault node identification and error correction functions in the reflective memory ring network link through software algorithm under FPGA.

[0008] The present invention solves the practical problem by adopting the following technical solutions:

[0009] A reflective memory data exchange fault node identification and error correction system based on FPGA, including a set of FPGA software programs; the FPGA software program includes: a GTX reflective memory data encoding and decoding module, a ring network forwarding control module, a channel reset monitoring module, a delay error correction module and a packet number and length monitoring module, which are used to realize the core algorithm logic control and any channel reception and forwarding of reflective memory data and other functions;

[0010] The GTX reflective memory data encoding and decoding module performs 8B / 10B encoding and decoding through the GTX hard core integrated in the FPGA to realize the conversion of the high-speed serial differential signal and the parallel low-speed signal of the reflective memory data, which is used to realize the subsequent ring network forwarding control and fault node identification and error correction;

[0011] The ring network forwarding control module realizes the timing control of data flow forwarding and the fault node jump error correction control through the jump algorithm;

[0012] The channel reset monitoring module implements the initialization configuration of all variables through the reset algorithm and recognizes the plugging and unplugging of external optical fiber hardware to realize the clock reset error correction control of the GTX channel fault node;

[0013] The delay error correction module implements error correction control of the erroneous data bits of the faulty node by gating and assigning values ​​to the intermediate variables;

[0014] The packet number and length monitoring module implements data packet counting statistics and packet length detection statistics through a packet number and length matching algorithm, and compares them with the communication protocol to determine whether there is a faulty node during data transmission in the ring network, and can directly identify the location of the faulty node based on the flag variable.

[0015] Moreover, the output end of the GTX reflective memory data encoding and decoding module is respectively connected to the input end of the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, and is used to output the external optical fiber link input data to the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module;

[0016] The output end of the channel reset monitoring module is respectively connected to the input end of the GTX reflective memory data encoding and decoding module, the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, so as to output the control signal to the above four processing modules;

[0017] The output end of the delay error correction module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the error-corrected data to the external optical fiber link through the GTX reflective memory data encoding and decoding module;

[0018] The output end of the packet number and length monitoring module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the normal or abnormal state of the data to the GTX reflective memory data encoding and decoding module.

[0019] Moreover, the GTX reflective memory data encoding and decoding module is implemented by the 8B / 10B encoding and decoding hard core integrated in the FPGA, which is used to realize the conversion of high-speed serial differential signals and parallel low-speed signals of reflective memory data; wherein, the data transmission rate is set to 2.125Gbps, and the clock synchronization design is considered; an 8-channel design is adopted, so 8 IP cores need to be instantiated to configure 8 independent GTX channels, wherein the basic configuration parameters of the 8 GTX channels are consistent; the 8 channels all use the CPLL in the same bank as the reference clock; the reference clock of the transceiver channel is set to the same TXOUTCLK; the 8 GTX reference clocks are all set to the same clock, that is, the GTX reference clock output by the first GTX channel.

[0020] Moreover, the ring network forwarding control module is implemented by designing a jump algorithm inside the FPGA, which is used for the timing control of data flow forwarding and the jump error correction control of the reflective memory network fault node; the node N may be any node from 0 to 7, and the 8 channels work in parallel. If the 8 channels are all normal nodes, the forwarding of the 8 channels is carried out simultaneously; the module can realize two functions: ring network forwarding of data packets for normal node channels and identification and jump of faulty node channels; when the data flow is transferred to the ring network forwarding control module, the working status of each node will be determined first by three flag bits, and the three flag bits are: the receiving signal detection indication signal output by the photoelectric conversion device in the hardware circuit, which is used to indicate whether a normal hardware link has been established between the corresponding channel receiving end and the external device; the RX_NOTINTABLE signal and RX_DISPERR signal output by the GTX channel IP core, which are used to indicate whether there are abnormalities in the receiving end 8B / 10B encoding and optical fiber link data transmission protocol. When any flag bit in a channel is abnormal, the channel is judged as a faulty node channel, its status indicator light is turned off, the input data of the channel is not accepted during the data forwarding process, and the channel jumps to the next node channel. When the flag bits of one or some channels are normal, the corresponding channel is judged as a normal node channel, and its corresponding status indicator light is turned on. When the status indicator light of one or some node channel N is normal, and there is external input data in the corresponding channel, the input data will be directly forwarded to the sending end of the next adjacent node (i.e., N+1 node) for sending. The external connection devices of this module are all reflective memory interface modules. The external reflective memory interface module will send the message received by its receiving end that complies with the data transmission protocol from the sending end back to the receiving channel of the same node (i.e., N+1 node) as is. At this time, if the N+1 node status indicator is on, the data sent back by the external reflective memory interface module will be forwarded again to the sending end of the next adjacent node (i.e., the N+2 node) for sending, and forwarded step by step until it returns to the original N node; if the N+1 node status indicator is off, the message sent back by the external reflective memory interface module received by the node will not be accepted, but the data of the sending end of the previous normal node (i.e., the N node) will be forwarded again to the sending end of the next adjacent node (i.e., the N+2 node) for sending, and forwarded step by step until it returns to the original N node; if all 8 channels are normal nodes, there will be a situation where the 8 channels receive input data at the same time, and the above judgment and forwarding are performed synchronously.

[0021] Moreover, the channel reset monitoring module is implemented by designing a reset algorithm inside the FPGA to realize clock reset error correction control; the module can realize two functions: initialization configuration of all variables and reset of single or multiple GTX channels by identifying the plugging and unplugging of optical fibers of photoelectric conversion devices in hardware circuits; when the channel reset monitoring module is powered on, the global reset signal can be pulled low to realize the function of initializing all variables and some parameters in GTX, providing a starting point for logical operation, and during the test process, the global reset signal can also be used to realize the troubleshooting and positioning of abnormal phenomena; in addition to the global reset signal, each GTX IP core also has a corresponding reset signal for resetting the internal state of a single IP core; the channel reset monitoring module adds control of the reset signal of each GTX channel, the GTX channel reset signal is valid on the falling edge, when the external receiving signal detection indication signal identifies the insertion of the optical fiber, the reset signal is set high; when the external receiving signal detection indication signal identifies the removal of the optical fiber, the reset signal is set low. Since the module will perform a global reset after power-on, there is no need to reset the individual GTX channel when the optical fiber is first inserted. When the optical fiber of a channel is unplugged during operation, the falling edge of the corresponding channel reset signal will be triggered, thereby completing the reset of the corresponding GTX channel and initializing its internal clock signal.

[0022] Moreover, the delay error correction module is implemented by designing a delay error correction algorithm inside the FPGA, which is used to realize error correction control of the erroneous data bits of the faulty node of the reflective memory network; the module delays the signal to be forwarded by two clocks, replaces the erroneous data bits with the BCBC idle code, eliminates the erroneous data bits generated in the underlying transmission, and then forwards the modified data normally to the sending end of the next node channel for transmission. Since the conditions for the occurrence of erroneous data bits generated by the underlying transmission are relatively fixed, the erroneous data bits can be screened for each occurrence condition.

[0023] Moreover, the packet number and length monitoring module is implemented by designing a packet number and packet length matching monitoring algorithm inside the FPGA; the packet number detection uses a counter to accumulate and count the data message header and data message tail for a long time, and compares the number of data message headers and tails, the number of messages between each node channel, and the number of external input messages to determine whether there are problems such as wrong packets, packet loss during forwarding, and packet loss during receiving; the packet length detection mainly marks the duration of the data message through a flag variable, counts through a counter, records the actual length of the data message, and compares it with the data message length specified in the data transmission protocol to determine whether there is an error packet problem, and can accurately locate the location of the error packet through the recorded length value, and capture the error message to achieve the location of the error data packet in the faulty node.

[0024] Advantages and beneficial effects of the present invention:

[0025] 1. The present invention proposes a ring network forwarding control module based on a jump algorithm, which can effectively realize the timing control of data stream forwarding in any channel and the jump error correction control of the faulty node in the reflective memory network. The existing technology is realized by an external dedicated interface chip, and the present invention is realized based on the internal algorithm of FPGA;

[0026] 2. The present invention proposes a channel reset monitoring module based on a reset algorithm, which can realize the initialization configuration of all variables and realize the clock reset error correction control of the GTX channel fault node by identifying the plugging and unplugging of external optical fiber hardware. The current existing technology is to realize the variable initialization operation after power-on through a global reset signal. In addition to the global reset signal, the present invention can also realize the clock reset error correction control of the faulty node by resetting the internal clock of the IP core separately;

[0027] 3. The present invention proposes a delay error correction module based on a delay error correction algorithm, which can realize error correction control of erroneous data bits of faulty nodes in a reflective memory network. The existing technology currently uses a delay clock to realize timing reliability in data transmission. The present invention eliminates erroneous data bits generated in the underlying transmission by real-time judgment of erroneous data bits, so as to ensure that the data stream can be correctly transmitted during the forwarding process of a multi-channel ring network;

[0028] 4. The present invention proposes a packet number and packet length monitoring module based on a packet number and packet length matching monitoring algorithm, which can determine in real time whether there is a faulty node in the reflective memory network ring network, and can accurately locate the data bit generated by the faulty node. The existing technology currently performs error data packet inspection through manual protocol comparison or through FPGA real-time simulation function, but since error data packets are often occasional or quickly cause network storms to generate a large number of new error data packets, it is difficult to accurately locate the starting error data packet. The present invention can accurately locate the starting error data bit generated by the faulty node by real-time determination of the number of packets and packet length of the transmitted data, thereby realizing the rapid positioning of the error data packet in the faulty node;

[0029] 5. The present invention has made a breakthrough by using FPGA internal algorithms to replace the currently common dedicated interface chips, and has proposed a new design concept. The current existing technology only realizes related functions through external dedicated interface chips. In the present invention, all functions are integrated in FPGA and realized through the aforementioned related algorithms, which greatly increases the openness and flexibility of reflective memory exchange technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a processing flow chart of the ring network forwarding control module of the present invention;

[0031] Figure 2It is a processing flow chart of the channel reset monitoring module of the present invention;

[0032] Figure 3 It is a processing flow chart of the delay error correction module of the present invention;

[0033] Figure 4 It is a processing flow chart of the packet number monitoring module of the present invention;

[0034] Figure 5 It is a processing flow chart of the packet length monitoring module of the present invention. DETAILED DESCRIPTION

[0035] The embodiments of the present invention are further described in detail below with reference to the accompanying drawings:

[0036] A reflective memory data exchange fault node identification and error correction system based on FPGA, including a set of FPGA software programs; the FPGA software program includes: a GTX reflective memory data encoding and decoding module, a ring network forwarding control module, a channel reset monitoring module, a delay error correction module and a packet number and length monitoring module, which are used to realize the core algorithm logic control and any channel reception and forwarding of reflective memory data and other functions;

[0037] The GTX reflective memory data encoding and decoding module performs 8B / 10B encoding and decoding through the GTX hard core integrated in the FPGA to realize the conversion of the high-speed serial differential signal and the parallel low-speed signal of the reflective memory data, which is used to realize the subsequent ring network forwarding control and fault node identification and error correction;

[0038] The ring network forwarding control module realizes the timing control of data flow forwarding and the fault node jump error correction control through the jump algorithm;

[0039] The channel reset monitoring module implements the initialization configuration of all variables through the reset algorithm and recognizes the plugging and unplugging of external optical fiber hardware to realize the clock reset error correction control of the GTX channel fault node;

[0040] The delay error correction module implements error correction control of the erroneous data bits of the faulty node by gating and assigning values ​​to the intermediate variables;

[0041] The packet number and length monitoring module implements data packet counting statistics and packet length detection statistics through a packet number and length matching algorithm, and compares them with the communication protocol to determine whether there is a faulty node during data transmission in the ring network, and can directly identify the location of the faulty node based on the flag variable.

[0042] The output end of the GTX reflective memory data encoding and decoding module is respectively connected to the input end of the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, and is used to output the external optical fiber link input data to the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module;

[0043] The output end of the channel reset monitoring module is respectively connected to the input end of the GTX reflective memory data encoding and decoding module, the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, so as to output the control signal to the above four processing modules;

[0044] The output end of the delay error correction module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the error-corrected data to the external optical fiber link through the GTX reflective memory data encoding and decoding module;

[0045] The output end of the packet number and length monitoring module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the normal or abnormal state of the data to the GTX reflective memory data encoding and decoding module.

[0046] The output end of the GTX reflective memory data encoding and decoding module is respectively connected to the input end of the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, and is used to output the external optical fiber link input data to the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module;

[0047] The output end of the channel reset monitoring module is respectively connected to the input end of the GTX reflective memory data encoding and decoding module, the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, so as to output the control signal to the above four processing modules;

[0048] The output end of the delay error correction module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the error-corrected data to the external optical fiber link through the GTX reflective memory data encoding and decoding module;

[0049] The output end of the packet number and length monitoring module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the normal or abnormal state of the data to the GTX reflective memory data encoding and decoding module.

[0050] The GTX reflective memory data encoding and decoding module is implemented by the 8B / 10B encoding and decoding hard core integrated in the FPGA, and is used to realize the conversion of high-speed serial differential signals and parallel low-speed signals of reflective memory data; wherein, the data transmission rate is set to 2.125Gbps, and the clock synchronization design is considered; an 8-channel design is adopted, so 8 IP cores need to be instantiated to configure 8 independent GTX channels, wherein the basic configuration parameters of the 8 GTX channels are consistent; the 8 channels all use the CPLL in the same bank as the reference clock; the reference clock of the transceiver channel is set to the same TXOUTCLK; the 8 GTX reference clocks are all set to the same clock, that is, the GTX reference clock output by the first GTX channel.

[0051] The ring network forwarding control module is implemented by designing a jump algorithm inside the FPGA, which is used for the timing control of data flow forwarding and the jump error correction control of the reflective memory network fault node; the node N may be any node from 0 to 7, and the 8 channels work in parallel. If the 8 channels are all normal nodes, the forwarding of the 8 channels is carried out simultaneously; the module can realize two functions: the ring network forwarding of data packets for normal node channels and the identification and jump of faulty node channels; when the data flow is transferred to the ring network forwarding control module, the working status of each node will be determined by three flags first, and the three flags are: the receiving signal detection indication signal output by the photoelectric conversion device in the hardware circuit, which is used to indicate whether the corresponding channel receiving end and the external device have established a normal hardware link; the RX_NOTINTABLE signal and RX_DISPERR signal output by the GTX channel IP core are used to indicate whether there are abnormalities in the receiving end 8B / 10B encoding and optical fiber link data transmission protocol. When any flag bit in a channel is abnormal, the channel is determined to be a faulty node channel, its status indicator light is turned off, the input data of the channel is not accepted during the data forwarding process, and it jumps to the next node channel. When the flag bits of one or some channels are normal, the corresponding channel is determined to be a normal node channel, and its corresponding status indicator light is turned on. When the status indicator light of one or some node channel N is normal, and there is external input data in the corresponding channel, the input data will be directly forwarded to the sending end of the next adjacent node (i.e., N+1 node) for sending. The external connection devices of this module are all reflective memory interface modules. The external reflective memory interface module will send the message received by its receiving end that complies with the data transmission protocol back to the receiving channel of the same node (i.e., N+1 node) as it is from the sending end. At this time, if the status indicator light of the N+1 node is on, the data sent back by the external reflective memory interface module will be forwarded again to the sending end of the next adjacent node (i.e., N+2 node) for sending, and thus forwarded step by step until it returns to the original N node; if the status indicator light of the N+1 node is off, the message sent back by the external reflective memory interface module received by the node will not be accepted, but the data of the sending end of the previous normal node (i.e., N node) will be forwarded again to the sending end of the next adjacent node (i.e., N+2 node) for sending, and thus forwarded step by step until it returns to the original N node. In the above description, only node channel N is used as an example. However, in fact, if all 8 channels are normal nodes, there will be a situation where the 8 channels receive input data at the same time and perform the above judgment and forwarding synchronously.

[0052] The channel reset monitoring module is implemented by designing a reset algorithm inside the FPGA, and is used to realize clock reset error correction control; the module can realize two functions: initialization configuration of all variables and reset of single or multiple GTX channels by identifying the plugging and unplugging of optical fibers of optoelectronic conversion devices in hardware circuits; when the channel reset monitoring module is powered on, the global reset signal can be pulled low to realize the function of initializing all variables and some parameters in GTX, providing a starting point for logical operation, and during the test process, the global reset signal can also be used to detect and locate abnormal phenomena; in addition to the global reset signal, each GTX IP core also has a corresponding reset signal for resetting the internal state of a single IP core; the channel reset monitoring module adds control of the reset signal of each GTX channel, and the GTX channel reset signal is valid on the falling edge. When the insertion of the optical fiber is recognized by the external reception signal detection indication signal, the reset signal is set high; when the optical fiber is unplugged by the external reception signal detection indication signal, the reset signal is set low. Since the module will perform a global reset after power-on, there is no need to reset the individual GTX channel when the optical fiber is first inserted. When the optical fiber of a channel is unplugged during operation, the falling edge of the corresponding channel reset signal will be triggered, thereby completing the reset of the corresponding GTX channel and initializing its internal clock signal.

[0053] The delay error correction module is implemented by designing a delay error correction algorithm inside the FPGA, and is used to realize error correction control of erroneous data bits of faulty nodes in the reflective memory network; the module delays the signal to be forwarded by two clocks, replaces the erroneous data bits with BCBC idle codes, eliminates the erroneous data bits generated in the underlying transmission, and then forwards the modified data normally to the sending end of the next node channel for transmission. Since the conditions for the occurrence of erroneous data bits generated by the underlying transmission are relatively fixed, the erroneous data bits can be screened for each occurrence condition.

[0054] The packet number and length monitoring module is implemented by designing a packet number and packet length matching monitoring algorithm inside the FPGA; the packet number detection uses a counter to count the data message header and the data message tail for a long time, and compares the number of data message headers and tails, the number of messages between each node channel, and the number of external input messages to determine whether there are problems such as wrong packets, packet loss during forwarding, and packet loss during receiving; the packet length detection mainly marks the duration of the data message through a flag variable, counts through a counter, records the actual length of the data message, and compares it with the data message length specified in the data transmission protocol to determine whether there is an error packet problem, and can accurately locate the location of the error packet through the recorded length value, and capture the error message to achieve the location of the error data packet in the faulty node.

[0055] The working principle of the present invention is:

[0056] The present invention proposes a reflective memory data exchange fault node identification and error correction system based on FPGA, which includes a set of FPGA software programs. The FPGA software program is internally divided into five parts: GTX reflective memory data encoding and decoding module, ring network forwarding control module, channel reset monitoring module, delay error correction module, and packet number and length monitoring module, so as to realize the core logic control and the reception and forwarding of reflective memory data. For ease of understanding, this example adopts an 8-channel design. It should be noted that the 8-channel is only an example, and the method can be expanded to any multiple channels.

[0057] The GTX reflective memory data encoding and decoding module is implemented by the 8B / 10B encoding and decoding hard core integrated in the FPGA, which is used to realize the conversion of high-speed serial differential signals and parallel low-speed signals of reflective memory data. The data transmission rate is set to 2.125Gbps. Since high-speed signals are more susceptible to interference caused by clock asynchrony during transmission and multi-channel forwarding, the clock synchronization design is focused on in the design of this module. This module adopts an 8-channel design, so 8 IP cores need to be instantiated to configure 8 independent GTX channels, and the basic configuration parameters of the 8 GTX channels are consistent. In order to avoid the problem of external clock asynchrony, the 8 channels all use the CPLL in the same bank as the reference clock; in order to avoid the problem of asynchrony of the transceiver channel clock, the reference clock of the transceiver channel is set to the same TXOUTCLK; in order to avoid the problem of asynchrony of the GTX clock of the 8 channels, the 8 GTX reference clocks are all set to the same clock, that is, the GTX reference clock output by the first GTX channel. This solution can effectively solve the data anomaly problem caused by clock misalignment during the forwarding process of data packets.

[0058] The ring network forwarding control module is implemented by designing a jump algorithm inside the FPGA, which is used for the timing control of data flow forwarding and the jump error correction control of the reflective memory network fault node. The flow chart is as follows Figure 1As shown. The node N marked in the figure may be any node from 0 to 7. At the same time, these 8 channels work in parallel. If all 8 channels are normal nodes, the forwarding of the 8 channels is carried out simultaneously. This module mainly implements two functions: data packet ring network forwarding of normal node channels; identification and jump of faulty node channels. When the data flows to the forwarding control logic module, the working status of each node will be determined by three flag bits first. These three flag bits are: the receiving signal detection indication signal output by the photoelectric conversion device in the hardware circuit, which is used to indicate whether the corresponding channel receiving end and the external device have established a normal hardware link; the RX_NOTINTABLE signal and RX_DISPERR signal output by the GTX channel IP core, which are used to indicate whether there are abnormalities in the 8B / 10B encoding and optical fiber link data transmission protocol of the receiving end. When any flag bit in a channel is abnormal, the channel is determined to be a faulty node channel, its status indicator light is turned off, the input data of the channel is not accepted during the data forwarding process, and it jumps to the next node channel. When the flag bits of one or some channels are normal, the corresponding channel is determined to be a normal node channel, and its corresponding status indicator light is turned on. When the status indicator of one or some node channels N is normal and there is external input data in the corresponding channel, the input data will be directly forwarded to the sending end of the next adjacent node (i.e., N+1 node) for sending. The external connection devices of this module are all reflective memory interface modules. The external reflective memory interface module will send the message received by its receiving end that complies with the data transmission protocol back to the receiving channel of the same node (i.e., N+1 node) as it is from the sending end. At this time, if the status indicator of the N+1 node is on, the data sent back by the external reflective memory interface module will be forwarded again to the sending end of the next adjacent node (i.e., N+2 node) for sending, and thus forwarded step by step until it returns to the original N node; if the status indicator of the N+1 node is off, the message sent back by the external reflective memory interface module received by the node will not be accepted, but the data of the sending end of the previous normal node (i.e., N node) will be forwarded again to the sending end of the next adjacent node (i.e., N+2 node) for sending, and thus forwarded step by step until it returns to the original N node. In the above description, only node channel N is used as an example. However, in fact, if all 8 channels are normal nodes, there will be a situation where the 8 channels receive input data at the same time and perform the above judgment and forwarding synchronously.

[0059] The channel reset monitoring module is implemented by designing a reset algorithm inside the FPGA to implement clock reset error correction control. The flow chart is as follows: Figure 2As shown. This module mainly implements two functions: initialization configuration of all variables; and reset of single or multiple GTX channels by identifying the plugging and unplugging of optical fiber of optoelectronic conversion device in hardware circuit. When the module is powered on, the global reset signal can be pulled low to realize the function of initializing all variables and some parameters in GTX, providing a starting point for logical operation to avoid the occurrence of timing disorder. At the same time, during the test process, the global reset signal can also be used to detect and locate abnormal phenomena. In addition to the global reset signal, each GTX IP core also has a corresponding reset signal, which is used to reset the internal state of a single IP core. In the optical communication interface circuit, when the optical fiber of a channel is plugged in or out, it will cause confusion in the internal clock logic of the GTX of the corresponding channel, resulting in bit errors when data is transmitted in the GTX of the corresponding channel. The erroneous data may cause confusion in the forwarding logic of the external reflective memory interface module during the step-by-step forwarding process, which will lead to a network storm that paralyzes the transmission mechanism of the entire network. In order to avoid this phenomenon, the channel reset module adds control of the reset signal of each GTX channel during the design process. The GTX channel reset signal is effective on the falling edge. When the optical fiber is inserted through the received signal detection indication signal of the photoelectric conversion module, the reset signal is set high; when the optical fiber is unplugged through the received signal detection indication signal of the photoelectric conversion module, the reset signal is set low. Since the module will perform a global reset after powering on, there is no need to reset a separate GTX channel when the optical fiber is first inserted. During operation, when the optical fiber of a channel is unplugged, the falling edge of the corresponding channel reset signal will be triggered, thereby completing the reset of the corresponding GTX channel and initializing its internal clock signal, effectively avoiding the problem of data anomalies caused by optical fiber plugging and unplugging.

[0060] The delay error correction module is implemented by designing a delay error correction algorithm inside the FPGA to realize the error correction control of the erroneous data bits of the faulty nodes in the reflective memory network. The flow chart is as follows: Figure 3 As shown. This module mainly delays the signal to be forwarded by two clocks, replaces the erroneous data bits with BCBC idle codes, removes the erroneous data bits generated in the underlying transmission, and then forwards the modified data normally to the sending end of the next node channel for transmission. Since the conditions for the occurrence of erroneous data bits generated by the underlying transmission are relatively fixed, the erroneous data bits can be screened for each occurrence condition to avoid data anomalies and network storms caused by erroneous data bits, and ensure that the data stream can be transmitted correctly during the multi-channel ring network forwarding process.

[0061] The packet number and length monitoring module is implemented by designing a packet number and packet length matching monitoring algorithm inside the FPGA. The flow chart is shown in the attached figure. Figure 4 And attached Figure 5As shown. The packet quantity detection mainly counts the data message header and data message tail for a long time through the counter, and judges whether there are wrong packets, packet loss during forwarding, and packet loss during receiving by comparing the number of data message headers and tails, the number of messages between each node channel, and the number of external input messages. The packet length detection mainly marks the duration of the data message through the flag variable, counts through the counter, records the actual length of the data message, and compares it with the data message length specified in the data transmission protocol to determine whether there is an error packet problem, and can accurately locate the location of the error packet through the recorded length value, and capture the error message to locate the error data packet in the faulty node.

[0062] In summary, the present invention proposes a reflective memory data exchange fault node identification and error correction system based on FPGA, which can realize the fault node identification and error correction function in the reflective memory ring network link through software algorithm under FPGA. This method uses FPGA internal algorithm to replace the commonly used dedicated interface chip, proposes a new design idea, and greatly increases the openness and flexibility of reflective memory exchange technology.

[0063] It should be emphasized that the embodiments of the present invention are illustrative rather than restrictive. Therefore, the present invention includes but is not limited to the embodiments described in the specific implementation modes. Any other implementation modes derived by those skilled in the art based on the technical solutions of the present invention also fall within the scope of protection of the present invention.

Claims

1. A reflective memory data exchange fault node identification and error correction system based on FPGA, characterized by: It includes a set of FPGA software programs; the FPGA software program includes: GTX reflective memory data encoding and decoding module, ring network forwarding control module, channel reset monitoring module, delay error correction module and packet number and length monitoring module, which are used to realize the core algorithm logic control and the arbitrary channel receiving and forwarding function of reflective memory data; The GTX reflective memory data encoding and decoding module performs 8B / 10B encoding and decoding through the GTX hard core integrated in the FPGA to realize the conversion of the high-speed serial differential signal and the parallel low-speed signal of the reflective memory data, which is used to realize the subsequent ring network forwarding control and fault node identification and error correction; The ring network forwarding control module realizes the timing control of data flow forwarding and the fault node jump error correction control through the jump algorithm; The channel reset monitoring module implements the initialization configuration of all variables through the reset algorithm and recognizes the plugging and unplugging of external optical fiber hardware to realize the clock reset error correction control of the GTX channel fault node; The delay error correction module implements error correction control of the erroneous data bits of the faulty node by gating and assigning values ​​to the intermediate variables; The packet number and length monitoring module implements data packet counting statistics and packet length detection statistics through a packet number and length matching algorithm, and compares them with the communication protocol to determine whether there is a faulty node during data transmission in the ring network, and can directly identify the location of the faulty node based on the flag variable.

2. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The output end of the GTX reflective memory data encoding and decoding module is respectively connected to the input end of the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, and is used to output the external optical fiber link input data to the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module; The output end of the channel reset monitoring module is respectively connected to the input end of the GTX reflective memory data encoding and decoding module, the ring network forwarding control module, the delay error correction module and the packet number and length monitoring module, so as to output the control signal to the above four processing modules; The output end of the delay error correction module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the error-corrected data to the external optical fiber link through the GTX reflective memory data encoding and decoding module; The output end of the packet number and length monitoring module is connected to the input end of the GTX reflective memory data encoding and decoding module, and is used to output the normal or abnormal state of the data to the GTX reflective memory data encoding and decoding module.

3. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The GTX reflective memory data encoding and decoding module is implemented by the 8B / 10B encoding and decoding hard core integrated in the FPGA, and is used to realize the conversion of high-speed serial differential signals and parallel low-speed signals of reflective memory data; wherein, the data transmission rate is set to 2.125Gbps, and the clock synchronization design is considered; an 8-channel design is adopted, so 8 IP cores need to be instantiated to configure 8 independent GTX channels, wherein the basic configuration parameters of the 8 GTX channels are consistent; the 8 channels all use the CPLL in the same bank as the reference clock; the reference clock of the transceiver channel is set to the same TXOUTCLK; the 8 GTX reference clocks are all set to the same clock, that is, the GTX reference clock output by the first GTX channel.

4. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The ring network forwarding control module is implemented by designing a jump algorithm inside the FPGA, which is used for the timing control of data flow forwarding and the jump error correction control of the reflective memory network fault node; the node N may be any node from 0 to 7, and the 8 channels work in parallel. If the 8 channels are all normal nodes, the forwarding of the 8 channels is carried out simultaneously; the module can realize two functions: ring network forwarding of data packets for normal node channels and identification and jump of faulty node channels; when the data flow is transferred to the ring network forwarding control module, the working status of each node will be determined first by three flag bits, which are: the receiving signal detection indication signal output by the photoelectric conversion device in the hardware circuit, which is used to indicate whether a normal hardware link has been established between the corresponding channel receiving end and the external device; the RX_NOTINTABLE signal and RX_DISPERR signal output by the GTX channel IP core, which are used to indicate whether there are abnormalities in the 8B / 10B encoding and optical fiber link data transmission protocol of the receiving end; When any flag bit in a channel is abnormal, the channel is determined to be a faulty node channel, its status indicator light is turned off, the input data of the channel is not accepted during data forwarding, and the channel jumps to the next node channel; When the flag bits of one or some channels are normal, the corresponding channels are determined to be normal node channels, and the corresponding status indicators are lit; when the status indicators of one or some node channels N are normal, and there is external input data in the corresponding channels, the input data will be directly forwarded to the sending end of the next adjacent node (i.e., N+1 node) for sending; the external connection devices of this module are all reflective memory interface modules, and the external reflective memory interface module will send the messages received by its receiving end that comply with the data transmission protocol as is from the sending end back to the receiving channel of the same node (i.e., N+1 node); at this time, if the status indicator of the N+1 node is on, the external The data sent back by the external reflective memory interface module is forwarded again to the sending end of the next adjacent node (i.e., the N+2 node) for sending, and is forwarded step by step until it returns to the original N node; if the N+1 node status indicator is off, the message sent back by the external reflective memory interface module received by the node will not be accepted, but the data of the sending end of the previous normal node (i.e., the N node) will be forwarded again to the sending end of the next adjacent node (i.e., the N+2 node) for sending, and is forwarded step by step until it returns to the original N node; if all 8 channels are normal nodes, there will be a situation where the 8 channels receive input data at the same time, and the above judgment and forwarding are performed synchronously.

5. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The channel reset monitoring module is implemented by designing a reset algorithm inside the FPGA to realize clock reset error correction control; the module can realize two functions: initialization configuration of all variables and reset of single or multiple GTX channels by identifying the plugging and unplugging of optical fibers of photoelectric conversion devices in the hardware circuit; when the channel reset monitoring module is powered on, the global reset signal can be pulled low to realize the function of initializing all variables and some parameters in GTX, providing a starting point for logical operation, and at the same time, during the test process, the global reset signal can also be used to realize the troubleshooting and positioning of abnormal phenomena; In addition to the global reset signal, each GTX IP core also has a corresponding reset signal for resetting the internal state of a single IP core; the channel reset monitoring module adds control over the reset signal of each GTX channel. The GTX channel reset signal is valid on the falling edge. When the external receiving signal detection indication signal identifies the insertion of the optical fiber, the reset signal is set high. When the external receiving signal detection indication signal identifies that the optical fiber is unplugged, the reset signal is set low; since the module will perform a global reset after power-on, there is no need to reset the individual GTX channel when the optical fiber is first inserted. During operation, when the optical fiber of a channel is unplugged, the falling edge of the corresponding channel reset signal will be triggered, thereby completing the reset of the corresponding GTX channel and initializing its internal clock signal.

6. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The delay error correction module is implemented by designing a delay error correction algorithm inside the FPGA, and is used to realize error correction control of erroneous data bits of faulty nodes in the reflective memory network; the module delays the signal to be forwarded by two clocks, replaces the erroneous data bits with BCBC idle codes, eliminates the erroneous data bits generated in the underlying transmission, and then forwards the modified data normally to the sending end of the next node channel for transmission. Since the conditions for the occurrence of erroneous data bits generated by the underlying transmission are relatively fixed, the erroneous data bits can be screened for each occurrence condition.

7. The FPGA-based reflective memory data exchange fault node identification and error correction system according to claim 1, characterized in that: The packet number and length monitoring module is implemented by designing a packet number and packet length matching monitoring algorithm inside the FPGA; the packet number detection uses a counter to count the data message header and the data message tail for a long time, and compares the number of data message headers and tails, the number of messages between each node channel, and the number of external input messages to determine whether there are problems such as wrong packets, packet loss during forwarding, and packet loss during receiving; the packet length detection mainly marks the duration of the data message through a flag variable, counts through a counter, records the actual length of the data message, and compares it with the data message length specified in the data transmission protocol to determine whether there is an error packet problem, and can accurately locate the location of the error packet through the recorded length value, and capture the error message to achieve the location of the error data packet in the faulty node.

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