Semiconductor Structure and Method of Forming the Same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same, relating to the field of semiconductor technologies. The forming method includes: forming a stacked film layer on a substrate, the stacked film layer including a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extending in a first direction and being spaced apart in a second direction, and there being a gap between two adjacent first semiconductor layers in the second direction, the second direction intersecting the first direction; the stacked film layer having a trench that penetrates through each of the first semiconductor layers in the second direction; protective layers being respectively formed on the end faces of the first semiconductor layers exposed in the trench; etching the first semiconductor layers to reduce the thickness of the first semiconductor layers; the etching rate of the protective layer being less than the etching rate of the first semiconductor layers. The forming method of the present disclosure can improve the storage density without increasing the number of layers of the first semiconductor layers.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same. Background Art

[0002] Memory is widely used in mobile devices such as mobile phones and tablet computers due to its advantages of small size, high integration level, and fast transmission speed. The memory includes multiple chip units integrated on a wafer. However, during the manufacturing process, affected by the manufacturing process, the number of chip units integrated on a single wafer is small and the storage density is low.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The present disclosure provides a semiconductor structure and a method for forming the same, which can improve the storage density without increasing the number of layers of the first semiconductor layer.

[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, including:

[0006] Forming a stacked film layer on a substrate, the stacked film layer including a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extending along a first direction and being spaced apart along a second direction, and there being a gap between two adjacent first semiconductor layers along the second direction, the second direction intersecting the first direction; the stacked film layer having a trench, the trench penetrating through each of the first semiconductor layers along the second direction; the protective layer being formed on the end faces of the first semiconductor layers exposed in the trench;

[0007] Etching the first semiconductor layer to reduce the thickness of the first semiconductor layer; the etching rate of the protective layer being less than the etching rate of the first semiconductor layer.

[0008] In an exemplary embodiment of the present disclosure, the forming a stacked film layer on a substrate includes:

[0009] Forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed along the second direction on the substrate;

[0010] Etching the first semiconductor layer and the second semiconductor layer to form a trench penetrating through each of the first semiconductor layers and each of the second semiconductor layers along the second direction;

[0011] Forming the protective layer on the end faces of the first semiconductor layers exposed in the trench;

[0012] Remove each of the second semiconductor layers to form the gap between adjacent first semiconductor layers.

[0013] In an exemplary embodiment of the present disclosure, forming the protective layer on the end faces of the first semiconductor layers exposed in the trenches includes:

[0014] Perform back-etching on the end portions of the second semiconductor layer close to the trenches to form recesses;

[0015] Form a covering layer in the recesses;

[0016] Form the protective layer on the end faces of the first semiconductor layers close to the trenches;

[0017] Remove the covering layer.

[0018] In an exemplary embodiment of the present disclosure, forming the protective layer on the end faces of the first semiconductor layers exposed in the trenches includes:

[0019] Simultaneously oxidize the end portions of the first semiconductor layer exposed in the trenches and the end portions of the second semiconductor layer exposed in the trenches to form the protective layer at the end portions of the first semiconductor layer close to the trenches and form a covering layer at the end portions of the second semiconductor layer;

[0020] Remove the covering layer.

[0021] In an exemplary embodiment of the present disclosure, the material of the first semiconductor layer is silicon, the material of the covering layer is silicon nitride, and forming the protective layer on the end faces of the first semiconductor layer close to the trenches includes:

[0022] Form a metal layer on the surface of the structure jointly formed by the covering layer and the first semiconductor layer;

[0023] Perform heat treatment on the metal layer to form a metal silicide layer on the surface of the first semiconductor layer;

[0024] Remove the unreacted metal layer and use the metal silicide layer as the protective layer.

[0025] In an exemplary embodiment of the present disclosure, forming the protective layer on the end faces of the first semiconductor layer close to the trenches includes:

[0026] Perform ion doping on the end portions of the first semiconductor layer close to the trenches and use the first semiconductor layer containing doping ions as the protective layer.

[0027] In an exemplary embodiment of the present disclosure, forming a stacked film layer on a substrate includes:

[0028] Forming a plurality of first semiconductor layers and second semiconductor layers that are alternately distributed along the second direction on the substrate;

[0029] Etching the first semiconductor layer and the second semiconductor layer to form trenches that penetrate through each of the first semiconductor layers and each of the second semiconductor layers along the second direction;

[0030] Removing the second semiconductor layer to form the gap;

[0031] Forming a covering layer in the gap, the covering layer covering the upper surface and the lower surface of the first semiconductor layer distributed along the second direction;

[0032] Forming the protective layer on the end face of the first semiconductor layer close to the trench;

[0033] Removing the covering layer to expose the gap.

[0034] In an exemplary embodiment of the present disclosure, forming a covering layer in the gap, the covering layer covering the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, includes:

[0035] Forming a covering material layer that conformally covers the surfaces of each of the first semiconductor layers;

[0036] Forming a filling layer between each of the first semiconductor layers having the covering material layer, the filling layer filling the gap between adjacent first semiconductor layers;

[0037] Removing the covering material layer located on the end face of the first semiconductor layer close to the trench to expose the end face of the first semiconductor layer close to the trench;

[0038] Removing the filling layer and using the remaining covering material layer as the covering layer.

[0039] In an exemplary embodiment of the present disclosure, forming a covering layer in the gap, the covering layer covering the upper surface and the lower surface of the first semiconductor layer distributed along the second direction, includes:

[0040] Forming a covering material layer on the surface of each of the first semiconductor layers, the covering material layer filling the gap;

[0041] Removing the covering material layer located on the end face of the first semiconductor layer close to the trench to expose the end face of the first semiconductor layer close to the trench, and using the remaining covering material layer as the covering layer.

[0042] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0043] After thinning the thickness of the first semiconductor layer, the protective layer is removed.

[0044] According to an aspect of the present disclosure, there is provided a semiconductor structure formed by the forming method of the semiconductor structure described in any one of the above.

[0045] The semiconductor structure and its forming method of the present disclosure form a plurality of first semiconductor layers distributed along the second direction on the substrate, so that more first semiconductor layers can be integrated per unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to thin its thickness, a larger process space can be reserved for preparing word lines between two adjacent first semiconductor layers distributed along the second direction subsequently, which helps to reduce the process difficulty of manufacturing word lines subsequently. And during the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of the first semiconductor layers exposed in the trenches, and the etching rate of the protective layer is less than that of the first semiconductor layer, during the process of etching and thinning the first semiconductor layer, the protective layer can be used to protect the end portions of the first semiconductor layer close to the trenches, the damage to the first semiconductor layer in the first direction during the etching process can be reduced, the distance between the first semiconductor layers on both sides of the trench is relatively small, and more first semiconductor layers can be arranged along the first direction on the substrate, which helps to fabricate a larger number of chip units on the substrate. That is, the storage density can be increased without increasing the number of layers of the first semiconductor layer.

[0046] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure and used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0048] Figure 1 It is a flowchart of the forming method of the semiconductor structure in the embodiment of the present disclosure.

[0049] Figure 2 It is a schematic diagram of the first semiconductor layer, the second semiconductor layer and the trench in the embodiment of the present disclosure.

[0050] Figure 3Schematic diagram of the protective layer in an embodiment of the present disclosure.

[0051] Figure 4 Schematic diagram of the recess in an embodiment of the present disclosure.

[0052] Figure 5 Schematic diagram of the covering material layer in an embodiment of the present disclosure.

[0053] Figure 6 Schematic diagram of the covering layer in an embodiment of the present disclosure.

[0054] Figure 7 Schematic diagram of the protective layer and the covering layer in an embodiment of the present disclosure.

[0055] Figure 8 Schematic diagram of the metal layer in an embodiment of the present disclosure.

[0056] Figure 9 Schematic diagram of the metal silicide layer in an embodiment of the present disclosure.

[0057] Figure 10 Schematic diagram of the protective layer and the covering layer in an embodiment of the present disclosure.

[0058] Figure 11 Schematic diagram of the gap in an embodiment of the present disclosure.

[0059] Figure 12 Schematic diagram of the gap in an embodiment of the present disclosure.

[0060] Figure 13 Schematic diagram of the covering layer in an embodiment of the present disclosure.

[0061] Figure 14 Schematic diagram of the covering layer in an embodiment of the present disclosure.

[0062] Figure 15 Schematic diagram of the covering material layer and the filling layer in an embodiment of the present disclosure.

[0063] Figure 16 Schematic diagram after removing part of the filling layer in an embodiment of the present disclosure.

[0064] Figure 17 Schematic diagram of the structure after completing step S730 in an embodiment of the present disclosure.

[0065] Figure 18 Schematic diagram of the structure after completing step S810 in an embodiment of the present disclosure.

[0066] Figure 19 Schematic diagram of the structure after completing step S650 in an embodiment of the present disclosure.

[0067] Figure 20Schematic diagram of the structure after completing step S120 in an embodiment of the present disclosure.

[0068] Figure 21 Schematic diagram of the structure after completing step S130 in an embodiment of the present disclosure.

[0069] In the figure: 1. Substrate; 2. Stacked film layer; 21. First semiconductor layer; 22. Protective layer; 23. Second semiconductor layer; 24. Protective material layer; 201. Groove; 202. Gap; 203. Recess; 3. Cover layer; 31. Cover material layer; 4. Metal layer; 41. Metal silicide layer; 5. Filling layer; x. First direction; y. Second direction. Detailed implementation manners

[0070] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed descriptions will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0071] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the accompanying drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component described as "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0072] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as labels and are not a limitation on the quantity of their objects.

[0073] In the manufacturing process of 3D dynamic random access memory (DRAM), in order to improve the storage density, multiple semiconductor groups are usually formed on a substrate with lateral spacing. Each semiconductor group includes multiple first semiconductor layers distributed longitudinally. At the same time, in order to facilitate the preparation of word lines between two adjacent first semiconductor layers distributed longitudinally, it is necessary to thin the first semiconductor layer. However, during the process of thinning the first semiconductor layer, the lateral loss of the first semiconductor layer is relatively large, resulting in a relatively large spacing between adjacent semiconductor groups distributed laterally, so that the number of chip units formed based on it in the lateral direction is small and the storage density is low.

[0074] Based on this, the embodiments of the present disclosure provide a method for forming a semiconductor structure, as Figure 1 shown. The forming method includes step S110 and step S120, where:

[0075] Step S110: Form a stacked film layer on the substrate. The stacked film layer includes multiple first semiconductor layers and a protective layer. The multiple first semiconductor layers extend along a first direction and are spaced apart along a second direction, and there is a gap between two adjacent first semiconductor layers along the second direction. The second direction intersects the first direction. The stacked film layer has a trench, and the trench penetrates through each of the first semiconductor layers along the second direction. The protective layer is formed on the end surface of each of the first semiconductor layers exposed in the trench.

[0076] Step S120: Etch the first semiconductor layer to thin the thickness of the first semiconductor layer. The etching rate of the protective layer is less than the etching rate of the first semiconductor layer.

[0077] The method for forming a semiconductor structure of the present disclosure forms a plurality of first semiconductor layers distributed along a second direction on a substrate, enabling more first semiconductor layers to be integrated per unit area, providing a basis for manufacturing more chip units. By etching the first semiconductor layer to reduce its thickness, a larger process space can be reserved for preparing word lines between two adjacent first semiconductor layers distributed along the second direction, which helps reduce the process difficulty of subsequent word line fabrication. And during the process of etching and thinning the first semiconductor layer, since protective layers are respectively formed on the end faces of the exposed first semiconductor layers in the trench, and the etching rate of the protective layer is less than that of the first semiconductor layer, during the process of etching and thinning the first semiconductor layer, the protective layer can be used to protect the end portions of the first semiconductor layer close to the trench, reducing the damage to the first semiconductor layer in the first direction during the etching process, making the distance between the first semiconductor layers on both sides of the trench relatively small, enabling more first semiconductor layers to be arranged along the first direction on the substrate, which helps prepare a larger number of chip units on the substrate. That is, the storage density can be increased without increasing the number of layers of the first semiconductor layer.

[0078] The following details each step and its specific details of the method for forming a semiconductor structure of the present disclosure:

[0079] As Figure 1 shown, in step S110, a stacked film layer is formed on the substrate. The stacked film layer includes a plurality of first semiconductor layers and protective layers. The plurality of first semiconductor layers extend along a first direction and are spaced apart along a second direction, and there is a gap between two adjacent first semiconductor layers along the second direction. The second direction intersects the first direction. The stacked film layer has a trench that penetrates each first semiconductor layer along the second direction. Protective layers are respectively formed on the end faces of the exposed first semiconductor layers in the trench.

[0080] As Figure 2 shown, the substrate 1 can be in a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape. Its material can be a semiconductor material. For example, its material can be silicon, but it is not limited to silicon or other semiconductor materials. The shape and material of the substrate 1 are not specially limited here.

[0081] In an exemplary embodiment of the present disclosure, forming the stacked film layer on the substrate 1 (i.e., step S110) may include steps S210 - S240, where:

[0082] Step S210, forming a plurality of first semiconductor layers 21 and second semiconductor layers 23 that are alternately distributed along the second direction y on the substrate 1.

[0083] Please continue to refer to Figure 2As shown, each first semiconductor layer 21 and each second semiconductor layer 23 can extend along the first direction x, and the first direction x can be any direction parallel to the substrate 1. Each first semiconductor layer 21 and each second semiconductor layer 23 can be stacked and distributed along the second direction y. For example, each first semiconductor layer 21 and each second semiconductor layer 23 can be alternately distributed in sequence along the second direction y on the substrate 1. In one embodiment, in the stacked film layer, the film layer farthest from the substrate 1 is the first semiconductor layer 21.

[0084] In some embodiments of the present disclosure, the material of the first semiconductor layer 21 can be silicon, and the material of the second semiconductor layer 23 can be silicon germanium. The thickness of the first semiconductor layer 21 can be greater than the thickness of the second semiconductor layer 23. For example, the thickness ratio of the first semiconductor layer 21 to the second semiconductor layer 23 can be 5:1 to 2:1. For example, the thickness of the first semiconductor layer 21 can be 50 nm, and the thickness of the second semiconductor layer 23 can be 10 nm; or, the thickness of the first semiconductor layer 21 can be 45 nm, and the thickness of the second semiconductor layer 23 can be 15 nm; or, the thickness of the first semiconductor layer 21 can be 40 nm, and the thickness of the second semiconductor layer 23 can be 20 nm.

[0085] For example, the number of the first semiconductor layers 21 can be 2 to 20. For example, the number can be 2, 6, 10, 14, 18, or 20. Of course, the number of the first semiconductor layers 21 can also be other numbers, which will not be listed one by one here.

[0086] In some embodiments of the present disclosure, the second direction y can intersect the first direction x. For example, the second direction y and the first direction x can be perpendicular to each other. It should be noted that perpendicular can be absolute perpendicular or approximately perpendicular. There will inevitably be deviations during the manufacturing process. In the present disclosure, due to process limitations, there may be angular deviations, resulting in a certain deviation in the included angle between the first direction x and the second direction y. As long as the angular deviation between the first direction x and the second direction y is within the preset range, it can be considered that the first direction x is perpendicular to the second direction y. For example, the preset range can be 10°, that is: when the included angle between the first direction x and the second direction y is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction x and the second direction y are perpendicular.

[0087] Multiple first semiconductor layers 21 and multiple second semiconductor layers 23 that are alternately distributed in sequence along the second direction y can be formed on the substrate 1 by means of atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, etc. Of course, the first semiconductor layer 21 and the second semiconductor layer 23 can also be formed by other means, and the formation methods of the first semiconductor layer 21 and the second semiconductor layer 23 are not specially limited here.

[0088] Step S220: Etch the first semiconductor layer 21 and the second semiconductor layer 23 to form trenches 201 that penetrate each first semiconductor layer 21 and each second semiconductor layer 23 along the second direction y.

[0089] Dry etching can be used to etch each first semiconductor layer 21 and each second semiconductor layer 23 on the substrate 1 to form trenches 201 (as Figure 2 shown); that is, the sidewalls of the trenches 201 can be composed of each first semiconductor layer 21 and each second semiconductor layer 23.

[0090] In some embodiments of the present disclosure, please continue to refer to Figure 2 shown. Before dry etching, a protective material layer 24 can be formed on the surface of the topmost first semiconductor layer 21 (i.e., the first semiconductor layer 21 farthest from the substrate 1) away from the substrate 1. The protective material layer 24 can cover the surface of the topmost first semiconductor layer 21. The material of the protective material layer 24 is different from the materials of the first semiconductor layer 21 and the second semiconductor layer 23, and during the dry etching process, the etching rate of the protective material layer 24 is much smaller than the etching rates of the first semiconductor layer 21 and the second semiconductor layer 23, which can ensure that the protective material layer 24 always covers the surface of the first semiconductor layer 21 farthest from the substrate 1 during the etching to form the trenches 201, thereby protecting the first semiconductor layer 21 farthest from the substrate 1 from being damaged. For example, the material of the protective material layer 24 can be silicon oxide.

[0091] In some embodiments of the present disclosure, the number of trenches 201 can be multiple, and the multiple trenches 201 can be spaced along the first direction x, so that the structure composed of each first semiconductor layer 21 and each second semiconductor layer 23 can be divided into multiple spaced semiconductor groups through the multiple trenches 201.

[0092] Step S230: Form a protective layer on the end face of the first semiconductor layer 21 close to the trench 201.

[0093] The material of the protective layer is different from the material of the first semiconductor layer 21; and during the subsequent etching of the first semiconductor layer 21, the etching rate of the protective layer is less than the etching rate of the first semiconductor layer 21. For example, when the material of the first semiconductor layer 21 is silicon, the material of the protective layer can be silicon oxide, metal silicide, silicon with doped ions, etc. The thickness of the protective layer can be 2 nm to 5 nm. For example, it can be 2 nm, 3 nm, 4 nm, or 5 nm. Of course, the thickness of the protective layer can also be other values, which are not specifically limited here, as long as it can ensure that the protective layer will not be completely consumed during the subsequent thinning of the first semiconductor layer 21.

[0094] As Figure 3As shown, protective layers 22 can be respectively formed on the surfaces of the end faces of the first semiconductor layers 21 exposed on the sidewalls of the trench 201. For example, processes such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ steam oxidation can be used to form the protective layers 22. Of course, the protective layers 22 can also be formed by other means, and no special limitation is imposed on the formation method of the protective layers 22 here.

[0095] In an exemplary embodiment of the present disclosure, forming the protective layer 22 (i.e., step S230) on the end faces of the first semiconductor layers 21 exposed in the trench 201 may include steps S310 - S340, where:

[0096] Step S310: Perform an etch-back on the end portion of the second semiconductor layer 23 close to the trench 201 to form a recess 203.

[0097] As Figure 4 shown, an isotropic etch can be performed on the end portion of the second semiconductor layer 23 close to the trench 201, thereby removing part of the second semiconductor layer 23. The space jointly surrounded by the remaining second semiconductor layer 23 and the two first semiconductor layers 21 located on both sides of the second semiconductor layer 23 in the second direction y can be used as the recess 203. It should be noted that when the number of second semiconductor layers 23 is multiple, the etch-back can be performed on the multiple second semiconductor layers 23 simultaneously, thereby forming multiple recesses 203 arranged along the second direction y.

[0098] Step S320: Form a covering layer 3 in the recess 203.

[0099] The material of the covering layer 3 is different from the material of the protective layer 22 to be formed subsequently. For example, the material of the protective layer 22 can be silicon oxide, and the material of the covering layer 3 can be silicon nitride, silicon oxynitride, silicon boron nitride, or aluminum oxide, etc. A covering material layer 31 can be formed on the surface of the structure jointly constituted by the first semiconductor layers 21 and the remaining second semiconductor layers 23 after the etch-back by means such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. As Figure 5 shown, the covering material layer 31 can fill each recess 203. It should be noted that when a protective material layer 24 is formed on the surface of the topmost first semiconductor layer 21, for process convenience, the covering material layer 31 can be formed on the surface of the protective material layer 24 simultaneously, that is, the covering material layer 31 can cover the surface of the protective material layer 24, cover the sidewalls and bottom of the trench 201, and fill the recesses 203.

[0100] As Figure 6As shown, the covering material layer 31 in the area outside the recess 203 can be removed (i.e., the side wall of the first semiconductor layer 21 close to the trench 201 is exposed), and the remaining covering material layer 31 in the recess 203 is used as the covering layer 3. It should be noted that in the first direction x, the end face of the covering layer 3 close to the trench 201 is substantially flush with the end face of the first semiconductor layer 21 close to the trench 201.

[0101] Step S330: Form a protective layer 22 on the end face of the first semiconductor layer 21 close to the trench 201.

[0102] As Figure 7 shown, the protective layer 22 can be formed on the end face of the first semiconductor layer 21 close to the trench 201 through an in-situ steam oxidation process. For example, when the material of the first semiconductor layer 21 is silicon, silicon oxide can be formed on the silicon surface through an in-situ steam oxidation process, and this silicon oxide can be used as the protective layer 22.

[0103] In an exemplary embodiment of the present disclosure, the material of the first semiconductor layer 21 is silicon, and the material of the covering layer 3 is silicon nitride. Forming the protective layer 22 on the end face of the first semiconductor layer 21 close to the trench 201 (i.e., step S330) may include steps S410 - S430, where:

[0104] Step S410: Form a metal layer on the surface of the structure jointly constituted by the covering layer 3 and the first semiconductor layer 21.

[0105] In some embodiments of the present disclosure, the material of the metal layer can be titanium, cobalt, nickel, platinum, etc. As Figure 8 shown, the metal layer 4 can be formed on the surface of the structure jointly constituted by the covering layer 3 and the first semiconductor layer 21 through chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. It should be noted that when a protective material layer 24 is formed on the surface of the topmost first semiconductor layer 21, for process convenience, the metal layer 4 can be formed on the surface of the protective material layer 24 simultaneously, that is, the metal layer 4 can cover the surface and side wall of the protective material layer 24, and cover the end faces of the first semiconductor layers 21 close to the trench 201 and the surfaces of the covering layers 3.

[0106] Step S420: Heat-treat the metal layer 4 to form a metal silicide layer 41 on the surface of the first semiconductor layer 21.

[0107] As Figure 9As shown, the metal layer 4 can be thermally annealed to cause metal ions in the metal layer 4 to diffuse into the first semiconductor layer 21, thereby forming a metal silicide layer 41 at the end of the first semiconductor layer 21. For example, when the material of the metal layer 4 is titanium, the material of the metal silicide layer 41 can be titanium silicide; when the material of the metal layer 4 is cobalt, the material of the metal silicide layer 41 can be cobalt silicide; when the material of the metal layer 4 is nickel, the material of the metal silicide layer 41 can be nickel silicide; when the material of the metal layer 4 is platinum, the material of the metal silicide layer 41 can be platinum silicide.

[0108] Step S430: Remove the unreacted metal layer 4 and use the metal silicide layer 41 as the protective layer 22.

[0109] After the metal silicide layer 41 is formed, the unreacted metal layer 4 can be removed by a selective etching process. For example, the unreacted metal layer 4 can be removed by a dry etching process, and the etching gas for dry etching can be reasonably set according to the specific material of the metal layer 4 and the specific material of the metal silicide layer 41, as long as the metal layer 4 can be removed without damaging (or slightly damaging, but not affecting its protective performance for the first semiconductor layer 21) the metal silicide layer 41.

[0110] In an exemplary embodiment of the present disclosure, forming the protective layer 22 (i.e., step S330) on the end face of the first semiconductor layer 21 close to the trench 201 may include: ion doping the end of the first semiconductor layer 21 close to the trench 201. For example, ion implantation can be used to ion dope the end of the first semiconductor layer 21 close to the trench 201; for example, under the action of a high-energy electric field, the doping ions can be accelerated and implanted into the end of the first semiconductor layer 21 close to the trench 201. Alternatively, the structure composed of the first semiconductor layer 21, the second semiconductor layer 23, and the cover layer 3 can be placed in a gas containing doping ions, and the doping ions can be diffused into the interior of the first semiconductor layer 21 by high-temperature heating, and the first semiconductor layer 21 containing doping ions can be used as the protective layer 22. In some embodiments of the present disclosure, the material of the doping ions can be boron, phosphorus, arsenic, etc.

[0111] Step S340: Remove the cover layer 3.

[0112] After the protective layer 22 is formed, the cover layer 3 in each recess 203 can be removed by isotropic etching, thereby exposing the ends of the remaining second semiconductor layers 23 close to the trench 201, so as to facilitate the subsequent removal of each second semiconductor layer 23.

[0113] In an exemplary embodiment of the present disclosure, forming the protective layer 22 (i.e., step S230) on the end faces of the first semiconductor layers 21 exposed in the trench 201 may include step S510 and step S520, where:

[0114] Step S510: Simultaneously oxidize the end portions of the first semiconductor layer 21 exposed in the trench 201 and the end portions of the second semiconductor layer 23 exposed in the trench 201, so as to form a protective layer 22 near the end of the first semiconductor layer 21 close to the trench 201 and form a covering layer 3 at the end of the second semiconductor layer 23.

[0115] In some embodiments of the present disclosure, as Figure 10 shown, the material of the protective layer 22 covering the end of the first semiconductor layer 21 is different from the material of the covering layer 3 covering the end of the second semiconductor layer 23. For example, when the material of the first semiconductor layer 21 is silicon and the material of the second semiconductor layer 23 is silicon germanium, the end portions of the first semiconductor layer 21 and the second semiconductor layer 23 close to the trench 201 can be simultaneously oxidized under low-temperature conditions, and then silicon oxide is formed on the surface of the first semiconductor layer 21, and a mixture of silicon oxide and germanium oxide is formed on the surface of the second semiconductor layer 23; for the convenience of distinction, the silicon oxide located on the first semiconductor layer 21 can be defined as the protective layer 22, and the mixture of silicon oxide and germanium oxide located on the second semiconductor layer 23 can be defined as the covering layer 3. In some embodiments of the present disclosure, the low-temperature conditions can be temperature conditions below 600 °C. For example, it can be 600 °C, 580 °C, 560 °C, 540 °C, 520 °C or 500 °C. Of course, it can also be other temperature conditions, which will not be enumerated one by one here.

[0116] Step S520: Remove the covering layer 3.

[0117] The covering layer 3 located on the second semiconductor layer 23 can be removed by means of isotropic etching, so as to expose the end portion of the second semiconductor layer 23 close to the trench 201. During this process, since the materials of the covering layer 3 and the protective layer 22 are different, when using the same etching solution to remove the covering layer 3, the etching rate of the covering layer 3 is greater than that of the protective layer 22. During the process of removing the covering layer 3, the damage to the protective layer 22 is less, and the protective layer 22 still remains on the surface of the first semiconductor layer 21 after the covering layer 3 is removed.

[0118] Step S240: Remove each second semiconductor layer 23 to form a gap 202 between adjacent first semiconductor layers 21.

[0119] As Figure 11As shown, after the formation of the protective layer 22, each second semiconductor layer 23 can be removed, and then a gap 202 is formed between two adjacent first semiconductor layers 21 distributed along the second direction y. That is, in the second direction y, the width of the gap 202 is equal to the thickness of the second semiconductor layer 23. For example, when the thickness of the second semiconductor layer 23 is 10 nm, in the second direction y, the width of the gap 202 is 10 nm; when the thickness of the second semiconductor layer 23 is 15 nm, in the second direction y, the width of the gap 202 is 15 nm; when the thickness of the second semiconductor layer 23 is 20 nm, in the second direction y, the width of the gap 202 is 20 nm.

[0120] In some embodiments of the present disclosure, each second semiconductor layer 23 can be removed by wet etching, and the etching solution for wet etching can be selected according to the specific materials of the first semiconductor layer 21, the second semiconductor layer 23, and the protective layer 22; that is, as long as the etching solution can remove the second semiconductor layer 23 and does not damage (or slightly damage, but does not affect its performance) the first semiconductor layer 21 and the protective layer 22, the specific solution for wet etching is not specifically limited herein.

[0121] In an exemplary embodiment of the present disclosure, forming the stacked film layer 2 on the substrate 1 (i.e., step S110) may include steps S610 - S660, where:

[0122] Step S610, forming a plurality of first semiconductor layers 21 and second semiconductor layers 23 that are alternately distributed along the second direction y on the substrate 1.

[0123] The specific materials, distribution patterns, quantities, and thicknesses of the first semiconductor layer 21 and the second semiconductor layer 23 are similar to those of the first semiconductor layer 21 and the second semiconductor layer 23 in step S210. Therefore, they will not be elaborated here. Please continue to refer to Figure 2 As shown, a plurality of first semiconductor layers 21 and a plurality of second semiconductor layers 23 that are alternately distributed along the second direction y can be formed on the substrate 1 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or epitaxial growth processes, etc. Of course, the first semiconductor layer 21 and the second semiconductor layer 23 can also be formed by other methods, and the formation methods of the first semiconductor layer 21 and the second semiconductor layer 23 are not specifically limited herein.

[0124] Step S620, etching the first semiconductor layer 21 and the second semiconductor layer 23 to form a trench 201 that penetrates each first semiconductor layer 21 and each second semiconductor layer 23 along the second direction y.

[0125] Please continue to refer to Figure 2As shown, dry etching can be used to etch each first semiconductor layer 21 and each second semiconductor layer 23 on the substrate 1 to form trenches 201; that is, the sidewalls of the trenches 201 are composed of each first semiconductor layer 21 and each second semiconductor layer 23.

[0126] In some embodiments of the present disclosure, please continue to refer to Figure 2 As shown, before dry etching, a protective material layer 24 can be formed on the surface of the topmost first semiconductor layer 21 (i.e., the first semiconductor layer 21 farthest from the substrate 1) away from the substrate 1. The protective material layer 24 can cover the surface of the topmost first semiconductor layer 21. The material of the protective material layer 24 is different from the materials of the first semiconductor layer 21 and the second semiconductor layer 23, and during the dry etching process, the etching rate of the protective material layer 24 is much smaller than the etching rates of the first semiconductor layer 21 and the second semiconductor layer 23, which can ensure that the protective material layer 24 always covers the surface of the first semiconductor layer 21 farthest from the substrate 1 during the etching process of forming the trenches 201, thereby protecting the first semiconductor layer 21 farthest from the substrate 1 from damage. For example, the material of the protective material layer 24 can be silicon oxide.

[0127] In some embodiments of the present disclosure, the number of trenches 201 can be multiple, and the multiple trenches 201 can be spaced apart along the first direction x, so that the structure composed of each first semiconductor layer 21 and each second semiconductor layer 23 can be divided into multiple spaced-apart semiconductor groups by the multiple trenches 201.

[0128] Step S630, removing the second semiconductor layer 23 to form a gap 202.

[0129] As Figure 12 shown, after forming the trenches 201, each second semiconductor layer 23 can be removed, and then a gap 202 located between two adjacent first semiconductor layers 21 in the second direction y is formed. For example, each second semiconductor layer 23 can be removed by wet etching, and the etching solution for wet etching can be selected according to the specific materials of the first semiconductor layer 21 and the second semiconductor layer 23; that is, as long as the etching solution can remove the second semiconductor layer 23 and does not damage (or slightly damage, but does not affect its performance) the first semiconductor layer 21, the specific solution for wet etching is not specifically limited herein.

[0130] Step S640, forming a covering layer 3 in the gap 202, and the covering layer 3 covers the upper surface and the lower surface of the first semiconductor layer 21 distributed in the second direction y.

[0131] As Figure 13 and Figure 14As shown, a covering layer 3 can be respectively formed in each gap 202. The covering layer 3 can completely cover the upper surface and the lower surface of the first semiconductor layer 21 distributed along the second direction y. At the same time, the covering layer 3 does not cover the end face of the first semiconductor layer 21 close to the trench 201. That is, the end face of the first semiconductor layer 21 close to the trench 201 is exposed, so as to facilitate the subsequent formation of the protective layer 22 on the end face of the first semiconductor layer 21 close to the trench 201. In some embodiments of the present disclosure, please continue to refer to Figure 13 As shown, the covering layer 3 can conformally cover the upper surface and the lower surface of the first semiconductor layer 21. In some other embodiments of the present disclosure, please continue to refer to Figure 14 As shown, the covering layer 3 can fill the gap 202 between two adjacent first semiconductor layers 21 along the second direction y. The material of the covering layer 3 is different from the material of the first semiconductor layer 21 and the material of the subsequent protective layer 22 to be formed, so as to reduce the damage to the first semiconductor layer 21 and the protective layer 22 during the subsequent removal of the covering layer 3.

[0132] In an exemplary embodiment of the present disclosure, forming the covering layer 3 in the gap 202 and covering the upper surface and the lower surface of the first semiconductor layer 21 distributed along the second direction y (i.e., step S640) may include steps S710 - S740, where:

[0133] Step S710, forming a covering material layer 31 that conformally covers the surfaces of the first semiconductor layers 21.

[0134] As Figure 15 shown, the material of the covering material layer 31 is different from the material of the first semiconductor layer 21. For example, the material of the covering material layer 31 can be silicon nitride, silicon oxynitride, silicon boron nitride, or aluminum oxide, etc. The covering material layer 31 that conformally covers the upper surface of the first semiconductor layer 21, the lower surface of the first semiconductor layer 21, and the end face of the first semiconductor layer 21 close to the trench 201 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc. It should be noted that when a protective material layer 24 is formed on the topmost first semiconductor layer 21, the covering material layer 31 will not be formed on the upper surface of the topmost first semiconductor layer 21. At the same time, the covering material layer 31 is formed on the top and the side walls of the protective material layer 24.

[0135] In some embodiments of the present disclosure, the thickness of the covering material layer 31 is less than half of the width of the gap 202 between two adjacent first semiconductor layers 21 distributed in the second direction y, that is, the covering material layer 31 does not fill the gap 202 between two adjacent first semiconductor layers 21 in the second direction y.

[0136] Step S720: A filling layer 5 is formed between the first semiconductor layers 21 each having a covering material layer 31, and the filling layer 5 fills the gap 202 between adjacent first semiconductor layers 21.

[0137] The material of the filling layer 5 is different from that of the covering material layer 31. For example, the material of the filling layer 5 is silicon oxide. The filling layer 5 can be formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, etc. For the convenience of the process, the filling layer 5 can simultaneously cover the covering material layer 31 on the end face of the first semiconductor layer 21 close to the trench 201 and the covering material layer 31 on the top of the stacked film layer 2. As Figure 16 shown, the filling layer 5 on the top of the stacked film layer 2 and the filling layer 5 on the side wall of the trench 201 can be removed, so as to expose the covering material layer 31 on the end face of the first semiconductor layer 21 close to the trench 201.

[0138] Step S730: The covering material layer 31 on the end face of the first semiconductor layer 21 close to the trench 201 is removed to expose the end face of the first semiconductor layer 21 close to the trench 201.

[0139] As Figure 17 shown, the covering material layer 31 on the end face of the first semiconductor layer 21 close to the trench 201 can be removed by a dry etching process, so as to expose the end face of the first semiconductor layer 21 close to the trench 201, which is convenient for forming the protective layer 22 on this end face later. The etching gas for dry etching can be reasonably set according to the specific materials of the first semiconductor layer 21 and the covering material layer 31, as long as it can remove the covering material layer 31 and does not damage the first semiconductor layer 21 (or causes slight damage but does not affect the performance of the first semiconductor layer 21). Here, no special limitation is imposed on the etching gas for removing the covering material layer 31.

[0140] Step S740: The filling layer 5 is removed, and the remaining covering material layer 31 is used as the covering layer 3.

[0141] Please continue to refer to Figure 13 shown. The filling layer 5 can be removed by wet etching. The etching solution for wet etching can be reasonably set according to the specific materials of the filling layer 5, the first semiconductor layer 21, and the covering material layer 31, as long as it can remove the filling layer 5 and does not damage the first semiconductor layer 21 and the covering material layer 31 (or causes slight damage but does not affect the electrical performance of the first semiconductor layer 21 and at the same time does not affect the protective performance of the covering material layer 31). Here, no special limitation is imposed on the etching solution for removing the filling layer 5. It should be noted that when the materials of the protective material layer 24 and the filling layer 5 are the same, the thickness of the protective material layer 24 can be synchronously thinned when removing the filling layer 5.

[0142] In some other embodiments of the present disclosure, forming the covering layer 3 within the gap 202, where the covering layer 3 covers the upper and lower surfaces of the first semiconductor layer 21 distributed along the second direction y (i.e., step S640) may include step S810 and step S820, where:

[0143] Step S810: Form a covering material layer 31 on the surface of each first semiconductor layer 21, and the covering material layer 31 fills the gap 202.

[0144] As Figure 18 shown, the material of the covering material layer 31 is different from that of the first semiconductor layer 21. For example, the material of the covering material layer 31 can be silicon nitride, silicon oxynitride, silicon boron nitride, or aluminum oxide, etc. The covering material layer 31 can be formed on the surface of the stacked film layer 2 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc. During this process, the covering material layer 31 can fill the gap 202 between adjacent first semiconductor layers 21 distributed in the second direction y. It should be noted that during the formation of the covering material layer 31, for the convenience of the process, the covering material layer 31 can be formed simultaneously on the end face of the first semiconductor layer 21 close to the trench 201 and on the top of the stacked film layer 2 (e.g., on the protective material layer 24).

[0145] Step S820: Remove the covering material layer 31 located on the end face of the first semiconductor layer 21 close to the trench 201 to expose the end face of the first semiconductor layer 21 close to the trench 201, and use the remaining covering material layer 31 as the covering layer 3.

[0146] Please continue to refer to Figure 14 shown. The covering material layer 31 located on the top of the stacked film layer 2 (e.g., on the protective material layer 24) and on the end face of the first semiconductor layer 21 close to the trench 201 can be removed by a dry etching process, and the remaining covering material layer 31 is used as the covering layer 3.

[0147] Step S650: Form a protective layer 22 on the end face of the first semiconductor layer 21 close to the trench 201.

[0148] As Figure 19 shown, the protective layer 22 can be formed on the end face of the first semiconductor layer 21 close to the trench 201 by an in-situ steam oxidation process. For example, when the material of the first semiconductor layer 21 is silicon, the material of the protective layer 22 is silicon oxide. It should be noted that during the in-situ steam oxidation process, since the upper and lower surfaces of the first semiconductor layer 21 are covered by other film layers (e.g., the covering layer 3 or the protective material layer 24), therefore, the protective layer 22 will not be formed on the upper and lower surfaces of the first semiconductor layer 21.

[0149] Step S660: Remove the covering layer 3 to expose the gap 202.

[0150] Please continue to refer to Figure 11 As shown, after forming the protective layer 22, the covering layer 3 can be removed through an isotropic etching process, thereby exposing the upper and lower surfaces of the first semiconductor layer 21 distributed along the second direction y. It should be noted that when the surface of the topmost first semiconductor layer 21 is still covered with the protective material layer 24, the lower surface of the topmost first semiconductor layer 21 is exposed, while the upper surface is not exposed.

[0151] As Figure 1 shown, in step S120, the first semiconductor layer 21 is etched to reduce the thickness of the first semiconductor layer 21; the etching rate of the protective layer 22 is less than the etching rate of the first semiconductor layer 21.

[0152] As Figure 20 shown, the first semiconductor layer 21 can be etched through a wet etching process, thereby reducing the thickness of the first semiconductor layer 21, and further leaving a larger process space for fabricating word lines between two adjacent first semiconductor layers 21 distributed along the second direction y, which helps to reduce the process difficulty of fabricating word lines subsequently. And during the process of etching and thinning the first semiconductor layer 21, since protective layers 22 are respectively formed on the end faces of the first semiconductor layers 21 exposed in the trenches 201, and the etching rate of the protective layer 22 is less than the etching rate of the first semiconductor layer 21, during the process of etching and thinning the first semiconductor layer 21, the protective layer 22 can protect the end portions of the first semiconductor layer 21 close to the trenches 201, and the damage to the first semiconductor layer 21 in the first direction x during the etching process can be reduced, so that the distance between the semiconductor groups on both sides of the trenches 201 is relatively small, and more semiconductor groups can be arranged on the substrate 1 along the first direction x, which helps to fabricate more chip units on the substrate 1. That is, the storage density can be increased without increasing the number of layers of the first semiconductor layer 21.

[0153] In an exemplary embodiment of the present disclosure, the method for forming the semiconductor structure of the present disclosure may further include:

[0154] Step S130, after reducing the thickness of the first semiconductor layer 21, removing the protective layer 22.

[0155] As Figure 21 shown, the protective layer 22 can be removed through a dry etching process. It should be noted that when the material of the protective layer 22 is titanium silicide or doped silicon, the protective layer 22 can also be retained and used as a functional layer of the subsequently formed chip unit. When the material of the protective layer 22 is the same as the material of the protective material layer 24, which is silicon oxide, during the process of removing the protective layer 22, the protective material layer 24 can be thinned or the protective material layer 24 can be removed synchronously.

[0156] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0157] Embodiments of the present disclosure further provide a semiconductor structure, which can be formed by the method for forming a semiconductor structure according to any of the above embodiments. In some embodiments of the present disclosure, in the semiconductor structure formed by the method for forming a semiconductor structure in the present disclosure, after the first semiconductor layer 21 is thinned, the thickness of the first semiconductor layer 21 lost on both sides of the trench 201 in the first direction x is approximately 2.5 nm. Compared with the length (180 nm) of the first semiconductor layer 21 in the first direction x before the first semiconductor layer 21 is thinned, the loss amount is approximately 1.3%. Compared with the prior art (the loss amount is approximately 9.5% after the first semiconductor layer 21 is thinned), the loss amount of the forming method in the present application is reduced by 86%.

[0158] The specific details and manufacturing processes of each part in the above semiconductor structure have been described in detail in the corresponding method for forming a semiconductor structure. Therefore, they will not be elaborated here.

[0159] For example, the semiconductor structure can be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it can also be other storage devices, which will not be listed one by one here.

[0160] Those skilled in the art will readily conceive of other implementations of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Forming a stacked film layer on a substrate, the stacked film layer including a plurality of first semiconductor layers and a protective layer, the plurality of first semiconductor layers extending in a first direction and spaced apart in a second direction, and there being a gap between two adjacent first semiconductor layers in the second direction, the second direction intersecting the first direction; the stacked film layer having a trench, the trench penetrating through each of the first semiconductor layers in the second direction; the protective layer being formed on the end surface of each of the first semiconductor layers exposed in the trench; Etching the first semiconductor layer to reduce the thickness of the first semiconductor layer; the etching rate of the protective layer being less than the etching rate of the first semiconductor layer.

2. The forming method according to claim 1, wherein, The forming of the stacked film layer on the substrate includes: Forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed in the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a trench penetrating through each of the first semiconductor layers and each of the second semiconductor layers in the second direction; Forming the protective layer on the end surface of each of the first semiconductor layers exposed in the trench; Removing each of the second semiconductor layers to form the gap between adjacent first semiconductor layers.

3. The forming method according to claim 2, wherein, The forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the trench includes: Performing a back-etching on the end portion of the second semiconductor layer close to the trench to form a recess; Forming a covering layer in the recess; Forming the protective layer on the end surface of the first semiconductor layer close to the trench; Removing the covering layer.

4. The forming method according to claim 2, characterized in that, The forming of the protective layer on the end surface of each of the first semiconductor layers exposed in the trench includes: Simultaneously oxidizing the end portion of the first semiconductor layer exposed in the trench and the end portion of the second semiconductor layer exposed in the trench to form the protective layer on the end portion of the first semiconductor layer close to the trench and form a covering layer on the end portion of the second semiconductor layer; Removing the covering layer.

5. The forming method according to claim 3, characterized in that The material of the first semiconductor layer is silicon, the material of the covering layer is silicon nitride, and the forming of the protective layer on the end surface of the first semiconductor layer close to the trench includes: Forming a metal layer on the surface of the structure jointly formed by the covering layer and the first semiconductor layer; Performing a heat treatment on the metal layer to form a metal silicide layer on the surface of the first semiconductor layer; Removing the unreacted metal layer and using the metal silicide layer as the protective layer.

6. The forming method according to claim 3, wherein The forming of the protective layer on the end surface of the first semiconductor layer close to the trench includes: Performing ion doping on the end portion of the first semiconductor layer close to the trench and using the first semiconductor layer containing doping ions as the protective layer.

7. The forming method according to claim 1, wherein The forming of the stacked film layer on the substrate includes: Forming a plurality of first semiconductor layers and second semiconductor layers alternately distributed in the second direction on the substrate; Etching the first semiconductor layer and the second semiconductor layer to form a trench penetrating through each of the first semiconductor layers and each of the second semiconductor layers in the second direction; Remove the second semiconductor layer to form the gap; Form a covering layer within the gap, the covering layer covering the upper and lower surfaces of the first semiconductor layer distributed along the second direction; Form the protective layer on the end face of the first semiconductor layer close to the trench; Remove the covering layer to expose the gap.

8. The forming method according to claim 7, wherein The forming the covering layer within the gap, the covering layer covering the upper and lower surfaces of the first semiconductor layer distributed along the second direction, includes: Form a covering material layer conformally covering the surfaces of the first semiconductor layers; Form a filling layer between the first semiconductor layers having the covering material layer, the filling layer filling the gap between adjacent first semiconductor layers; Remove the covering material layer on the end face of the first semiconductor layer close to the trench to expose the end face of the first semiconductor layer close to the trench; Remove the filling layer and use the remaining covering material layer as the covering layer.

9. The forming method according to claim 7, wherein The forming the covering layer within the gap, the covering layer covering the upper and lower surfaces of the first semiconductor layer distributed along the second direction, includes: Form a covering material layer on the surfaces of the first semiconductor layers, the covering material layer filling the gap; Remove the covering material layer on the end face of the first semiconductor layer close to the trench to expose the end face of the first semiconductor layer close to the trench and use the remaining covering material layer as the covering layer.

10. The forming method according to any one of claims 1-4, 7-9, characterized in that, The forming method further includes: After thinning the thickness of the first semiconductor layer, remove the protective layer.

11. A semiconductor structure, characterized in that, The semiconductor structure is formed by the forming method of the semiconductor structure according to any one of claims 1-10.

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