A low-capacitance electrostatic protection device and a manufacturing method thereof

Abstract

The present invention provides a low-capacitance electrostatic protection device and a manufacturing method thereof, including an N-type heavily doped substrate, a first P-type epitaxial layer, and a second P-type epitaxial layer. The resistivity of the first P-type epitaxial layer is high resistance. An N-type inversion layer, an isolation deep trench, and a P-type heavily doped buried layer are provided in the first P-type epitaxial layer and the second P-type epitaxial layer. The N-type inversion layer is segmented by the P-type heavily doped buried layer, and the length of the inner part of the P-type heavily doped buried layer segmented by the isolation deep trench is W1, where W1 > the thickness of the N-type inversion layer. The P-type heavily doped buried layer, the first P-type epitaxial layer, and the N-type heavily doped substrate form a PIN diode. H is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate, and the breakdown voltage of the PIN diode can be changed by adjusting H. The beneficial effect of the present invention is that an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of electrostatic protection devices, and particularly relates to a low-capacitance electrostatic protection device and a manufacturing method thereof. Background Art

[0002] Electro-Static discharge (ESD) and Electrical OverStress (EOS) are natural phenomena existing in the application environment of electronic devices. These phenomena not only cause electronic devices to fail and greatly reduce the reliability of products, but in severe cases, may even directly cause irreversible damage to electronic devices. One of the effective methods to solve ESD and EOS is to add Transient Voltage Suppressors (TVS) to various interfaces of the system. TVS can provide efficient electrostatic and surge protection for the backend circuit or chip, and is a very common electrostatic protection device.

[0003] In recent years, with the increasingly complex system architecture of electronic products, the internal signal transmission frequency of electronic systems has been continuously climbing, and the transmission speed has also become faster and faster. In high-speed signal transmission lines, the presence of capacitance will affect the signal, such as causing signal attenuation and distortion. At this time, it is required that the electrostatic protection device must have low-capacitance characteristics, so as to ensure that high-speed signals can avoid the damage of ESD and EOS during transmission and maintain the signal quality and transmission speed without being interfered by the electrostatic protection device. However, in the prior art, it is often difficult to achieve the low-capacitance characteristics of electrostatic protection devices.

[0004] As shown in FIG. 1(a), for on-chip and off-chip electrostatic protection, avalanche diodes are usually used in the prior art. The negative electrode of the avalanche diode is usually connected to the "I / O or power port", and its positive electrode is usually connected to the "ground port". When a positive ESD pulse comes, the avalanche diode is reverse-biased and avalanche-conducts, and its avalanche breakdown voltage usually needs to be higher than the maximum operating voltage of the port. When a negative ESD pulse comes, the avalanche diode is forward-biased and conducts, equivalent to a forward-biased PN junction. FIG. 1(b) shows the structure of a vertical avalanche diode, which is fabricated on an N-type heavily doped substrate, a P-type epitaxial layer is grown, and then isolation deep trenches and P-type heavily doped active regions are fabricated. Generally speaking, the doping concentration of the P-type epitaxial layer is relatively heavy to obtain a lower and appropriate avalanche breakdown voltage. At this time, the overall parasitic capacitance of the avalanche diode is relatively large and cannot be used for electrostatic protection of high-speed I / O ports.

[0005] As shown in FIGS. 2(a) and 2(b), to reduce the parasitic capacitance of the avalanche diode, a P-type epitaxial layer with high resistivity can be used, thereby reducing the junction capacitance between the N-type heavily doped substrate / P-type epitaxial layer (corresponding to FIG. 2(a), representing the case where "the doping types of the substrate and the epitaxial layer are different") or the N-type active region / P-type epitaxial layer (corresponding to FIG. 2(b), representing the case where "the doping types of the substrate and the epitaxial layer are the same"). However, due to the presence of oxide charges C (usually positive charges), an "N-type inversion layer" will be formed on the high-resistance P-type epitaxial side. These inversion layers are connected to the N-type heavily doped substrate or the N-type heavily doped active region, ultimately equivalently increasing the junction area and introducing an additional parasitic capacitance of the N-type heavily doped substrate or active region / P-type epitaxial layer, deteriorating the overall parasitic capacitance. At the same time, the avalanche breakdown voltage of the N-type heavily doped substrate or active region / P-type epitaxial junction will also increase with the increase in the resistivity of the epitaxial layer. An excessively high breakdown voltage cannot meet the effective electrostatic protection requirements for some low-voltage circuit ports, such as the 3.3V / 5V USB (Universal Serial Bus) and HDMI (High-Definition Multimedia Interface) ports. Therefore, this method also cannot meet people's usage requirements. Summary of the Invention

[0006] To solve the problems in the prior art, the present invention provides a low-capacitance electrostatic protection device and a manufacturing method thereof. By arranging an N-type heavily doped substrate, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, an isolation deep trench, and a P-type heavily doped buried layer that cooperate with each other in the low-capacitance electrostatic protection device, the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance value of the entire electrostatic protection device, that is, a new type of vertical avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer induced by oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Ultimately, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is particularly suitable for electrostatic and surge protection of high-speed I / O ports, solving the problem in the prior art that it is difficult to achieve the low-capacitance characteristic of the electrostatic protection device, resulting in difficulty in meeting people's usage requirements.

[0007] A low-capacitance electrostatic protection device provided by the present invention includes an N-type heavily doped substrate, a first P-type epitaxial layer and a second P-type epitaxial layer disposed in the N-type heavily doped substrate from bottom to top. The resistivity of the first P-type epitaxial layer is high resistance. An N-type inversion layer and isolation deep trenches are provided in the first P-type epitaxial layer and the second P-type epitaxial layer in a matching manner. A P-type heavily doped buried layer is further provided between the first P-type epitaxial layer and the second P-type epitaxial layer. The N-type inversion layer is divided into a first N-type inversion layer and a second N-type inversion layer by the P-type heavily doped buried layer. The P-type heavily doped buried layer is divided into two parts by the isolation deep trenches. The length of the inner part of the P-type heavily doped buried layer divided by the isolation deep trenches is W1, and W1 > the thickness of the N-type inversion layer. The lower surface of the N-type heavily doped substrate can be connected to an I / O port one. A P+-heavily doped active region capable of being connected to an I / O port two is provided on the upper surface of the second P-type epitaxial layer. The P-type heavily doped buried layer, the first P-type epitaxial layer, and the N-type heavily doped substrate together form a PIN diode. The effective thickness H of the first P-type epitaxial layer is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate. The breakdown voltage of the PIN diode can vary with the adjustment of the effective thickness H of the first P-type epitaxial layer. The high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance value of the entire electrostatic protection device.

[0008] In a further improvement of the present invention, the resistivity of the first P-type epitaxial layer is M, and the value range of M is 20 ohm*cm ≤ M ≤ 300 ohm*cm.

[0009] In a further improvement of the present invention, an insulating oxide layer is further provided on the upper surface of the second P-type epitaxial layer, and the insulating oxide layer is disposed around the P+-heavily doped active region.

[0010] In a further improvement of the present invention, the top of the isolation deep trench is connected to the insulating oxide layer, and the bottom of the isolation deep trench extends into the N-type heavily doped substrate.

[0011] In a further improvement of the present invention, the I / O port two is a ground port, and the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

[0012] The present invention also provides a manufacturing method applied to the above-mentioned low-capacitance electrostatic protection device, including:

[0013] Step 1, prepare an N-type heavily doped substrate, and the doping concentration of the N-type heavily doped substrate is C1. The value range of C1 is 10 19 cm -3 ≤ C1 ≤ 10 21 cm -3 ;

[0014] Step 2: Grow a first P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤ C1 ≤ 10 16 cm -3 ;

[0015] Step 3: On the first P-type epitaxial layer, form a P-type heavily doped buried layer through ion implantation or diffusion process. The optional impurity types are boron or boron fluoride;

[0016] Step 4: Grow a second P-type epitaxial layer. The thickness of the second P-type epitaxial layer is larger than that of the first P-type epitaxial layer;

[0017] Step 5: Manufacture isolation deep trenches;

[0018] Step 6: Manufacture a P+ heavily doped active region through ion implantation or diffusion process, and then perform window opening of contact holes, deposition and etching of metal, and PAD window opening.

[0019] For further improvement of the present invention, in the said Step 3, a subsequent push-junction process can be added to control the junction depth of the P-type heavily doped buried layer; in the said Step 6, a subsequent push-junction process can also be added to control the junction depth of the P+ heavily doped active region.

[0020] For further improvement of the present invention, only the second P-type epitaxial layer is provided in the N-type heavily doped substrate, and the first P-type epitaxial layer is not provided. The corresponding N-type inversion layer and the isolation deep trenches are provided in the N-type heavily doped substrate and the second P-type epitaxial layer. The P-type heavily doped buried layer is provided between the N-type heavily doped substrate and the second P-type epitaxial layer. W1 is slightly larger than the thickness of the N-type inversion layer. The P-type heavily doped buried layer and the N-type heavily doped substrate form a PN junction. The avalanche breakdown voltage of the PN junction can vary with the adjustment of the doping concentration of the P-type heavily doped buried layer. The P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer above it and the second P-type epitaxial layer.

[0021] The present invention also provides a manufacturing method applied to the above low-capacitance electrostatic protection device, including:

[0022] Step 1: Prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤ C1 ≤ 10 21 cm -3 ;

[0023] Step 2: On the N-type heavily doped substrate, a P-type heavily doped buried layer is formed through ion implantation or diffusion process. The optional impurity types are boron or boron fluoride;

[0024] Step 3: Grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ;

[0025] Step 4: Fabricate isolation deep trenches;

[0026] Step 5: Fabricate a P+ heavily doped active region through ion implantation or diffusion process, and then perform window opening of contact holes, deposition and etching of metal, and window opening of PAD.

[0027] For further improvement of the present invention, in the said Step 2, a subsequent push-junction process can be added to regulate the junction depth of the P-type heavily doped buried layer; in the said Step 5, a subsequent push-junction process can also be added to regulate the junction depth of the P+ heavily doped active region.

[0028] Compared with the prior art, the beneficial effects of the present invention are: providing a low-capacitance electrostatic protection device and its manufacturing method. By arranging an N-type heavily doped substrate, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, isolation deep trenches and a P-type heavily doped buried layer that cooperate with each other in the low-capacitance electrostatic protection device, the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device, that is, designing a new type of vertical avalanche diode structure, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer due to oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem that it is difficult to meet the user's needs due to the low-capacitance characteristics of electrostatic protection devices in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0030] FIG. 1(a) is a schematic diagram of electrostatic protection of a typical existing avalanche diode;

[0031] Figure 1(b) is a schematic structural diagram of a typical existing avalanche diode;

[0032] Figure 2(a) is a schematic structural diagram of an existing low-capacitance vertical avalanche diode with different doping types in the substrate and epitaxy;

[0033] Figure 2(b) is a schematic structural diagram of an existing low-capacitance vertical avalanche diode with the same doping types in the substrate and epitaxy;

[0034] Figure 3 Figure 10 is a schematic structural diagram of the first embodiment of the low-capacitance electrostatic protection device of the present invention;

[0035] Figure 4 Figure 11 is a schematic layout diagram of the first embodiment of the low-capacitance electrostatic protection device of the present invention;

[0036] Figure 5 Figure 12 is a flowchart of the manufacturing method of the first embodiment of the low-capacitance electrostatic protection device of the present invention;

[0037] Figure 6 Figure 13 is a schematic structural diagram of the second embodiment of the low-capacitance electrostatic protection device of the present invention;

[0038] Figure 7 Figure 14 is a flowchart of the manufacturing method of the second embodiment of the low-capacitance electrostatic protection device of the present invention. Detailed implementation manners

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field of the present invention; the terms used in the description of the present application in the specification are only for the purpose of describing specific embodiments, and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the specification and claims of the present invention or the above drawings are used to distinguish different objects, rather than to describe a specific order.

[0040] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present invention. The phrase appearing in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0041] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0042] As shown Figures 3 - 5 in FIG. 1, Embodiment 1 of a low-capacitance electrostatic protection device provided by the present invention includes an N-type heavily doped substrate 300, a first P-type epitaxial layer 310 and a second P-type epitaxial layer 312 which are arranged in the N-type heavily doped substrate 300 from bottom to top. The resistivity of the first P-type epitaxial layer 310 is high resistance. An N-type inversion layer and an isolation deep trench 313 are provided in the first P-type epitaxial layer 310 and the second P-type epitaxial layer 312 in a matching manner. A P-type heavily doped buried layer 311 is further provided between the first P-type epitaxial layer 310 and the second P-type epitaxial layer 312. The N-type inversion layer is divided into a first N-type inversion layer 316 and a second N-type inversion layer 317 by the P-type heavily doped buried layer 311. The P-type heavily doped buried layer 311 is divided into two parts by the isolation deep trench 313. The length of the inner part of the P-type heavily doped buried layer 311 divided by the isolation deep trench 313 is W1, and W1 > the thickness of the N-type inversion layer. The lower surface of the N-type heavily doped substrate 300 can be connected to an I / O port 130. A P+-heavily doped active region 314 capable of being connected to an I / O port 2 120 is provided on the upper surface of the second P-type epitaxial layer 312. The P-type heavily doped buried layer 311, the first P-type epitaxial layer 310, and the N-type heavily doped substrate 300 together form a PIN diode. The effective thickness H of the first P-type epitaxial layer 310 is the distance between the P-type heavily doped buried layer 311 and the N-type heavily doped substrate 300. Among them, the resistivity of the first P-type epitaxial layer 310 is M, and the value range of M is 20 ohm*cm ≤ M ≤ 300 ohm*cm. The breakdown voltage of the PIN diode can change with the adjustment of the effective thickness H of the first P-type epitaxial layer 310. The high-resistance first P-type epitaxial layer 310 and the second N-type inversion layer 317 can reduce the capacitance of the entire electrostatic protection device, that is, a new type of vertical avalanche diode structure is designed, which can effectively shield the deterioration of the N-type inversion layer on the capacitance of the electrostatic protection device caused by oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports.

[0043] As shown Figures 3 - 4As shown, an insulating oxide layer is further provided on the upper surface of the second P-type epitaxial layer 312. The insulating oxide layer is disposed around the P+-heavily doped active region 314. The top of the isolation deep trench 313 is connected to the insulating oxide layer 315. The bottom of the isolation deep trench 313 extends into the N-type heavily doped substrate 300. The I / O port two 120 is a ground port. The filling material in the isolation deep trench 313 is silicon dioxide or silicon nitride or High-K. In this embodiment, the resistivity of the first P-type epitaxial layer 310 is high resistance to achieve low parasitic capacitance. The resistivity of the second P-type epitaxial layer 312 can be selected as high resistance, or medium resistance or low resistance. The P-type heavily doped buried layer 311 surrounds the isolation deep trench 313 in the layout. The inner part length W1 of the P-type heavily doped buried layer 311 divided by the isolation deep trench 313 needs to ensure that it is greater than the thickness of the N-type inversion layer to completely block the inversion layer. The outer length W2 of the P-type heavily doped buried layer 311 exceeding the isolation deep trench 313 is not limited. At this time, the N-type inversion layer is divided into a first N-type inversion layer 316 and a second N-type inversion layer 317 by the P-type heavily doped buried layer 311. Among them, only the second N-type inversion layer 317 is connected to the N-type heavily doped substrate 300. Therefore, only the second N-type inversion layer 317 will contribute additional capacitance. The capacitance of the first N-type inversion layer 316 can be optimized, thereby reducing the overall parasitic capacitance of the electrostatic protection device and shielding the influence of oxide charges to the greatest extent. In addition, the breakdown voltage of the avalanche diode can be regulated by the effective thickness H of the first P-type epitaxial layer 310 (H is the "spacing between the P-type heavily doped buried layer 311 and the N-type heavily doped substrate 300"). Specifically, at this time, the P-type heavily doped buried layer 311 / the first P-type epitaxial layer 310 / the N-type heavily doped substrate 300 together form a PIN diode. Therefore, when H is smaller, the breakdown voltage of the PIN diode will decrease accordingly, so that the turn-on voltage of this embodiment can be flexibly adjusted, and thus it can be used for electrostatic and surge protection of various low / medium / high voltage circuits. It is worth mentioning that when the base region of the PIN diode is fully depleted, the second N-type inversion layer 317 brought by the isolation deep trench 313 will no longer have a deteriorating effect on the overall parasitic capacitance.

[0044] As Figure 5 shown, the manufacturing method of the first embodiment of the present invention includes:

[0045] Step 1, prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1. The doping concentration of the N-type heavily doped substrate is usually high. In this embodiment, the value range of C1 is 10 19 cm -3 ≤ C1 ≤ 10 21 cm -3 ;

[0046] Step 2, grow the first P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2. To reduce capacitance, its doping concentration needs to be very low. In this embodiment, the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; In addition, the effective thickness H determines the avalanche voltage of the entire electrostatic protection device. Therefore, the effective thickness H can be adjusted according to different voltage requirements;

[0047] Step 3, on the first P-type epitaxial layer, form a P-type heavily doped buried layer through ion implantation or diffusion process. The optional impurity types are boron or boron fluoride. A subsequent drive-in process can be added to control the junction depth of the P-type heavily doped buried layer;

[0048] Step 4, grow the second P-type epitaxial layer. The thickness of the second P-type epitaxial layer is larger than that of the first P-type epitaxial layer. The doping concentration can be equal to, greater than, or less than that of the first P-type epitaxial layer;

[0049] Step 5, manufacture isolation deep trenches. The filling material in the isolation deep trenches is silicon dioxide, silicon nitride, or High-K;

[0050] Step 6, manufacture a P+ heavily doped active region through ion implantation or diffusion process. A subsequent drive-in process can also be added to control the junction depth of the P+ heavily doped active region. Then, perform a typical back-end-of-line (BEOL) process, including opening contact holes, depositing and etching metals, and opening PADs.

[0051] Such as Figure 6As shown in the figure, this is the second embodiment of a low-capacitance electrostatic protection device provided by the present invention. The difference from the first embodiment is that only the second P-type epitaxial layer is provided in the N-type heavily doped substrate, and the first P-type epitaxial layer is not provided. The corresponding N-type inversion layer and isolation deep trench are provided in the N-type heavily doped substrate and the second P-type epitaxial layer. The P-type heavily doped buried layer is provided between the N-type heavily doped substrate and the second P-type epitaxial layer. W1 is slightly larger than the thickness of the N-type inversion layer. The P-type heavily doped buried layer and the N-type heavily doped substrate form a PN junction, and the avalanche breakdown voltage of the PN junction can vary with the adjustment of the doping concentration of the P-type heavily doped buried layer. The P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer above it and the second P-type epitaxial layer. That is to say, in this embodiment, only one epitaxial layer, namely the second P-type epitaxial layer, is used, the structure is simpler, the cost is lower, and the yield is easier to control. At this time, the P-type heavily doped buried layer and the N-type heavily doped substrate form a PN junction. By adjusting the doping concentration of the P-type heavily doped buried layer, the avalanche breakdown voltage can be regulated; and the presence of the P-type heavily doped buried layer, although it can shield the parasitic capacitance between the N-type inversion layer above it and the second P-type epitaxial layer, the junction between the P-type heavily doped buried layer and the N-type heavily doped substrate itself may also introduce a considerable parasitic capacitance. Therefore, it is necessary to finely optimize the size of W1 so that it only exceeds the thickness of the N-type inversion layer and leave a certain margin as a preference.

[0052] As Figure 7 shown, this is the manufacturing method of the second embodiment of the present invention, including:

[0053] Step 1: Prepare an N-type heavily doped substrate with a doping concentration of C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ;

[0054] Step 2: On the N-type heavily doped substrate, form a P-type heavily doped buried layer by ion implantation or diffusion process. The optional impurity types are boron or boron fluoride; a subsequent push-junction process can be added to regulate the junction depth of the P-type heavily doped buried layer;

[0055] Step 3: Grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ;

[0056] Step 4: Carry out the manufacture of the isolation deep trench;

[0057] Step 5: fabricate the P+ heavily doped active region through ion implantation or diffusion process. A subsequent drive-in process can also be added to control the junction depth of the P+ heavily doped active region. Then, perform the typical back-end-of-line (BEOL) process, including opening contact holes, depositing and etching metals, and opening PADs.

[0058] The manufacturing process of a low-capacitance electrostatic protection device according to the present invention is applicable to various common integrated circuit manufacturing processes, such as nanoscale complementary metal oxide semiconductor (CMOS) process, three-dimensional fin field-effect transistor (FinFET) or gate-all-around FET (GAA) process, or silicon-on-insulator (SOI) process, etc.

[0059] As can be seen from the above, the present invention provides a low-capacitance electrostatic protection device and its manufacturing method. By arranging a mutually cooperating N-type heavily doped substrate, a first P-type epitaxial layer, a second P-type epitaxial layer, an N-type inversion layer, isolation deep trenches, and a P-type heavily doped buried layer in the low-capacitance electrostatic protection device, the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device. That is, a new type of vertical avalanche diode structure is designed, which can effectively shield the deterioration of the capacitance of the electrostatic protection device caused by the N-type inversion layer due to oxide charges, and can solve the contradiction between the parasitic capacitance and the avalanche breakdown voltage. Finally, an electrostatic protection device with ultra-low parasitic capacitance and adjustable breakdown voltage can be realized, which is especially suitable for electrostatic and surge protection of high-speed I / O ports, and solves the problem in the prior art that it is difficult to achieve the low-capacitance characteristic of the electrostatic protection device, resulting in difficulty in meeting people's usage requirements.

[0060] The above-described specific embodiments are the preferred embodiments of the present invention, and do not limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific embodiment. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A low capacitance electrostatic protection device, characterized in that: The invention comprises an N-type heavily doped substrate and a first P-type epitaxial layer and a second P-type epitaxial layer arranged from bottom to top in the N-type heavily doped substrate, wherein the resistivity of the first P-type epitaxial layer is high resistance, and the first P-type epitaxial layer and the second P-type epitaxial layer are provided with matching N-type inversion layers and isolation deep trenches, and a P-type heavily doped buried layer is further provided between the first P-type epitaxial layer and the second P-type epitaxial layer, and the N-type inversion layer is divided into a first N-type inversion layer and a second N-type inversion layer by the P-type heavily doped buried layer, and the P-type heavily doped buried layer is divided into two parts by the isolation deep trench, and the inner part of the P-type heavily doped buried layer divided by the isolation deep trench is W1, and W1>the length of ... The thickness of the N-type inversion layer, the lower surface of the N-type heavily doped substrate can be connected to the I / O port one, the upper surface of the second P-type epitaxial layer is provided with a P+ heavily doped active area that can be connected to the I / O port two, the P-type heavily doped buried layer, the first P-type epitaxial layer, and the N-type heavily doped substrate together constitute a PIN diode, the effective thickness H of the first P-type epitaxial layer is the distance between the P-type heavily doped buried layer and the N-type heavily doped substrate, the breakdown voltage of the PIN diode can be adjusted with the effective thickness H of the first P-type epitaxial layer, and the high-resistance first P-type epitaxial layer and the second N-type inversion layer can reduce the capacitance of the entire electrostatic protection device.

2. The low capacitance electrostatic protection device according to claim 1, characterized in that: The resistivity of the first P-type epitaxial layer is M, and the value range of M is 20ohm*cm≤M≤300ohm*cm.

3. The low capacitance electrostatic protection device according to claim 2, characterized in that: An insulating oxide layer is also provided on the upper surface of the second P-type epitaxial layer, and the insulating oxide layer is arranged around the P+ heavily doped active region.

4. The low capacitance electrostatic protection device according to claim 3, characterized in that: The top of the isolation deep trench is connected to the insulating oxide layer, and the bottom of the isolation deep trench extends into the N-type heavily doped substrate.

5. The low capacitance electrostatic protection device according to claim 4, characterized in that: The second I / O port is a ground port, and the filling material in the isolation deep trench is silicon dioxide or silicon nitride or High-K.

6. The low capacitance electrostatic protection device according to any one of claims 1 to 5, characterized in that: Only the second layer of P-type epitaxial layer is arranged in the N-type heavily doped substrate, and the first layer of P-type epitaxial layer is not arranged. The corresponding N-type inversion layer and the isolation deep trench are arranged in the N-type heavily doped substrate and the second layer of P-type epitaxial layer. The P-type heavily doped buried layer is arranged between the N-type heavily doped substrate and the second layer of P-type epitaxial layer. W1 is slightly larger than the thickness of the N-type inversion layer. The P-type heavily doped buried layer forms a PN junction with the N-type heavily doped substrate. The avalanche breakdown voltage of the PN junction can change with the adjustment of the doping concentration of the P-type heavily doped buried layer. The P-type heavily doped buried layer can shield the parasitic capacitance between the N-type inversion layer above it and the second layer of P-type epitaxial layer.

7. A manufacturing method, applied to the low capacitance electrostatic protection device according to any one of claims 1 to 5, characterized in that: include: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: grow the first P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the first P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 3, forming a P-type heavily doped buried layer on the first P-type epitaxial layer by ion implantation or diffusion process, wherein the optional impurity type is boron or boron fluoride; Step 4, growing a second P-type epitaxial layer, wherein the thickness of the second P-type epitaxial layer is greater than the thickness of the first P-type epitaxial layer; Step 5, manufacturing the isolation deep trench; Step 6: Create a P+ heavily doped active area through ion implantation or diffusion process, and then open contact holes, deposit and etch metal, and open PAD windows.

8. The manufacturing method according to claim 7, characterized in that: In step 3, a subsequent junction pushing process may be added to control the junction depth of the P-type heavily doped buried layer; in step 6, a subsequent junction pushing process may also be added to control the junction depth of the P+ heavily doped active region.

9. A manufacturing method, applied to the low capacitance electrostatic protection device according to claim 6, characterized in that: include: Step 1: prepare an N-type heavily doped substrate. The doping concentration of the N-type heavily doped substrate is C1, and the value range of C1 is 10 19 cm -3 ≤C1≤10 21 cm -3 ; Step 2: On the N-type heavily doped substrate, a P-type heavily doped buried layer is formed by ion implantation or diffusion process, and the optional impurity type is boron or boron fluoride; Step 3: grow a second P-type epitaxial layer on the N-type heavily doped substrate. The doping concentration of the second P-type epitaxial layer is C2, and the value range of C2 is 10 13 cm -3 ≤C1≤10 16 cm -3 ; Step 4, manufacturing isolation deep trenches; Step 5: Create a P+ heavily doped active area through ion implantation or diffusion process, and then perform contact hole opening, metal deposition and etching, and PAD window opening.

10. The manufacturing method according to claim 9, characterized in that: In step 2, a subsequent junction pushing process may be added to control the junction depth of the P-type heavily doped buried layer; in step 5, a subsequent junction pushing process may also be added to control the junction depth of the P+ heavily doped active region.

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