Display substrate and display device

Abstract

The application provides a display substrate and a display device. The display substrate comprises a substrate, a sub-pixel, a data line and a selection switch. The substrate comprises a display area and a peripheral area. The sub-pixel and the data line are located in the display area, and the selection switch is located in the peripheral area. The selection switch comprises a first selection switch and a second selection switch located on both sides of the first selection switch. The data lead comprises a plurality of first data leads and a plurality of second data leads. The first selection switch and the second selection switch are electrically connected with the first data lead and the second data lead respectively. The width of at least part of the line segment in the first data lead is greater than the width of at least part of the line segment in the second data lead. The width of the first data lead and the second data lead is set, which can effectively reduce the parasitic capacitance difference between different areas, thereby effectively improving the dark stripe defect of the display substrate.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to a display substrate and a display device. Background Technology

[0002] Currently, data driver chips in monitors output pixel voltages to pixel units via data lines. Because monitors have a large number of data lines, the data driver chip requires a corresponding number of pins. This results in a larger number of data transmission lines for each data line, which is detrimental to achieving narrow bezels in monitors. Summary of the Invention

[0003] In view of this, this application provides a display substrate, a display device, and a wiring method.

[0004] The display substrate of this application includes:

[0005] A substrate, the substrate including a display area and at least a peripheral area located on one side of the display area;

[0006] Multiple sub-pixels are located in the display area;

[0007] Multiple data lines, located in the display area and the surrounding area, are configured to provide data signals to the multiple sub-pixels;

[0008] Multiple data leads are located in the surrounding area and electrically connected to the multiple data lines;

[0009] Multiple selection switches are located in the peripheral area and arranged at intervals. The multiple selection switches are located on the side of the multiple data lines away from the display area. At least one of the multiple selection switches is electrically connected to at least two of the multiple data lines and one of the multiple data leads.

[0010] The plurality of selection switches include a plurality of first selection switches located on one side of the display area and a plurality of second selection switches located on both sides of the plurality of first selection switches. The plurality of data leads include a plurality of first data leads and a plurality of second data leads. The first selection switches are electrically connected to the first data leads, and the second selection switches are electrically connected to the second data leads. The width of at least a portion of the line segments in the first data leads is greater than the width of at least a portion of the line segments in the second data leads.

[0011] In some embodiments, the display substrate further includes:

[0012] Multiple switch lines are located in the peripheral area, each switch line is electrically connected to the multiple selector switches, the multiple switch lines are configured to provide switch signals to the multiple selector switches, and the multiple switch lines overlap with at least a portion of the line segments of the first data lead and at least a portion of the line segments of the second data lead.

[0013] In some implementations, the time interval between the switching signals of adjacent switching lines ranges from 0.5 to 2 microseconds.

[0014] In some embodiments, the first data lead includes a first sub-segment that intersects the plurality of switch lines perpendicularly, and the second data lead includes a second sub-segment that intersects the plurality of switch lines perpendicularly, wherein at least a portion of the width of the first sub-segment is greater than at least a portion of the width of the second sub-segment.

[0015] In some implementations, the peripheral area includes a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area, wherein the first selection switch and the second selection switch are located in the first peripheral area.

[0016] In some embodiments, the first selection switch and the second selection switch are arranged sequentially along the edge of the display area.

[0017] In some embodiments, the first selection switch and the second selection switch are staggered along a direction perpendicular to the direction in which the display area extends.

[0018] In some implementations, at least one of the plurality of selector switches is connected to six or three of the data lines.

[0019] In some embodiments, the display substrate further includes:

[0020] Multiple gate lines are located at least in the display area and electrically connected to the multiple sub-pixels, the multiple gate lines being configured to provide gate signals to the multiple sub-pixels;

[0021] Multiple light-emitting control lines are located at least in the display area and electrically connected to the multiple sub-pixels, and the multiple light-emitting control lines are configured to provide light-emitting control signals to the multiple sub-pixels;

[0022] A gate driving circuit, located at least in the peripheral region, includes a plurality of gate driving units, the plurality of gate driving units being electrically connected to the plurality of gate lines;

[0023] The light-emitting control driving circuit, located at least in the peripheral area, includes multiple light-emitting control driving units, which are electrically connected to the multiple light-emitting control lines.

[0024] In some implementations, at least one of the plurality of sub-pixels includes:

[0025] The driving transistor includes:

[0026] The first active layer located on the substrate,

[0027] The first gate is located on the side of the first active layer away from the substrate.

[0028] A first insulating layer located on the side of the first gate away from the substrate.

[0029] The second insulating layer is located on the side of the first insulating layer away from the substrate, and

[0030] Located on the side of the second insulating layer away from the substrate and electrically connected to the source and drain of the first active layer; and

[0031] Storage capacitors, including:

[0032] The first electrode plate is located on the same layer as the first gate, and

[0033] The second electrode plate is located between the first insulating layer and the second insulating layer.

[0034] In some embodiments, at least one of the plurality of selection switches includes a plurality of switching transistors, wherein the at least one switching transistor includes:

[0035] A second active layer located on one side of the substrate;

[0036] The second gate is located on the side of the second active layer away from the substrate and is electrically connected to one of the multiple switching lines.

[0037] The first electrode is located on the side of the second gate away from the substrate and is electrically connected to one of the plurality of data leads;

[0038] The second electrode is located on the same layer as the first electrode and is electrically connected to one of the multiple data lines.

[0039] In some embodiments, the orthographic projections of the first electrode on the substrate, the orthographic projections of the second electrode on the substrate, and the orthographic projections of the second gate on the substrate do not overlap.

[0040] In some embodiments, at least a portion of the first data lead electrically connected to the first selection switch is located on the same layer as the second electrode plate, and at least a portion of the second data lead electrically connected to the second selection switch is located on the same layer as the first electrode plate.

[0041] This application also provides a display device, which includes the aforementioned display substrate.

[0042] The display substrate and display device in this application,

[0043] By using multiple selection switches, including multiple first selection switches and multiple second selection switches located on both sides of the multiple first selection switches, and by electrically connecting the first selection switches to the first data leads and the second selection switches to the second data leads, and by setting at least a portion of the width of the first data leads to be greater than the width of at least a portion of the width of the second data leads, the overlap area between the first data leads and other wirings can be increased. This makes the overlap area between the first data leads and other wirings and the overlap area between the second data leads and other wirings similar. In this way, the difference between the data signals provided by the first data leads and the data signals provided by the second data leads can be improved, thereby enhancing the uniformity of display brightness.

[0044] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0045] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0046] Figure 1 This is a schematic diagram of the planar structure of a display substrate according to certain embodiments of this application.

[0047] Figure 2 yes Figure 1 A partial schematic diagram of point II in the middle.

[0048] Figure 3 This is a timing diagram of the switching signal according to an embodiment of this application.

[0049] Figure 4 This is a schematic diagram of the planar structure of a display substrate according to certain embodiments of this application.

[0050] Figure 5 yes Figure 4 A cross-sectional view at point VV.

[0051] Figure 6 This is a schematic diagram of the planar structure of the display substrate according to an embodiment of this application.

[0052] Figure 7 yes Figure 2 A magnified view of section VII in the middle.

[0053] Figure 8 yes Figure 7 A schematic cross-sectional view of section VIII-VIII.

[0054] Figure 9 This is a schematic diagram illustrating the pixel circuit layout of a sub-pixel according to an embodiment of the present disclosure, representing certain implementations of this application.

[0055] Explanation of key component symbols:

[0056] Substrate 11, display area 111, peripheral area 112, first peripheral area 112A, corner area 112B, second peripheral area 112C;

[0057] Sub-pixel 12, driving transistor 121, first active layer 1211, gate dielectric layer 1212, first gate 1213, first insulating layer 1214, second insulating layer 1215, source 1216, drain 1217, storage capacitor 122, first electrode plate 1221, second electrode plate 1222, light-emitting diode 123, anode 1231, light-emitting layer 1232, cathode 1233, buffer layer 124, planarization layer 125, pixel boundary layer 126, support layer 127, encapsulation layer 128, first inorganic layer 1281, second inorganic layer 1282, organic layer 1283;

[0058] Data line 13, gate line 14, light emission control line 15, driver chip 20, gate drive circuit 21, gate drive unit 211, light emission control drive circuit 22, light emission control drive unit 221, selection switch 23, first selection switch 23A, second selection switch 23B, switching transistor 231, second active layer 2311, second gate 2312, first electrode 2313, second electrode 2314, switch line 24;

[0059] Data lead 31, first data lead 31A, first sub-segment 311, second data lead 31B, second sub-segment 312;

[0060] Switch connection line M1, first initial signal line GSTV, first clock signal line GCB, second clock signal line GCK, second initial signal line ESTV, third clock signal line ECK, fourth clock signal line ECB, and second gate connection line M2. Detailed Implementation

[0061] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0062] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0063] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0064] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0065] In related technologies, a multiplexer (MUX) can be set between the data driver chip and the data transmission line. The data driver chip can connect three sub-pixels (referred to as the 1:3 MUX scheme) or six sub-pixels (referred to as the 1:6 MUX scheme) through the data selector, thereby reducing the number of data transmission lines, reducing the size of the data driver chip, and reducing the size of the display bezel.

[0066] However, the inventors learned that because data transmission lines and other wiring have overlapping areas, they are prone to mutual influence and parasitic capacitance. Furthermore, the overlapping area of ​​data transmission lines and other wiring in different areas is different, resulting in different parasitic capacitance in different areas, which makes the display prone to low grayscale dark stripe defects.

[0067] In view of this, please combine Figure 1 and Figure 2 This application provides a display substrate, which includes a substrate 11 and a plurality of sub-pixels 12, a plurality of data lines 13 and a plurality of gate lines 14 on the substrate 11.

[0068] The substrate 11 includes a display area 111 and a peripheral area 112 located at least on one side of the display area 111. A plurality of sub-pixels 12 are located in the display area 111, and a plurality of data lines 13 are located in the display area 111 and the peripheral area 112. The data lines 13 are configured to provide data signals to the plurality of sub-pixels 12. A plurality of data leads 31 are located in the peripheral area 112 and electrically connected to the plurality of data lines 13. A plurality of selection switches 23 are located in the peripheral area 112 and spaced apart. The plurality of selection switches 23 are located on the side of the plurality of data lines 13 away from the display area 111, and at least one of the selection switches 23 is electrically connected to at least two of the plurality of data lines 13 and one of the plurality of data leads 31.

[0069] The plurality of selection switches 23 include a plurality of first selection switches 23A located on one side of the display area 111 and a plurality of second selection switches 23B located on both sides of the plurality of first selection switches 23A. The plurality of data leads 31 include a plurality of first data leads 31A and a plurality of second data leads 31B. The first selection switches 23A are electrically connected to the first data leads 31A, and the second selection switches 23B are electrically connected to the second data leads 31B. The width of at least a portion of the line segments in the first data leads 31A is greater than the width of at least a portion of the line segments in the second data leads 31B.

[0070] This application also provides a display device. The display substrate provided in this application can be applied to the display device of this application. That is to say, the display device of this application can display images through the display substrate of this application.

[0071] In the display substrate and display device of this application embodiment, a plurality of selection switches 23 include a plurality of first selection switches 23A and a plurality of second selection switches 23B located on both sides of the plurality of first selection switches 23A. The first selection switches 23A are electrically connected to the first data lead 31A, and the second selection switches 23B are electrically connected to the second data lead 31B. The setting that the width of at least a portion of the line segments in the first data lead 31A is greater than the width of at least a portion of the line segments in the second data lead 31B can increase the overlapping area of ​​the first data lead 31A with other wirings. This makes the overlapping area of ​​the first data lead 31A with other wirings and the overlapping area of ​​the second data lead 31B with other wirings similar. In this way, the difference between the data signal provided by the first data lead 31A and the data signal provided by the second data lead 31B can be reduced, thereby improving the brightness uniformity of the display.

[0072] Please combine further Figures 1 to 7 The following explanation will focus on the specific structure of the display substrate and the display device.

[0073] In some embodiments, the display device may be a camera gimbal, translation pen, smartphone, tablet computer, smart bracelet, virtual reality device, personal data terminal, laptop computer, or other display device capable of displaying images, but is not limited thereto. For example, in this embodiment, the display device may be described as a camera gimbal.

[0074] The display substrate can be an organic light-emitting diode (OLED) display substrate.

[0075] like Figure 1 As shown, the display substrate includes a substrate 11. This display substrate is, for example, a motherboard in which the pixel array has been fabricated during the manufacturing process and before the cutting process. After the display substrate undergoes a testing process, the circuit units, connecting lines, etc. used in the testing stage are cut off to prepare a display panel for the final product.

[0076] like Figure 1 As shown, the substrate 11 includes a display area 111 and a peripheral area 112. The peripheral area 112 is located on at least one side of the display area 111. For example, the peripheral area 112 surrounds the display area 111 and occupies the largest area below the display area 111 (the area with the most circuit units, connecting lines, etc.). The display area 111 includes a pixel array, which includes a plurality of sub-pixels 12 for performing the display functions of the display area 111. For example, the plurality of sub-pixels 12 are arranged in an array including multiple rows and multiple columns.

[0077] like Figure 1-2As shown, the display substrate also includes multiple data lines 13 located in the display area 111 and the peripheral area 112. These data lines 13 are configured to be electrically connected to sub-pixels 12 in multiple columns, respectively, to provide data signals to the sub-pixels 12 in each column, thereby controlling and driving the multiple sub-pixels 12 to display the image. For example, each connection of the multiple data lines 13 is located in the same column (e.g., column direction refers to...). Figure 1 The 12th sub-pixel (vertical direction) in the middle.

[0078] like Figure 2 As shown, the display substrate also includes multiple data leads 31 and a driver chip 20 located in the peripheral area 112. The multiple data leads 31 are electrically connected to multiple data lines 13. That is, one end of the data lead 31 near the display area 111 is electrically connected to the data line 13, and the other end of the data lead 31 away from the display area 111 extends to the side of the peripheral area 112 away from the display area 111 to connect to the driver chip 20 in the peripheral area 112. The driver chip 20 is configured to provide data signals to each data lead 31.

[0079] like Figure 2 As shown, the display substrate also includes a plurality of selection switches 23 located in the peripheral area 112. The plurality of selection switches 23 are arranged at intervals, and at least one of the selection switches 23 is electrically connected to at least two of the plurality of data lines 13 and one of the plurality of data leads 31. That is, the data lead 31 can be connected to the data lines 13 located in the display area 111 via the plurality of selection switches 23. For example, the plurality of selection switches 23 are located in the peripheral area 112 and near one end of the display area 111, and at least one of the plurality of selection switches 23 has one end connected to one of the plurality of data leads 31, and the other end connected to three of the plurality of data lines 13. As another example, the plurality of selection switches 23 are located in the peripheral area 112 and near one end of the display area 111, and at least one of the plurality of selection switches 23 has one end connected to one of the plurality of data leads 31, and the other end connected to six of the plurality of data lines 13.

[0080] The multiple selection switches 23 include multiple first selection switches 23A located on one side of the display area 111 and multiple second selection switches 23B located on both sides of the multiple first selection switches 23A. The multiple data leads 31 include multiple first data leads 31A and multiple second data leads 31B. The first selection switches 23A are electrically connected to the first data leads 31A, and the second selection switches 23B are electrically connected to the second data leads 31B. The width of at least a portion of the line segments in the first data leads 31A is greater than the width of at least a portion of the line segments in the second data leads 31B.

[0081] The peripheral area 112 includes a first peripheral area 112A located on one side of the display area 111 and a corner area 112B adjacent to the first peripheral area 112A. In some embodiments, the first peripheral area 112A may be a straight edge area. In some embodiments, the corner area 112B may have a curvature, such as an arc. It should be understood that the peripheral area 112 also includes other peripheral areas 112, such as a second peripheral area 112C adjacent to the corner area 112B.

[0082] In some embodiments, a first selection switch 23A is located in a first peripheral area 112A, a second selection switch 23B is located in a corner area 112B, at least a portion of a second data lead 31B is located on one side of the first data lead 31A, and at least a portion of the first data lead 31A and the second data lead 31B, at the ends away from the display area 111, are bonded to the driver chip 20 in the first peripheral area 112A. The other end of the first data lead 31A near the display area 111 extends toward and connects to the first selection switch 23A located in the first peripheral area 112A, and the other end of the second data lead 31B near the display area 111 extends toward and connects to the second selection switch 23B located in the corner area 112B. The width of at least a portion of the line segment of the first data lead 31A located in the first peripheral area 112A is greater than the width of at least a portion of the line segment of the second data lead 31B located in the corner area 112B.

[0083] Understandably, since the second data lead 31B is longer than the first data lead 31A, the longer the data lead 31A, the larger the parasitic capacitance generated by coupling with other lines. This results in the parasitic capacitance of the corner area 112B being greater than that of the first peripheral area 112A, causing a difference between the data signal provided by the first data lead 31A and the data signal provided by the second data lead 31B, leading to dark pattern defects in the display area 111. Therefore, by making the width of at least a portion of the line segment in the first data lead 31A located in the first peripheral area 112A greater than the width of at least a portion of the line segment in the second data lead 31B located in the corner area 112B, the difference between the data signal provided by the first data lead 31A and the data signal provided by the second data lead 31B can be improved, thereby enhancing the brightness uniformity of the display area 111 and reducing dark pattern defects in the display device.

[0084] In some embodiments, the first selection switch 23A and the second selection switch 23B are located in the first peripheral area 112A. The ends of the first data lead 31A and the second data lead 31B furthest from the display area 111 are bonded to the driver chip 20 in the first peripheral area 112A. The other end of the first data lead 31A near the display area 111 extends toward and connects to the first selection switch 23A located in the first peripheral area 112A. The other end of the second data lead 31B near the display area 111 extends toward and connects to the second selection switch 23B located in the first peripheral area 112A.

[0085] Since both the first selection switch 23A and the second selection switch 23B are located in the first peripheral area 112A, and the first data lead 31A and the second data lead 31B are basically located in the first peripheral area 112A, the difference in length between the first data lead 31A and the second data lead 31B can be reduced. The overlapping areas of the first data lead 31A and other wirings and the overlapping areas of the second data lead 31B and other wirings are similar, which reduces the difference between the data signal provided by the first data lead 31A and the data signal provided by the second data lead 31B. This can further improve the brightness uniformity of the display area 111 and reduce the dark pattern defects of the display device.

[0086] In some embodiments, the first selection switch 23A and the second selection switch 23B are arranged sequentially along the edge of the display area 111, and the plurality of second selection switches 23B and the first selection switch 23A are at least partially located in the first peripheral area 112A.

[0087] For example, multiple first data leads 31A, multiple second data leads 31B, multiple first selection switches 23A, and multiple second selection switches 23B can be located in the first peripheral area 112A. At least one first selection switch 23A is electrically connected to one of the multiple first data leads 31A and at least two of the multiple data lines 13. At least one second selection switch 23B is electrically connected to one of the multiple second data leads 31B and at least two of the multiple data lines 13. In this way, the first selection switches 23A and the second selection switches 23B can provide data signals to the data lines 13.

[0088] In some embodiments, the first selection switch 23A and the second selection switch 23B are staggered along a direction perpendicular to the direction extending from the edge of the display area 111. For example, multiple first data leads 31A and multiple first selection switches 23A may be located in the first peripheral area 112A, and multiple second data leads 31B and multiple second selection switches 23B may be located in the corner area 112B. At least one first selection switch 23A is electrically connected to one of the multiple first data leads 31A and at least two of the multiple data lines 13, and at least one second selection switch 23B is electrically connected to one of the multiple second data leads 31B and at least two of the multiple data lines 13. In this way, the first selection switches 23A and the second selection switches 23B can provide data signals to the data lines 13.

[0089] like Figure 2 and Figure 5 As shown, the display substrate also includes multiple switch lines 24. The multiple switch lines 24 are located in the peripheral area 112 and are arranged sequentially at intervals. Each switch line 24 is electrically connected to multiple selector switches 23. The multiple switch lines 24 are configured to provide switch signals to the multiple selector switches 23. For example, each switch line 24 is electrically connected to multiple selector switches 23 respectively, and each switch line 24 provides a switch signal to the multiple selector switches 23 respectively.

[0090] The number of switch lines 24 is related to the number of data lines 13 connected to each selector switch 23. For example, if each selector switch 23 is connected to 6 data lines 13, then there can be 6 switch lines 24. Or, if each selector switch 23 is connected to 3 data lines 13, then there can be 3 switch lines 24.

[0091] It should be noted that there is an overlap between the multiple switch lines 24 and the multiple data lines 31. The multiple switch lines 24 and the multiple data lines 31 will affect each other and generate parasitic capacitance. However, the overlap between the multiple data lines 31 and the multiple switch lines 24 is uneven. The overlap area between the multiple first data lines 31A and the multiple switch lines 24 is smaller than the overlap area between the multiple second data lines 31B and the multiple switch lines 24. This makes the parasitic capacitance generated by the second data lines 31B greater than that generated by the first data lines 31A. The data signal input from the first data lines 31A to the data line 13 is different from the data signal input from the second data lines 31B, which makes the display prone to low grayscale dark stripe defects.

[0092] In some embodiments, at least a portion of the plurality of first data leads 31A include a first sub-segment 311 that intersects the plurality of switch lines 24 perpendicularly, and at least a portion of the plurality of second data leads 31B include a second sub-segment 312 that intersects the plurality of switch lines 24 perpendicularly. The number of second sub-segments 312 in the at least a portion of the second data leads 31B is greater than or equal to the number of first sub-segments 311 in the at least a portion of the first data leads 31A. For example, the at least a portion of the second data leads 31B includes a plurality of second sub-segments 312. The first sub-segments 311 are located in a first peripheral area 112A, and the second sub-segments 312 are located in a corner area 112B. The width of the at least a portion of the first sub-segments 311 is greater than the width of the at least a portion of the second sub-segments 312.

[0093] Understandably, the perpendicular overlap of the first sub-segment 311, the second sub-segment 312, and the switch line 24 minimizes the overlap area between the first data lead 31A, the second data lead 31B, and the switch line 24. Therefore, the parasitic capacitance generated by the switch line 24 and the data lead 31 can be effectively reduced, thereby reducing the interference of parasitic capacitance on the data lead 31 and improving the display effect of the display substrate.

[0094] Please combine Figure 2 The second data lead 31B overlaps with other traces twice, while the first data lead 31A overlaps with other traces only once. Therefore, the overlap area of ​​the second data lead 31B with other traces is larger than that of the first data lead 31A with other traces, resulting in a larger parasitic capacitance for the second data lead 31B compared to the first data lead 31A. To balance this, the width of the first sub-segment 311 of the first data lead 31A is made larger than the width of the second sub-segment 312, thereby increasing the overlap area of ​​the first data lead 31A with other traces and increasing the parasitic capacitance. This brings the parasitic capacitance of the first data lead 31A and the second data lead 31B to a point where they are essentially the same. This avoids low-grayscale dark stripe defects on the display.

[0095] In some embodiments, the display substrate further includes multiple switch connection lines M1, which are located at least in the peripheral area 112. The number of switch connection lines M1 is equal to the number of switch lines 24. For example, if there are 6 switch lines 24, then there are also 6 switch connection lines M1. Each switch connection line M1 is connected to the driver chip 20 and one switch line 24. The driver chip 20 provides a switching signal to the switch line 24 through the switch connection line M1.

[0096] In some implementations, the second data lead 31B overlaps at least partially with multiple switch connection lines M1. For example, referring to the figure, the second data lead 31B located on one side of the first data lead 31A overlaps perpendicularly with three switch connection lines M1, and the second data lead 31B located on the other side of the first data lead 31A overlaps perpendicularly with three switch connection lines M1.

[0097] Please combine Figure 3 In some implementations, the time interval between the switching signals of adjacent switching lines 24 is in the range of 0.5-2 microseconds.

[0098] It should be noted that if the time interval between the switching signals of adjacent switching lines 24 is less than 0.5 microseconds, the optical brightness uniformity of the display substrate is poor, resulting in dark pattern defects. When the time interval between the switching signals of adjacent switching lines 24 is 0.5-1 microseconds, the optical brightness uniformity of the display substrate gradually improves. When the time interval between the switching signals of adjacent switching lines 24 is 1-1.7 microseconds, the dark pattern defects of the display substrate disappear. However, when the time interval between the switching signals of adjacent switching lines 24 is greater than 2 microseconds, the Mura compensation deteriorates, leading to the Mura phenomenon on the display substrate. Thus, by setting the time interval between the switching signals of adjacent switching lines 24, the dark pattern defects of the display substrate can be further reduced.

[0099] In some embodiments, the time interval between the switching signals of adjacent switching lines 24 is in the range of 1-1.7 microseconds. When the time interval between the switching signals of adjacent switching lines 24 is in the range of 1-1.7 microseconds, the dark pattern defect of the display substrate disappears. For example, in this embodiment, the time interval between the switching signals of adjacent switching lines 24 is 1.7 microseconds.

[0100] like Figure 4 As shown, in some embodiments, the display substrate further includes multiple gate lines 14 and multiple light-emitting control lines 15.

[0101] Multiple gate lines 14 are located at least in the display area 111 and are electrically connected to multiple sub-pixels 12. The multiple gate lines 14 are configured to provide gate signals to the multiple sub-pixels 12. For example, each gate line 14 is electrically connected to a row of sub-pixels 12. Multiple light-emitting control lines 15 are located at least in the display area 111 and are electrically connected to the multiple sub-pixels 12. The multiple light-emitting control lines 15 are configured to provide light-emitting control signals to the multiple sub-pixels 12. For example, each light-emitting control line 15 is electrically connected to a row of sub-pixels 12.

[0102] Figure 5 This is a schematic cross-sectional view illustrating a sub-pixel according to an embodiment of the present disclosure. At least one of the plurality of sub-pixels 12 may include Figure 5 The structure shown.

[0103] like Figure 5 As shown, sub-pixel 12 includes a driving transistor 121 and a storage capacitor 122. The driving transistor 121 includes a first active layer 1211 on the substrate 11, a first gate 1213 on the side of the first active layer 1211 away from the substrate 11, a first insulating layer 1214 on the side of the first gate 1213 away from the substrate 11, a second insulating layer 1215 on the side of the first insulating layer 1214 away from the substrate 11, and a source 1216 and a drain 1217 on the side of the second insulating layer 1215 away from the substrate 11 and electrically connected to the first active layer 1211.

[0104] In some embodiments, the driving transistor 121 further includes a gate dielectric layer 1212 located on the side of the first active layer 1211 away from the substrate 11, and a first gate 1213 located on the side of the gate dielectric layer 1212 away from the substrate 11. For example, the source 1216 and the drain 1217 are electrically connected to the first active layer 1211 through vias penetrating the second insulating layer 1215, the first insulating layer 1214, and the gate dielectric layer 1212, respectively.

[0105] The storage capacitor 122 includes a first electrode plate 1221 located on the same layer as the first gate 1213, and a second electrode plate 1222 located between a first insulating layer 1214 and a second insulating layer 1215. It should be understood that the storage capacitor 122 also includes a first insulating layer 1214 located between the first electrode plate 1221 and the second electrode plate 1222.

[0106] Sub-pixel 12 also includes a light-emitting diode 123, such as an OLED. The light-emitting diode 123 includes an anode 1231, a light-emitting layer 1232 located on the side of the anode 1231 away from the substrate 11, and a cathode 1233 located on the side of the light-emitting layer 1232 away from the substrate 11. For example, the anode 1231 of the light-emitting diode 123 is electrically connected to the drain 1217 of the driving transistor 121. Here, the light-emitting layer 1232 includes at least an organic light-emitting layer. In some embodiments, the light-emitting layer 1232 may further include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

[0107] In some embodiments, see Figure 5The sub-pixel 12 may further include a buffer layer 124 located between the substrate 11 and the first active layer 1211, a planarization layer 125 covering the source 1216 and the drain 1217, a pixel defining layer 126 for defining a plurality of sub-pixels 12, a support layer 127, and an encapsulation layer 128. For example, the anode 1231 of the light-emitting diode 123 can be electrically connected to the drain 1217 of the driving transistor 121 through a via penetrating the planarization layer 125. For example, the pixel defining layer 126 has a plurality of openings corresponding to the plurality of sub-pixels 12, and the light-emitting diodes 123 of the plurality of sub-pixels 12 are located in the plurality of openings. For example, the encapsulation layer 128 may include a thin film encapsulation layer. In some embodiments, the encapsulation layer 128 may include a first inorganic layer 1281, a second inorganic layer 1282, and an organic layer 1283 located between the first inorganic layer 1281 and the second inorganic layer 1282.

[0108] As some implementations, one or more of the second insulating layer 1215, the first insulating layer 1214, the gate dielectric layer 1212, the buffer layer 124, the planarization layer 125, the pixel defining layer 126, and the support layer 127 may include organic insulating materials such as polyimide and resin materials, or inorganic insulating materials such as silicon oxides, silicon nitrides, and silicon oxynitrides.

[0109] Please combine Figure 4 and Figure 6 In some embodiments, the display substrate further includes a gate driving circuit 21 and a light emission control driving circuit 22.

[0110] The gate driving circuit 21 is located in the peripheral region 112. For example, the gate driving circuit 211 may be located in the second peripheral region 112C. The gate driving circuit 21 includes a plurality of cascaded gate driving units 211. Each gate driving unit 211 is electrically connected to a gate line 14. The gate driving unit 211 is used to provide gate signals to a row of sub-pixels 12 through the gate line 14.

[0111] The light-emitting control driving circuit 22 is located in the peripheral area 112. For example, the light-emitting control driving circuit 22 may be located in the second peripheral area 112C, and the light-emitting control driving circuit 22 and the gate driving circuit 21 are located on both sides of the display area 111, respectively. The light-emitting control driving circuit 22 includes a plurality of cascaded light-emitting control driving units 221, which are electrically connected to a plurality of light-emitting control lines 15. The light-emitting control driving units 221 are used to provide light-emitting control signals to a row of sub-pixels 12 through the light-emitting control lines 15.

[0112] In some embodiments, the display substrate further includes a first initial signal line GSTV, a first clock signal line GCB, a second clock signal line GCK, a third clock signal line ECK, a fourth clock signal line ECB, and a second initial signal line ESTV located in the peripheral area 112.

[0113] The first initial signal line GSTV, the first clock signal line GCK, and the second clock signal line GCB are arranged sequentially along the row direction of sub-pixel 12. The first initial signal line GSTV is electrically connected to a gate driving unit 211 in the driver chip 20 and the gate driving circuit 21, respectively. For example, the gate driving unit 211 includes GOA0-GOAn, and the first initial signal line GSTV is electrically connected to the gate driving unit GOA0. The driver chip 20 provides a first initialization signal to the gate driving circuit 21 through the first initial signal line GSTV. The first clock signal line GCB is connected to each gate driving unit 211 in the driver chip 20 and the gate driving circuit 21, respectively, and the driver chip 20 provides a first clock signal to the gate driving circuit 21 through the first clock signal line GCB. The second clock signal line GCK is connected to each gate driving unit 211 in the driver chip 20 and the gate driving circuit 21, respectively, and the driver chip 20 provides a second clock signal to the gate driving circuit 21 through the second clock signal line GCK.

[0114] The third clock signal line ECK, the fourth clock signal line ECB, and the second initial signal line ESTV are arranged sequentially along the row direction of sub-pixel 12. The second initial signal line ESTV is connected to one light-emitting control driving unit 221 in the driver chip 20 and the light-emitting control driving circuit 22, respectively. The driver chip 20 provides a second initialization signal to the light-emitting control driving circuit 22 through the second initial signal line ESTV. The third clock signal line ECK is connected to each light-emitting control driving unit 221 in the driver chip 20 and the light-emitting control driving circuit 22, respectively. The driver chip 20 provides a third clock signal to the light-emitting control driving circuit 22 through the third clock signal line ECK. The fourth clock signal line ECB is connected to each light-emitting control driving unit 221 in the driver chip 20 and the light-emitting control driving circuit 22, respectively. The driver chip 20 provides a fourth clock signal to the light-emitting control driving circuit 22 through the fourth clock signal line ECB.

[0115] In some embodiments, the second data lead 31B overlaps with at least one of the first initial signal line GSTV, the first clock signal line GCB, the second clock signal line GCK, the third clock signal line ECK, the fourth clock signal line ECB, and the second initial signal line ESTV. For example, the second data lead 31B located on one side of the first data lead 31A overlaps perpendicularly with the first initial signal line GSTV, the first clock signal line GCB, and the second clock signal line GCK, while the second data lead 31B located on the other side of the first data lead 31A overlaps perpendicularly with the third clock signal line ECK, the fourth clock signal line ECB, and the second initial signal line ESTV.

[0116] Figure 7 It is shown Figure 2 The diagram shows an enlarged view of a local area included in VII of the display substrate. Figure 8 It is shown Figure 7 The diagram shows a cross-sectional view of point VIII in the display substrate.

[0117] It should be understood that Figure 7 and Figure 8 The selection switch 23 shown includes a plurality of switching transistors 231, for example, the selection switch 23 includes six or more switching transistors 231. Here, Figure 7 Six switching transistors 231 are schematically shown. At least one switching transistor 231 includes a second active layer 2311, a second gate 2312, a first electrode 2313, and a second electrode 2314 located on one side of the substrate 11.

[0118] The second gate 2312 is located on the side of the second active layer 2311 away from the substrate 11. The second gate 2312 and the first gate 1213 may be located on the same layer and are electrically connected to one of the multiple switching lines 24.

[0119] In some embodiments, the display substrate further includes multiple second gate connection lines M2, and the second gate 2312 can be electrically connected to the switch line 24 through the second gate connection lines M2.

[0120] The first electrode 2313 is located on the side of the second gate 2312 away from the substrate 11 and is electrically connected to the second active layer 2311 and one of the multiple data leads 31. A first insulating layer 1214 and a second insulating layer 1215 may be disposed between the first electrode 2313 and the second gate 2312. For example, each first electrode 2313 can be electrically connected to the second active layer 2311 through a via penetrating the second insulating layer 1215, the first insulating layer 1214, and the gate dielectric layer 1212.

[0121] The second electrode 2314 is located on the side of the second gate 2312 away from the substrate 11, and is electrically connected to the second active layer 2311 and to one of the multiple data lines 13. In some embodiments, the second electrode 2314 and the first electrode 2313 are located on the same layer, and are also located on the same layer as the source 1216 and drain 1217 of the sub-pixel 12. For example, a first insulating layer 1214 and a second insulating layer 1215 are disposed between the second electrode 2314 and the second gate 2312. For example, the second electrode 2314 can be electrically connected to the second active layer 2311 through a via penetrating the second insulating layer 1215, the first insulating layer 1214, and the gate dielectric layer 1212.

[0122] The orthographic projections of the first electrode 2313 and the second electrode 2314 on the substrate 11 do not overlap with the orthographic projections of the second gate 2312 on the substrate 11.

[0123] In addition, the switching transistor 231 may also include a buffer layer 124 located between the substrate 11 and the second active layer 2311, and a planarization layer 125 covering the second electrode 2314 and the first electrode 2313.

[0124] In some embodiments, the switch line 24 is located on the same layer as the source 1216 and the drain 1217, at least a portion of the first data lead 31A electrically connected to the first selector switch 23A is located on the same layer as the second electrode plate 1222, and at least a portion of the second data lead 31B electrically connected to the second selector switch 23B is located on the same layer as the first electrode plate 1221.

[0125] It should be noted that the closer the interlayer distance between the data lead 31 and other overlapping areas, the larger the parasitic capacitance will be. Conversely, the farther the interlayer distance between the data lead 31 and other overlapping areas, the smaller the parasitic capacitance will be. The parasitic capacitance generated by the first data lead 31A and other overlapping areas is greater than that generated by the second data lead 31B and other overlapping areas. Therefore, by placing at least a portion of the line segments in the first data lead 31A on the same layer as the second electrode plate 1222, and placing at least a portion of the line segments in the second data lead 31B on the same layer as the first electrode plate 1221, the interlayer distance between the second electrode plate 1222 and the source 1216 and drain 1217 is smaller than the interlayer distance between the first electrode plate 1221 and the source 1216 and drain 1217. This increases the parasitic capacitance generated by the first data lead 31A and the switch line 24, making the parasitic capacitances of the first data lead 31A and the second data lead 31B essentially the same. In this way, the dark stripe defects of the display substrate can be effectively improved, ensuring the yield of the display device.

[0126] Figure 9This is a schematic diagram showing the layout of the pixel circuit of sub-pixel 12 connected to the switching transistor 231 according to an embodiment of the present disclosure.

[0127] Figure 9 As shown, the pixel circuit of sub-pixel 12 may include driving transistor T1 (i.e., the aforementioned driving transistor 121), data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, second reset transistor T7, and storage capacitor C1.

[0128] The driving transistor T1 includes a channel region T14, the data writing transistor T2 includes a channel region T24, the threshold compensation transistor T3 includes a channel region T34, the first light-emitting control transistor T4 includes a channel region T44, the second light-emitting control transistor T5 includes a channel region T54, the first reset transistor T6 includes a channel region T64, and the second reset transistor T7 includes a channel region T74.

[0129] The gate T20 of the data writing transistor T2 is electrically connected to the gate line 14, the first electrode T21 of the data writing transistor T2 is electrically connected (e.g., via via VH1) to the data line 13, and the second electrode T22 of the data writing transistor T2 is electrically connected to the first electrode T11 of the driving transistor T1.

[0130] The gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 14. The first electrode T31 of the threshold compensation transistor T3 is electrically connected to the second electrode T12 of the driving transistor T1. The second electrode T32 of the threshold compensation transistor T3 is electrically connected to the gate T10 of the driving transistor T1 through the connecting electrode 31b, which is the second electrode plate C12 of the storage capacitor.

[0131] The gates T40 of the first light-emitting control transistor T4 and T50 of the second light-emitting control transistor T5 are both electrically connected to the light-emitting control line 15. For example, a portion of the light-emitting control line 15 serves as the gate T40 of the first light-emitting control transistor T4, and another portion of the light-emitting control line 110 serves as the gate T50 of the second light-emitting control transistor T5. The first electrode T41 of the first light-emitting control transistor T4 (e.g., via via VH2) is electrically connected to the power supply line 16, and the second electrode T42 of the first light-emitting control transistor T4 is electrically connected to the first electrode T11 of the driving transistor T1. The first electrode T51 of the second light-emitting control transistor T5 is electrically connected to the second electrode T12 of the driving transistor T1, and the second electrode T52 of the second light-emitting control transistor T5 is electrically connected to the anode 1231 of the light-emitting diode 123. For example, the second electrode T52 of the second light-emitting control transistor T5 is electrically connected to the anode 1231 of the light-emitting diode 123 via the connecting electrode 31d.

[0132] The gate T60 of the first reset transistor T6 is electrically connected to the reset control line 18. The first electrode T61 of the first reset transistor T6 is electrically connected to the initialization signal line 17 via the connection electrode 31a. The second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 via the connection electrode 31b. For example, the first electrode T61 of the first reset transistor T6 is electrically connected to one end of the connection electrode 31a via the via VH11. The initialization signal line 17 is electrically connected to the other end of the connection electrode 31a via the via VH12. For example, the second electrode T62 of the first reset transistor T6 is electrically connected to one end of the connection electrode 31b via the via VH21, and the gate T10 of the driving transistor T1 is connected to the other end of the connection electrode 31b via the via VH22.

[0133] The gate T70 of the second reset transistor T7 is electrically connected to another reset control line 18. The first electrode T71 of the second reset transistor T7 is electrically connected to another initialization signal line 17 through the connection electrode 31c. The second electrode T72 of the second reset transistor T7 is electrically connected to the anode 1231 of the light-emitting diode 123 (see...). Figure 5 For example, the first electrode T71 of the second reset transistor T7 is electrically connected to one end of the connection electrode 31c via via VH31, and another initialization signal line 17 is electrically connected to the other end of the connection electrode 31c via via VH32.

[0134] The first electrode plate C11 of the storage capacitor C1 (e.g., via via VH3) is electrically connected to the power line 16. The power line 16 is connected to the connection element 214 via via VH0.

[0135] The second electrode 2314 in the switching transistor 311 is electrically connected to the data line 13.

[0136] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with the described embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0137] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, comprising: A substrate, the substrate including a display area and at least a peripheral area located on one side of the display area; Multiple sub-pixels are located in the display area; Multiple data lines, located in the display area and the surrounding area, are configured to provide data signals to the multiple sub-pixels; Multiple data leads are located in the surrounding area and electrically connected to the multiple data lines; Multiple selection switches are located in the peripheral area and arranged at intervals. The multiple selection switches are located on the side of the multiple data lines away from the display area. At least one of the multiple selection switches is electrically connected to at least two of the multiple data lines and one of the multiple data leads. The plurality of selection switches include a plurality of first selection switches located on one side of the display area and a plurality of second selection switches located on both sides of the plurality of first selection switches. The plurality of data leads include a plurality of first data leads and a plurality of second data leads. The first selection switches are electrically connected to the first data leads, and the second selection switches are electrically connected to the second data leads. The width of at least a portion of the line segments in the first data leads is greater than the width of at least a portion of the line segments in the second data leads. The display substrate further includes: Multiple switch lines are located in the peripheral area, each switch line being electrically connected to the multiple selector switches. The multiple switch lines are configured to provide switch signals to the multiple selector switches. The multiple switch lines overlap with at least a portion of the first data lead and at least a portion of the second data lead. The first data lead includes a first sub-segment that intersects the plurality of switch lines perpendicularly, and the second data lead includes a second sub-segment that intersects the plurality of switch lines perpendicularly.

2. The display substrate according to claim 1, characterized in that, The time interval between the switching signals of adjacent switching lines ranges from 0.5 to 2 microseconds.

3. The display substrate according to claim 1, characterized in that... At least a portion of the width of the first sub-segment is greater than at least a portion of the width of the second sub-segment.

4. The display substrate according to claim 1, characterized in that, The peripheral area includes a first peripheral area located on one side of the display area and a corner area adjacent to the first peripheral area, and the first selection switch and the second selection switch are located in the first peripheral area.

5. The display substrate according to claim 4, characterized in that, The first selection switch and the second selection switch are arranged sequentially along the edge of the display area.

6. The display substrate according to claim 4, characterized in that, The first selection switch and the second selection switch are staggered along a direction perpendicular to the direction extending from the edge of the display area.

7. The display substrate according to claim 1, characterized in that, At least one of the plurality of selector switches is connected to six or three of the data lines.

8. The display substrate according to claim 1, characterized in that, The display substrate further includes: Multiple gate lines are located at least in the display area and electrically connected to the multiple sub-pixels, the multiple gate lines being configured to provide gate signals to the multiple sub-pixels; Multiple light-emitting control lines are located at least in the display area and electrically connected to the multiple sub-pixels, and the multiple light-emitting control lines are configured to provide light-emitting control signals to the multiple sub-pixels; A gate driving circuit, located in the peripheral region, includes multiple gate driving units, which are electrically connected to the multiple gate lines. The light-emitting control driving circuit, located in the peripheral area, includes multiple light-emitting control driving units, which are electrically connected to the multiple light-emitting control lines.

9. The display substrate according to claims 1-3, characterized in that, At least one of the plurality of sub-pixels includes: The driving transistor includes: The first active layer is located on the substrate. A first gate located on the side of the first active layer away from the substrate; A first insulating layer located on the side of the first gate away from the substrate. The second insulating layer is located on the side of the first insulating layer away from the substrate, and Located on the side of the second insulating layer away from the substrate and electrically connected to the source and drain of the first active layer; and Storage capacitors, including: The first electrode plate is located on the same layer as the first gate, and The second electrode plate is located between the first insulating layer and the second insulating layer.

10. The display substrate according to claim 9, characterized in that, At least one of the plurality of selector switches includes a plurality of switching transistors, wherein the at least one switching transistor includes: A second active layer located on one side of the substrate; The second gate is located on the side of the second active layer away from the substrate and is electrically connected to one of the multiple switching lines. The first electrode is located on the side of the second gate away from the substrate and is electrically connected to one of the plurality of data leads; The second electrode is located on the same layer as the first electrode and is electrically connected to one of the multiple data lines.

11. The display substrate according to claim 10, characterized in that, The orthographic projection of the first electrode on the substrate does not overlap with the orthographic projection of the second gate on the substrate, and the orthographic projection of the second electrode on the substrate does not overlap with the orthographic projection of the second gate on the substrate.

12. The display substrate according to claim 10, characterized in that, At least a portion of the first data lead connected to the first selection switch is located on the same layer as the second electrode plate, and at least a portion of the second data lead connected to the second selection switch is located on the same layer as the first electrode plate.

13. A display device, characterized in that, Includes the display substrate as described in any one of claims 1-12.

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