Semiconductor device, manufacturing method, power module, conversion circuit, and vehicle

Abstract

The present invention discloses a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle, relating to the technical field of semiconductors. The semiconductor device includes: a semiconductor body including a first surface and a second surface arranged oppositely; wherein, the first surface includes a first surface of a cell region and a first surface of a terminal region, and a plurality of spaced-apart limiting grooves are arranged on the first surface of the terminal region; the semiconductor body further includes a plurality of field limiting rings, and each field limiting ring is located on one side of a corresponding limiting groove close to the second surface; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases. The technical solution provided by the present invention improves the terminal breakdown voltage characteristics of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. Background Art

[0002] As a representative of third-generation semiconductor materials, silicon carbide (SiC) has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap and have advantages such as a high breakdown electric field, a high thermal conductivity, a high electron saturation velocity, and a strong radiation resistance. Therefore, semiconductor devices prepared using SiC materials can not only operate stably at higher temperatures but also be applicable to high-voltage and high-frequency scenarios.

[0003] In order to improve the reverse breakdown voltage of semiconductor devices and reduce the electric field concentration effect, in high-voltage devices, a junction termination technology is required to modulate the electric field distribution in the internal breakdown voltage region of the device. Figure 1 is a schematic cross-sectional structure diagram of a terminal structure of a power device provided in the related art. Refer to Figure 1 , the field limiting ring 100 is a commonly used edge terminal structure of a power device. This structure can be fabricated simultaneously with the main junction region of the device, so the manufacturing process is simple and the cost is low. However, the field limiting ring 100 requires precise design of the ring spacing, ring width, and ring depth. A slight deviation may cause a significant drop in the breakdown voltage. However, the ions in the field limiting ring 100 will diffuse during the high-temperature annealing process, causing adjacent field limiting rings 100 to be connected together, reducing the breakdown voltage characteristics of the terminal structure. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle to improve the terminal breakdown voltage characteristics of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, including:

[0006] A semiconductor body including a first surface and a second surface disposed opposite to each other; wherein, the first surface includes a first surface of a cell region and a first surface of a terminal region, and a plurality of spaced-apart limiting grooves are provided on the first surface of the terminal region; the semiconductor body further includes a plurality of field limiting rings, and each field limiting ring is correspondingly located on one side of a corresponding limiting groove close to the second surface; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

[0007] Optionally, the semiconductor body includes a cell portion and a terminal portion; the field limiting rings are located in the terminal portion; in the direction from the cell portion to the terminal portion, the plurality of field limiting rings are arranged at intervals in sequence;

[0008] The maximum width of each of the field limiting rings is less than the width of the corresponding limiting groove.

[0009] Optionally, the plurality of field limiting rings includes at least one first field limiting ring;

[0010] The first field limiting ring includes a first side wall, a second side wall, a third side wall, and a fourth side wall connecting the first side wall and the second side wall; wherein, the third side wall is located at the bottom surface of the limiting groove, and the fourth side wall is disposed opposite to the third side wall; the area of the fourth side wall is less than the area of the third side wall.

[0011] Optionally, the plurality of field limiting rings further includes at least one second field limiting ring;

[0012] The second field limiting ring includes a fifth side wall, a sixth side wall, and a seventh side wall connecting the fifth side wall and the sixth side wall; wherein, the seventh side wall is located at the bottom surface of the limiting groove, and in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it becomes zero;

[0013] Wherein, the distance from the first field limiting ring to the cell portion is greater than the distance from the second field limiting ring to the cell portion.

[0014] Optionally, among the plurality of field limiting rings, the field limiting ring closest to the cell portion has the largest width, and the field limiting ring closest to the cell portion is the closest to the second surface;

[0015] Among the plurality of limiting grooves, the limiting groove closest to the cell portion has the largest width, and different limiting grooves have the same depth.

[0016] Optionally, the conductive type of the semiconductor material of the field limiting ring is different from that of the semiconductor body material;

[0017] And / or, the semiconductor material of the field limiting ring and the semiconductor body material include SiC.

[0018] Optionally, the limiting groove is provided with a filling material, and the filling material includes at least one of silicon oxide, silicon nitride, and polyimide.

[0019] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, including:

[0020] Providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; wherein, the first surface includes a first surface of the cell region and a first surface of the terminal region;

[0021] Forming a plurality of spaced-apart limiting grooves on the first surface of the terminal region;

[0022] A mask layer is formed, and the mask layer is located on the bottom surface, side walls of the limiting groove, and the first surface of the terminal region; wherein, the mask layer has a cavity at the position where the limiting groove is located, and in the direction from the first surface to the second surface, the width of the cavity gradually increases;

[0023] Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limiting groove; in the direction from the first surface to the second surface, the distance between adjacent two field limiting rings gradually increases.

[0024] Optionally, the forming of the mask layer includes:

[0025] Form a first mask layer on the side walls of the limiting groove, the bottom surface of the limiting groove, and the first surface of the terminal region by low-pressure chemical vapor deposition;

[0026] Form a second mask layer on the surface of the first mask layer by plasma-enhanced chemical vapor deposition; wherein, the first mask layer and the second mask layer are used to enclose a cavity at the position where the limiting groove is located.

[0027] Optionally, the cross-sectional shape of the cavity closest to the first surface of the cell region is trapezoidal, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface;

[0028] Based on the mask layer, correspondingly forming a field limiting ring at the bottom of each limiting groove includes:

[0029] Based on the trapezoidal cavity of the mask layer, form a first field limiting ring at the bottom of the limiting groove; wherein, at least one first field limiting ring is included in the multiple field limiting rings, and the first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located on the bottom surface of the limiting groove, and the fourth side wall is arranged opposite to the third side wall; the area of the four side walls is smaller than the area of the third side wall.

[0030] Optionally, the cross-sectional shape of at least one cavity outside the cavity closest to the first surface of the cell region is triangular;

[0031] Based on the mask layer, correspondingly forming a field limiting ring at the bottom of each limiting groove further includes:

[0032] Based on the triangular cavity of the mask layer, a second field limiting ring is formed at the bottom of the limiting groove; at least one second field limiting ring is further included in the plurality of field limiting rings, and the second field limiting ring includes a fifth sidewall, a sixth sidewall, and a seventh sidewall connecting the fifth sidewall and the sixth sidewall; the seventh sidewall is located on the bottom surface of the limiting groove; in the direction from the first surface to the second surface, the distance between the fifth sidewall and the sixth sidewall gradually decreases until it becomes zero.

[0033] According to another aspect of the present invention, there is provided a power module, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0034] According to another aspect of the present invention, there is provided a power conversion circuit, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0035] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0036] According to another aspect of the present invention, there is provided a vehicle, including a load and a power conversion circuit as described in any embodiment of the present invention, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0037] Embodiments of the present invention provide a semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body, including a first surface and a second surface arranged opposite to each other; wherein, the first surface includes a first surface of the cell region and a first surface of the terminal region, and the first surface of the terminal region includes a plurality of limiting grooves arranged at intervals; the semiconductor body further includes a plurality of field limiting rings, and each field limiting ring is correspondingly located on one side of a limiting groove close to the second surface; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases. The technical solution provided by the embodiments of the present invention can increase the ion implantation depth and at the same time reduce the energy required for ion implantation by forming a field limiting ring through ion implantation at the bottom of the limiting groove, and avoid the implantation damage to the semiconductor body caused by high-energy implantation. Based on the shape setting of the mask layer in the limiting groove, the width of the field limiting ring formed by ion implantation gradually decreases in the direction from the first surface to the second surface, that is, the distance between two adjacent field limiting rings gradually increases, so as to avoid the connection of adjacent field limiting rings caused by ion diffusion in the field limiting ring, improve the voltage division effect and breakdown voltage resistance of the terminal structure in the semiconductor device, and further improve the breakdown voltage resistance of the semiconductor device.

[0038] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily apparent from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0040] Figure 1 is a schematic cross-sectional structure diagram of a terminal structure of a power device provided in the related art;

[0041] Figure 2 is a top view of a semiconductor device provided in an embodiment of the present invention;

[0042] Figure 3 is Figure 2 a schematic cross-sectional structure diagram of the structure shown along AA1;

[0043] Figure 4 is a schematic cross-sectional structure diagram of another semiconductor device provided in an embodiment of the present invention;

[0044] Figure 5 is a flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0045] Figure 6 is a schematic cross-sectional structure diagram corresponding to step S10 in a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0046] Figure 7 is a schematic cross-sectional structure diagram corresponding to step S20 in a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0047] Figures 8 - 9 is a schematic cross-sectional structure diagram corresponding to step S30 in a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 10 is a schematic cross-sectional structure diagram corresponding to step S40 in a method for manufacturing a semiconductor device provided in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solution in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0051] An embodiment of the present invention provides a semiconductor device. Figure 2 is a top view of a semiconductor device provided by an embodiment of the present invention. Figure 3 is Figure 2 a schematic cross-sectional structure diagram of the structure shown along AA1, referring to Figure 2 and Figure 3 , the semiconductor device includes:

[0052] A semiconductor body 1, including a first surface 11 and a second surface 12 which are oppositely arranged; wherein, the first surface 11 includes a first surface of a cell region and a first surface of a terminal region, and the first surface of the terminal region includes a plurality of spaced-apart limiting grooves 30; the semiconductor body 1 further includes a plurality of field limiting rings 2, and each field limiting ring 2 is located on one side of a corresponding limiting groove 30 close to the second surface 12.

[0053] In the direction Y from the first surface 11 to the second surface 12, the distance between two adjacent field limiting rings 2 gradually increases.

[0054] Specifically, the semiconductor body 1 can be formed by one-time epitaxy or by multiple epitaxies. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20, or can be a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes the substrate 10 and at least one layer of semiconductor epitaxial layer 20 formed on one side of the substrate 10. Figure 3The semiconductor body 1 shown includes a substrate 10 and a layer of semiconductor epitaxial layer 20 formed on one side of the substrate 10.

[0055] The material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be the same, or the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 may be different. In the embodiments of the present invention, the material of the semiconductor epitaxial layer 20 and the material of the substrate 10 may be SiC, and the semiconductor device may be a planar SiC power device with a terminal structure, a trench SiC power device, or other SiC devices. SiC has excellent physical and electrical properties. Compared with silicon materials, SiC materials have a large bandgap, and have advantages such as a high breakdown electric field, a high thermal conductivity, a high electron saturation rate, and a strong radiation resistance. Therefore, semiconductor devices prepared with SiC materials can not only operate stably at higher temperatures, but also be suitable for high-voltage and high-frequency scenarios.

[0056] The semiconductor body 1 includes a cell portion 01 located in the central region and a terminal portion 02 located in the edge region, and the terminal portion 02 surrounds the cell portion 01. The cell portion 01 of the semiconductor body 1 is used to prepare a SiC power device, and the terminal portion 02 of the semiconductor body 1 is used to prepare a terminal structure of the SiC power device. The semiconductor body 1 further includes a first surface 11 and a second surface 12 that are oppositely arranged. In the case where the semiconductor body 1 only includes the semiconductor epitaxial layer 20, the second surface 12 is the surface of the semiconductor body 1 close to the substrate 10, and the first surface 11 is the surface of the semiconductor body 1 far from the substrate 10. In the case where the semiconductor body 1 includes the substrate 10 and at least one layer of semiconductor epitaxial layer 20, the second surface 12 is the surface of the substrate 10 far from the semiconductor epitaxial layer 20, and the first surface 11 is the surface of the semiconductor epitaxial layer 20 farthest from the substrate 10 on the side far from the substrate 10.

[0057] Among them, the first surface 11 includes a first surface of the cell region and a first surface of the terminal region. The first surface 11 located in the cell portion 01 is the first surface of the cell region, and the first surface 11 located in the terminal portion 02 is the first surface of the terminal region. The first surface of the terminal region surrounds the first surface of the cell region. The terminal structure includes a plurality of field limiting rings 2, and the limiting grooves 30 are arranged in one-to-one correspondence with the field limiting rings 2. Each field limiting ring 2 extends from the bottom surface of the corresponding limiting groove 30 towards the second surface 12 of the semiconductor body 1. In the direction Y from the first surface 11 to the second surface 12, the distance between two adjacent field limiting rings 2 gradually increases.

[0058] The semiconductor device provided by the embodiment of the present invention forms a field limiting ring 2 by ion implantation at the bottom of the limiting groove 30, which can increase the ion implantation depth, reduce the energy required for ion implantation at the same time, and avoid the implantation damage to the semiconductor body 1 caused by high-energy implantation; during the preparation of the semiconductor device, by adjusting the thickness of the mask layer at different positions in the limiting groove 30, the width of the field limiting ring 2 formed by ion implantation gradually decreases in the direction Y from the first surface 11 to the second surface 12, so that the distance between two adjacent field limiting rings 2 gradually increases, which can avoid the connection of adjacent field limiting rings 2 caused by ion diffusion in the field limiting ring 2, improve the voltage division effect and breakdown voltage resistance of the terminal structure in the semiconductor device, and improve the breakdown voltage resistance of the semiconductor device.

[0059] Based on the above embodiments, referring to Figure 3 , optionally, the conductivity type of the field limiting ring 2 is different from that of the semiconductor body 1. The conductivity type of the semiconductor body 1 can be N-type, doped with N-type doping ions; the conductivity type of the field limiting ring 2 is P-type, doped with P-type doping ions. Or, the conductivity type of the semiconductor body 1 can be P-type, doped with P-type doping ions; the conductivity type of the field limiting ring 2 is N-type, doped with N-type doping ions. The N-type doping ions can be P (phosphorus) or N (nitrogen) ions, and the P-type doping ions can be Al (aluminum) ions or B (boron) ions. In the embodiment of the present invention, the conductivity type of the semiconductor body 1 is N-type, and the conductivity type of the field limiting ring 2 is P-type.

[0060] Furthermore, the material of the field limiting ring 2 and the semiconductor body 1 are both SiC. The field limiting ring 2 can be directly formed by implanting doping ions different from the conductivity type of the semiconductor body 1 in the semiconductor body 1, which can simplify the manufacturing process of the semiconductor device.

[0061] Based on the above embodiments, referring to Figure 3 , optionally, in the direction X from the cell part 01 to the terminal part 02, a plurality of field limiting rings 2 are arranged at intervals in sequence.

[0062] Specifically, when the voltage applied to the main junction (located in the cell part 01) gradually increases, the depletion region of the main junction also gradually expands outwards. Before the voltage increases to the avalanche voltage of the main junction, the depletion regions of the two junctions (the main junction and the field limiting ring 2) have already converged, playing a role in increasing the junction curvature radius and improving the breakdown voltage of the device. The field limiting ring 2 acts as a voltage divider to some extent and helps to significantly reduce the curvature of the depletion region of the main junction. The breakdown voltage increases with the increase in the number of field limiting rings 2, but it is not a linear increase. The effect of increasing the breakdown voltage by increasing the number of field limiting rings 2 will gradually become weaker. The more the number of field limiting rings 2, the larger the total area of the device occupied. Therefore, it is necessary to balance the relationship between the number of rings and the breakdown electric field size.

[0063] Moreover, the distance between the main junction and the field limiting ring 2, the distance between the field limiting rings 2, and the width of the field limiting ring 2 have a significant impact on the voltage dividing ability. If the distance between the main junction and the field limiting ring 2 and the distance between the field limiting rings 2 are too small, the increase in the curvature radius of the main junction is limited, and the voltage dividing effect is not obvious. If the distance between the main junction and the field limiting ring 2 and the distance between the field limiting rings 2 are too large, before the main junction avalanche breakdown, the depletion regions of the field limiting ring 2 and the main junction do not converge, so the field limiting ring 2 does not play a role in voltage division. Therefore, it is necessary to select appropriate ring spacings and the spacing between the main junction and the field limiting ring 2 so that the electric field strengths of the main junction and the field limiting ring 2 reach the critical breakdown electric field simultaneously, in order to obtain the highest breakdown voltage.

[0064] In addition, if the width of the field limiting ring 2 is too small, it will affect the voltage dividing effect of the field limiting ring 2. If the width of the field limiting ring 2 is too large, it will waste chip area. In the embodiments of the present invention, the width of the field limiting ring 2 closest to the cell portion 01 is set to be the largest, and the widths of the other field limiting rings 2 are smaller than the width of the field limiting ring 2 closest to the cell portion 01, which can reduce the waste of chip area while ensuring the voltage dividing effect of the field limiting ring 2.

[0065] Based on the above embodiments, referring to Figure 3 , optionally, the maximum width L1 of each field limiting ring 2 is smaller than the width L2 of the corresponding limiting groove 30.

[0066] Specifically, since the width of the field limiting ring 2 gradually decreases in the direction Y from the first surface 11 to the second surface 12, the maximum width L1 of the field limiting ring 2 is the width of the field limiting ring 2 at the bottom surface of the limiting groove 30, that is, the width of the field limiting ring 2 at the bottom surface of the limiting groove 30 is smaller than the width L2 of the limiting groove 30. By setting the maximum width L1 of each field limiting ring 2 to be smaller than the width L2 of the corresponding limiting groove 30, during the process of manufacturing a semiconductor device, sufficient space can be provided for forming a mask layer with a certain thickness in the limiting groove 30. Furthermore, when depositing a mask material in the limiting groove 30, due to the relatively wide width of the limiting groove 30, a cavity is formed in the limiting groove 30. Based on the shape of the cavity, the thickness of the mask layer at different positions in the limiting groove 30 can be adjusted, so that the width of the field limiting ring 2 formed by ion implantation gradually decreases in the direction Y from the first surface 11 to the second surface 12, thereby increasing the distance between adjacent two field limiting rings 2 gradually, which can prevent the ion diffusion in the field limiting ring 2 from causing adjacent field limiting rings 2 to be connected together, and improve the breakdown voltage resistance of the terminal portion 02 in the semiconductor device.

[0067] Based on the above embodiments, referring to Figure 3, Optionally, multiple field limit rings 2 include at least one first field limit ring 21. The first field limit ring 21 includes a first side wall a, a second side wall b, a third side wall c and a fourth side wall d connecting the first side wall a and the second side wall b; wherein, the third side wall c is located at the bottom surface of the limiting groove 30, and the fourth side wall d is arranged opposite to the third side wall c; the area of the fourth side wall d is smaller than the area of the third side wall c.

[0068] The multiple field limit rings 2 further include at least one second field limit ring 22. The second field limit ring 22 includes a fifth side wall e, a sixth side wall f and a seventh side wall g connecting the fifth side wall e and the sixth side wall f; wherein, the seventh side wall g is located at the bottom surface of the limiting groove 30, and in the direction Y from the first surface 11 to the second surface 12, the distance between the fifth side wall e and the sixth side wall b gradually decreases until it becomes zero. Wherein, the distance from the first field limit ring 21 to the cell part 01 is smaller than the distance from the second field limit ring 22 to the cell part 01.

[0069] Exemplarily, Figure 3 Five field limit rings 2 are shown, including one first field limit ring 21 and four second field limit rings 22. The cross-sectional shape of the first field limit ring 21 is an inverted trapezoid, and the cross-sectional shape of the second field limit ring 22 is an inverted triangle. Wherein, the maximum width L1 of the first field limit ring 21 is greater than the maximum width L1 of the second field limit ring 22, and the maximum widths L1 of the four second field limit rings 22 are equal. In other embodiments of the present invention, all the field limit rings 2 can be set as the first field limit rings 21, or all the field limit rings 2 can be set as the second field limit rings 22, or multiple first field limit rings 21 and multiple second field limit rings 22 can be set.

[0070] During the preparation process of the first field limit ring 21 and the second field limit ring 22, by adjusting the width L2 of the limiting groove 30, the width L2 of the limiting groove 30 corresponding to the first field limit ring 21 (the limiting groove 30 directly above the first field limit ring 21) can be made greater than the width L2 of the limiting groove 30 corresponding to the second field limit ring 22 (the limiting groove 30 directly above the second field limit ring 22). For Figure 3For the semiconductor device shown, the width L2 of the limiting trench 30 closest to the cell portion 01 (the limiting trench 30 corresponding to the first field limiting ring 21) is the largest, and the widths L2 of the remaining limiting trenches 30 are all equal. The step coverage of Plasma Enhance Chemical Vapor Deposition (PECVD) is relatively poor, and a mask layer can be formed by depositing a mask material using PECVD. During the process of depositing the mask material, due to the poor step coverage of PECVD, the thickness of the mask layer at the bottom of the limiting trench 30 is inconsistent with the thickness of the mask layer on the upper sidewall of the limiting trench 30, and the thickness of the mask layer at the bottom of the limiting trench 30 is less than the thickness of the mask layer on the upper sidewall of the limiting trench 30. When depositing the mask material in the limiting trench 30, the width of the limiting trench 30 corresponding to the first field limiting ring 21 is larger, so that an open-top trapezoidal cavity can be formed in this limiting trench 30; while the width of the limiting trench 30 corresponding to the second field limiting ring 22 is smaller, and the mask layers on the upper sidewalls of the limiting trench 30 can be connected together to form a sealed equilateral triangular cavity; when performing ion implantation to form the field limiting ring 2, based on the shape of the trapezoidal cavity, a first field limiting ring 21 with an inverted trapezoidal cross-sectional shape can be formed; based on the shape of the equilateral triangular cavity, a second field limiting ring 22 with an inverted triangular cross-sectional shape can be formed. Among them, the trapezoidal cavity refers to a trapezoidal cavity whose upper base (the side away from the second surface) length is greater than the lower base (the side close to the second surface) length. The trapezoidal cavity is axisymmetric with the inverted trapezoidal first field limiting ring 21. The equilateral triangular cavity refers to an equilateral triangular cavity whose apex angle of the triangle is located on the side of the base of the triangle away from the second surface 12, and the equilateral triangular cavity is axisymmetric with the inverted triangular second field limiting ring 22.

[0071] Furthermore, the depths of different limiting trenches 30 are the same. Specifically, setting the depths of different limiting trenches 30 to be the same can form all the limiting trenches 30 in the same process step, thereby reducing the manufacturing difficulty of the semiconductor device. Among them, since the cavity formed in the limiting trench 30 corresponding to the first field limiting ring 21 is not capped, in the direction from the first surface 11 to the second surface 12, the thickness of the first field limiting ring 21 is greater than the thickness of the second field limiting ring 22, that is, the distance from the field limiting ring 2 (the first field limiting ring 21) closest to the cell portion 01 to the second surface 12 is the closest. The distance from each field limiting ring to the second surface is greater than 0.

[0072] Based on the above embodiments, Figure 4 is a schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present invention. Refer to Figure 4, Optionally, a filling material 40 is disposed in the limit groove 30. Specifically, after the field limiting ring 2 is formed, the mask layer located in the limit groove 30 can be removed, and then the filling material 40 is disposed in the limit groove 30 to achieve planarization of the device surface. The filling material 40 includes at least one of silicon oxide, silicon nitride, and polyimide.

[0073] An embodiment of the present invention further provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device described in any of the above embodiments. Figure 5 is a flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. Refer to Figure 5 , the manufacturing of the semiconductor device includes:

[0074] S10. Provide a semiconductor body, where the semiconductor body includes a first surface and a second surface that are oppositely disposed; wherein, the first surface includes a first surface of the cell region and a first surface of the terminal region.

[0075] Specifically, refer to Figure 6 , the semiconductor body 1 can be formed by one epitaxial growth or multiple epitaxial growths. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer 20, or a stacked structure formed by multiple semiconductor epitaxial layers 20. The semiconductor body 1 can also include a substrate 10, that is, the semiconductor body 1 includes the substrate 10 and at least one semiconductor epitaxial layer 20 formed on one side of the substrate 10. The material of the substrate 10 and the material of the semiconductor epitaxial layer 20 can be the same, or the material of the substrate 10 and the material of the semiconductor epitaxial layer 20 can be different. The material of the semiconductor body 1 can be SiC.

[0076] The semiconductor body 1 includes a cell portion located in the central region and a terminal portion located in the edge region, and the terminal portion surrounds the cell portion. The cell portion of the semiconductor body 1 is used to manufacture a SiC power device, and the terminal portion of the semiconductor body 1 is used to manufacture a terminal structure of the SiC power device. Among them, the first surface 11 includes a first surface of the cell region and a first surface of the terminal region. The first surface 11 located in the cell portion is the first surface of the cell region 11, and the first surface 11 located in the terminal portion is the first surface of the terminal region.

[0077] S20. Form a plurality of spaced-apart limit grooves on the first surface of the terminal region.

[0078] Specifically, refer to Figure 7 , a plurality of spaced-apart limit grooves 30 can be formed on the first surface of the terminal region by a dry etching process. By setting the depths of different limit grooves 30 to be the same, all the limit grooves 30 can be formed in the same process step, thereby reducing the manufacturing difficulty of the semiconductor device. Among the plurality of limit grooves 30, the width of the limit groove 30 closest to the cell portion is the largest.

[0079] S30. Form a mask layer, which is located on the bottom surface, side walls and the first surface of the terminal region of the limit trench; wherein, the mask layer has a cavity at the position where the limit trench is located, and in the direction from the first surface to the second surface, the width of the cavity gradually increases.

[0080] Specifically, forming the mask layer may specifically include: forming a first mask layer on the side walls of the limit trench 30, the bottom surface of the limit trench 30 and the first surface 11 of the terminal region by low-pressure chemical vapor deposition; forming a second mask layer on the surface of the first mask layer by plasma-enhanced chemical vapor deposition; the first mask layer and the second mask layer are used to enclose a cavity at the position where the limit trench 30 is located. The mask layer includes a first mask layer and a second mask layer.

[0081] Specifically, referring to Figure 8 , a first mask layer 51 with a certain thickness is formed by low-pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD). The material of the first mask layer 51 can be SiO2 or SiN. Since the step coverage of LPCVD is good, a first mask layer 51 with a certain thickness will be formed along the side walls and the bottom surface of the limit trench 30 during the deposition process. Referring to Figure 9 , after forming the first mask layer 51, a SiO2 or SiN thin film with a certain thickness is deposited by plasma-enhanced chemical vapor deposition (PECVD) to form a second mask layer 52. Since the step coverage of PECVD is poor, a cavity will be formed in the limit trench 30 during the deposition process.

[0082] S40. Based on the mask layer, a field limiting ring is correspondingly formed at the bottom of each limit trench; in the direction from the first surface to the second surface, the distance between two adjacent field limiting rings gradually increases.

[0083] Specifically, referring to Figure 10 , based on the mask layer 50, a field limiting ring 2 is correspondingly formed at the bottom of each limit trench 30; wherein, each field limiting ring 2 extends from the bottom surface of the corresponding limit trench 30 to the second surface 12 of the semiconductor body 1; in the direction from the first surface 11 to the second surface 12, the distance between two adjacent field limiting rings 2 gradually increases.

[0084] The manufacturing method of the semiconductor power device provided by the embodiment of the present invention forms a limiting groove 30 first, and then performs ion implantation at the bottom of the limiting groove 30 to form a field limiting ring 2, which can increase the ion implantation depth, reduce the energy required for ion implantation at the same time, and avoid the implantation damage to the semiconductor body 1 caused by high-energy implantation. In addition, before forming the field limiting ring 2, by forming a mask layer 50 on the bottom surface, side wall and the first surface 11 of the terminal area of the limiting groove 30, and making the mask layer 50 have a cavity at the position where the limiting groove 30 is located, the shape of the cavity can be used to adjust the ion implantation depth at different positions, so that the width of the formed field limiting ring 2 gradually decreases in the direction from the first surface 11 to the second surface 12, that is, the distance between two adjacent field limiting rings 2 gradually increases, thereby avoiding the connection of adjacent field limiting rings 2 caused by ion diffusion in the field limiting ring 2 and improving the breakdown voltage of the terminal part 02 in the semiconductor device.

[0085] Optionally, referring to Figure 10 , the cross-sectional shape of the cavity closest to the first surface of the cell area is a trapezoid, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface. In step S40, forming a field limiting ring corresponding to the bottom of each limiting groove based on the mask layer includes:

[0086] Forming a first field limiting ring 21 at the bottom of the limiting groove 30 based on the trapezoidal cavity 61 of the mask layer.

[0087] Among them, at least one first field limiting ring 21 is included in the multiple field limiting rings 2. The first field limiting ring 21 includes a first side wall, a second side wall, a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located at the bottom surface of the limiting groove 30, and the fourth side wall is arranged opposite to the third side wall; the area of the four side walls is smaller than the area of the third side wall.

[0088] Optionally, the cross-sectional shape of at least one cavity outside the cavity closest to the first surface 11 of the cell area is a triangle. In step S40, forming a field limiting ring 2 corresponding to the bottom of each limiting groove 30 based on the mask layer further includes:

[0089] Forming a second field limiting ring 22 at the bottom of the limiting groove 30 based on the triangular cavity 62.

[0090] Among them, at least one second field limiting ring 22 is further included in the multiple field limiting rings 2. The second field limiting ring 22 includes a fifth side wall, a sixth side wall and a seventh side wall connecting the fifth side wall and the sixth side wall; the seventh side wall is located at the bottom surface of the limiting groove 30; in the direction from the first surface 11 to the second surface 12, the distance between the fifth side wall and the sixth side wall gradually decreases until it becomes zero.

[0091] Specifically, during the preparation of the first field stop ring 21 and the second field stop ring 22, the width of the limiting groove 30 can be adjusted so that the width of the limiting groove 30 corresponding to the first field stop ring 21 (the limiting groove 30 directly above the first field stop ring 21) is greater than the width of the limiting groove 30 corresponding to the second field stop ring 22 (the limiting groove 30 directly above the second field stop ring 22). For Figure 3 the semiconductor device shown, the width of the limiting groove 30 closest to the cell portion 01 (the limiting groove 30 corresponding to the first field stop ring 21) is the largest, and the widths of the remaining limiting grooves 30 are equal. A mask layer is deposited with a certain thickness of mask material by plasma enhanced chemical vapor deposition (PECVD). Due to the poor step coverage of PECVD, during the deposition process, the thickness of the mask layer at the bottom of the groove is inconsistent with the thickness of the mask layer on the upper sidewall of the groove, and the thickness of the mask layer at the bottom of the groove is less than the thickness of the mask layer on the upper sidewall of the groove.

[0092] When depositing the mask material in the limiting groove 30, the width of the limiting groove 30 corresponding to the first field stop ring 21 is larger, so that a trapezoidal cavity 61 can be formed in this limiting groove 30; while the width of the limiting groove 30 corresponding to the second field stop ring 22 is smaller, and the mask layers on the upper sidewalls of the limiting groove 30 can be connected together to form a sealed triangular cavity 62; when performing ion implantation to form the field stop ring 2, based on the trapezoidal cavity 61, the first field stop ring 21 with an inverted trapezoidal cross-sectional pattern is formed; based on the triangular cavity 62, the second field stop ring 22 with an inverted triangular cross-sectional pattern is formed.

[0093] The embodiment of the present invention also provides a power module, including a substrate and at least one semiconductor device as described in any embodiment of the present invention, and the substrate is used to carry the semiconductor device. It has the same technical effects and will not be elaborated here.

[0094] The embodiment of the present invention also provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be elaborated here.

[0095] The embodiment of the present invention also provides a vehicle, including a load and a power conversion circuit as described in any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. It has the same technical effects and will not be elaborated here.

[0096] Note that the above is only a preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; wherein, the first surface includes a first surface of a cell region and a first surface of a terminal region; Forming a plurality of spaced-apart limiting trenches on the first surface of the terminal region; Forming a mask layer, the mask layer being located on the bottom surface, side walls of the limiting trenches and the first surface of the terminal region; wherein, the mask layer has a cavity at the position where the limiting trenches are located, and in the direction from the first surface to the second surface, the width of the cavity gradually increases; Based on the mask layer, forming a field limiting ring corresponding to the bottom of each limiting trench; in the direction from the first surface to the second surface, the distance between adjacent two field limiting rings gradually increases.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The forming of the mask layer includes: Forming a first mask layer on the side walls of the limiting trenches, the bottom surface of the limiting trenches and the first surface of the terminal region by low-pressure chemical vapor deposition; Forming a second mask layer on the surface of the first mask layer by plasma-enhanced chemical vapor deposition; wherein, the first mask layer and the second mask layer are used to enclose a cavity at the position where the limiting trenches are located.

3. The manufacturing method of the semiconductor device according to claim 2, characterized in that, The cross-sectional shape of at least the cavity closest to the first surface of the cell region is trapezoidal, and the length of the side of the trapezoid close to the second surface is greater than the length of the side away from the second surface; Based on the mask layer, forming a field limiting ring corresponding to the bottom of each limiting trench includes: Based on the trapezoidal cavity of the mask layer, forming a first field limiting ring at the bottom of the limiting trench; wherein, at least one of the plurality of field limiting rings is a first field limiting ring, and the first field limiting ring includes a first side wall, a second side wall, and a third side wall and a fourth side wall connecting the first side wall and the second side wall; the third side wall is located on the bottom surface of the limiting trench, and the fourth side wall is arranged opposite to the third side wall; the area of the four side walls is smaller than the area of the third side wall.

4. The method for manufacturing a semiconductor device according to claim 3, wherein, The cross-sectional shape of at least one cavity outside the cavity closest to the first surface of the cell region is triangular; Based on the mask layer, forming a field limiting ring corresponding to the bottom of each limiting trench further includes: Based on the triangular cavity of the mask layer, forming a second field limiting ring at the bottom of the limiting trench; At least one of the plurality of field limiting rings is also a second field limiting ring, and the second field limiting ring includes a fifth side wall, a sixth side wall, and a seventh side wall connecting the fifth side wall and the sixth side wall; the seventh side wall is located on the bottom surface of the limiting trench; in the direction from the first surface to the second surface, the distance between the fifth side wall and the sixth side wall gradually decreases until it becomes zero.

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