A SiC mosfet device with double auxiliary gates

Abstract

The application relates to a double auxiliary gate SiC MOSFET device, and belongs to the technical field of semiconductors. The device is integrated with a gate auxiliary trench gate, a source auxiliary trench gate, and a P-connect region is arranged, thereby forming a P-type potential barrier region controlled by the gate auxiliary trench gate. When the device is forwardly conducted, the gate auxiliary trench gate and the source auxiliary trench gate jointly pinch off the P-connect in the P-type potential barrier region, disconnect the P+ source region and the P-well, make the P-well float, and reduce the specific on-resistance; when the device is blocked, the P-connect is not pinched off, the potential barrier between the P-well and the P+ source region is almost 0, and good grounding is formed. When the device is reversely conducted, a low-potential reverse conducting channel is introduced beside the source auxiliary trench gate, the inhibition of the reverse conducting channel to the body diode eliminates the bipolar degradation effect, and the reverse recovery rate of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a SiC MOSFET device with dual auxiliary gates. Background Technology

[0002] With the transformation of the global energy structure and the rapid development of power electronics technology, power semiconductor devices, as core components of power conversion, directly determine the efficiency, reliability, and integration of energy systems. Especially in fields such as new energy vehicles, smart grids, industrial frequency converters, and renewable energy power generation, more stringent requirements are placed on the high-voltage withstand capability, high-frequency switching characteristics, high-temperature stability, and low-loss characteristics of power devices. Traditional power devices, represented by silicon (Si)-based materials, are increasingly facing performance bottlenecks in high-voltage, high-temperature, and high-switching-frequency applications due to their physical characteristics (such as narrow bandgap, low critical breakdown electric field, and limited thermal conductivity). For example, the on-resistance of silicon-based devices increases sharply under high voltage, leading to increased conduction losses; the carrier mobility decreases at high temperatures, exacerbating the risk of thermal runaway; and parasitic capacitance effects are significant during high-frequency switching, limiting switching speed and generating additional losses. Therefore, wide-bandgap semiconductor materials, represented by silicon carbide (SiC), have become the ideal choice for next-generation power devices due to their superior physical characteristics—wider bandgap, higher breakdown voltage, and lower on-resistance.

[0003] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiC MOSFETs), as a typical representative of SiC power devices, exhibit significant advantages in high-voltage blocking capability, on-resistance, and switching speed by combining MOS gate control with a vertical conduction structure. However, with the increasing complexity of application scenarios and the rising performance requirements, existing SiC MOSFET technology still faces challenges, including:

[0004] 1) On-resistance (R) on,sp The trade-off between ) and breakdown voltage (BV)

[0005] Traditional SiC MOSFETs employ a vertical trench gate structure to reduce on-resistance, but the trench gate design introduces the JFET effect. Specifically, when the device is forward-biased, current flows through the JFET region between the drift region and the channel region. The doping concentration and geometry of this region directly affect the on-resistance. To optimize on-resistance, the lateral dimension of the JFET region needs to be increased or the doping concentration increased, but this leads to a decrease in breakdown voltage. On the other hand, if the breakdown voltage is increased by reducing the JFET region size or decreasing the doping concentration, the on-resistance increases significantly. This contradiction limits the device's performance in high-efficiency applications, especially in high-voltage scenarios requiring low conduction losses, making it difficult to simultaneously achieve excellent static and dynamic characteristics.

[0006] 2) Bipolar Degradation Effect of Body Diode During Reverse-Freewheeling

[0007] In inverter circuits, motor drives, and other applications, SiC MOSFETs are required to withstand reverse-freewheeling conditions. In this case, the parasitic body diode (composed of P-well and N-drift) inside the device is forced to conduct. However, the conduction of the body diode causes a minority carrier injection effect, leading to bipolar degradation phenomena: on one hand, the heat generated when the injected holes and electrons recombine in the drift region exacerbates the device temperature rise, reducing reliability; on the other hand, the rapid release of stored charge during reverse recovery can cause current spikes and voltage oscillations, increasing switching losses and potentially damaging the peripheral circuit. In addition, the conduction voltage drop of the body diode is high, further increasing the conduction loss during reverse-freewheeling. In the prior art, although the conduction of the body diode can be suppressed by optimizing the doping distribution or introducing a Schottky contact, these methods often sacrifice the forward characteristics of the device or increase the process complexity.

[0008] In summary, although SiC MOSFETs perform well in multiple fields, they still face some technical bottlenecks, particularly the trade-off between on-resistance and breakdown voltage and the conduction loss and bipolar degradation effect of the body diode during reverse-freewheeling, which affects their performance in high-efficiency, high-frequency applications. SUMMARY

[0009] Therefore, the purpose of the present application is to provide a SiC MOSFET device with double auxiliary gates, which further reduces the on-resistance and accelerates the reverse recovery rate of the diode by optimizing the structural design and doping process of the device, thereby improving the performance of the device in high-frequency, high-performance applications.

[0010] To achieve the above purpose, the present application provides the following technical solutions:

[0011] A SiC MOSFET device with double auxiliary gates, comprising:

[0012] a drift region formed on the surface of a substrate;

[0013] a drain electrode formed on the other surface of the substrate;

[0014] an N-CSL formed on the surface of the drift region;

[0015] a P-base formed on the surface of the N-CSL;

[0016] a first P-well and a second P-well formed on the surface of the N-CSL and distributed on both sides of the P-base;

[0017] an Auxiliary Source formed on the surface of the first P-well and an Auxiliary Gate formed on the surface of the first P-well;

[0018] a Barrier Switch formed on the surface of the first P-well between the Auxiliary Source and the Auxiliary Gate, the Barrier Switch being controlled by the Auxiliary Source and the Auxiliary Gate to regulate the floating or grounding of the first P-well;

[0019] a Gate Trench Gate formed on the surface of the N-CSL and the second P-well;

[0020] a P-base formed on the surface of the N-CSL between the Auxiliary Gate Trench Gate and the Gate Trench Gate;

[0021] a first Source N+ region and a second Source P+ region formed on the surface of the P-base;

[0022] a second Source N+ region formed on the surface of the P-base and the second P-well respectively, and the second Source N+ region being distributed on both sides of the Gate Trench Gate;

[0023] and a Gate Electrode formed on the top of the device, the Gate Electrode being in contact with the first Source P+ region, the second Source P+ region, the first Source N+ region and the second Source N+ region respectively.

[0024] Further, the Barrier Switch includes a P-connect and a first Source P+ region. The P-connect is formed on the surface of the first P-well, and the first Source P+ region is formed on the surface of the P-connect. The Barrier Switch and the first P-well form a P-type barrier region between the two Auxiliary Trench Gates, and the height of the barrier of the barrier region can be controlled by the Auxiliary Gate Trench Gate.

[0025] When the device is in forward conduction, the Auxiliary Source and the Auxiliary Gate together pinch off the P-connect to disconnect the connection between the first P-well and the first Source P+ region, so that the first P-well is floating, which can reduce the JFET effect and reduce the on-resistance of the device. When the device is in blocking condition, the P-connect is not pinched off, and the barrier between the first P-well and the first Source P+ region is almost 0, which can form a good grounding.

[0026] Further, the source auxiliary trench gate, the first source N+ region and the P-base form a source control MOS channel structure, when the device is in reverse current conduction, the source auxiliary trench gate adds positive pressure, a low barrier reverse conduction channel is formed at the P-base, the bipolar degradation effect caused by the conduction of the body diode is avoided, and the reverse recovery rate is improved.

[0027] Further, the gate trench gate, the source auxiliary trench gate and the gate auxiliary trench gate are respectively wrapped by a trench gate oxide layer.

[0028] By adjusting the thickness of the trench gate oxide layer, the capacitive coupling between the gate and the source of the device can be controlled, thereby improving the performance of the device.

[0029] The beneficial effects of the present application are that the present application embeds the source auxiliary trench gate and the auxiliary gate trench gate, and sets the P-connect region, to achieve the following beneficial effects:

[0030] (1) By setting the P-connect region, a P-type barrier region composed of the first source P+ region, the P-connect region and the P-well is formed at the source auxiliary trench gate and the auxiliary gate trench gate, and the barrier region is controlled by the P-connect to float or ground the P-well. When forward conduction, the gate auxiliary trench gate is connected to a 15V positive voltage, and together with the source auxiliary trench gate, the P-connect region is exhausted and pinched off, so that the P-well is disconnected from the source, thereby the P-well region is floating, reducing the JFET effect, reducing the on-resistance without loss of breakdown voltage, compared with the traditional asymmetric trench SiC MOSFET, the R on,sp of the device proposed by the present application can be reduced by 12.5%. When blocking, the P-connect is not pinched off, and the barrier between the P-well and the source P+ region is almost 0, which can form a good ground.

[0031] (2) By embedding the source auxiliary trench gate, a MOS channel structure controlled by the source auxiliary trench gate, composed of the source auxiliary trench gate, the trench gate oxide layer, the first source N+ region and the P-base, is formed. Based on the MOS channel structure, when the device is in reverse current conduction, the source auxiliary trench gate adds positive pressure, a low barrier reverse conduction channel is formed at the P-base, the opening voltage V cut-in of the channel is about 1.9V, which is reduced by 29.6% compared with the opening voltage (about 2.7-3V) of the body diode, thus avoiding the bipolar degradation effect caused by the conduction of the body diode, and improving the reverse recovery rate.

[0032] In conclusion, the application designs a SiC MOSFET device with double auxiliary gates, reduces the specific on-resistance of the device, and improves the reverse recovery rate of the device.

[0033] Additional advantages, objects, and features of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or can be learned from practice of the application. The objects and other advantages of the application can be realized and attained by the structure particularly pointed out in the description. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to make the purposes, technical solutions and advantages of the application clearer, the preferred detailed description of the application will be combined with the drawings as follows, wherein:

[0035] Figure 1 The overall structure schematic diagram of the SiC MOSFET with double auxiliary gates provided by the embodiment of the application is shown in the figure;

[0036] Figure 2 The equivalent circuit diagram of the device shown in the figure is shown in the figure; Figure 1 The equivalent circuit diagram of the device shown in the figure is shown in the figure;

[0037] Figure 3 The structure schematic diagram of the traditional asymmetric trench SiC MOSFET is shown in the figure;

[0038] Figure 4 The comparison diagram of the output characteristic curves of the device of the application and the traditional asymmetric trench SiC MOSFET when the gate voltage is 15V forward on, and the current path diagram of the SiC MOSFET of the application when working in the first quadrant is shown in the figure;

[0039] Figure 5 The total current density distribution diagram of the device of the application and the traditional asymmetric trench SiC MOSFET when forward on is shown in the figure;

[0040] Figure 6 The comparison diagram of the breakdown characteristic curves of the device of the application and the traditional asymmetric trench SiC MOSFET is shown in the figure;

[0041] Figure 7 The breakdown electric field distribution schematic diagram of the device of the application and the traditional asymmetric trench SiC MOSFET is shown in the figure;

[0042] Figure 8 The valence band barrier height curve between ab of the device of the application under the conditions of on and blocking is shown in the figure;

[0043] Figure 9For reverse conduction, the third quadrant curve comparison of the inventive device and conventional asymmetric trench SiC MOSFET when the gate voltage is -5V, and the hole current density distribution map when the reverse current is 200A / cm 2

[0044] Figure 10 For reverse conduction, the hole current curve comparison of the inventive device and conventional asymmetric trench SiC MOSFET when the gate voltage is -5V, and the hole current density distribution map when the reverse current is 200A / cm 2

[0045] Figure 11 For the comparison of the reverse recovery current of the inventive device and conventional asymmetric trench SiC MOSFET;

[0046] Figure 12 For the comparison of the capacitance of the inventive device and conventional asymmetric trench SiC MOSFET;

[0047] Figure 13 For the comparison of the gate charge characteristics of the inventive device and conventional asymmetric trench SiC MOSFET;

[0048] Figure 14 For the comparison of the switching characteristics of the inventive device and conventional asymmetric trench SiC MOSFET;

[0049] Figure 15 For the comparison of the switching loss of the inventive device and conventional asymmetric trench SiC MOSFET.

[0050] Reference signs: 1-drain, 2-N+SUB, 3-N-Drift, 4-N-CSL, 5-P-well, 6-gate trench gate, 7-gate auxiliary trench gate, 8-source auxiliary trench gate, 9-P-connect, 10-first source P+ region, 11-P-base, 12-trench gate oxide layer, 13-first source N+ region, 14-second source P+ region, 15-second source N+ region, 16-source. DETAILED DESCRIPTION

[0051] The present application will be described in detail below with reference to specific embodiments. Other advantages and effects of the present application will be easily understood by those skilled in the art from the disclosure of the present application. The present application can also be implemented or applied in other different embodiments, and the details in the present specification can be modified or changed in various ways based on different views and applications without departing from the spirit of the present application. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present application in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.​​

[0052] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0053] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0054] like Figure 1 As shown, a SiC MOSFET device with dual auxiliary gates is provided in an embodiment of the present invention. The device can be divided into three parts according to its structural characteristics: a traditional MOSFET structure, a source-controlled MOS channel structure, and a gate-assisted trench gate-controlled P-type barrier region.

[0055] The device provided in this embodiment includes drain 1, N+SUB2, N-Drift3, N-CSL4, P-well5, gate trench gate 6, gate auxiliary trench gate 7, source auxiliary trench gate 8, P-connect9, first source P+ region 10, P-base11, trench gate oxide layer 12, first source N+ region 13, second source P+ region 14, second source N+ region 15, and source 16.

[0056] The traditional MOSFET structure consists of a source 16, a second source P+ region 14, a second source N+ region 15, a P-base 11, a trench gate oxide layer 12, a gate trench gate 6, a P-well 5, an N-CSL 4, a drain 1, an N+SUB 2, and an N-Drift 3.

[0057] The drain electrode 1 is located on the lower surface of N+SUB2.

[0058] The N+SUB2 is located on the lower surface of N-Drift3 and the upper surface of drain 1, with a thickness of 3 μm. It is made of SiC doped with N-type nitrogen (N) impurities at a concentration of 1 × 10⁻⁶. 19 cm -3 .

[0059] The N-Drift 3 is located on the upper surface of the N+SUB 2 and the lower surface of the N-CSL 4, with a thickness of 11 μm, and SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 7 x 1018cm-3. 15 -3 .

[0060] The N-CSL 4 is located on the upper surface of the N-Drift 3 and the lower surface of the P-base 11, and the left side is in contact with the left side P-well 5, and the right side is in contact with the trench gate oxide layer 12 and the right side P-well 5, and the shape of the N-CSL 4 is irregular rectangle, with a thickness of 1.5 μm, a lower side width of 2.7 μm, a middle part width of 0.9 μm, and an upper side width of 0.6 μm, and SiC is doped with N-type impurity nitrogen (N) with a doping concentration of 2.5 x 1018cm-3. 16 -3 .

[0061] The P-well 5 is divided into left and right side parts, the left side P-well 5 is located on the lower surface of the gate auxiliary trench gate 7, the source auxiliary trench gate 8 and the P-connect 9, and the right side P-well 5 is located on the lower surface of the source 16 and is in contact with the gate trench gate 6 in L shape. Among them, the thickness of the left side P-well 5 is 1.4 μm, and the width is 1.1 μm, the thickness of the right side P-well 5 is 1.7 μm, and the width is 0.7 μm, SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 1 x 1018cm-3. 19 -3 .

[0062] The gate trench gate 6 is wrapped in the trench gate oxide layer 12, and the left side is separated from the P-base 11, the P-well 5 and the left side second source N+ area 15 through the trench gate oxide layer 12, and the right side is separated from the right side second source N+ area 15 and the P-well 5 through the trench gate oxide layer 12. The thickness of the gate trench gate 6 is 1.0 μm, and the width is 0.5 μm, and the material is pure polysilicon. Among them, the thickness of the left, right and lower side of the trench gate oxide layer 12 wrapping the gate trench gate 6 is 0.05 μm.

[0063] The P-base 11 is located on the upper surface of the N-CSL 4, and the lower surface of the first source N+ area 13, the second source P+ area 14 and the left side second source N+ area 15, and the left side thickness of the P-base 11 is 0.15 μm, the right side thickness is 0.35 μm, the width is 0.6 μm, SiC is doped with P-type impurity aluminum (AL) with a doping concentration of 2.5 x 1018cm-3. 17 -3 .

[0064] ​​​​The second source P+ area 14 is located on the upper surface of the P-base 11, and contacts the second source N+ area 15 on the right and left sides. The thickness of the second source P+ area 14 is 0.3 μm, the width is 0.2 μm, SiC is doped into P-type impurity aluminum (AL), and the doping concentration is 1×1019 cm-3. 19 cm -3 .

[0065] The second source N+ area 15 is divided into two parts, which are located on the left and right sides of the gate trench gate 6 respectively. Among them, the left second source N+ area 15 is located on the upper surface of the P-base 11, contacts the second source P+ area 14 on the left side, and is separated from the gate trench gate 6 on the right side through the trench gate oxide layer 12; the right second source N+ area 15 contacts the P-well 5 on the right and lower sides, and is separated from the gate trench gate 6 on the left side through the trench gate oxide layer 12. The SiC of the second source N+ area 15 is doped into N-type impurity nitrogen (N), and the doping concentration is 1×1019 cm-3. 19 cm -3 .

[0066] The source control MOS channel structure is composed of a source auxiliary trench gate 8, a trench gate oxide layer 12, a first source N+ area 13 and a P-base 11.

[0067] Among them, the source auxiliary trench gate 8 is wrapped in the trench gate oxide layer 12, and the left, right and lower sides of the trench gate oxide layer 12 wrapping the source auxiliary trench gate 8 are all 0.05 μm in thickness. The left side of the source auxiliary trench gate 8 is separated from the P-connect 9 and the first source P+ area 10, and the right side is separated from the first source N+ area 13, the P-base 11 and the N-CSL 4 through the trench gate oxide layer 12. The thickness of the source auxiliary trench gate 8 is 0.7 μm, the width is 0.4 μm, and the material is pure polysilicon.

[0068] The first source N+ area 13 is located on the left upper surface of the P-base 11 and is separated from the source auxiliary trench gate 8. The thickness of the first source N+ area 13 is 0.2 μm, the width is 0.2 μm, SiC is doped into N-type impurity nitrogen (N), and the doping concentration is 1×1019 cm-3. 19 cm -3 .

[0069] The P-type potential barrier area controlled by the gate auxiliary trench gate is composed of the P-well 5, the gate auxiliary trench gate 7, the source auxiliary trench gate 8, the P-connect 9 and the left source P+ area 10.

[0070] The gate auxiliary trench gate 7 is located at the left side of the P-connect 9 and the first source P+ area 10, at the upper side of the P-well 5 and the lower side of the source 16. The trench gate oxide layer 12 wraps the gate auxiliary trench gate 7, the right side oxide layer thickness of the trench gate oxide layer 12 wrapping the gate auxiliary trench gate 7 is 0.03 μm, the left side and the lower side thickness are both 0.05 μm. The thickness of the gate auxiliary trench gate 7 is 0.7 μm, the width is 0.4 μm, and the material is pure polysilicon.

[0071] The P-connect 9 is located at the lower surface of the first source P+ area 10 and the upper surface of the left side P-well 5, and is in the middle of the gate auxiliary trench gate 7 and the source auxiliary trench gate 8. The thickness of the P-connect 9 is 0.4 μm, the width is 0.1 μm, SiC is doped into P-type impurity aluminum (AL), and the doping concentration is 6×10 17 cm -3 .

[0072] The first source P+ area 10 is located at the upper surface of the P-connect 9 and is connected with the source 16, the thickness of the first source P+ area 10 is 0.2 μm, the width is 0.1 μm, SiC is doped into P-type impurity aluminum (AL), and the doping concentration is 1×10 19 cm -3 . Wherein, the P-well 5, the P-connect 9 and the first source P+ area 10 are vertically arranged to form a P-type potential barrier area.

[0073] Figure 2 The equivalent circuit diagram of the device is shown, it can be seen that the SiC MOSFET device of the application actually integrates a P-type potential barrier area controlled by an auxiliary gate, which is similar to the floating and grounding of the switch controlled P-well for the P-well. In addition, the SiC MOSFET device also integrates a reverse conducting MOSFET controlled by a source auxiliary trench gate.

[0074] As Figure 4 shown is the comparison of the output characteristic curve of the device of the application and the traditional asymmetric trench SiC MOSFET (the structure is shown in Figure 3 ), when the gate voltage is 15V and the forward is turned on, and the current path of the SiC MOSFET device of the application when working in the first quadrant, I ds =200A / cm 2 , the on-resistance is 2.65mΩ·cm 2 and 3.03mΩ·cm 2 , respectively. The on-resistance of the device of the application is smaller than that of the traditional asymmetric trench SiC MOSFE.

[0075] As Figure 5The image shows a comparison of the total current density distribution of the device of this invention and a conventional asymmetric trench SiC MOSFET during forward conduction. From... Figure 5 As can be seen, during forward conduction, the current width of the device of this invention in the J-FET region is 0.41 μm, while the current width of a conventional asymmetric trench SiC MOSFET is 0.34 μm. This is because when the gate is connected to a positive voltage of 15V, the P-connect9 in the P-type barrier region is depleted, causing the first source P+ region 10 connected to the source to disconnect from P-well 5. This floating of P-well 5 reduces the JFET effect, reduces the depletion region width, and thus increases the current path width, enabling the device of this invention to achieve a lower on-resistance.

[0076] like Figure 6 The figure shows a comparison of the breakdown characteristic curves of the device of the present invention and that of a traditional asymmetric trench SiC MOSFET. It can be seen that the two devices exhibit similar BV characteristics. Figure 5 The leakage current of the two devices under breakdown conditions was also demonstrated. The curves show that the P-connect region 9 introduced in the device of this invention can effectively ground P-well 5 under blocking conditions, exhibiting good BV characteristics.

[0077] like Figure 7 The diagram shows the breakdown electric field distribution of the device of this invention and a traditional asymmetric trench SiC MOSFET. It can be seen that the maximum breakdown electric field of both devices is at Pwell 5, and the gate oxide electric field is less than 3 MV / cm, which is beneficial for enhancing the long-term reliability of the gate oxide layer.

[0078] like Figure 8 The figure shows the valence band barrier height curves between ab (i.e., P-well5, P-connect9, and the first source P+ region 10 are arranged perpendicularly to form a P-type barrier region) of the device of the present invention under both on and off conditions. Figure 8 As can be seen, when the P-well5 is conducting, it can be depleted and disconnected through P-connect9, thus achieving good floating and reducing on-resistance. When the P-well5 is blocking, it can be grounded through P-connect9, exhibiting excellent BV characteristics.

[0079] like Figure 9 The figure shows a comparison of the third quadrant curves of the device of this invention and a conventional asymmetric trench SiC MOSFET when reverse conduction is achieved and the gate voltage is -5V, as well as the reverse current at 200A / cm. 2 The total current density distribution during reverse conduction is shown. It can be seen that, during reverse conduction, the device of this invention conducts in the reverse channel at approximately 1.9V, while the body diode of a conventional device only turns on at approximately 2.7V. From... Figure 9 It can be seen that when the reverse current is 200A / cm2 The device of the present application inhibits the conduction of the body diode and avoids the bipolar degradation effect.

[0080] As shown in Figure 10 , the hole current curves of the device of the present application and the conventional asymmetric trench SiC MOSFET are compared when the gate voltage is -5V, and the hole current density distribution is compared when the reverse current is 200A / cm 2 . It can be seen that when the reverse voltage is close to -3.1V, the body diode of the device of the present application starts to conduct, and the single-polarity conduction changes to bipolar conduction, and before this, the hole current is almost 0, and the conduction of the body diode is completely inhibited, and the bipolar degradation effect is avoided.

[0081] As shown in Figure 11 , the change relationship of the reverse recovery current of the device of the present application and the conventional asymmetric trench SiC MOSFET is compared. Due to the existence of the low-potential barrier channel, the opening of the body diode can be inhibited during the reverse recovery process, thereby greatly reducing the hole injection efficiency of the body diode device, thereby reducing the reverse recovery charge, the reverse peak current and the reverse recovery time, and finally improving the reverse recovery performance of the device. As can be seen from Figure 11 , the reverse recovery time (T rr ) of the conventional SiC MOSFET device is 13ns, and the reverse recovery time of the device of the present application is 6ns, which is reduced by 53.8% compared with the conventional device; the reverse recovery current peak (I rr ) of the conventional SiC MOSFET device is 423A / cm 2 , and the reverse recovery current peak of the device of the present application is 346A / cm 2 , which is reduced by 18.8% compared with the conventional device; the reverse recovery charge Q rr of the conventional SiC MOSFET device is 2.76μC / cm 2 , and the reverse recovery charge Q rr of the device of the present application is 0.96μC / cm 2 , which is reduced by 65.2% compared with the conventional device.

[0082] As shown in Figure 12 , the capacitances of the device of the present application and the conventional asymmetric trench SiC MOSFET are compared. As can be seen from Figure 12 , the feedback capacitance (C rss ) and the output capacitance (C oss ) of the device of the present application are slightly lower than those of the conventional asymmetric trench SiC MOSFET, but the input capacitance (C issThe gate-source overlapping area is increased by the auxiliary trench gate introduced in the device, the capacitive coupling between the gate and the source is increased, the capacitive coupling between the gate and the source can be reduced by adjusting the thickness of the oxide layer, and the device performance is improved.

[0083] As shown in Figure 13 , the gate charge (Q gd ) and the total gate charge (Q g ) of the device of the present application are 56.7nC / cm 2 and 780nC / cm 2 , respectively, and those of the conventional asymmetric trench SiC MOSFET are 58.2nC / cm2 and 610nC / cm2, respectively. This is because the C gs of the device of the present application is increased, and the gate current in the later stage after the platform stage is mainly C gs charging, so that the total gate charge of the device of the present application is higher.

[0084] As shown in Figure 14 , the switching characteristic curves of the device of the present application and the conventional asymmetric trench SiC MOSFET are shown. It can be seen that the performances of the two devices are almost the same in the closing process, but the device of the present application needs slightly longer time in the opening process due to the larger input capacitance.

[0085] As shown in Figure 15 , the switching loss of the device of the present application and the conventional asymmetric trench SiC MOSFET is compared, and it can be seen from Figure 15 that the switching loss of the device of the present application and the conventional asymmetric trench SiC MOSFET is 1.32mJ / cm 2 , 0.85mJ / cm 2 and 0.90mJ / cm 2 , 0.78mJ / cm 2 , respectively. It can be seen that the turn-off performances of the two devices are basically the same, and in the opening performance, the device of the present application has more loss due to the larger input capacitance. It can be improved that the capacitive coupling can be shielded and reduced by adjusting the thickness of the oxide layer in the device of the present application to improve the device performance.

[0086] The related parameter comparison between the SiC MOSFET device of the present application and the conventional asymmetric trench SiC MOSFET device is shown in the following Table 1:

[0087] Table 1

[0088] Device of the invention Conventional device [R on,sp ]] 2.65 mΩ-cm 2 ]] 3.03 mΩ-cm 2 ]] Q gd ]]> 56.7 nC / cm 2 ]] 58.2 nC / cm 2 ]]> BV 1265V 1229V V cut-in ]]> 1.9V 2.7V Q rr ]]> 0.96 μC 2.76 μC [TECHNICAL FIELD] rr ]] 6 ns 13 ns I rr ]] 346 A / cm 2 ]] 423 A / cm 2 ]] E on ]]> 1.32 mJ / cm 2 ]]> 0.90 mJ / cm 2 <!-- 7 -->]]> E off ]]> 0.85 mJ / cm 2 ]] 0.78 mJ / cm 2 ]]

[0089] Finally, it is to be explained that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit the present application. Although the present application is described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or equivalently replaced without departing from the purpose and scope of the technical solutions, and all should be covered in the scope of the claims of the present application.

Claims

1. A SiC MOSFET device with double auxiliary gates, characterized by, The device comprises: a drift region formed on a surface of a substrate; an N-CSL formed on a surface of the drift region; a P-base formed on a surface of the N-CSL; a first P-well and a second P-well formed on a surface of the N-CSL and distributed on both sides of the P-base; a source auxiliary trench gate and a gate auxiliary trench gate formed on a surface of the first P-well; a barrier switch formed on a surface of the first P-well and between the source auxiliary trench gate and the gate auxiliary trench gate, the barrier switch being controlled by the source auxiliary trench gate and the gate auxiliary trench gate to regulate floating or grounding of the first P-well; the barrier switch comprises a P-connect and a first source P+ region; the P-connect is formed on a surface of the first P-well, and the first source P+ region is formed on a surface of the P-connect; a gate trench gate formed on a surface of the N-CSL and the second P-well; a P-base formed on a surface of the N-CSL and between the gate auxiliary trench gate and the gate trench gate; a first source N+ region and a second source P+ region formed on a surface of the P-base; a second source N+ region formed on a surface of the P-base and the second P-well respectively, and the second source N+ region is distributed on both sides of the gate trench gate.

2. The SiC MOSFET device of claim 1, wherein, When the device is forwardly turned on, the source auxiliary trench gate and the gate auxiliary trench gate jointly pinch off the P-connect to disconnect the connection between the first P-well and the first source P+ region, so that the first P-well is floating.

3. The SiC MOSFET device of claim 1, wherein, The source auxiliary trench gate, the first source N+ region and the P-base constitute a source control MOS channel structure, when the device is reversely conducted, the source auxiliary trench gate adds a positive pressure, a low-potential barrier reverse conduction channel is formed in the P-base to avoid a bipolar degradation effect and improve a reverse recovery rate of the device.

4. The SiC MOSFET device of claim 1, wherein, The gate trench gate, the source auxiliary trench gate and the gate auxiliary trench gate are respectively wrapped by a trench gate oxide layer.

5. The SiC MOSFET device of claim 4, wherein, By adjusting the thickness of the trench gate oxide layer, the capacitive coupling between the gate and the source of the device is regulated, so that the performance of the device is improved.

6. The SiC MOSFET device of any one of claims 1-5, wherein, The device further comprises a source electrode on the top and a drain electrode on the bottom; The source electrode is in contact with the first source P+ region, the second source P+ region, the first source N+ region and the second source N+ region respectively; The drain electrode is located on a surface of the substrate away from the drift region.

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