A trench MOSFET device and a manufacturing method thereof

Abstract

The present application provides a trench MOSFET device and a manufacturing method thereof, relating to the field of semiconductor technology. It includes an N-type substrate; a first N-type epitaxial layer; an oxide layer located on the surface of the first N-type epitaxial layer, and a low-K dielectric layer is provided in the oxide layer; a second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, and a trench region is provided in the second N-type epitaxial layer; a gate oxide layer and a gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and is arranged around the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; a P-type well region located in the second N-type epitaxial layer, an N-type doped region and a PP region located on the surface of the second N-type epitaxial layer, and an interlayer dielectric layer located on the surface of the gate polysilicon; an ohmic contact layer located on the surface of the PP region and the N-type doped region, and a first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer. The present application has the advantages of greatly reducing the probability of gate oxide failure, improving the reliability of the gate oxide and the robustness of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a trench MOSFET device and a manufacturing method thereof. Background Art

[0002] For Si IGBT or Si MOSFET, the design of the trench gate structure has obvious performance advantages compared with the planar gate structure. However, for SiC MOSFET, this advantage is no longer significant at present.

[0003] According to Gauss's theorem, the electric field strength on the surface of the gate SiO2 in SiC MOSFET is about 2.5 times that of the corresponding SiC surface electric field strength (E ox = 2.5E sic ). Since silicon carbide material is known for its high critical breakdown electric field strength (about 10 times that of silicon material), the electric field strength borne by the gate SiO2 in SiC MOSFET is extremely high, which is one order of magnitude higher than that borne by the gate SiO2 in Si MOSFET / IGBT. Therefore, the reliability of the gate SiO2 in SiC MOSFET faces serious challenges.

[0004] On this basis, the gate oxide reliability problem in the design of trench SiC MOSFET is more serious because the trench gate corner close to 90° further exacerbates the concentration of power lines, and the gate oxide layer here is extremely easy to be broken down.

[0005] In summary, in the prior art, there are problems that the trench of the MOSFET is prone to breakdown at the corner, the gate oxide failure rate is relatively high, and the reliability and robustness of the device are poor. Summary of the Invention

[0006] The purpose of this application is to provide a trench MOSFET device and a manufacturing method thereof, so as to solve the problems in the prior art that the trench gate of the MOSFET is prone to breakdown at the corner, the gate oxide failure rate is relatively high, and the reliability and robustness of the device are poor.

[0007] In order to achieve the above purpose, the technical solutions adopted in the embodiments of this application are as follows:

[0008] On the one hand, the embodiments of this application provide a trench MOSFET device, and the trench MOSFET device includes:

[0009] An N-type substrate;

[0010] A first N-type epitaxial layer located on the surface of the substrate;

[0011] An oxide layer located on the surface layer of the first N-type epitaxial layer, wherein a low-K dielectric layer is provided in the oxide layer;

[0012] A second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, wherein a trench region is provided in the second N-type epitaxial layer; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewalls of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region;

[0013] A P-type well region located in the second N-type epitaxial layer, an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively;

[0014] An interlayer dielectric layer located on the surface of the gate polysilicon;

[0015] An ohmic contact layer located on the surfaces of the PP region and the N-type doped region;

[0016] A first metal layer located on the surfaces of the ohmic contact layer and the interlayer dielectric layer;

[0017] A second metal layer located on the back surface of the substrate.

[0018] Optionally, the PP region extends to the first N-type epitaxial layer, and the bottom of the PP region is deeper than the oxide layer.

[0019] Optionally, the trench MOSFET device is symmetrically arranged about the central axis of the trench region.

[0020] Optionally, the gate polysilicon includes a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer arranged layer by layer from bottom to top, and the doping concentration of the second polysilicon layer is greater than the doping concentrations of the first polysilicon layer and the third polysilicon layer;

[0021] The bottom height of the second polysilicon is not lower than the bottom height of the P-type well region, and the top height of the second polysilicon is not higher than the top height of the P-type well region.

[0022] Optionally, the depth of the second polysilicon is half of the depth of the P-type well region, and the top height of the second polysilicon is flush with the top height of the P-type well region.

[0023] Optionally, the second polysilicon layer includes a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are arranged at intervals, and the first sub-layer is in contact with the gate oxide layer on the left side of the trench region, and the second sub-layer is in contact with the gate oxide layer on the right side of the trench region.

[0024] Optionally, the depth of the low-k dielectric layer is equal to the depth of the oxide layer.

[0025] Optionally, the oxide layer is arranged in an arc structure.

[0026] On the other hand, an embodiment of the present application further provides a method for manufacturing a trench MOSFET device for manufacturing the above-mentioned trench MOSFET device, and the method includes:

[0027] Providing an N-type substrate;

[0028] Manufacturing a first N-type epitaxial layer on the surface of the substrate;

[0029] Manufacturing a first trench on the surface layer of the first N-type epitaxial layer, and manufacturing an oxide layer based on the first trench;

[0030] Manufacturing a second N-type epitaxial layer on the surface of the first N-type epitaxial layer, the second N-type epitaxial layer being provided with a trench region; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the side walls of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon is in contact with the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-k dielectric layer is less than the width of the trench region; the second N-type epitaxial layer further includes a P-type well region, an N-type doping region and a PP region on the surface layer of the second N-type epitaxial layer, the N-type doping region is located on the surface of the P-type well region, and both sides of the N-type doping region and the P-type well region are in contact with the PP region and the gate oxide layer respectively;

[0031] Manufacturing an interlayer dielectric layer on the surface of the gate polysilicon;

[0032] Manufacturing an ohmic contact layer on the surfaces of the PP region and the N-type doping region;

[0033] Manufacturing a first metal layer on the surfaces of the ohmic contact layer and the interlayer dielectric layer;

[0034] Manufacturing a second metal layer on the back surface of the substrate.

[0035] Optionally, the step of manufacturing the second N-type epitaxial layer on the surface of the first N-type epitaxial layer includes:

[0036] Growing a second N-type epitaxial layer on the surface of the first N-type epitaxial layer; wherein, a trench region is provided in the second N-type epitaxial layer, and the oxide layer is exposed in the trench region;

[0037] Based on the second N-type epitaxial layer, P-type well region ion implantation, N-type doped region ion implantation, PP region ion implantation, and terminal region ion implantation are successively performed, and furnace annealing is carried out at high temperature;

[0038] Based on the bottom of the trench region, the oxide layer is etched to form a second trench;

[0039] Based on the second trench, a low-K dielectric layer is filled and etched back;

[0040] Based on the sidewall of the trench region, oxidation is carried out to form a gate oxide layer;

[0041] Based on the trench region, polysilicon deposition and etching are carried out to form a complete gate structure.

[0042] Compared with the prior art, the present application has the following beneficial effects:

[0043] The present application provides a trench MOSFET device and a manufacturing method thereof. The trench MOSFET device includes: an N-type substrate; a first N-type epitaxial layer located on the surface of the substrate; an oxide layer located on the surface layer of the first N-type epitaxial layer, wherein a low-K dielectric layer is arranged in the oxide layer; a second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, and a trench region is arranged in the second N-type epitaxial layer; a gate oxide layer and gate polysilicon are arranged in the trench region, the gate oxide layer is located on the sidewall of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; a P-type well region located in the second N-type epitaxial layer, an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are respectively in contact with the PP region and the gate oxide layer; an interlayer dielectric layer located on the surface of the gate polysilicon; an ohmic contact layer located on the surfaces of the PP region and the N-type doped region; a first metal layer located on the surfaces of the ohmic contact layer and the interlayer dielectric layer; a second metal layer located on the back surface of the substrate.

[0044] On the one hand, since a relatively thick oxide layer is arranged at the bottom of the gate polysilicon and the width of the oxide layer is greater than the width of the trench region, the peak electric field intensity at the trench corner can be effectively reduced, the gate oxide failure probability can be greatly reduced, and the gate oxide reliability and device robustness can be improved. At the same time, the thick oxide layer at the bottom of the gate polysilicon increases the equivalent thickness of the gate-drain parasitic capacitance C gd thereby reducing the gate-drain parasitic capacitance C gd , improving the Miller effect of the device, increasing the switching frequency of the device, reducing the switching loss of the device, and at the same time preventing the device mis-conduction problem caused by high dV / dt working conditions. On the other hand, since a low-K dielectric layer is arranged in the oxide layer, the gate-drain parasitic capacitance C can be reducedgd The effects of the equivalent area and equivalent thickness, thereby further reducing the gate-drain parasitic capacitance C of the device gd , improving the switching frequency of the device, reducing the power loss of the device, and further preventing the problem of mis-conduction of the device caused by high dV / dt.

[0045] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically describes preferred embodiments in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0046] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 It is a schematic cross-sectional view of a trench MOSFET in the prior art.

[0048] Figure 2 It is a schematic cross-sectional view of the first cross-sectional structure of the trench MOSFET device provided by the embodiment of the present application.

[0049] Figure 3 It is an equivalent circuit diagram of the trench MOSFET device provided by the embodiment of the present application.

[0050] Figure 4 It is a parameter schematic diagram of the trench MOSFET device provided by the embodiment of the present application.

[0051] Figure 5 It is a schematic cross-sectional view of the second cross-sectional structure of the trench MOSFET device provided by the embodiment of the present application.

[0052] Figure 6 It is a schematic cross-sectional view of the third cross-sectional structure of the trench MOSFET device provided by the embodiment of the present application.

[0053] Figure 7 It is a schematic cross-sectional view of the fourth cross-sectional structure of the trench MOSFET device provided by the embodiment of the present application.

[0054] Figure 8 It is a schematic cross-sectional view corresponding to the production of the first N-type epitaxial layer in the embodiment of the present application.

[0055] Figure 9 It is a schematic cross-sectional view corresponding to the production of the oxide layer in the embodiment of the present application.

[0056] Figure 10It is a schematic cross-sectional structure diagram corresponding to the production of the second N-type epitaxial layer provided by the embodiment of the present application.

[0057] Figure 11 It is a schematic cross-sectional structure diagram corresponding to the annealing in a high-temperature furnace tube provided by the embodiment of the present application.

[0058] Figure 12 It is a schematic cross-sectional structure diagram corresponding to the production of the second trench provided by the embodiment of the present application.

[0059] Icon:

[0060] 110 - Substrate; 120 - First N-type epitaxial layer; 130 - Oxide layer; 140 - Low-K dielectric layer; 150 - Second N-type epitaxial layer; 160 - Gate polysilicon; 161 - First polysilicon layer; 162 - Second polysilicon layer; 163 - Third polysilicon layer; 1621 - First sub-layer; 1622 - Second sub-layer; 170 - Gate oxide layer; 180 - P-type well region; 190 - N-type doping region; 200 - PP region; 210 - Interlayer dielectric layer; 220 - Ohmic contact layer; 230 - First metal layer; 240 - Second metal layer. Detailed implementation manners

[0061] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. The components of the embodiments of the present application described and illustrated herein can be arranged and designed in various different configurations.

[0062] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but merely represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0063] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0064] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0065] In the description of the present application, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of this application is usually placed during use. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0066] As described in the background art, in trench SiC MOSFETs, due to the trench gate corners approaching 90°, the concentration of power lines is further aggravated. Therefore, the corners of trench MOSFETs are prone to breakdown, the gate oxide failure rate is relatively high, and the reliability and robustness of the device are poor.

[0067] For example, please refer to Figure 1 , which is a cross-sectional schematic diagram of a trench MOSFET in the prior art. When the device is in a high blocking voltage state, the electric field at the bottom corner of the trench gate (position A in the figure) is more concentrated and extremely easy to exceed the maximum critical electric field strength, thereby causing the gate oxide layer to breakdown and affecting the reliability of the device. Therefore, it is of great significance to design and manufacture a trench MOSFET with high gate oxide reliability and low failure rate.

[0068] In view of this, to solve the above problems, the embodiments of the present application provide a trench MOSFET device. By optimizing the structure at the corner of the gate oxide layer, the corner of the gate oxide layer is not easily broken down, thereby reducing the gate oxide failure rate and improving the reliability and robustness of the device.

[0069] The trench MOSFET device provided by the present application will be exemplarily described below:

[0070] As an optional implementation, please refer to Figure 2, the trench MOSFET device includes: an N-type substrate 110; a first N-type epitaxial layer 120 located on the surface of the substrate 110; an oxide layer 130 located on the surface layer of the first N-type epitaxial layer 120, wherein a low-K dielectric layer 140 is provided in the oxide layer 130; a second N-type epitaxial layer 150 located on the surface of the first N-type epitaxial layer 120, and the second N-type epitaxial layer 150 is provided with a trench region; a gate oxide layer 170 and a gate polysilicon 160 are provided in the trench region, the gate oxide layer 170 is located on the sidewall of the trench region and surrounds the gate polysilicon 160, and the bottom of the gate polysilicon 160 is in contact with the oxide layer 130; wherein, the thickness of the oxide layer 130 is greater than the thickness of the gate oxide layer 170, the width of the oxide layer 130 is greater than the width of the trench region, and the width of the low-K dielectric layer 140 is less than the width of the trench region; a P-type well region 180 located in the second N-type epitaxial layer 150, an N-type doped region 190 and a PP region 200 located on the surface layer of the second N-type epitaxial layer 150, the N-type doped region 190 is located on the surface of the P-type well region 180, and both sides of the N-type doped region 190 and the P-type well region 180 are in contact with the PP region 200 and the gate oxide layer 170 respectively; an interlayer dielectric layer 210 located on the surface of the gate polysilicon 160; an ohmic contact layer 220 located on the surfaces of the PP region 200 and the N-type doped region 190; a first metal layer 230 located on the surfaces of the ohmic contact layer 220 and the interlayer dielectric layer 210; a second metal layer 240 located on the back surface of the substrate 110.

[0071] Figure 2 Among them, N+ sub represents the N-type substrate, N- epi represents the N-type epitaxial layer, N+ CSL1 represents the N+ type extended layer, and the N-type epitaxial layer and the N+ type extended layer form the first N-type epitaxial layer 120.

[0072] It should be noted that the statement "X is located on the surface layer of Y" in this application means that X is located in Y and is exposed above Y; while the statement "X is located on the surface of Y" means that X and Y are two independent parts, X is located above Y, and X is in contact with Y.

[0073] On the one hand, since a relatively thick oxide layer 130 is provided at the bottom of the gate polysilicon 160, and the width of the oxide layer 130 is greater than the width of the trench region, the peak electric field intensity at the trench corner can be effectively reduced, the gate oxide failure probability can be greatly reduced, and the gate oxide reliability and device robustness can be improved. At the same time, the thick oxide at the bottom of the gate polysilicon 160 increases the equivalent thickness of the gate-drain parasitic capacitance C gd Thereby reducing the gate-drain parasitic capacitance C gd , improving the Miller effect of the device, increasing the device switching frequency, reducing the device switching loss, and also preventing the device mis-conduction problem caused by high dV / dt conditions. Specifically, according to the delay formula t = Rg-int * C gd, where t represents the delay time and Rg-int represents the equivalent resistance of the gate polysilicon. It can be seen that when the gate-drain parasitic capacitance C gd decreases, the delay time decreases, and thus the switching frequency of the device can be improved. On the other hand, since the low-k dielectric layer 140 is provided in the oxide layer 130, the equivalent area and equivalent thickness of the gate-drain parasitic capacitance C gd can be reduced, and further the gate-drain parasitic capacitance C gd of the device can be further reduced, the switching frequency of the device is increased, the power loss of the device is reduced, and the problem of mis-conduction of the device caused by high dV / dt is further prevented.

[0074] Among them, the first N-type epitaxial layer 120 and the second N-type epitaxial layer 150 provided in this application can both adopt SiC epitaxial layers.

[0075] In the trench MOSFET device provided in this application, the oxide layer 130 is arranged in an arc structure. By arranging the relatively thick oxide layer 130 at the bottom of the gate polysilicon in an arc shape, it can buffer the high-voltage electric field between the drain and the source, further reduce the electrical stress borne by the oxide layer at the trench gate corner position, and greatly improve the breakdown voltage and avalanche reliability of the device.

[0076] Moreover, the width of the oxide layer 130 is greater than the width of the trench region, and the bottom of the trench can be wrapped by the oxide layer 130, alleviating the concentration of the power lines at the trench gate corner. Thus, the peak electric field intensity at the trench corner can be effectively reduced, the probability of gate oxide failure can be greatly reduced, and the gate oxide reliability and device robustness can be improved.

[0077] It should be noted that the width of the oxide layer 130 described in this application refers to the maximum width of the oxide layer 130.

[0078] Moreover, in the device, regarding the gate polysilicon 160 as one electrode plate and the drain (i.e., the second metal layer 240) as the other electrode plate, the gate-drain parasitic capacitance of the entire device can be formed. After the oxide layer 130 is arranged, the dielectric constant between the two electrode plates can be effectively reduced (the dielectric constant of SiC is about 9.7, and the dielectric constant of the oxide layer 130 is about 3.9). According to the formula C = ε * A / d, where C represents the capacitance value, ε represents the dielectric constant of the dielectric, A represents the facing area of the two electrode plates, and d represents the distance between the two electrode plates.

[0079] It can be seen that after the oxide layer 130 is arranged, the gate-drain parasitic capacitance C gd is reduced, the Miller effect of the device is improved, the switching frequency of the device is increased, and the switching loss of the device is reduced. At the same time, please refer to Figure 3 , which is the equivalent circuit diagram of the trench MOSFET device. In the figure, Rg-int represents the equivalent resistance of the gate polysilicon, and C gdrepresents the gate-drain parasitic capacitance, C gs represents the gate-source parasitic capacitance, C DS represents the drain-source parasitic capacitance. When the gate-drain parasitic capacitance C gd is reduced, it can effectively prevent the problem of device mis-conduction caused by high dV / dt conditions.

[0080] Meanwhile, depositing a low-K dielectric layer 140 in the oxide layer 130 can further reduce the dielectric constant between the two electrodes, and further reduce the gate-drain parasitic capacitance C gd of the device, achieving the effect of improving the switching frequency of the device, reducing the power loss of the device, and further preventing the problem of device mis-conduction caused by high dV / dt. It should be noted that the dielectric constant of the low-K dielectric layer 140 described in this application is at least less than that of the oxide layer 130.

[0081] And for the parameter design of the low-K dielectric layer 140, please refer to Figure 4 , in the figure, H0 represents the thickness of the oxide layer, Hd represents the thickness of the low-K dielectric layer, Lw represents the width of the low-K dielectric layer, L0 represents the maximum width of the oxide layer, and Lp represents the width of the trench region. In terms of parameter setting, it is necessary to satisfy that the width of the low-K dielectric layer 140 is less than the width of the trench region, that is, Lw < Lp. At the same time, it is necessary to satisfy L0 > Lp. The thickness of the low-K dielectric layer 140 needs to be less than or equal to the thickness of the oxide layer 130, that is, Hd ≤ H0. By reducing the equivalent dielectric constant of the gate-drain parasitic capacitance C gd , the purpose of further reducing the gate-drain parasitic capacitance C gd of the device is achieved. And theoretically, the smaller the width Lw of the low-K dielectric layer 140 and the larger the thickness Hd, the better the effect of reducing the gate-drain parasitic capacitance C gd of the device. In view of this, as an implementation method, this application sets the depth of the low-K dielectric layer 140 to be equal to the depth of the oxide layer 130, that is, Hd = H0.

[0082] Among them, the PP region 200 has the functions of reducing the base region resistance and improving the breakdown characteristics of the device. In one implementation method, please refer to Figure 5, the PP region 200 extends to the first N-type epitaxial layer 120, and the bottom of the PP region 200 is deeper than the oxide layer 130. Through this setting method, the thick oxide layer 130 at the bottom of the gate polysilicon 160 can cooperate with the "pinch-off" of the depletion region of the PP region 200 and the N-type epitaxial layer to shield and protect the gate oxide layer 170, play a buffering role for the high drain-source electric field, reduce the electric stress borne by the oxide layer at the trench gate corner position, and improve the breakdown voltage and avalanche reliability of the device. And when the thickness Hd of the low-K dielectric = the thickness H0 of the thick oxide layer at the bottom of the gate polysilicon, that is, when the bottom is flat, according to Gauss's theorem, the trench gate oxide layer can further withstand the peak electric field as large as possible, greatly improving the breakdown voltage and avalanche reliability of the device.

[0083] It should be noted that the trench MOSFET device provided in this application is symmetrically arranged about the central axis of the trench region. That is, the overall structures of the PP region 200, the oxide layer 130, and the low-K dielectric layer 140 are symmetric with respect to the gate trench structure, which can balance the internal stress and thermal stress of the device materials and improve the reliability and robustness of the device.

[0084] In one implementation, please refer to Figure 6 , the gate polysilicon 160 includes a first polysilicon layer 161, a second polysilicon layer 162, and a third polysilicon layer 163 arranged layer by layer from bottom to top. Figure 6 In, Poly represents polysilicon. The doping concentration of the second polysilicon layer 162 is greater than that of the first polysilicon layer 161 and the third polysilicon layer 163. For example, both the first polysilicon layer 161 and the third polysilicon layer 163 are doped with N+, and the second polysilicon layer 162 is doped with N++. In practical applications, the production of the three-stage polysilicon layer with low-high-low can be realized by adjusting the deposition process. And, the bottom height of the second polysilicon is not lower than the bottom height of the P-type well region 180, and the top height of the second polysilicon is not higher than the top height of the P-type well region 180.

[0085] By introducing the second polysilicon layer 162 with a higher doping concentration, on the one hand, the purpose of changing the work function can be achieved, thereby enhancing the gate control ability of the device and the corresponding minority carrier inversion effect, and reducing the threshold voltage V th of the device, reducing the channel resistance R ch of the device, and then reducing the switching speed of the device and the switching loss of the device. On the other hand, it helps to make the electric field distribution in the gate oxide layer SiO2 more uniform, reduce the electric field concentration phenomenon, avoid too high electric field intensity in some local areas of SiO2, thereby reducing the risk of gate oxide breakdown and improving the reliability of the device.

[0086] Specifically, when in a high dV / dt working condition, such as the peak voltage generated by the grid voltage fluctuation and the line stray inductance at the moment of switching, through the gate-drain parasitic capacitance Cgd The coupled transient current flows through the gate resistor Rg-int, causing the gate-source voltage V GS to rise. When the gate-source voltage V GS exceeds the threshold voltage V of the device th , the device enters the mis-conduction state. Therefore, minimizing the gate-drain parasitic capacitance C gd and the gate resistor Rg-int can effectively reduce the probability of mis-conduction of the device. By introducing a second polysilicon layer with a higher doping concentration, on the one hand, the equivalent resistance Rg-int of the gate polysilicon can be reduced, thereby reducing the probability of mis-conduction of the device and improving the reliability and robustness of the device. On the other hand, according to the delay time formula t = Rg-int * C gd , reducing the equivalent resistance Rg-int of the gate polysilicon can increase the switching speed of the device and reduce the switching loss of the device. That is, in the present application, by setting the oxide layer 130, the low-K dielectric layer 140, and the second polysilicon layer 162, the gate-drain parasitic capacitance C gd and the gate resistor Rg-int can be reduced simultaneously, thereby significantly increasing the switching frequency of the device.

[0087] Regarding the parameters of the second polysilicon layer 162, the present application is set as follows:

[0088] H2 + H3 ≤ H NP +H PW ; where H2 represents the thickness of the second polysilicon layer 162, H3 represents the thickness of the third polysilicon layer 163, and H NP represents the thickness of the N-type doped region 190, and H pw represents the thickness of the P-type well region 180. And the bottom of the second polysilicon layer 162 cannot exceed the bottom of the P-type well region 180. At the same time, H3 ≥ H NP , that is, the top of the second polysilicon layer 162 cannot exceed the top of the P-type well region 180. Therefore, the entire second polysilicon layer 162 is limited to the surface of the P-type well region channel area, which is beneficial to flexibly adjusting the gate resistance Rg-int, the threshold voltage V th , the channel resistance R ch , the gate oxide breakdown and other characteristics by adjusting the sizes of H2 and H3, thereby flexibly improving the electrical properties such as the switching speed and switching loss of the device, as well as the reliability and robustness of the device.

[0089] At the same time, within the range allowed by the electrical performance and reliability of the device, the distance H1 between the second polysilicon layer 162 and the oxide layer 130 and the low-K dielectric at the bottom of the gate polysilicon 160 (the difference between the thickness of the selective epitaxial layer and the thicknesses of the P-type well region 180 and the N-type doped region 190, H epi -H NP -H PW)The larger, the better. It can reduce the internal stress of the material of the overall gate structure and the thermal stress after annealing activation, and greatly improve the reliability and robustness of the device.

[0090] On this basis, the depth of the second polysilicon layer 162 provided in this application is half of the depth of the P-type well region 180, and the top height of the second polysilicon layer 162 is flush with the top height of the P-type well region 180. This makes the thickness of the first polysilicon layer 161 the largest, which can reduce the internal stress of the material of the overall gate structure (mainly the stress between the bottom oxide layer 130 of the gate polysilicon 160 and the low-K dielectric layer 140) and the thermal stress after annealing activation to the greatest extent, and greatly improve the reliability and robustness of the device.

[0091] It should be noted that in this setting method, both the delay time t = Rg-int * C gd is minimized, and the internal stress of the material of the overall gate structure and the thermal stress after annealing activation are the lowest. Therefore, the reliability and robustness of the device can reach the best state.

[0092] As an implementation method, please refer to Figure 7 , the second polysilicon layer 162 can also be made into two parts on the left and right. That is, the second polysilicon layer 162 includes a first sub-layer 1621 and a second sub-layer 1622. The first sub-layer 1621 and the second sub-layer 1622 are arranged at intervals, and the first sub-layer 1621 is in contact with the gate oxide layer 170 on the left side of the trench region, and the second sub-layer 1622 is in contact with the gate oxide layer 170 on the right side of the trench region.

[0093] It can be understood that this application can flexibly adjust the sizes of H1, H2, and H3 to flexibly adjust the gate resistance Rg-int, the threshold voltage V th , the channel resistance R ch , the gate oxide breakdown and other characteristics. At the same time, it can also achieve the effect of adjusting the internal stress and thermal stress of the device material, and flexibly adjust and improve the electrical properties such as the switching speed and switching loss of the device, as well as the reliability and robustness of the device.

[0094] Based on the above implementation method, the embodiment of this application also provides a method for manufacturing a trench MOSFET device for manufacturing the above trench MOSFET device. The method includes:

[0095] S102, providing an N-type substrate.

[0096] S104, manufacturing a first N-type epitaxial layer on the surface of the substrate.

[0097] S106, manufacturing a first trench on the surface layer of the first N-type epitaxial layer, and manufacturing an oxide layer based on the first trench.

[0098] S108. Fabricate a second N-type epitaxial layer on the surface of the first N-type epitaxial layer. The second N-type epitaxial layer is provided with a trench region. A gate oxide layer and gate polysilicon are provided in the trench region. The gate oxide layer is located on the sidewalls of the trench region and is disposed around the gate polysilicon. The bottom of the gate polysilicon is in contact with the oxide layer. Among them, the thickness of the oxide layer is greater than that of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region. The second N-type epitaxial layer further includes a P-type well region, an N-type doped region and a PP region on the surface layer of the second N-type epitaxial layer. The N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively.

[0099] S110. Fabricate an interlayer dielectric layer on the surface of the gate polysilicon.

[0100] S112. Fabricate an ohmic contact layer on the surfaces of the PP region and the N-type doped region.

[0101] S114. Fabricate a first metal layer on the surfaces of the ohmic contact layer and the interlayer dielectric layer.

[0102] S116. Fabricate a second metal layer on the back surface of the substrate.

[0103] The trench MOSFET device provided by the present application will be described exemplarily below with reference to the accompanying drawings:

[0104] First, please refer to Figure 8 , fabricate a first N-type epitaxial layer on the surface of the substrate. Among them, N+ sub represents an N-type substrate, N- epi represents an N-type epitaxial layer, and N+ CSL1 represents an N+-type extended layer. N-type ion implantation is performed in the N-type epitaxial layer to form the N+ CSL1 layer shown in the figure. It should be noted that the first N-type epitaxial layer described in the present application includes an N- epi layer and an N+ CSL1 layer.

[0105] After that, please refer to Figure 9 , fabricate a first trench on the surface layer of the first N-type epitaxial layer, and fabricate an oxide layer based on the first trench. Among them, by adjusting the lithography and etching process parameters, the first trench can be made to have an arc-shaped structure in terms of structure, so as to buffer the drain-source high-voltage electric field, further reduce the electrical stress borne by the oxide layer at the trench gate corner position, and greatly improve the breakdown voltage and avalanche reliability of the device. And after etching the first trench, the oxide layer can be formed by a thermal oxidation process or a process of depositing SiO2 and back-etching.

[0106] Then fabricate a second N-type epitaxial layer on the surface of the first N-type epitaxial layer. S108 includes:

[0107] The second N-type epitaxial layer is grown on the surface of the first N-type epitaxial layer; wherein, a trench region is provided in the second N-type epitaxial layer, and the trench region exposes the oxide layer. Please refer to Figure 10 , N+ CSL2 represents the second N-type epitaxial layer. Since an oxide layer is provided in the middle region, when the second N-type epitaxial layer is formed, the second N-type epitaxial layer will be selectively grown on the left and right sides, and a trench region will be formed above the oxide layer.

[0108] After that, P-type well region ion implantation, N-type doped region ion implantation, PP region ion implantation and terminal region ion implantation are sequentially performed based on the second N-type epitaxial layer, and high-temperature furnace tube annealing is carried out. The structure after annealing is as Figure 11 shown. It should be noted that the ion implantation depth of the PP region can be adjusted according to actual needs. When the bottom of the PP region is deeper than the oxide layer, it can buffer the drain-source high-voltage electric field, reduce the electric stress borne by the oxide layer at the trench gate corner position, and improve the breakdown voltage and avalanche reliability of the device.

[0109] Then, the low-K dielectric layer is fabricated. First, the oxide layer is etched based on the bottom of the trench region to form a second trench, as Figure 12 shown, and then the low-K dielectric layer is filled in the second trench and etched back.

[0110] After that, the sidewall of the trench region is oxidized to form a gate oxide layer. Polysilicon deposition and etching are carried out based on the trench region to form gate polysilicon. It should be noted that when a multi-layer gate polysilicon structure needs to be fabricated, the first polysilicon layer, the second polysilicon layer and the third polysilicon layer can be formed layer by layer from bottom to top by adjusting the deposition process, and the doping concentration of the second polysilicon layer is greater than that of the first polysilicon layer and the third polysilicon layer.

[0111] Finally, the interlayer dielectric layer, ohmic contact layer, first metal layer and second metal layer are fabricated, which will not be elaborated here.

[0112] In summary, the present application provides a trench MOSFET device and a manufacturing method thereof. The trench MOSFET device includes: an N-type substrate; a first N-type epitaxial layer located on the surface of the substrate; an oxide layer located on the surface layer of the first N-type epitaxial layer, wherein a low-K dielectric layer is provided in the oxide layer; a second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, and a trench region is provided in the second N-type epitaxial layer; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; a P-type well region located in the second N-type epitaxial layer, an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; an interlayer dielectric layer located on the surface of the gate polysilicon; an ohmic contact layer located on the surface of the PP region and the N-type doped region; a first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; a second metal layer located on the back surface of the substrate. On the one hand, since a relatively thick oxide layer is provided at the bottom of the gate polysilicon, and the width of the oxide layer is greater than the width of the trench region, the peak electric field intensity at the trench corner can be effectively reduced, the gate oxide failure probability can be greatly reduced, and the gate oxide reliability and device robustness can be improved. At the same time, the thick oxide layer at the bottom of the gate polysilicon increases the equivalent thickness of the gate-drain parasitic capacitance C gd and thus reduces the gate-drain parasitic capacitance C gd , improves the Miller effect of the device, increases the switching frequency of the device, reduces the switching loss of the device, and can also prevent the problem of device mis-conduction caused under high dV / dt conditions. On the other hand, since a low-K dielectric layer is provided in the oxide layer, the effect of reducing the equivalent area and equivalent thickness of the gate-drain parasitic capacitance C gd can be achieved, and thus the gate-drain parasitic capacitance C gd of the device is further reduced, the switching frequency of the device is increased, the power loss of the device is reduced, and the problem of device mis-conduction caused by high dV / dt is further prevented.

[0113] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0114] It will be apparent to those skilled in the art that the present application is not limited to the details of the above-described exemplary embodiments, and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, in all respects, the embodiments should be regarded as exemplary and non-limiting. The scope of the present application is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present application. Any reference signs in the claims should not be construed as limiting the claims concerned.

Claims

1. A trench MOSFET device, characterized in that, The trench MOSFET device includes: An N-type substrate; A first N-type epitaxial layer located on the surface of the substrate; An oxide layer located on the surface layer of the first N-type epitaxial layer, wherein a low-K dielectric layer is provided in the oxide layer; A second N-type epitaxial layer located on the surface of the first N-type epitaxial layer, a trench region is provided in the second N-type epitaxial layer; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewall of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; A P-type well region located in the second N-type epitaxial layer, an N-type doped region and a PP region located on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are respectively in contact with the PP region and the gate oxide layer; An interlayer dielectric layer located on the surface of the gate polysilicon; An ohmic contact layer located on the surface of the PP region and the N-type doped region; A first metal layer located on the surface of the ohmic contact layer and the interlayer dielectric layer; A second metal layer located on the back surface of the substrate.

2. The trench MOSFET device according to claim 1, wherein The PP region extends to the first N-type epitaxial layer, and the bottom of the PP region is deeper than the oxide layer.

3. The trench MOSFET device as claimed in claim 1, wherein The trench MOSFET device is symmetrically arranged about the central axis of the trench region.

4. The trench MOSFET device according to claim 1, wherein The gate polysilicon includes a first polysilicon layer, a second polysilicon layer, and a third polysilicon layer arranged layer by layer from bottom to top, and the doping concentration of the second polysilicon layer is greater than the doping concentrations of the first polysilicon layer and the third polysilicon layer; The bottom height of the second polysilicon is not lower than the bottom height of the P-type well region, and the top height of the second polysilicon is not higher than the top height of the P-type well region.

5. The trench MOSFET device according to claim 4, characterized in that, The depth of the second polysilicon is half of the depth of the P-type well region, and the top height of the second polysilicon is flush with the top height of the P-type well region.

6. The trench MOSFET device according to claim 4, characterized in that, The second polysilicon layer includes a first sub-layer and a second sub-layer, the first sub-layer and the second sub-layer are arranged at intervals, and the first sub-layer is in contact with the gate oxide layer on the left side of the trench region, and the second sub-layer is in contact with the gate oxide layer on the right side of the trench region.

7. The trench MOSFET device according to claim 1, wherein, The depth of the low-K dielectric layer is equal to the depth of the oxide layer.

8. The trench MOSFET device as claimed in claim 1, wherein The oxide layer is arranged in an arc structure.

9. A manufacturing method of a trench MOSFET device, characterized in that, For fabricating the trench MOSFET device according to any one of claims 1 to 8, the method includes: Providing an N-type substrate; Fabricating a first N-type epitaxial layer based on the surface of the substrate; Fabricating a first trench based on the surface layer of the first N-type epitaxial layer, and fabricating an oxide layer based on the first trench; A second N-type epitaxial layer is fabricated on the surface of the first N-type epitaxial layer, and a trench region is provided in the second N-type epitaxial layer; a gate oxide layer and gate polysilicon are provided in the trench region, the gate oxide layer is located on the sidewalls of the trench region and surrounds the gate polysilicon, and the bottom of the gate polysilicon contacts the oxide layer; wherein, the thickness of the oxide layer is greater than the thickness of the gate oxide layer, the width of the oxide layer is greater than the width of the trench region, and the width of the low-K dielectric layer is less than the width of the trench region; the second N-type epitaxial layer further includes a P-type well region, an N-type doped region and a PP region on the surface layer of the second N-type epitaxial layer, the N-type doped region is located on the surface of the P-type well region, and both sides of the N-type doped region and the P-type well region are in contact with the PP region and the gate oxide layer respectively; An interlayer dielectric layer is fabricated on the surface of the gate polysilicon; An ohmic contact layer is fabricated on the surface of the PP region and the N-type doped region; A first metal layer is fabricated on the surface of the ohmic contact layer and the interlayer dielectric layer; A second metal layer is fabricated on the back surface of the substrate.

10. The manufacturing method of the trench MOSFET device according to claim 9, wherein, The step of fabricating the second N-type epitaxial layer on the surface of the first N-type epitaxial layer includes: Growing a second N-type epitaxial layer on the surface of the first N-type epitaxial layer; wherein, a trench region is provided in the second N-type epitaxial layer, and the oxide layer is exposed in the trench region; Performing P-type well region ion implantation, N-type doped region ion implantation, PP region ion implantation and terminal region ion implantation on the second N-type epitaxial layer in sequence, and performing high-temperature furnace tube annealing; Etching the oxide layer based on the bottom of the trench region to form a second trench; Filling the second trench with a low-K dielectric layer and back etching; Oxidizing the sidewalls of the trench region to form a gate oxide layer; Depositing and etching polysilicon based on the trench region to form a complete gate structure.

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