Two-dimensional semiconductor material in-situ oxidation high-dielectric-constant gate dielectric material and preparation method and application thereof

Abstract

The invention provides a preparation method of a two-dimensional semiconductor material in-situ oxidized high-dielectric-constant gate dielectric material, which comprises the following steps: irradiating a two-dimensional semiconductor material by ultraviolet light, decomposing oxygen in air by the ultraviolet light and oxidizing the two-dimensional semiconductor material, performing in-situ growth on the surface of the two-dimensional semiconductor material to obtain a high-dielectric-constant gate dielectric material; and carrying out rapid thermal annealing on the high-dielectric-constant gate dielectric material to obtain the compact high-dielectric-constant gate dielectric material. Wherein the two-dimensional semiconductor material is two-dimensional tantalum sulfide, the surface flatness of the two-dimensional tantalum sulfide is + / -0.5 nm, the high-dielectric-constant gate dielectric material is tantalum oxide, the dielectric constant of the tantalum oxide is 18-22, and the surface flatness of the tantalum oxide is + / -0.7 nm. The invention further provides the high-dielectric-constant gate dielectric material obtained according to the preparation method, and a transistor and a complementary metal-oxide-semiconductor phase inverter using the high-dielectric-constant gate dielectric material as the gate dielectric material.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor chip technology, and specifically relates to a high dielectric constant gate dielectric material of in-situ oxidation of a two-dimensional semiconductor material, and a preparation method and application thereof. Background Art

[0002] With the development of semiconductor technology, increasing the density of transistors in chips and reducing the size of transistors is an inevitable trend to achieve Moore's Law. However, as the size of chips has shrunk to sub-10nm levels, it is becoming increasingly difficult to scale down the size of transistors, and Moore's Law has become unsustainable due to the physical limitations of bulk materials.

[0003] Due to the physical limitations of silicon, the feature size of its process is only 5 nanometers (nm), and the lattice constant of silicon atoms is 0.54nm, which means that in nano-process chips, the feature size of transistors can only place 10 silicon atoms side by side. As the feature size is further reduced, the number will be further reduced, and problems such as heat dissipation, increased leakage current, and slowed clock frequency growth will be difficult to solve; at the same time, the short channel effect is aggravated by the shrinking transistor channel length, and there are various adverse effects such as reduced threshold voltage, carrier velocity saturation, and subthreshold characteristic degradation. These have led to a significant increase in silicon transistor leakage current and energy dissipation, making the development of the silicon-based integrated circuit industry face huge challenges.

[0004] Two-dimensional (2D) semiconductor materials have advantages such as high carrier mobility and suppression of short channel effects, and are ideal channel materials for the next generation of integrated circuit chips. The development of two-dimensional semiconductor channel materials can overcome the process limits of traditional silicon-based integrated circuits and promote the progress of semiconductor technology. Developing ultra-thin gate dielectric layer integration processes that target the characteristics of two-dimensional semiconductor materials and meet the needs of future devices to achieve low-power two-dimensional transistors is the basis for the application and development of two-dimensional semiconductor devices in microelectronics technology. For example, the semiconductor channel or dielectric gate stack in the field effect transistor (FET), the non-dangling bond surface of most two-dimensional semiconductor materials gives them the ability to be compatible with any substrate or channel semiconductor, which helps improve performance, structural diversity and simplify manufacturing. However, in the traditional semiconductor field, oxide gate dielectric materials are prepared by deposition nucleation. Since there are no dangling bonds on the surface of two-dimensional semiconductor materials, it is difficult to integrate high interface quality, uniform and flat, ultra-thin thickness high dielectric constant (κ) gate dielectric layers on their surfaces using standard atomic layer deposition processes, which makes the development of two-dimensional semiconductor transistors face the problems of high operating voltage, high power consumption and low yield.

[0005] Therefore, in order to ensure the excellent device performance of two-dimensional semiconductor transistors, designing a gate dielectric material with a high dielectric constant is of far-reaching significance. Summary of the invention

[0006] In view of this, in order to solve at least one technical problem in the related art and other aspects, the present disclosure proposes a method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material, comprising: firstly irradiating the two-dimensional semiconductor material with ultraviolet light, the ultraviolet light decomposing oxygen in the air and oxidizing the two-dimensional semiconductor material, so as to in-situ grow a high dielectric constant gate dielectric material on the surface of the two-dimensional semiconductor material; and then performing rapid thermal annealing on the high dielectric constant gate dielectric material to obtain a dense high dielectric constant gate dielectric material. Wherein, the two-dimensional semiconductor material is two-dimensional tantalum sulfide, the surface flatness of the two-dimensional tantalum sulfide is ±0.5nm, and the high dielectric constant gate dielectric material is tantalum oxide, the dielectric constant of tantalum oxide is 18-22, and the surface flatness of tantalum oxide is ±0.7nm.

[0007] According to an embodiment of the present disclosure, in irradiating the two-dimensional semiconductor material with ultraviolet light, the wavelength of the ultraviolet light is 185 nm, the irradiation temperature is room temperature, and the irradiation time is 1-30 min.

[0008] According to an embodiment of the present disclosure, in the rapid thermal annealing of the high dielectric constant gate dielectric material, the high dielectric constant gate dielectric material is heated to 250-300° C., kept warm for 10-30 minutes, and then cooled in an environment of -10-5° C.

[0009] In another aspect of the present disclosure, a high dielectric constant gate dielectric material obtained according to the above preparation method is also provided, wherein the high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of tantalum oxide is 18-22.

[0010] According to an embodiment of the present disclosure, tantalum oxide is amorphous.

[0011] In another aspect of the present disclosure, a transistor with a high dielectric constant gate dielectric is also provided, wherein the gate dielectric layer of the transistor is the aforementioned high dielectric constant gate dielectric material, or is obtained by the aforementioned preparation method.

[0012] According to an embodiment of the present disclosure, the gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

[0013] According to an embodiment of the present disclosure, the substrate of the transistor is a rigid substrate or a flexible substrate; wherein the rigid substrate is a composite material of silicon and silicon dioxide; the flexible substrate includes a polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

[0014] In another aspect of the present disclosure, a complementary metal-oxide-semiconductor inverter is also proposed, wherein the gate dielectric layer of the complementary metal-oxide-semiconductor inverter is the aforementioned high dielectric constant gate dielectric material, or is obtained by the aforementioned preparation method.

[0015] According to an embodiment of the present disclosure, the N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

[0016] According to the embodiments of the present disclosure, the method proposed in the present disclosure directly oxidizes and generates a high dielectric constant gate dielectric material (tantalum oxide) on the surface of two-dimensional tantalum sulfide by ultraviolet light irradiation, avoiding the deposition problems in traditional methods, reducing interface contamination and defects, and being conducive to maintaining the high performance and stability of two-dimensional semiconductor materials. Through rapid thermal annealing treatment, the density and crystal quality of the tantalum oxide gate dielectric layer can be further improved, pores and defects can be reduced, and dielectric properties and reliability can be improved. This high-quality gate dielectric layer with a dense and flat surface and a high dielectric constant is crucial to improving the electrical performance and long-term stability of the device. This method not only simplifies the preparation process of the gate dielectric layer of a two-dimensional semiconductor device, improves the material quality and device performance, but also has cost-effectiveness and environmental friendliness, providing a new way for the development of high-performance and highly integrated two-dimensional semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a flow chart of a method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material in an embodiment of the present disclosure;

[0018] Figure 2 is a graph showing the relationship between height and time during the ultraviolet oxidation of tantalum sulfide in Example 1 of the present disclosure;

[0019] Figure 3 is a projection electron microscope image of a high dielectric constant gate dielectric material in which the two-dimensional semiconductor material is in-situ oxidized in Example 1 of the present disclosure, wherein a is a projection electron microscope image of the overall structure, and b is a local magnified image of the interface between tantalum sulfide and tantalum oxide;

[0020] Figure 4 is an atomic force microscope comparison diagram before and after oxidation in Example 1 of the present disclosure, wherein a is an atomic force microscope diagram of a two-dimensional tantalum sulfide sheet before oxidation, and b is an atomic force microscope diagram of tantalum oxide after oxidation;

[0021] Figure 5 is a schematic diagram of the structure of a transistor prepared based on a rigid substrate in Example 3 of the present disclosure;

[0022] Figure 6 is a transfer curve performance diagram of the transistor prepared in Example 3 of the present disclosure;

[0023] Figure 7 is a schematic structural diagram of a transistor prepared based on a flexible substrate in Example 4 of the present disclosure;

[0024] Figure 8 is a transfer curve performance diagram of the transistor prepared in Example 4 of the present disclosure;

[0025] Fig. 9 is a transfer curve performance diagram of the transistor prepared in Example 4 of the present disclosure at different bending radii;

[0026] Fig.10 It is a schematic diagram of the structure of a complementary metal-oxide-semiconductor inverter (CMOS tube) prepared in Example 5 of the present disclosure;

[0027] Fig.11 It is a voltage transfer curve performance diagram of the complementary metal-oxide-semiconductor inverter prepared in Example 5 of the present disclosure. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0029] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in this disclosure.

[0030] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0031] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0032] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. If the full text involves descriptions such as "first", "second", etc., the descriptions such as "first", "second", etc. are only used to distinguish similar objects, and cannot be understood as indicating or implying their relative importance, order of precedence, or implicitly indicating the number of technical features indicated. It should be understood that the data described by "first", "second", etc. can be interchangeable under appropriate circumstances.

[0033] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. The shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual size, proportion, and actual positional relationship. In addition, in the present disclosure, any reference symbol between brackets should not be constructed as a limitation to the present disclosure.

[0034] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0035] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0036] The controlled self-oxidation of some two-dimensional semiconductor materials to prepare high-quality native oxide dielectric layers is expected to break through the bottleneck of the difficulty in depositing ultra-thin high-quality oxides in the existing common process, and promote the development of two-dimensional semiconductor materials in the field of large-scale device arrays and integrated circuits. Compared with relatively inert semiconductors such as MoS2, MoSe2 and WSe2, metals such as TaS2 are prone to surface oxidation in ambient environments. Tantalum oxide (Ta2O5) has a high dielectric constant (κ), which is an important advantage as a high-quality gate dielectric.

[0037] In the process of the present disclosure, it is found that the dielectric constant of Ta2O5 formed after the oxidation of two-dimensional tantalum sulfide can effectively adjust the electric field and enhance the capacitance effect, thereby optimizing the performance of the transistor. In contrast, other two-dimensional sulfide materials may not be able to obtain a sufficiently high dielectric constant after oxidation. For example, the dielectric constant of the product after oxidation of some sulfides is low, and under the action of the gate electric field, the carrier concentration in the channel cannot be effectively controlled, resulting in a decrease in the switching performance and current control ability of the transistor. The band structure of tantalum oxide (Ta2O5) is conducive to achieving good electrical properties. It can form a suitable band alignment and reduce the interface state density when in contact with the semiconductor channel material. This means that during the operation of the transistor, the transmission of charge at the gate-channel interface is smoother, reducing undesirable phenomena such as charge scattering at the interface. At the same time, tantalum oxide (Ta2O5) exhibits good chemical stability and oxidation resistance. In the complex working environment and long-term use of semiconductor devices, it can resist the erosion of chemical substances and further redox reactions.

[0038] Figure 1 It is a flow chart of the method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material in an embodiment of the present disclosure.

[0039] The present disclosure proposes a method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material, such as Figure 1 As shown, it includes: firstly irradiating the two-dimensional semiconductor material with ultraviolet light, the ultraviolet light decomposes oxygen in the air and oxidizes the two-dimensional semiconductor material, so as to in-situ grow a high dielectric constant gate dielectric material on the surface of the two-dimensional semiconductor material; further, performing rapid thermal annealing on the high dielectric constant gate dielectric material to obtain a dense high dielectric constant gate dielectric material. Wherein, the two-dimensional semiconductor material is two-dimensional tantalum sulfide, the surface flatness of the two-dimensional tantalum sulfide is ±0.5nm, and the high dielectric constant gate dielectric material is tantalum oxide, the dielectric constant of tantalum oxide is 18-22, and the surface flatness of tantalum oxide is ±0.7nm.

[0040] According to the embodiments of the present disclosure, the method proposed in the present disclosure directly oxidizes and generates a high dielectric constant gate dielectric material (tantalum oxide) on the surface of two-dimensional tantalum sulfide by ultraviolet light irradiation, avoiding the deposition problems in traditional methods, reducing interface contamination and defects, and being conducive to maintaining the high performance and stability of two-dimensional semiconductor materials. Through rapid thermal annealing treatment, the density and crystal quality of the tantalum oxide gate dielectric layer can be further improved, pores and defects can be reduced, and dielectric properties and reliability can be improved. This high-quality gate dielectric layer with a dense and flat surface and a high dielectric constant is crucial to improving the electrical performance and long-term stability of the device. This method not only simplifies the preparation process of the gate dielectric layer of a two-dimensional semiconductor device, improves the material quality and device performance, but also has cost-effectiveness and environmental friendliness, providing a new way for the development of high-performance and highly integrated two-dimensional semiconductor devices.

[0041] Specifically, the method proposed in the present invention requires that the initial surface flatness of the two-dimensional tantalum sulfide reaches ±0.5nm, which provides a good growth foundation. After oxidation and annealing, the surface flatness of the tantalum oxide gate dielectric layer can still be maintained at ±0.7nm, ensuring the density and flatness of the tantalum oxide gate dielectric layer material, which is crucial for ensuring the uniformity of subsequent processes such as gate metal deposition and the consistency of device performance.

[0042] Specifically, the tantalum oxide gate dielectric material obtained by the preparation method proposed in the present disclosure has a dielectric constant of 18-22, which is higher than that of traditional gate dielectric materials (for example, the dielectric constant of traditional tantalum oxide is about 15, and the dielectric constant of traditional silicon dioxide is about 3.9), which helps to reduce the physical size of the gate capacitor and improve the integration, while reducing the gate leakage current and improving the energy efficiency of the device.

[0043] In some specific embodiments, after the rapid thermal annealing, a nitrogen gun may be used to dry the moisture condensed on the surface of the tantalum oxide to obtain a dry tantalum oxide material for subsequent testing and process treatment.

[0044] According to an embodiment of the present disclosure, when irradiating a two-dimensional semiconductor material with ultraviolet light, the wavelength of the ultraviolet light is 185 nm, the irradiation temperature is room temperature, and the irradiation time is 1-30 min, for example, it can be 1 min, 5 min, 10 min, 15 min, 20 min, 25 min, 30 min, etc.

[0045] According to the embodiments of the present disclosure, ultraviolet light has high energy and can effectively decompose oxygen in the air to generate active oxygen atoms, oxygen free radicals and ozone. These active oxygen species can react with two-dimensional semiconductor materials (two-dimensional tantalum sulfide) to achieve in-situ oxidation. At the same time, ultraviolet light with a wavelength of 185nm can provide sufficient energy to drive the oxidation reaction on the one hand, and avoid material damage that may be caused by excessive energy on the other hand. The irradiation time of ultraviolet light can be adjusted according to actual needs to control the thickness and properties of the generated tantalum oxide. This flexibility makes the preparation process more controllable and can adapt to different application requirements. Specifically, short-term irradiation (for example, less than 10min) can quickly form a thin layer of oxide film, which is suitable for scenes requiring a smaller oxide layer thickness. Longer irradiation can form a thicker oxide layer, or control the degree of ultraviolet oxidation, which is suitable for scenes requiring a higher dielectric constant, or devices with higher requirements for the thickness of the oxide layer. Ultraviolet oxidation operation at room temperature does not require heating, avoids material damage that may be caused by ultraviolet light at high temperatures, improves the quality of the oxide layer and the performance of the device, saves energy, and improves production efficiency.

[0046] According to an embodiment of the present disclosure, in the rapid thermal annealing of the high dielectric constant gate dielectric material, the high dielectric constant gate dielectric material is heated to 250-300°C, for example, 250°C, 260°C, 270°C, 280°C, 290°C, 300°C, etc., and kept warm for 10-30 minutes, for example, 10 minutes, 15 minutes, 20 minutes, 25 minutes, 30 minutes, etc., and then placed in a -10-5°C environment for cooling, for example, -10°C, -5°C, 0°C, 5°C, etc.

[0047] According to the embodiments of the present disclosure, rapid thermal annealing treatment helps to eliminate the pores and defects in the in-situ generated tantalum oxide material, making the high dielectric constant gate dielectric material (tantalum oxide) more dense. The dense structure can reduce charge traps, improve the electrical properties of tantalum oxide, optimize the dielectric constant and leakage characteristics, and make it more suitable for gate dielectric applications. Specifically, within this temperature range, the atomic migration and structural reorganization in tantalum oxide can be effectively promoted, but it will not be too high to cause decomposition or damage to tantalum oxide. Keeping the temperature at high temperature for a sufficient time can release the stress inside the tantalum oxide and repair the defects. Rapid cooling can fix the lattice structure formed during the annealing process, reduce grain growth, and maintain the fine grain structure of the material. The rapid thermal annealing process increases the density of tantalum oxide, reduces the interface state density, and optimizes the dielectric properties.

[0048] In another aspect of the present disclosure, a high dielectric constant gate dielectric material obtained according to the above preparation method is also provided, wherein the high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of tantalum oxide is 18-22.

[0049] According to the embodiments of the present disclosure, the high dielectric constant transistor device prepared based on the aforementioned method has excellent electrical properties, such as lower off-state current, lower gate leakage current, higher switching ratio, subthreshold swing close to the room temperature limit, and is effectively immune to short channel effects, thereby improving the stability and reliability of transistor performance.

[0050] According to an embodiment of the present disclosure, tantalum oxide is amorphous.

[0051] According to the embodiments of the present disclosure, amorphous tantalum oxide does not have a long-range ordered structure and is therefore uniform at the microscopic level. This means that the electrical properties of the tantalum oxide gate dielectric layer are uniform at the macroscopic scale, which helps to reduce fluctuations in device performance. Compared with polycrystalline materials, amorphous tantalum oxide has no grain boundaries, which may lead to increased charge traps and leakage current. Therefore, amorphous tantalum oxide can reduce these defects and improve the reliability, stability, and carrier mobility of the device.

[0052] In another aspect of the present disclosure, a transistor with a high dielectric constant gate dielectric is also provided, wherein the gate dielectric layer of the transistor is the aforementioned high dielectric constant gate dielectric material, or is obtained by the aforementioned preparation method.

[0053] According to the embodiments of the present disclosure, transistor devices based on high dielectric constant gate dielectric materials prepared by the aforementioned method have excellent electrical properties, such as lower off-state current, lower gate leakage current, higher switching ratio, and subthreshold swing close to the room temperature limit, and are effectively immune to short channel effects, thereby improving transistor performance stability and reliability.

[0054] According to an embodiment of the present disclosure, the gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

[0055] According to the embodiments of the present disclosure, the high dielectric constant gate dielectric layer of tantalum oxide can effectively reduce the leakage current of the transistor, improve the switching ratio, and thus improve the energy efficiency of the transistor. And because the dielectric constant of tantalum oxide is relatively high, a thinner physical gate dielectric layer can be achieved while maintaining the same capacitance, which helps to improve the operating speed and integration of the transistor. The high conductivity characteristics of graphene can reduce the gate resistance and improve the overall performance of the transistor when used as an electrode. The atomic-level thickness of molybdenum disulfide helps to achieve ultra-thin transistors and reduce the power consumption of the device. This transistor has broad application prospects in the field of future electronic devices, especially in flexible electronics and high-speed, low-power applications.

[0056] According to an embodiment of the present disclosure, the substrate of the transistor is a rigid substrate or a flexible substrate; wherein the rigid substrate is a composite material of silicon and silicon dioxide; the flexible substrate includes a polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

[0057] According to the embodiments of the present disclosure, the transistor structure proposed in the present disclosure has broad application prospects in the field of future electronic devices, especially in high-speed and low-power applications. Specifically, the rigid substrate provides good mechanical support to ensure the stability of the transistor during operation and use; the flexible substrate allows the transistor to be bent, which is suitable for applications such as wearable devices, flexible electronic skin, and flexible displays, and the gate dielectric material obtained by the ultraviolet oxidation method can adapt to complex curved surface environments. The device can work in different bending states with a bending radius of 5-20 mm, adapting to different application scenarios and design requirements.

[0058] In another aspect of the present disclosure, a complementary metal-oxide-semiconductor inverter (CMOS transistor) is also proposed, wherein the gate dielectric layer of the complementary metal-oxide-semiconductor inverter is the aforementioned high dielectric constant gate dielectric material, or is obtained by the aforementioned preparation method.

[0059] According to an embodiment of the present disclosure, the N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

[0060] According to the embodiments of the present disclosure, the high dielectric constant gate dielectric layer can reduce the subthreshold swing of the transistor on the one hand, thereby improving the switching characteristics of the inverter and reducing power loss. On the other hand, it can also provide a stronger electric field, thereby improving the driving capability of the transistor and enhancing the performance of the inverter. Molybdenum disulfide, as a two-dimensional semiconductor material, has high mobility and good electrical properties. At the same time, tungsten diselenide and molybdenum disulfide have good complementarity and can form an efficient CMOS structure. Tungsten diselenide, as a P-type channel material, provides stable electrical properties and helps to improve the reliability of the inverter. Furthermore, although the CMOS tube proposed in the present disclosure uses a new type of high dielectric constant material, the overall process is compatible with the traditional CMOS process, which is convenient for integration and large-scale production, and the atomic-level thickness of the two-dimensional semiconductor material provides the possibility for further reduction of the device, which helps to achieve a higher level of integration.

[0061] It should be noted that the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by ordinary technicians in the field without creative work are all within the scope of protection of the present disclosure.

[0062] In the preparation and testing of the following specific examples, the images of the height changes of the two-dimensional tantalum sulfide samples due to oxidation time were measured by Bruker's Dimension ICON atomic force microscope (AFM) in tapping mode. The high-definition images of the tantalum disulfide surface before and after oxidation were taken using a spherical aberration-corrected field emission transmission electron microscope (Themis Z) from Thermo Fisher Scientific, USA. The optical images of the devices were collected by an RX50M microscope. All electrical measurements and were performed at 10 -3 The measurements were performed using a Keithley 4200A-SCS semiconductor parameter analyzer under torr vacuum conditions.

[0063] Example 1

[0064] TaS2 flakes are selected and mechanical exfoliation operations are performed on a clean SiO2 / Si substrate to obtain two-dimensional TaS2 flakes, and the integrity and uniformity of the two-dimensional TaS2 flakes are ensured.

[0065] The peeled two-dimensional TaS2 flakes were placed in an ultraviolet ozone (UV-O3) cleaner, and the cleaner was turned on so that its low-pressure mercury lamp emitted ultraviolet light with a wavelength of 185nm. During the ultraviolet irradiation process, the ultraviolet light decomposed the O2 in the atmosphere to produce atomic oxygen and ozone, which oxidized the two-dimensional TaS2 flakes. During the oxidation process, the ambient temperature was kept constant at 25°C.

[0066] The samples were taken out every 5 minutes, and the thickness change of the samples was measured using an atomic force microscope (AFM). The data was recorded and an error graph of the thickness change versus oxidation time was plotted.

[0067] Figure 2 This is a graph showing the relationship between height and time during the ultraviolet oxidation process of tantalum sulfide in Example 1 of the present disclosure.

[0068] like Figure 2 As shown in the figure, the thickness of the TaS2 flakes changes with the irradiation of ultraviolet light. The reason for the change is that the electrons in the two-dimensional TaS2 flakes are transformed into higher energy states under the excitation of ultraviolet light. These high-energy electrons can interact with sulfur atoms or tantalum atoms in tantalum sulfide, resulting in the breaking of chemical bonds. In addition to exciting the electrons in the two-dimensional TaS2 flakes, ultraviolet light can also decompose oxygen molecules (O2) in the air to generate oxygen atoms (O) or oxygen free radicals (·O) or ozone (O3). These highly active oxygen species act as strong oxidants and react with tantalum sulfide to form tantalum oxide. With the continuous adsorption of oxygen atoms and the release of sulfur atoms, the structure of tantalum sulfide gradually changes to that of tantalum oxide. In this process, the coordination number and oxidation state of tantalum atoms change, thus forming a stable tantalum oxide layer.

[0069] More specifically, according to the rule that the oxidation rate is almost constant in the first 20 minutes and then decreases with increasing oxide thickness, the oxidation time can be controlled to obtain Ta2O5 material of target thickness and quality.

[0070] After the oxidation is completed, after 30 minutes of UV oxidation, the material is placed on a hot table heated to 300°C for 15-30 minutes, and then quickly placed on a prepared -10°C iron table for thermal annealing.

[0071] The materials were characterized by transmission electron microscopy to confirm the completion of the chemical transformation.

[0072] Figure 3 It is a projection electron microscope image of the high dielectric constant gate dielectric material of the in-situ oxidation of the two-dimensional semiconductor material in Example 1 of the present disclosure, wherein a is a projection electron microscope image of the overall structure, and b is a local enlarged image of the interface between tantalum sulfide and tantalum oxide.

[0073] like Figure 3 As shown in a, the two-dimensional semiconductor material has a clear layered structure, marked as Ta2O5, TaS2 and SiO2 from top to bottom, verifying the existence of tantalum oxide and confirming the chemical conversion of TaS2 to Ta2O5. The thickness of the entire structure is about 100 nanometers. Figure 3 As shown in (b), in the detailed view at a smaller scale (10nm), the fine structure and uniformity of the interface between the two layers of Ta2O5 and TaS2 exist. It can also be seen that Ta2O5 has a relatively low density and an amorphous structure.

[0074] Figure 4 3 is an atomic force microscope comparison image before and after oxidation in Example 1 of the present disclosure, wherein a is an atomic force microscope image of a two-dimensional tantalum sulfide sheet before oxidation, and b is an atomic force microscope image of tantalum oxide after oxidation.

[0075] like Figure 4 As shown, the root mean square roughness of the TaS2 sample before oxidation is 0.20 nanometers, and the root mean square roughness of the surface Ta2O5 after oxidation for 30 minutes is 0.55 nanometers, showing good flatness and uniformity.

[0076] Example 2

[0077] In this embodiment 2, the tantalum oxide prepared in embodiment 1 is used as the gate dielectric material of the transistor, and a transistor with a high dielectric constant gate dielectric is prepared based on a rigid substrate. The specific preparation method is as follows.

[0078] On the Si / SiO2 substrate, a 5-nanometer chromium metal (Gr) adhesion layer and a 20-nanometer gold (Au) layer are sequentially deposited using processes such as electron beam evaporation to form a bottom electrode.

[0079] Using dry transfer technology, the pre-prepared two-dimensional TaS2 flakes are precisely placed on the bottom electrode, and then placed in the UV-O3 cleaner again for oxidation reaction, so that the two-dimensional TaS2 flakes are converted into Ta2O5 to form a Ta2O5 gate dielectric layer.

[0080] On top of the Ta2O5 gate dielectric layer, 10 nanometers of Gr and 20 nanometers of Au are deposited by processes such as electron beam evaporation to make multiple top electrodes, thus completing the fabrication of the parallel plate capacitor device.

[0081] Using a capacitance-voltage (CV) measurement system, different frequencies of 1 MHz and 0.5 MHz, and a DC bias from -5.0 V to 5.0 V were applied to the capacitor, and the functional relationship between the capacitance and the applied DC bias voltage (CV) was measured. The background capacitance interference was eliminated by plotting the functional relationship between the total capacitance and the area, and the relative dielectric constant of Ta2O5 was calculated and its stability was verified.

[0082] After testing and calculation, the dielectric constant of the tantalum oxide material obtained by the method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material proposed in the present invention is 15-22. Specifically, by adjusting the oxidation time, the dielectric constant can reach 18-22, which is much higher than that of traditional dielectric materials.

[0083] Example 3

[0084] In this embodiment 3, high dielectric constant (HKMG) field effect transistors (FETs) are prepared using Ta2O5 with a high dielectric constant as a dielectric layer, multilayer graphene as a gate, and molybdenum disulfide (MoS2) as a channel.

[0085] Figure 5 It is a schematic diagram of the structure of the transistor prepared based on the rigid substrate in Example 3 of the present disclosure.

[0086] After completing the steps of preparing Ta2O5 as in Example 1, the multilayer graphene is transferred to the top of the Ta2O5 layer as a gate, and then a MoS2 channel is prepared, and the channel length is controlled to be about 8.8 μm. Finally, the electrodes are connected by metal wires to complete the Figure 5 The transistor device shown is prepared. The transfer characteristics, output curve and other electrical performance parameters of the device are measured at room temperature when the drain-source voltage (Vds) is 500 mV using a semiconductor parameter analyzer and other equipment.

[0087] Figure 6 It is a transfer curve performance diagram of the transistor prepared in Example 3 of the present disclosure.

[0088] like Figure 6As shown in Figure 2, the device exhibits typical n-type characteristics, with an on / off ratio of the channel current as high as 1.2×10 8 , gate leakage current (Ig) as low as 10 -15 A level, very low gate leakage and low hysteresis, indicating that the generated Ta2O5 is highly uniform, and the subthreshold swing is close to the room temperature limit (61.2mV / dec). When Vg is greater than the threshold voltage, Id increases rapidly and tends to be stable in the saturation region, indicating that the transistor has good switching characteristics.

[0089] Example 4

[0090] Figure 7 It is a schematic diagram of the structure of a transistor prepared based on a flexible substrate in Example 4 of the present disclosure.

[0091] A polyester (PET) with a thickness of 130 μm was used as a flexible substrate, and a bottom electrode, a Ta2O5 gate dielectric layer, a top electrode, and a MoS2 channel structure were prepared on its surface using a process similar to that of Example 3 to obtain the following: Figure 7 Flexible HKMG field effect transistor with the structure shown.

[0092] Using semiconductor parameter analyzers and other equipment, the electrical properties of the flexible HKMG field effect transistor, including transfer characteristics, gate leakage current and other parameters, are measured at different bending curvature radii. The data is recorded and analyzed to study its stability under static tensile strain.

[0093] Figure 8 It is a transfer curve performance diagram of the transistor prepared in Example 4 of the present disclosure.

[0094] like Figure 8 As shown in Figure 2, the HKMG field effect transistor on the flexible substrate exhibits good electrical performance at different source-drain voltages (Vds), with an on / off ratio close to 10. 6 , with a counterclockwise hysteresis loop and a gate leakage current of less than 1pA.

[0095] Furthermore, in this Example 4, the transfer characteristics of the flexible HKMG field effect transistor at different bending radii are also verified.

[0096] Fig. 9 It is a transfer curve performance diagram of the transistor prepared in Example 4 of the present disclosure at different bending radii.

[0097] like Fig. 9As shown in the figure, its bending radius (Rb) changes from 14.8 mm to 6.1 mm. When the bending radius is as low as 6.1 mm, it can still maintain good performance and the subthreshold swing changes slightly. Specifically, the curve is relatively flat when the bending radius is 14.8 mm, and the turn-on voltage is slightly higher; the curve is steep when the bending radius is 10.5 mm, and the turn-on voltage is low; the curve is the steepest when the bending radius is 6.1 mm, and the turn-on voltage is the lowest.

[0098] The performance of the transistor based on the flexible substrate prepared in Example 4 at different bending radii shows its flexibility and adjustability, making it an important element in the field of electronic engineering. By adjusting the bending radius, the performance of the transistor can be optimized to adapt to different application scenarios.

[0099] Example 5

[0100] FET devices with molybdenum disulfide as N-type channel and tungsten diselenide as P-type channel were prepared respectively, wherein the gate dielectrics were Ta2O5 generated by UV oxidation. The specific preparation process was similar to the preparation of the corresponding channel transistor in the HKMG transistor device in Example 3.

[0101] Fig.10 It is a schematic diagram of the structure of the complementary metal-oxide-semiconductor inverter (CMOS tube) prepared in Example 5 of the present disclosure.

[0102] The prepared molybdenum disulfide transistor and tungsten diselenide transistor are connected in series to construct Fig.10 The CMOS inverter shown in the figure. Using a semiconductor parameter analyzer and other equipment, the corresponding transfer characteristic curve is measured under the conditions of drain-source voltage (Vds) of 0.5V, 1.0V, 2.0V, etc., the transistor polarity interval is determined, and the output characteristics are measured. Then, the voltage transfer curve of the inverter is measured under different power supply voltages (Vdd), that is, the relationship between the input voltage (Vin) and the output voltage (Vout), and the performance parameters such as the voltage gain of the inverter are obtained.

[0103] Fig.11 It is a voltage transfer curve performance diagram of the complementary metal-oxide-semiconductor inverter prepared in Example 5 of the present disclosure.

[0104] like Fig.11 As shown, the inverter has good performance and a steep voltage transition region. Even when the power supply voltage is as low as 0.75V, signal inversion can still be clearly observed at low input voltage and high output voltage. A voltage gain of up to 26.15V / V can be achieved at 2.0V Vdd.

[0105] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a high dielectric constant gate dielectric material by in-situ oxidation of a two-dimensional semiconductor material, characterized in that: The preparation method comprises: Irradiating the two-dimensional semiconductor material with ultraviolet light, wherein the ultraviolet light decomposes oxygen in the air and oxidizes the two-dimensional semiconductor material, so as to in-situ grow a high dielectric constant gate dielectric material on the surface of the two-dimensional semiconductor material; Performing rapid thermal annealing on the high dielectric constant gate dielectric material to obtain a dense high dielectric constant gate dielectric material; Among them, the two-dimensional semiconductor material is two-dimensional tantalum sulfide, and the surface flatness of the two-dimensional tantalum sulfide is ±0.5nm. The high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of the tantalum oxide is 18-22, and the surface flatness of the tantalum oxide is ±0.7nm.

2. The preparation method according to claim 1, wherein In the irradiation of the two-dimensional semiconductor material by ultraviolet light, the wavelength of the ultraviolet light is 185 nm, the irradiation temperature is room temperature, and the irradiation time is 1-30 min.

3. The preparation method according to claim 1, wherein In the rapid thermal annealing of the high dielectric constant gate dielectric material, the high dielectric constant gate dielectric material is heated to 250-300° C., kept warm for 10-30 minutes, and then placed in a -10-5° C. environment for cooling.

4. A high dielectric constant gate dielectric material obtained by the preparation method according to any one of claims 1 to 3, characterized in that: The high dielectric constant gate dielectric material is tantalum oxide, and the dielectric constant of the tantalum oxide is 18-22.

5. The high dielectric constant gate dielectric material according to claim 4, wherein: The tantalum oxide is amorphous.

6. A transistor having a high dielectric constant gate dielectric, characterized in that: The gate dielectric layer of the transistor is a high dielectric constant gate dielectric material as claimed in claim 4 or 5, or is obtained by the preparation method as claimed in any one of claims 1 to 3.

7. The transistor according to claim 6, wherein: The gate of the transistor is graphene, and the channel layer of the transistor is molybdenum disulfide.

8. The transistor according to claim 6, wherein The substrate of the transistor is a rigid substrate or a flexible substrate; wherein, The rigid substrate is a composite material of silicon and silicon dioxide; The flexible substrate comprises polyester polymer material, and the bending radius of the flexible substrate is 5-20 mm.

9. A complementary metal-oxide-semiconductor inverter, characterized in that: The gate dielectric layer of the complementary metal-oxide-semiconductor inverter is a high dielectric constant gate dielectric material as claimed in claim 4 or 5, or is obtained by the preparation method as claimed in any one of claims 1 to 3.

10. The complementary metal-oxide-semiconductor inverter according to claim 9, wherein: The N-type channel material of the complementary metal-oxide-semiconductor inverter is molybdenum disulfide, and the P-type channel material of the complementary metal-oxide-semiconductor inverter is tungsten diselenide.

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