Preparation method of stacked transistor, stacked transistor and semiconductor device

Abstract

The invention provides a preparation method of a stacked transistor, the stacked transistor and a semiconductor device. The method comprises the following steps: removing the second pseudo gate structure to expose the second active structure and the gate isolation layer; coating photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and at least removing the gate isolation layer in the second semiconductor unit through a photoetching process; sequentially removing the first pseudo gate structure and the photoresist to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit and the first active structure and the second active structure in the second semiconductor unit; and forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and in particular to a method for preparing a stacked transistor, a stacked transistor and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] In some schemes for preparing stacked transistors, active regions of upper and lower layers of transistors of the same source are formed by etching, and stacked transistors are made on the front and back sides of the wafer by flipping the wafer. This can also be called a "self-aligned flip transistor" scheme. However, in the "self-aligned flip transistor" scheme, the stacked transistors formed by the same wafer can only be unified as a split-gate structure or a common-gate structure, which limits the design flexibility on the one hand and the further miniaturization of the circuit size on the other. Summary of the invention

[0004] The present application provides a method for preparing a stacked transistor, a stacked transistor and a semiconductor device, so as to optimize the preparation process of the gate structure in the "self-aligned flip-chip transistor" scheme, and realize the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure, so as to increase the flexibility of circuit design and enable the size of the circuit standard unit and the size of the circuit as a whole to be further miniaturized.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor, comprising: the stacked transistor comprises a first semiconductor unit and a second semiconductor unit, the first semiconductor unit and the second semiconductor unit are arranged adjacent to each other in a first direction; the first semiconductor unit and the second semiconductor unit both comprise: a first active structure and a second active structure stacked along a second direction, a first dummy gate structure corresponding to the first active structure, a first source-drain structure corresponding to the first active structure, a second dummy gate structure corresponding to the second active structure, and a second source-drain structure corresponding to the second active structure; wherein a gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure; wherein the method comprises: removing the second dummy gate structure to expose the second active structure and the gate isolation layer; coating a photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and removing at least the gate isolation layer in the second semiconductor unit through a photolithography process; removing the first dummy gate structure and the photoresist in sequence to expose the first active structure and the gate isolation layer in the first semiconductor unit; layer and a second active structure, and a first active structure and a second active structure in the second semiconductor unit; based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and based on the first active structure and the second active structure in the second semiconductor unit at the same time, a third gate structure and a fourth gate structure are formed; wherein the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure constitute a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure constitute a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure constitute a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure constitute a fourth transistor; the first transistor and the second transistor constitute a first stacked transistor, and the third transistor and the fourth transistor constitute a second stacked transistor.

[0006] In some embodiments, a first gate structure and a second gate structure are formed based on the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and a third gate structure and a fourth gate structure are formed based on the first active structure and the second active structure in the second semiconductor unit at the same time, including: depositing a dielectric material on the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit to form a gate dielectric layer; forming a second gate structure and a fourth gate structure respectively based on the second active structure covered with the gate dielectric layer; forming a first gate structure and a third gate structure respectively based on the first active structure covered with the gate dielectric layer.

[0007] In some embodiments, the stacked transistor also includes: a first carrier wafer; the first semiconductor unit and the second semiconductor unit also include: a first interlayer dielectric layer wrapping the first source and drain structure; the first interlayer dielectric layer is connected to the first carrier wafer; wherein, based on the second active structure covered with the gate dielectric layer, a second gate structure and a fourth gate structure are respectively formed, including: depositing semiconductor material on the first carrier wafer to form a gate filling structure, wherein the gate filling structure wraps the first active structure in the first semiconductor unit, and the second active structure and the gate isolation layer in the first semiconductor unit are exposed outside the gate filling structure; the gate filling structure wraps the first active structure in the second semiconductor unit, and the second active structure in the second semiconductor unit is exposed outside the gate filling structure; depositing gate metal material on the gate isolation layer in the first semiconductor unit and the initial gate filling structure in the second semiconductor unit to form a second gate structure and a fourth gate structure, respectively, wherein the second gate structure is connected to the gate isolation layer in the first semiconductor unit.

[0008] In some embodiments, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method further includes: forming a back source and drain metal on the second source and drain structure; forming a back metal interconnection layer on the second gate structure, the fourth gate structure and the back source and drain metal; bonding the back metal interconnection layer to a second carrier wafer; and inverting and removing the first carrier wafer to expose the gate filling structure.

[0009] In some embodiments, the first semiconductor unit and the second semiconductor unit also include: a second interlayer dielectric layer wrapping the second source and drain structure; wherein, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method includes: forming a second carrier wafer on the second gate structure, the fourth gate structure and the second interlayer dielectric layer; flipping and removing the first carrier wafer to expose the gate filling structure.

[0010] In some embodiments, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method further includes: using a fin cutting process to etch the second gate structure and the fourth gate structure to form a back isolation groove, wherein the back isolation groove is at least located between the second gate structure and the fourth gate structure; and depositing an insulating material in the back isolation groove to form a back gate isolation structure.

[0011] In some embodiments, based on a first active structure covered with a gate dielectric layer, a first gate structure and a third gate structure are formed respectively, including: removing the gate filling structure to expose the gate isolation layer and the fourth gate structure in the first semiconductor unit respectively; depositing a gate metal material on the exposed gate isolation layer and the fourth gate structure in the first semiconductor unit to form the first gate structure and the third gate structure respectively, wherein the first gate structure is connected to the gate isolation layer in the first semiconductor unit.

[0012] In some embodiments, after forming a first gate structure and a third gate structure respectively based on a first active structure covered with a gate dielectric layer, the method further includes: forming a front source and drain metal on the first source and drain structure; and forming a front metal interconnection layer on the first gate structure, the third gate structure and the front source and drain metal.

[0013] In some embodiments, when a back metal interconnection layer is not formed, after forming a front metal interconnection layer, the method further includes: bonding the front metal interconnection layer and a third carrier wafer; flipping and removing the second carrier wafer to expose the second gate structure, the fourth gate structure and the second interlayer dielectric layer; forming a back source and drain metal on the second source and drain structure; and forming a back metal interconnection layer on the second gate structure, the fourth gate structure and the back source and drain metal.

[0014] In some embodiments, after forming a first gate structure and a third gate structure respectively based on a first active structure covered with a gate dielectric layer, the method further includes: using a fin cutting process to etch the first gate structure and the third gate structure to form a front isolation groove, wherein the front isolation groove is at least located between the first gate structure and the third gate structure; depositing an insulating material in the front isolation groove to form a front gate isolation structure.

[0015] In some embodiments, the first semiconductor unit and the second semiconductor unit also include: a blocking layer, wherein the blocking layer is located on a side of the second active structure away from the first active structure; removing at least the gate isolation layer in the second semiconductor unit through a photolithography process, including: using the blocking layer as a mask, removing the gate isolation layer in the second semiconductor unit through an anisotropic etching process; removing the first part of the first dummy gate structure in the second semiconductor unit through an anisotropic etching process or an isotropic etching process, wherein the first part corresponds to the gate isolation layer in the second semiconductor unit; removing the first dummy gate structure and the photoresist in sequence, including: removing the second part of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit through an isotropic etching process, wherein the second part and the first part constitute the first dummy gate structure in the second semiconductor unit; removing the photoresist.

[0016] In some embodiments, before removing the second dummy gate structure to expose the second source-drain structure and the gate isolation layer, the method further includes: forming a first semiconductor unit and a second semiconductor unit.

[0017] In some embodiments, forming a first semiconductor unit and a second semiconductor unit includes: forming a first active structure and a second active structure on a semiconductor substrate, wherein the second active structure is closer to the semiconductor substrate than the first active structure; sequentially forming a second dummy gate structure, a gate isolation layer and a first dummy gate structure on the semiconductor substrate; sequentially forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; forming a first carrier wafer on the first dummy gate structure and the first interlayer dielectric layer; flipping the wafer and removing the semiconductor substrate; and sequentially forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure.

[0018] In some embodiments, each of the first transistor, the second transistor, the third transistor, and the fourth transistor is any one of a fin field effect transistor, a gate-all-around field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a forkplate transistor, and a planar field effect transistor.

[0019] In a second aspect, an embodiment of the present application provides a stacked transistor, comprising: a first stacked transistor and a second stacked transistor arranged adjacent to each other in a first direction; wherein the first stacked transistor comprises: a first transistor and a second transistor arranged back to back along a second direction; a gate isolation layer is formed between the first gate structure of the first transistor and the second gate structure of the second transistor, and the gate isolation layer is used to electrically isolate the first gate structure and the second gate structure; the second stacked transistor comprises: a third transistor and a fourth transistor arranged back to back along the second direction; the third gate structure of the third transistor and the fourth gate structure of the fourth transistor are connected.

[0020] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a stacked transistor as described in the above embodiment.

[0021] In an embodiment of the present application, by retaining the gate isolation layer in the first semiconductor unit, the first gate structure and the second gate structure in the first stacked transistor formed subsequently can be separated by the gate isolation layer, thereby forming a split-gate structure. By removing the gate isolation layer in the second semiconductor unit, the third gate structure and the fourth gate structure in the second stacked transistor formed subsequently are connected to form a common-gate structure. Furthermore, the first semiconductor unit and the second semiconductor unit are adjacently arranged in the first direction, which can meet the requirements of the circuit standard logic unit. It can be seen that the embodiment of the present application simultaneously prepares a stacked transistor with a split-gate structure and a stacked transistor with a common-gate structure, which not only increases the flexibility of the circuit design, but also allows the size of the circuit standard unit and the size of the circuit as a whole to be further miniaturized.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0024] Figure 1 A schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application;

[0025] Figure 2 is a top view of a stacked transistor according to an embodiment of the present application;

[0026] Figures 3 to 38 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application;

[0027] Figure 39 to Figure 40 It is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application.

[0028] Figures 10, stacked transistor; 101, first stacked transistor; 102, second stacked transistor; 11, first transistor; 12, second transistor; 13, third transistor; 14, fourth transistor; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, front metal interconnect layer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, back metal interconnect layer; 134, third gate structure; 144, fourth gate structure;

[0029] 20. semiconductor substrate; 21. initial stacking structure; 22. initial barrier layer; 23. stacking structure; 24. barrier layer; 25. shallow trench isolation structure; 26. first pseudo-gate structure; 27. gate isolation layer; 28. second pseudo-gate structure; 29. ​​first active structure; 30. first sacrificial layer; 31. second active structure; 32. second sacrificial layer; 33. pseudo-gate spacer; 34. isolation structure; 35. inner spacer; 36. first deep trench; 37. filling structure; 38, source-drain isolation structure; 39, first insulating layer; 40, first carrier wafer; 41, first semiconductor unit; 42, second semiconductor unit; 43, photoresist; 44, gate dielectric layer; 45, gate filling structure; 46, back gate isolation structure; 47, back dielectric layer; 48, second insulating layer; 49, second carrier wafer; 50, front gate isolation structure; 51, front dielectric layer; 52, third insulating layer; 53, third carrier wafer. DETAILED DESCRIPTION

[0030] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0031] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0032] In one embodiment, there are two schemes for the manufacturing process of stacked transistors, the first is a monolithic scheme, and the second is a sequential scheme.

[0033] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0034] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used in the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0035] In order to solve the technical problems of the above two solutions, a flip-chip solution for realizing self-aligned stacked transistors is proposed. The flip-chip solution forms the active areas of the upper and lower layers of the same source transistors by etching, and realizes the manufacture of stacked transistors on the front and back sides of the wafer by flipping the wafer to overcome the shortcomings of the above two solutions. This can also be called the "self-aligned flip-chip transistor" solution.

[0036] However, in the "self-aligned flip-chip transistor" solution, the stacked transistors formed by the same wafer can only be unified into a split-gate structure or a common-gate structure, which limits the design flexibility on the one hand and the further miniaturization of the circuit size on the other. Therefore, there is a certain room for optimization in the "self-aligned flip-chip transistor" solution.

[0037] In order to solve the above technical problems, the embodiments of the present application provide a method for preparing a stacked transistor, a stacked transistor and a semiconductor device, so as to optimize the preparation process of the gate structure in the "self-aligned flip-chip transistor" scheme, and realize the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure, so as to increase the flexibility of circuit design and further miniaturize the size of the circuit standard unit and the size of the circuit as a whole.

[0038] In a first aspect, an embodiment of the present application provides a method for preparing a stacked transistor.

[0039] In some embodiments, the stacked transistor includes a first semiconductor unit and a second semiconductor unit, and the first semiconductor unit and the second semiconductor unit are adjacently arranged in a first direction; the first semiconductor unit and the second semiconductor unit both include: a first active structure and a second active structure stacked along a second direction, a first dummy gate structure corresponding to the first active structure, a first source-drain structure corresponding to the first active structure, a second dummy gate structure corresponding to the second active structure, and a second source-drain structure corresponding to the second active structure; wherein a gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure.

[0040] It can be understood that the first semiconductor unit and the second semiconductor unit are used to prepare a first stacked transistor and a second stacked transistor, respectively. The first stacked transistor and the second stacked transistor are arranged adjacent to each other in the first direction. That is, the first direction can be the arrangement direction of adjacent stacked transistor units, and the second direction can be the stacking direction of the internal structure of each stacked transistor unit. For example, when each stacked transistor unit includes two transistors, the second direction can be the stacking direction of the two transistors. The second direction can be perpendicular to the first direction.

[0041] It can be understood that the first active structure and the second active structure are stacked along the second direction, and the first active structure and the second active structure can be used to form different transistors respectively. Similarly, the first dummy gate structure and the first source-drain structure corresponding to the first active structure are used together to prepare and form the same transistor. The second dummy gate structure and the second source-drain structure corresponding to the second active structure are used together to prepare and form the same transistor.

[0042] It should be noted that the first dummy gate structure and the first source-drain structure corresponding to the first active structure refer to structures adjacent to the first active structure in the first direction or the third direction. The second dummy gate structure and the second source-drain structure corresponding to the second active structure refer to structures adjacent to the second active structure in the first direction or the third direction. The third direction may be perpendicular to the second direction and the first direction.

[0043] In some embodiments, the gate isolation layer between the first dummy gate structure and the second dummy gate structure corresponds to the junction of the first active structure and the second active structure. The gate isolation layer is used to isolate the gate structures of transistors on both sides.

[0044] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a stacked transistor according to an embodiment of the present application. Figure 1 As shown, after obtaining the above-mentioned first semiconductor unit and second semiconductor unit, the method for preparing the stacked transistor may include:

[0045] Step S101: removing the second dummy gate structure to expose the second active structure and the gate isolation layer;

[0046] Step S102: coating a photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and removing at least the gate isolation layer in the second semiconductor unit by a photolithography process;

[0047] Step S103: removing the first dummy gate structure and the photoresist in sequence to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit;

[0048] Step S104: forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit;

[0049] Among them, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure constitute a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure constitute a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure constitute a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure constitute a fourth transistor; the first transistor and the second transistor constitute a first stacked transistor, and the third transistor and the fourth transistor constitute a second stacked transistor.

[0050] It should be noted that Figure 1 The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 1 The steps shown in the figure can be adjusted in sequence according to actual needs.

[0051] It should be noted that, for ease of explanation, the source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the source structure and / or the drain structure. In addition, the "source-drain" in the source-drain metal, source-drain groove and other structures is also an abbreviation of the "source and / or drain".

[0052] It can be understood that, through the above-mentioned preparation process, the gate isolation layer in the first semiconductor unit can be retained, so that the first gate structure and the second gate structure in the first stacked transistor formed subsequently are separated by the gate isolation layer, thereby forming a split-gate structure. And through the above-mentioned preparation process, the gate isolation layer in the second semiconductor unit can be removed, so that the third gate structure and the fourth gate structure in the second stacked transistor formed subsequently are connected, thereby forming a common-gate structure. Furthermore, the first semiconductor unit and the second semiconductor unit are arranged adjacent to each other in the first direction, which can meet the requirements of the circuit standard logic unit. It can be seen that the embodiment of the present application realizes the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure, thereby increasing the flexibility of circuit design, so that the size of the circuit standard unit and the size of the circuit as a whole can be further miniaturized.

[0053] The above steps are further explained below.

[0054] In some embodiments, during the process of preparing a stacked transistor, a first semiconductor unit and a second semiconductor unit may be formed first, and then the above steps S101 to S104 may be performed based on the first semiconductor unit and the second semiconductor unit.

[0055] It can be understood that the first semiconductor unit and the second semiconductor unit both include a first active structure, a second active structure, a first source-drain structure, a second source-drain structure, a first dummy gate structure, a second dummy gate structure and a gate isolation layer. The first source-drain structure is formed based on the first active structure, and the first dummy gate structure wraps the first active structure; the second source-drain structure is formed based on the second active structure, and the second dummy gate structure wraps the second active structure. The gate isolation layer is located between the first dummy gate structure and the second dummy gate structure.

[0056] It is understandable that the first semiconductor unit and the second semiconductor unit can be formed by using a standard manufacturing process of stacked transistors. For example, the first semiconductor unit and the second semiconductor unit can be formed by using a manufacturing process of a "self-aligned flip-chip stacked transistor".

[0057] In some embodiments, forming a first semiconductor unit and a second semiconductor unit includes: forming a first active structure and a second active structure on a semiconductor substrate, wherein the second active structure is closer to the semiconductor substrate than the first active structure; sequentially forming a second dummy gate structure, a gate isolation layer and a first dummy gate structure on the semiconductor substrate; sequentially forming a first source-drain structure and a first interlayer dielectric layer based on the first active structure; forming a first carrier wafer on the first dummy gate structure and the first interlayer dielectric layer; flipping the wafer and removing the semiconductor substrate; and sequentially forming a second source-drain structure and a second interlayer dielectric layer based on the second active structure.

[0058] It can be understood that after the first active structure and the second active structure are formed on the semiconductor substrate, the first pseudo-gate structure and the second pseudo-gate structure can be first prepared by the post-gate process. Among them, a gate isolation layer can also be formed between the first pseudo-gate structure and the second pseudo-gate structure. After the first pseudo-gate structure and the second pseudo-gate structure are prepared, a first source-drain structure can be formed based on the first active structure (the active structure away from the semiconductor substrate), and a first interlayer dielectric layer wrapping the first source-drain structure. And connected to the first pseudo-gate structure and the first interlayer dielectric layer through the first carrier wafer. Flip the first carrier wafer so that the semiconductor substrate is located at the upper part in the preparation direction (or the second direction) to facilitate the subsequent preparation process. After the semiconductor substrate is located at the upper part, the semiconductor substrate can be removed to expose the second active structure, and a second source-drain structure is formed based on the second active structure, and a second interlayer dielectric layer wrapping the second source-drain structure. At this point, the first semiconductor unit and the second semiconductor unit are obtained.

[0059] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming a stacked structure on the semiconductor substrate, and etching the stacked structure to form the first active structure and the second active structure at one time.

[0060] In one embodiment, the stacking structure may be different depending on the type of transistor in the stacked transistor. In one embodiment, when the transistor in the stacked transistor is a fin field-effect transistor (FinFET), the stacking structure may be formed by depositing one semiconductor material; in one embodiment, when the transistor in the stacked transistor is a gate-all-around field-effect transistor (GAAFET), the stacking structure may be formed by alternately depositing multiple semiconductor materials.

[0061] In one example, in a gate-all-around field effect transistor, the stacked structure may be formed by alternately depositing silicon and silicon germanium, wherein silicon is used to form a channel layer in the transistor and silicon germanium is used to form a support layer in the transistor.

[0062] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming an initial barrier layer and a stacked structure on the semiconductor substrate, and sequentially etching the stacked structure and the initial barrier layer to form the first active structure, the second active structure, and the barrier layer at one time. The barrier layer is formed by preparing the initial barrier layer, and the barrier layer is located on a side of the second source-drain structure away from the first active structure.

[0063] In one embodiment, the initial barrier layer may be formed by depositing a material having a predetermined hardness. In one example, the first material layer may be silicon germanium.

[0064] In some embodiments, forming a first active structure and a second active structure on a semiconductor substrate includes: forming a first stacked structure, an initial first sacrificial layer, a second stacked structure, and an initial second sacrificial layer on the semiconductor substrate, and sequentially etching the first stacked structure, the initial first sacrificial layer, the second stacked structure, and the initial second sacrificial layer to form a first active structure, a first sacrificial layer, a second active structure, and a second sacrificial layer at one time. Here, the first sacrificial layer is used to isolate the first active structure and the second active structure. The specific structure of the first stacked structure and the second stacked structure can refer to the above-mentioned stacked structure, and for the sake of brevity of the specification, it will not be repeated here. The first stacked structure is used to form the first active structure, and the second stacked structure is used to form the second active structure.

[0065] In one embodiment, the first sacrificial layer may be removed in a subsequent preparation step. An insulating material may be deposited at the location where the first sacrificial layer is removed to form an isolation structure, thereby achieving electrical isolation between the upper and lower layers of transistors. In one example, the first sacrificial layer may be formed by deposition of silicon germanium. Here, the percentage of germanium atoms in the silicon germanium forming the first sacrificial layer is different from the percentage of germanium atoms in the silicon germanium forming the stacked structure.

[0066] In one embodiment, the second sacrificial layer may be removed in a subsequent preparation step. A gate structure may be deposited at the location where the second sacrificial layer is removed, thereby realizing a fully surrounding gate structure. In one example, the first sacrificial layer may be formed by deposition of silicon germanium.

[0067] In some embodiments, when the first semiconductor unit and the second semiconductor unit have a barrier layer, after forming the first active structure and the second active structure, an oxide material can be deposited on the semiconductor substrate to form an initial shallow trench isolation structure (STI), and the initial shallow trench isolation structure is etched back to form a shallow trench isolation structure. Here, the shallow trench isolation structure wraps the barrier layer, and the second active structure and the first active structure are exposed outside the shallow trench isolation structure.

[0068] In one embodiment, the oxide material forming the shallow trench isolation structure may be: silicon-based oxide (SiOx, x is the number of oxygen atoms), such as silicon dioxide (SiO2).

[0069] In some embodiments, after forming the shallow trench isolation structure, a dummy gate material and an isolation material may be deposited in the gate region of the stacked transistor (the gate region corresponding to the first semiconductor unit and the second semiconductor unit) to form a first dummy gate structure, a gate isolation layer, and a second dummy gate structure. Here, the first dummy gate structure and the second dummy gate structure are formed of dummy gate materials, and the gate isolation layer is formed of isolation materials. In some embodiments, after forming the first dummy gate structure and the second dummy gate structure, a sidewall material may be deposited on the semiconductor substrate to form a dummy gate sidewall on the side surface of the dummy gate structure, the surface (upper surface and side surface) of the first active structure, and the surface (side surface) of the second active structure.

[0070] In one embodiment, the pseudo gate material may be polysilicon, amorphous silicon or the like. In one embodiment, the isolation material may be an insulating material. The sidewall material may be an insulating material. In the embodiment of the present application, the insulating material may be, for example, silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbon nitride (SiCN) or the like.

[0071] In some embodiments, when a first sacrificial layer is formed between the first active structure and the second active structure, when the above-mentioned pseudo gate sidewall is formed, the pseudo gate sidewall also covers the surface (side surface) of the first sacrificial layer. After the above-mentioned pseudo gate sidewall is formed, the pseudo gate sidewall on the surface of the first active structure and the first sacrificial layer can be removed to expose the first active structure and the first sacrificial layer. In some embodiments, after exposing the first active structure and the first sacrificial layer, the first active structure in the source and drain region of the stacked transistor can be removed, and the first sacrificial layer in the source and drain region and the gate region can be removed. In some embodiments, after removing the first sacrificial layer, a gap is formed between the first active structure and the second active structure in the gate region. At this time, an insulating material can be deposited in the gap to form an isolation structure.

[0072] It can be understood that when removing the first active structure in the source / drain region, the first dummy gate structure can be used as a hard mask to etch the first active structure.

[0073] In some embodiments, after forming the isolation structure, the support layer in the first active structure in the gate region (formed by the support layer in the stacked structure) can be laterally etched to form an internal sidewall (also understood as a first pseudo-gate sidewall) of the front transistor (composed of the first transistor and the third transistor) in the stacked transistor. In some embodiments, after forming the first pseudo-gate sidewall, the second active structure in the source and drain region can be removed to expose the semiconductor substrate. Subsequently, an insulating material is deposited in the source and drain region to form a filling structure. Here, the height of the filling structure is greater than the height of the second active structure and less than the height of the first active structure.

[0074] In one embodiment, a supporting layer in a first active structure in a gate region is laterally etched to form an internal sidewall of a front transistor in a stacked transistor, including: laterally etching a supporting layer in a first active structure in a gate region to form a sidewall trench, and depositing a sidewall material in the sidewall trench to form an internal sidewall of the front transistor in the stacked transistor.

[0075] In some embodiments, after forming the filling structure, an insulating material may be deposited on the filling structure to form a source-drain isolation structure. Here, the source-drain isolation structure is used to electrically isolate the source-drain structure in the front transistor from the source-drain structure in the back transistor. In some embodiments, after forming the source-drain isolation structure, a first source-drain structure may be epitaxially grown in the source-drain region based on the channel layer in the first active structure in the gate region (formed by the channel layer in the stacked structure). In some embodiments, after forming the first source-drain structure, a dielectric material may be deposited on the first active structure to form a first interlayer dielectric layer that wraps the first source-drain structure.

[0076] In one embodiment, the dielectric material forming the first interlayer dielectric layer may be silicon carbon nitride (SiCN), silicon nitride (Si3N4) or the like.

[0077] In some embodiments, after forming the first interlayer dielectric layer, an insulating material may be deposited on the first dummy gate structure and the first interlayer dielectric layer to form a first insulating layer, and the first insulating layer may be bonded to the first carrier wafer. Subsequently, the first carrier wafer is flipped so that the first active structure and the second active structure are changed in preparation position. In some embodiments, after the first carrier wafer is flipped, the semiconductor substrate may be removed to expose the second active structure.

[0078] In some embodiments, when a shallow trench isolation structure having a barrier layer and a barrier layer wrapped therein is formed, removing the semiconductor substrate can expose the shallow trench isolation structure and the filling structure. The shallow trench isolation structure can then be removed, and a dummy gate material can be deposited at the location where the shallow trench isolation structure is removed, so that the height of the second dummy gate structure is equal to the height of the filling structure.

[0079] In some embodiments, after removing the semiconductor substrate, the filling structure in the source-drain region can be removed to expose the second active structure in the source-drain region. Subsequently, the supporting layer in the second active structure in the gate region can be laterally etched to form the internal sidewall of the back transistor in the stacked transistor (which can also be understood as the second pseudo-gate sidewall). In some embodiments, on the source-drain isolation structure, a second source-drain structure can be epitaxially grown in the source-drain region based on the channel layer in the second active structure in the gate region. In some embodiments, after forming the second source-drain structure, a dielectric material can be deposited on the second active structure to form a second interlayer dielectric layer that wraps the second source-drain structure.

[0080] At this point, the first semiconductor unit and the second semiconductor unit are formed.

[0081] In step S101 , the second dummy gate structure is removed to expose the second active structure and the gate isolation layer.

[0082] It can be understood that after obtaining the above-mentioned first semiconductor unit and the second semiconductor unit, the first dummy gate structure is usually located in the lower layer, and the second dummy gate structure is usually located in the upper layer. In order to facilitate the preparation of stacked transistors, the second dummy gate structure can be removed to expose the second active structure corresponding to the second dummy gate structure, and the gate isolation layer located between the first dummy gate structure and the second dummy gate structure.

[0083] In some embodiments, when a barrier layer is formed in the first semiconductor unit and the second semiconductor unit, when removing the second dummy gate structure, the barrier layer may be used as a hard mask and an etching process may be used to remove the second dummy gate structure.

[0084] In step S102, a photoresist is coated on the second active structure and the gate isolation layer in the first semiconductor unit, and at least the gate isolation layer in the second semiconductor unit is removed by a photolithography process.

[0085] It is understandable that after exposing the second active structure and the gate isolation layer, a photoresist may be coated on the second active structure and the gate isolation layer in the gate region of the first semiconductor unit. At the same time, in order to protect the structure in the source-drain region (e.g., the second interlayer dielectric layer), a photoresist may also be coated on the structure in the source-drain region of the first semiconductor unit and the second semiconductor unit. Since the second active structure and the gate isolation layer in the gate region of the second semiconductor unit are exposed outside the photoresist, at least the gate isolation layer in the second semiconductor unit may be removed by the photolithography process.

[0086] In some embodiments, when a blocking layer is formed in the second semiconductor unit, at least the gate isolation layer in the second semiconductor unit is removed by a photolithography process, including: using the blocking layer as a mask, removing the gate isolation layer in the second semiconductor unit by an anisotropic etching process; removing the first part of the first pseudo-gate structure in the second semiconductor unit by an anisotropic etching process or an isotropic etching process, wherein the first part corresponds to the gate isolation layer in the second semiconductor unit.

[0087] It can be understood that when a barrier layer is formed in the second semiconductor unit, when the gate isolation layer is removed by an etching process, the barrier layer can protect the second active structure in the second semiconductor unit from being damaged.

[0088] It can be understood that the embodiment of the present application can use the barrier layer as a mask to sequentially etch the gate isolation layer in the second semiconductor unit and the first portion of the first dummy gate structure below the gate isolation layer through an anisotropic etching process. The embodiment of the present application can also use the barrier layer as a mask to etch the gate isolation layer in the second semiconductor unit through an anisotropic etching process, and then remove the first portion of the first dummy gate structure below the gate isolation layer through an isotropic etching process.

[0089] Step S103 , removing the first dummy gate structure and the photoresist in sequence to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit.

[0090] It can be understood that after the gate isolation layer in the second semiconductor unit is removed by photolithography, the first dummy gate structure and the photoresist can be removed in sequence to open the gate regions of the first semiconductor unit and the second semiconductor unit and expose the active structure in the gate region. Here, since the first semiconductor unit includes a gate isolation layer, after removing the first dummy gate structure and the photoresist, the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit can be exposed; since the gate isolation layer in the second semiconductor unit is removed by photolithography in step S102, after removing the first dummy gate structure and the photoresist, the first active structure and the second active structure in the second semiconductor unit can be exposed.

[0091] In some embodiments, removing the first dummy gate structure and the photoresist in sequence includes: removing the first dummy gate structure by an etching process, and then removing the photoresist.

[0092] In some embodiments, the first dummy gate structure and the photoresist are removed in sequence, including: removing the second portion of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit through an isotropic etching process, wherein the second portion and the first portion constitute the first dummy gate structure in the second semiconductor unit; and removing the photoresist.

[0093] It can be understood that in step S102, the first part of the first dummy gate structure in the second semiconductor unit can be removed, and then the second part of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit can be removed by an isotropic etching process, thereby completely removing the first dummy gate structure. Then, the photoresist is removed to complete the opening of the gate region.

[0094] Step S104, forming a first gate structure and a second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and simultaneously forming a third gate structure and a fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit.

[0095] It can be understood that after the active structure of the gate region is exposed, the same preparation process can be used to form the first gate structure and the second gate structure, as well as the third gate structure and the fourth gate structure.

[0096] It can be understood that, through the standard process of semiconductor preparation, a first gate structure can be formed based on the first active structure in the first semiconductor unit, a second gate structure can be formed based on the second active structure in the first semiconductor unit, a third gate structure can be formed based on the first active structure in the second semiconductor unit, and a fourth gate structure can be formed based on the second active structure in the second semiconductor unit. Here, the standard process of semiconductor preparation can be selected according to actual needs, and the embodiments of the present application are not limited to this.

[0097] In one embodiment, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure to form a split gate structure; the third gate structure and the fourth gate structure are connected to form a common gate structure. The first gate structure and the first source-drain structure in the first semiconductor structure constitute a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure constitute a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure constitute a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure constitute a fourth transistor; the first transistor and the second transistor constitute a first stacked transistor, and the third transistor and the fourth transistor constitute a second stacked transistor. It can be seen that in the embodiment of the present application, a first stacked transistor with a split gate structure and a second stacked transistor with a common gate structure can be formed simultaneously.

[0098] In some embodiments, step S104 may include: depositing a dielectric material on the first active structure, the gate isolation layer, and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit to form a gate dielectric layer; forming a second gate structure and a fourth gate structure based on the second active structure covered with the gate dielectric layer; and forming a first gate structure and a third gate structure based on the first active structure covered with the gate dielectric layer.

[0099] It can be understood that in the process of preparing the gate structures in the first stacked transistor and the second stacked transistor, a dielectric material can be first deposited on the active structure in the gate region to prepare a gate dielectric layer. Subsequently, a second gate structure is formed based on the second active structure covered with the gate dielectric layer in the first semiconductor unit, and a fourth gate structure is formed based on the second active structure covered with the gate dielectric layer in the second semiconductor unit. Finally, a first gate structure is formed based on the first active structure covered with the gate dielectric layer in the first semiconductor unit, and a third gate structure is formed based on the first active structure covered with the gate dielectric layer in the second semiconductor unit.

[0100] In some embodiments, the dielectric material forming the gate dielectric layer can be set according to actual needs, and the embodiments of the present application are not limited to this. For example, the gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. In one example, the first gate dielectric layer may include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

[0101] In one embodiment, the first active structure and the second active structure include channel layers and support layers alternately stacked along the second direction. Step S104 may include: removing the support layers in the first active structure and the second active structure to retain the first channel layer in the first active structure and the second channel layer in the second active structure. Depositing dielectric material on the first channel layer, the gate isolation layer and the second channel layer in the first semiconductor unit, and the first channel layer and the second channel layer in the second semiconductor unit to form a gate dielectric layer. Subsequently, forming a second gate structure based on the second channel layer covered with the gate dielectric layer in the first semiconductor unit, and forming a fourth gate structure based on the second channel layer covered with the gate dielectric layer in the second semiconductor unit. Finally, forming a first gate structure based on the first channel layer covered with the gate dielectric layer in the first semiconductor unit, and forming a third gate structure based on the first channel layer covered with the gate dielectric layer in the second semiconductor unit.

[0102] It can be understood that in the embodiment of the present application, the gate dielectric layers of all transistors in the stacked transistor are formed by the same process, which can reduce the steps of preparing the gate structure, simplify the preparation process, and reduce the difficulty of preparation.

[0103] In some embodiments, based on the second active structure covered with the gate dielectric layer, a second gate structure and a fourth gate structure are formed respectively, including: depositing a semiconductor material on the first carrier wafer to form a gate filling structure. Here, the gate filling structure wraps the first active structure in the first semiconductor unit, and the second active structure and the gate isolation layer in the first semiconductor unit are exposed outside the gate filling structure; the gate filling structure wraps the first active structure in the second semiconductor unit, and the second active structure in the second semiconductor unit is exposed outside the gate filling structure. On the gate isolation layer in the first semiconductor unit and the initial gate filling structure in the second semiconductor unit, a gate metal material is deposited to form a second gate structure and a fourth gate structure respectively, wherein the second gate structure is connected to the gate isolation layer in the first semiconductor unit.

[0104] It can be understood that the second gate structure and the fourth gate structure are back gate structures. In the process of forming the back gate structure, a semiconductor material can be first deposited on the first carrier wafer to form an initial gate filling structure, and the initial gate filling structure can be back-etched to form a gate filling structure. Here, the gate filling structure can at least cover the first active structure and expose the second active structure. Subsequently, a gate metal material is deposited on the gate filling structure to simultaneously form the second gate structure and the fourth gate structure.

[0105] In some embodiments, the gate metal material forming the gate structure can be set according to actual needs, and the embodiments of the present application are not limited to this.

[0106] It is understandable that, since the gate isolation layer in the first semiconductor unit is retained, the gate filling structure may be located at different positions in the first semiconductor unit and the second semiconductor unit. For example, the gate filling structure is between the gate isolation layer and the first carrier wafer in the first semiconductor unit. The upper surface of the gate filling structure is at the junction of the first active structure and the second active structure in the second semiconductor unit.

[0107] In one embodiment, an isolation structure is formed between the first active structure and the second active structure, and an upper surface of the gate filling structure may correspond to the isolation structure.

[0108] It can be understood that the gate filling structure can protect the first active structure during the process of forming the second gate structure and the fourth gate structure, thereby reducing the device failure rate. In one example, the material forming the gate filling structure can be amorphous silicon.

[0109] It should be noted that the first carrier wafer here is a carrier wafer connected to the first interlayer dielectric layer during the process of forming the first semiconductor unit and the second semiconductor unit. Since the second active structure in the first semiconductor unit and the second semiconductor unit is on the top and the first active structure is on the bottom, the first carrier wafer can be located at the bottom to carry other structures, which is convenient for the processing and preparation of stacked transistors.

[0110] In some embodiments, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method further includes: using a fin cutting process to etch the second gate structure and the fourth gate structure to form a back isolation groove, wherein the front isolation groove is at least located between the second gate structure and the fourth gate structure; depositing an insulating material in the back isolation groove to form a back gate isolation structure.

[0111] It can be understood that after forming the second gate structure and the fourth gate structure, an isolation structure between cells can also be formed. By adopting a fin cutting process, the second gate structure and the fourth gate structure are etched, and a back isolation groove can be formed at least between the second gate structure and the fourth gate structure. The back isolation groove is located at the junction of the second gate structure and the fourth gate structure in the first direction, so that after depositing an insulating material in the back isolation groove, a back gate isolation structure for electrically isolating the second gate structure and the fourth gate structure can be formed.

[0112] In one embodiment, the second gate structure and the fourth gate structure are etched by using a fin cutting process, and a back isolation groove can be formed at both ends of the second gate structure, and a back isolation groove can be formed at both ends of the fourth gate structure. Here, the two ends of the second gate structure refer to the two ends of the second gate structure in the first direction. The two ends of the fourth gate structure refer to the two ends of the fourth gate structure in the first direction.

[0113] In some embodiments, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method further includes: forming a back source and drain metal on the second source and drain structure; forming a back metal interconnection layer on the second gate structure, the fourth gate structure and the back source and drain metal; bonding the back metal interconnection layer to a second carrier wafer; and inverting and removing the first carrier wafer to expose the gate filling structure.

[0114] It can be understood that after forming the second gate structure and the fourth gate structure, the second interlayer dielectric layer can be etched to form a back source and drain metal through hole, and a metal material can be deposited in the back source and drain metal through hole to form a back source and drain metal. Subsequently, a dielectric material is deposited on the second gate structure, the fourth gate structure and the back source and drain metal to form a back dielectric layer, and a standard back-end process for semiconductor preparation (such as dielectric deposition between interconnects, metal line formation, lead pad formation, etc.) is used on the back dielectric layer to prepare a back metal interconnection layer. After forming the back metal interconnection layer, an insulating material can be deposited on the back metal interconnection layer to form a second insulating layer, and the second insulating layer is bonded to the second carrier wafer. After bonding, the second carrier wafer is flipped so that the first carrier wafer is located on top, and then the first carrier wafer is removed to expose the gate filling structure.

[0115] In this embodiment, after the second gate structure and the fourth gate structure are formed, a back metal interconnection layer is formed. The back metal interconnection layer electrically connects the second source-drain structure, the second gate structure and the fourth gate structure, thereby completing the preparation of the back transistor.

[0116] In some embodiments, after forming a second gate structure and a fourth gate structure respectively based on a second active structure covered with a gate dielectric layer, the method further includes: forming a second carrier wafer above the second gate structure, the fourth gate structure and the second interlayer dielectric layer; and flipping and removing the first carrier wafer to expose the gate filling structure.

[0117] It can be understood that after forming the second gate structure and the fourth gate structure, an insulating material can be deposited on the second gate structure, the fourth gate structure and the second interlayer dielectric layer to form a second insulating layer, and the second insulating layer is bonded to the second carrier wafer. After bonding, the second carrier wafer is flipped so that the first carrier wafer is located on top, and then the first carrier wafer is removed to expose the gate filling structure.

[0118] In this embodiment, after the second gate structure and the fourth gate structure are prepared, the back metal interconnection layer is not prepared first, but the front transistor is prepared first, so that a higher preparation temperature can be used in the process of forming the front transistor, thereby improving the thermal budget in the preparation process.

[0119] In some embodiments, based on a first active structure covered with a gate dielectric layer, a first gate structure and a third gate structure are formed respectively, including: removing the gate filling structure to expose the gate isolation layer and the fourth gate structure in the first semiconductor unit respectively; depositing a gate metal material on the exposed gate isolation layer and the fourth gate structure in the first semiconductor unit to form the first gate structure and the third gate structure respectively, wherein the first gate structure is connected to the gate isolation layer in the first semiconductor unit.

[0120] It can be understood that the first gate structure and the third gate structure are front gate structures. In the process of forming the front gate structure, the gate filling structure protecting the first active structure can be firstly removed to expose the gate isolation layer in the first semiconductor unit and the fourth gate structure in the second semiconductor unit respectively. Subsequently, the gate metal material is deposited on the exposed gate isolation layer in the first semiconductor unit and the fourth gate structure in the first semiconductor unit, and the first gate structure and the third gate structure can be formed simultaneously.

[0121] The first gate structure and the second gate structure are stacked, and a gate isolation layer is provided between the first gate structure and the second gate structure, thereby forming a split gate structure. The third gate structure and the fourth gate structure are stacked, and the third gate structure and the fourth gate structure are connected, thereby forming a common gate structure.

[0122] In some embodiments, after forming a first gate structure and a third gate structure respectively based on a first active structure covered with a gate dielectric layer, the method further includes: using a fin cutting process to etch the first gate structure and the third gate structure to form a front isolation groove, wherein the front isolation groove is at least located between the first gate structure and the third gate structure; depositing an insulating material in the front isolation groove to form a front gate isolation structure.

[0123] It can be understood that after forming the first gate structure and the third gate structure, an isolation structure between cells can also be formed. By adopting a fin cutting process, etching the first gate structure and the third gate structure, a front isolation groove can be formed at least between the first gate structure and the third gate structure. The front isolation groove is located at the junction of the first gate structure and the third gate structure in the first direction, so that after depositing an insulating material in the front isolation groove, a front gate isolation structure for electrically isolating the first gate structure and the third gate structure can be formed.

[0124] In one embodiment, the first gate structure and the third gate structure are etched by using a fin cutting process, so that a front isolation groove can be formed at both ends of the first gate structure, and a front isolation groove can be formed at both ends of the third gate structure. Here, the two ends of the first gate structure refer to the two ends of the first gate structure in the first direction. The two ends of the third gate structure refer to the two ends of the third gate structure in the first direction.

[0125] In some embodiments, after forming a first gate structure and a third gate structure respectively based on a first active structure covered with a gate dielectric layer, the method further includes: forming a front source and drain metal on the first source and drain structure; and forming a front metal interconnection layer on the first gate structure, the third gate structure and the front source and drain metal.

[0126] It can be understood that after forming the first gate structure and the third gate structure, the first interlayer dielectric layer can be etched to form a front source-drain metal through hole, and a metal material can be deposited in the front source-drain metal through hole to form a front source-drain metal. Subsequently, a dielectric material is deposited on the first gate structure, the third gate structure and the front source-drain metal to form a front dielectric layer, and a front metal interconnection layer is formed on the front dielectric layer using a standard back-end process for semiconductor manufacturing.

[0127] In this embodiment, after the first gate structure and the third gate structure are formed, a front metal interconnection layer is formed. The front metal interconnection layer electrically connects the first source-drain structure, the first gate structure, and the third gate structure, thereby completing the preparation of the front transistor. At this point, when the back transistor and the front transistor are completed, the preparation of the first stacked transistor and the second stacked transistor is completed.

[0128] In some embodiments, when a back metal interconnection layer is not formed, after forming a front metal interconnection layer, the method further includes: bonding the front metal interconnection layer and a third carrier wafer; flipping and removing the second carrier wafer to expose the second gate structure, the fourth gate structure and the second interlayer dielectric layer; forming a back source and drain metal on the second source and drain structure; and forming a back metal interconnection layer on the second gate structure, the fourth gate structure and the back source and drain metal.

[0129] It is understandable that in the case where the second gate structure and the fourth gate structure are formed without forming the back metal interconnection layer, the back metal interconnection layer can be formed after the front metal interconnection layer is formed. The third insulating layer is formed by depositing an insulating material on the front metal interconnection layer, and the third insulating layer is bonded to the third carrier wafer. After bonding, the third carrier wafer is flipped so that the second carrier wafer is located above, and then the second carrier wafer is removed to expose the second gate structure, the fourth gate structure and the second interlayer dielectric layer. The second interlayer dielectric layer is etched to form a back source and drain metal groove, and a metal material is deposited in the back source and drain metal groove to form a back source and drain metal. A dielectric material is deposited on the second gate structure, the fourth gate structure and the back source and drain metal to form a back dielectric layer, and a standard back-end process for semiconductor preparation is used on the back dielectric layer to prepare and form a back metal interconnection layer.

[0130] In this embodiment, after the first gate structure and the third gate structure are prepared, a front metal interconnection layer is prepared to complete the preparation of the front transistor. After the front transistor is prepared, a back metal interconnection layer is prepared to complete the preparation of the back transistor. At this point, when the back transistor and the front transistor are prepared, the preparation of the first stacked transistor and the second stacked transistor is completed.

[0131] In an embodiment of the present application, by retaining the gate isolation layer in the first semiconductor unit, the first gate structure and the second gate structure in the first stacked transistor formed subsequently can be separated by the gate isolation layer, thereby forming a split-gate structure. By removing the gate isolation layer in the second semiconductor unit, the third gate structure and the fourth gate structure in the second stacked transistor formed subsequently are connected, thereby forming a common-gate structure. Furthermore, the first semiconductor unit and the second semiconductor unit are arranged adjacent to each other in the first direction, which can meet the requirements of the circuit standard logic unit. It can be seen that the embodiment of the present application simultaneously prepares a stacked transistor with a split-gate structure and a stacked transistor with a common-gate structure, which not only increases the flexibility of the circuit design, but also allows the size of the circuit standard unit and the size of the circuit as a whole to be further miniaturized.

[0132] Figure 2 FIG. 1 is a top view of a stacked transistor according to an embodiment of the present application, see Figure 2 As shown, only the fin structure, gate structure and source-drain structure of the stacked transistor 10 are shown in the top view. Figures 3 to 38 FIG. 1 is a schematic diagram of a preparation process of a first stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 38 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figures 3 to 38 (b) shows the Figure 2The cross-sectional view along the dotted line BB', Figures 3 to 38 (c) shows the Figure 2 The cross-sectional view along the dotted line CC'. Figures 1 to 38 The manufacturing process of the stacked transistor shown is used as a specific example to illustrate the manufacturing method of the stacked transistor in the present application.

[0133] In one example, a process for preparing a stacked transistor may include the following steps:

[0134] Step 1: epitaxially grow silicon germanium and silicon on a semiconductor substrate 20 (formed from silicon) to form an initial stacking structure 21 and an initial barrier layer 22, and obtain Figure 3 The structure shown.

[0135] It can be understood that the initial barrier layer 22 is located between the semiconductor substrate 20 and the initial stacked structure 21. Here, the initial stacked structure 21 is formed by alternately depositing silicon germanium and silicon. The initial barrier layer 22 is formed of silicon germanium.

[0136] Step 2: Through photolithography, a stacked structure 23 and a barrier layer 24 are formed by etching at one time, and the obtained structure is as follows: Figure 4 The structure shown.

[0137] It can be understood that in the cross-sectional view along the AA′ direction and the cross-sectional view along the BB′ direction, portions on both sides of the initial stacked structure 21 are etched, thereby forming a stacked structure 23 for preparing a full-surround gate field effect transistor.

[0138] In some embodiments, the percentage of germanium atoms in the silicon germanium forming the barrier layer 24 is different from the percentage of germanium atoms in the silicon germanium forming the stacked structure 23. The barrier layer 24 may have a certain hardness so that the barrier layer 24 can serve as an etching barrier layer after flipping.

[0139] In some embodiments, silicon germanium forms a support layer in the stack structure 23, and silicon forms a channel layer in the stack structure 23. Figure 4 As shown, the stack structure 23 may include a first active structure 29 , a first sacrificial layer 30 , a second active structure 31 , and a second sacrificial layer 32 .

[0140] In the third step, an oxide material is deposited on the semiconductor substrate 20 and the oxide material is etched to a preset height to form a shallow trench isolation structure 25, so as to obtain Figure 5 The structure shown.

[0141] Here, the shallow trench isolation structure 25 wraps the barrier layer 24 , and the stacked structure 23 is exposed outside the shallow trench isolation structure 25 .

[0142] In the fourth step, polysilicon and isolation materials are deposited in the gate region of the stacked transistor to form a first dummy gate structure 26, a gate isolation layer 27, and a second dummy gate structure 28. After the first dummy gate structure 26 and the second dummy gate structure 28 are formed, a spacer material is deposited to form a dummy gate spacer 33, and the structure shown in FIG. Figure 6 The structure shown.

[0143] Here, the first dummy gate structure 26 and the second dummy gate structure 28 are formed of polysilicon, and the gate isolation layer 27 is formed of an isolation material. In one embodiment, the first dummy gate structure 26 and the second dummy gate structure 28 are self-aligned.

[0144] In the fifth step, the pseudo gate sidewall 33 is etched to expose the first active structure 29 and the first sacrificial layer 30 to obtain Figure 7 The structure shown.

[0145] It can be understood that an anisotropic etching process can be used to expose the first active structure 29 and the first sacrificial layer 30 .

[0146] It should be noted that if Figure 7 As shown, after the first active structure 29 and the first sacrificial layer 30 are exposed, in the cross-sectional view along the CC' direction, a portion of the dummy gate spacer 33 is still retained on the sidewall of the first dummy gate structure 26. The dummy gate spacer 33 can be used as a hard mask in subsequent fabrication processes.

[0147] Step 6: remove the first active structure 29 in the source / drain region to obtain Figure 8 The structure shown.

[0148] It can be understood that by using the first dummy gate structure 26 and the dummy gate spacer 33 as a hard mask, the first active structure 29 located in the source and drain regions can be selectively etched.

[0149] In the seventh step, an isolation structure 34 is formed between the first active structure 29 and the second active structure 31 in the gate region to obtain Fig. 9 The structure shown.

[0150] It is understood that the isolation structure 34 is a middle dielectric isolation (MDI). In some embodiments, the isolation structure 34 may also be a silicon-on-insulator (SOI) isolation.

[0151] In one embodiment, forming the isolation structure 34 may include: selectively removing the first sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31. Depositing an insulating material such as silicon nitride, and using a chemical-mechanical planarization process (CMP) to planarize the isolation structure 34 formed of the silicon nitride material. Using an anisotropic etching process to remove excess isolation structure 34, retaining the isolation structure 34 between the first active structure 29 and the second active structure 31 in the gate region.

[0152] Step 8: Laterally etch the support layer in the first active structure 29 to a preset depth. Deposit insulating materials such as silicon nitride at the position where the support layer is removed to form the inner sidewalls 35 of the front transistors (including the first transistor 11 and the third transistor 13), and obtain Fig.10 The structure shown.

[0153] It is understood that in this embodiment, the stacked transistor 10 is a full-surround gate field effect transistor, and therefore, it is necessary to form an internal spacer 35. When the stacked transistor 10 is a fin field effect transistor, a planar field effect transistor, etc., it is not necessary to form the internal spacer 35.

[0154] In the ninth step, the second active structure 31 in the source / drain region and the second sacrificial layer 32 at the bottom of the second active structure 31 are etched by an anisotropic etching process to form a first deep trench 36. Fig.11 The structure shown.

[0155] In the tenth step, the barrier layer 24 and the shallow trench isolation structure 25 in the source and drain regions are anisotropically etched to obtain Fig.12 The structure shown.

[0156] It can be understood that after anisotropic etching of the barrier layer 24 in the source and drain regions, an etched barrier layer 24 is formed. The etched barrier layer 24 is located in the gate region, and after flipping, the position of the gate region can be obtained based on the etched barrier layer 24.

[0157] Step 11: deposit insulating material in the source / drain region to form a filling structure 37, and obtain Fig.13 The structure shown.

[0158] In one embodiment, the height of the upper surface of the filling structure 37 is lower than the height of the upper surface of the isolation structure 34 and higher than the height of the lower surface of the isolation structure 34 .

[0159] In the twelfth step, an insulating material is deposited on the filling structure 37 in the source-drain region and the insulating material is etched back to a preset height to form a source-drain isolation structure 38, thereby obtaining Fig.14The structure shown.

[0160] It can be understood that the source-drain isolation structure 38 is used to electrically isolate the first source-drain structure 112 from the second source-drain structure 122 .

[0161] In the thirteenth step, based on the first active structure 29 in the gate region, a first source-drain structure 112 is formed in the source-drain region by epitaxy, so as to obtain Fig.15 The structure shown.

[0162] In the fourteenth step, a dielectric material is deposited in the source / drain region to form a first interlayer dielectric layer 113, and the dielectric material is deposited in the source / drain region to form a first interlayer dielectric layer 113. Fig.16 The structure shown.

[0163] In step 15, an insulating material is deposited on the first dummy gate structure 26 and the first interlayer dielectric layer 113 to form a first insulating layer 39, and the first insulating layer 39 is bonded to the first carrier wafer 40 to obtain Fig.17 The structure shown.

[0164] In step 16, the first carrier wafer 40 is turned over and the semiconductor substrate 20 is removed to obtain Fig.18 The structure shown.

[0165] Here, after the semiconductor substrate 20 is removed, the barrier layer 24 , the shallow trench isolation structure 25 , and the filling structure 37 may be exposed.

[0166] In step 17, the shallow trench isolation structure 25 wrapping the barrier layer 24 is removed to obtain Fig.19 The structure shown.

[0167] In step 18, polysilicon is deposited at the position where the shallow trench isolation structure 25 is removed to complete the second dummy gate structure 28, so as to obtain Fig. 20 The structure shown.

[0168] In the nineteenth step, the filling structure in the source and drain regions is removed to obtain Fig.21 The structure shown.

[0169] Step 20: Laterally etch the support layer in the second active structure 31 to a certain depth. Deposit insulating materials such as silicon nitride at the position where the support layer is removed to form the inner sidewall 35 of the back transistor (including the second transistor 12 and the fourth transistor 14), and obtain Fig. 22 The structure shown.

[0170] In the 21st step, based on the second active structure 31 in the gate region, a second source-drain structure 122 is formed in the source-drain region by epitaxy; a dielectric material is deposited in the source-drain region to form a second interlayer dielectric layer 123, and the following is obtained: Fig.23 The structure shown.

[0171] It can be understood that by performing the first step to the twenty-first step, the first semiconductor unit 41 and the second semiconductor unit 42 in the embodiment of the present application can be obtained, see Fig.23 shown.

[0172] Step 22: remove the second dummy gate structure 28 to obtain Fig.24 The structure shown.

[0173] In the twenty-third step, a photoresist 43 is applied to the gate region and the source-drain region of the first semiconductor unit 41, and a photoresist 43 is applied to the source-drain region of the second semiconductor unit 42 to obtain Fig.25 The structure shown.

[0174] In step 24, an anisotropic etching process is used to remove the gate isolation layer 27 in the second semiconductor unit 42 and the first dummy gate structure 26 located below the gate isolation layer 27 to obtain Fig.26 The structure shown.

[0175] It can be understood that the first semiconductor unit 41 has a gate isolation layer 27, and the second semiconductor unit 42 does not have a gate isolation layer 27. The photoresist 43 is used to protect the gate isolation layer 27 in the first semiconductor unit 41 from being etched.

[0176] In step 25, an isotropic etching process is used to remove the first dummy gate structure 26 in the first semiconductor unit 41 and the first dummy gate structure 26 in the second semiconductor unit 42, thereby obtaining Fig. 27 The structure shown.

[0177] In the twenty-sixth step, the photoresist 43 coated in the gate region and the source-drain region of the first semiconductor unit 41 and the photoresist 43 coated in the source-drain region of the second semiconductor unit 42 are removed to obtain Fig.28 The structure shown.

[0178] It can be understood that after removing the photoresist, the first active structure 29 and the second active structure 31 in the gate region can be completely exposed.

[0179] In step 27, a dielectric material is deposited on the first active structure 29 and the second active structure 31 to form a gate dielectric layer 44, and a gate dielectric layer 44 is obtained. Fig.29 The structure shown.

[0180] It can be understood that the first semiconductor unit 41 has a gate isolation layer 27 , and during the process of depositing the dielectric material, a gate dielectric layer 44 may also be formed on the gate isolation layer 27 .

[0181] In step 28, polysilicon material is deposited in the gate region to form a gate filling structure 45, so as to obtain Fig.30 The structure shown.

[0182] It can be understood that the gate filling structure 45 in the first semiconductor unit 41 is between the gate isolation layer 27 and the first carrier wafer 40. The height of the gate filling structure 45 in the second semiconductor unit 42 is greater than the height of the gate filling structure 45 in the first semiconductor unit 41.

[0183] In some embodiments, a polysilicon material is deposited to form an initial gate filling structure, and then the initial gate filling structure is etched back to a predetermined height to form the gate filling structure 45 .

[0184] In step 29, a metal material is deposited in the gate region to form a second gate structure 124 and a fourth gate structure 144, and the Fig.31 The structure shown.

[0185] In the 30th step, the second gate structure 124 and the fourth gate structure 144 are etched by a gate removal process to form a back gate isolation groove, and an insulating material is deposited in the back gate isolation groove to form a back gate isolation structure 46, so as to obtain Fig.32 The structure shown.

[0186] It can be understood that the back gate isolation structure 46 is used to electrically isolate the second gate structure 124 from the fourth gate structure 144 .

[0187] In the 31st step, the second interlayer dielectric layer 123 is etched to form a back source-drain metal through hole, and a metal material is deposited in the back source-drain metal through hole to form a second source-drain metal 125; a dielectric material is deposited on the second gate structure 124, the fourth gate structure 144 and the second source-drain metal 125 to form a back dielectric layer 47. A back metal interconnection layer 126 is formed on the back dielectric layer 47 to obtain Fig.33 The structure shown.

[0188] It should be noted that, since the back metal interconnection layer 126 is formed before the front gate structure, the back metal interconnection layer 126 can be made of high temperature resistant materials in most cases.

[0189] Step 32: deposit an insulating material on the back metal interconnect layer 126 to form a second insulating layer 48, and bond the second insulating layer 48 to the second carrier wafer 49. Flip the second carrier wafer 49, remove the first carrier wafer 40 and the first insulating layer 39, and obtain Fig.34 The structure shown.

[0190] Here, after the first carrier wafer 40 and the first insulating layer 39 are removed, the gate filling structure 45 may be exposed.

[0191] Step 33: remove the gate filling structure 45 to obtain Fig.35 The structure shown.

[0192] In step 34, a metal material is deposited in the gate region to form a first gate structure 114 and a third gate structure 134, and a Fig.36 The structure shown.

[0193] In some embodiments, during the formation of the first gate structure 114 and the third gate structure 134 , the gate dielectric layer and the high-resistance metal material layer may be etched as needed to reduce parasitic capacitance and resistance.

[0194] In the thirty-fifth step, the first gate structure 114 and the third gate structure 134 are etched by a gate removal process to form a front gate isolation groove, and an insulating material is deposited in the front gate isolation groove to form a front gate isolation structure 50, so as to obtain Fig.37 The structure shown.

[0195] It can be understood that the front gate isolation structure 50 is used to electrically isolate the first gate structure 114 from the third gate structure 134 .

[0196] Step 36: The first interlayer dielectric layer 113 is etched to form a front source-drain metal through hole, and a metal material is deposited in the front source-drain metal through hole to form a first source-drain metal 115; a dielectric material is deposited on the first gate structure 114, the third gate structure 134 and the first source-drain metal 115 to form a front dielectric layer 51. A front metal interconnection layer 116 is formed on the front dielectric layer 51 to obtain a Fig.38 The structure shown.

[0197] It can be understood that the first gate structure 114 and the first source-drain structure 112 and the first interlayer dielectric layer 113 corresponding to the first semiconductor unit 41 constitute the first transistor 11; the second gate structure 124 and the second source-drain structure 122 and the second interlayer dielectric layer 123 corresponding to the first semiconductor unit 41 constitute the first transistor 11; the third gate structure 134 and the first source-drain structure 112 and the first interlayer dielectric layer 113 corresponding to the second semiconductor unit 42 constitute the third transistor 13; the fourth gate structure 144 and the second source-drain structure 122 and the second interlayer dielectric layer 123 corresponding to the second semiconductor unit 42 constitute the fourth transistor 14. The first transistor 11 and the second transistor 12 constitute the first stacked transistor 101, and the third transistor 13 and the fourth transistor 14 constitute the second stacked transistor 102. Among them, the first stacked transistor 101 has a split-gate structure, and the second stacked transistor 102 has a common-gate structure.

[0198] It should be noted that the types of structures such as the gate structure, the source-drain structure, and the isolation structure in the first transistor 11 , the second transistor 12 , the third transistor 13 , and the fourth transistor 14 are not limited.

[0199] At this point, the stacked transistor in the embodiment of the present application is completed.

[0200] In the embodiment of the present application, a two-time flipping scheme is adopted, taking into account the preparation order of the stacked transistor device structure and its back-end interconnection structure, thereby improving the thermal budget of the overall device preparation process; on the basis of the two flippings, a photolithography patterning method is used to realize the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure in two adjacent units on the same wafer, thereby bringing about the possibility of more flexible design methods and further miniaturization of circuit standard units; at the same time, the process complexity and device failure rate are reduced by integrally forming the gate dielectric layer and depositing the gate filling structure.

[0201] Figure 39 to Figure 40 FIG. 1 is a schematic diagram of a preparation process of a second stacked transistor according to an embodiment of the present application. For ease of understanding, Figure 39 to Figure 40 (a) shows the Figure 2 The cross-sectional view along the dashed line AA'. Figure 39 to Figure 40 (b) shows the Figure 2 The cross-sectional view along the dotted line BB', Figure 39 to Figure 40 (c) shows the Figure 2 The cross-sectional view along the dotted line CC'. Figures 1 to 40 The manufacturing process of the stacked transistor shown is used as a specific example to illustrate the manufacturing method of the stacked transistor in the present application.

[0202] The first step is the same as the first to thirtieth steps in the above specific example, which can be found in Figures 3 to 32 For the sake of brevity of the specification, the structure shown will not be described in detail here.

[0203] The second step is Fig.32 On the basis of the structure shown in FIG. 1 , an insulating material is deposited on the second gate structure 124 and the fourth gate structure 144 to form a second insulating layer 48, and the second insulating layer 48 is bonded to the second carrier wafer 49. The second carrier wafer 49 is flipped over, and the first carrier wafer 40 and the first insulating layer 39 are removed to expose the gate filling structure 45. After the gate filling structure 45 is exposed, the same steps 33 to 36 in the above specific example are used until the front metal interconnection layer 116 is prepared to obtain. Fig.39 The structure shown.

[0204] In the third step, an insulating material is deposited on the front metal interconnection layer 116 to form a third insulating layer 52, and the third insulating layer 52 is bonded to the third carrier wafer 53. The third carrier wafer 53 is flipped over, and the second carrier wafer 49 and the second insulating layer 48 are removed to expose the second gate structure 124 and the fourth gate structure 144. A dielectric material is deposited on the second gate structure 124, the fourth gate structure 144 and the second source and drain metal 125 to form a back dielectric layer 47. A back metal interconnection layer 126 is formed on the back dielectric layer 47 to obtain a back dielectric layer 47. Fig.40 The structure shown.

[0205] It should be noted that compared with the two-time flipping solution, since the metal interconnection layer is prepared after the gate structure is prepared, structures such as the front metal interconnection layer 116 and the back metal interconnection layer 126 do not need to be prepared using high-temperature resistant materials, thereby effectively reducing the preparation cost.

[0206] At this point, the stacked transistor in the embodiment of the present application is completed.

[0207] In the embodiment of the present application, a three-time flipping scheme is adopted, taking into account the preparation order of the stacked transistor device structure and its back-end interconnection structure, thereby improving the thermal budget of the overall device preparation process; on the basis of the three-time flipping, a photolithography patterning method is used to realize the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure in two adjacent units on the same wafer, thereby bringing about the possibility of more flexible design methods and further miniaturization of circuit standard units; at the same time, the process complexity and device failure rate are reduced by integrally forming the gate dielectric layer and depositing the gate filling structure.

[0208] In a second aspect, a stacked transistor is provided in an embodiment of the present application. The stacked transistor can be used Figure 1 The method of one or more corresponding embodiments is prepared. Fig.38 and Fig.40 As shown, the stacked transistor 10 includes: a first stacked transistor 101 and a second stacked transistor 102 arranged adjacent to each other in a first direction. The first stacked transistor 101 includes: a first transistor 11 and a second transistor 12 arranged opposite to each other along a second direction; a gate isolation layer 27 is formed between a first gate structure 114 of the first transistor 11 and a second gate structure 124 of the second transistor 12, and the gate isolation layer 27 is used to electrically isolate the first gate structure 114 from the second gate structure 124; the second stacked transistor 102 includes: a third transistor 13 and a fourth transistor 14 arranged opposite to each other along the second direction; a third gate structure 134 of the third transistor 13 and a fourth gate structure 144 of the fourth transistor 14 are connected.

[0209] It can be understood that the first stacked transistor 101 and the second stacked transistor 102 can be two adjacent transistors, or can be understood as transistors in two adjacent rows. The gate structure of the upper and lower layers of transistors in the first stacked transistor 101 is a split-gate structure, and the gate structure of the upper and lower layers of transistors in the second stacked transistor 102 is a common-gate structure, thereby increasing the flexibility of circuit design, so that the circuit standard unit and the circuit as a whole can be further miniaturized.

[0210] Further, see Fig.38 or Fig.40 As shown, there is a gate isolation layer 27 in the middle of the front and back gate structures of the first stacked transistor 101 , and there is no gate isolation layer 27 in the middle of the front and back gate structures of the second stacked transistor 102 .

[0211] In some embodiments, each of the first transistor 11, the second transistor 12, the third transistor 13 and the fourth transistor 14 is any one of a fin field effect transistor, a full-surround gate field effect transistor, a vertical field effect transistor (VTFET), a complementary field effect transistor, a forksheet transistor and a planar field effect transistor, which is not limited in the embodiments of the present application.

[0212] It can be understood that the scheme of multiple flipping is adopted, the preparation order of the stacked transistor device structure and its back-end interconnection structure is taken into consideration, and the thermal budget of the overall device preparation process is improved; on the basis of multiple flipping, the photolithography patterning method is used to realize the simultaneous preparation of stacked transistors with a split-gate structure and stacked transistors with a common-gate structure in two adjacent units on the same wafer, which brings more flexible design methods and the possibility of further miniaturization of circuit standard units; at the same time, the process complexity and device failure rate are reduced by integrally forming the gate dielectric layer and depositing the gate filling structure.

[0213] Finally, the solution of realizing upper and lower transistors by flipping the chip is compatible with the existing mainstream device architecture, and can realize the front and back stacking of planar field effect transistors, fin field effect transistors, all-around gate field effect transistors, fork-plate transistors and even vertical field effect transistors without the need for special process development for specific device architectures. It is highly flexible and has strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, is highly practical, and has broad prospects for expansion.

[0214] In a third aspect, an embodiment of the present application provides a semiconductor device, including: a stacked transistor as in the above embodiment. The specific definition of the stacked transistor can be found in the above Fig.38 and Fig.40 The stacked transistors shown are not described in detail here.

[0215] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device comprises the above stacked transistor. The specific definition of the stacked transistor can be found in the above Fig.38 and Fig.40 The structure shown will not be described in detail here.

[0216] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0217] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The stacked transistor includes a first semiconductor unit and a second semiconductor unit, wherein the first semiconductor unit and the second semiconductor unit are adjacently arranged in a first direction; The first semiconductor unit and the second semiconductor unit each include: a first active structure and a second active structure stacked along a second direction, a first dummy gate structure corresponding to the first active structure, a first source-drain structure corresponding to the first active structure, a second dummy gate structure corresponding to the second active structure, and a second source-drain structure corresponding to the second active structure; wherein a gate isolation layer is formed between the first dummy gate structure and the second dummy gate structure; Wherein, the method comprises: removing the second dummy gate structure to expose the second active structure and the gate isolation layer; Coating a photoresist on the second active structure and the gate isolation layer in the first semiconductor unit, and removing at least the gate isolation layer in the second semiconductor unit by a photolithography process; removing the first dummy gate structure and the photoresist in sequence to expose the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit; Based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, a first gate structure and a second gate structure are formed, and based on the first active structure and the second active structure in the second semiconductor unit, a third gate structure and a fourth gate structure are formed; Among them, the gate isolation structure in the first semiconductor structure is located between the first gate structure and the second gate structure, and the third gate structure and the fourth gate structure are connected; the first gate structure and the first source-drain structure in the first semiconductor structure constitute a first transistor, the second gate structure and the second source-drain structure in the first semiconductor structure constitute a second transistor, the third gate structure and the first source-drain structure in the second semiconductor structure constitute a third transistor, and the fourth gate structure and the second source-drain structure in the second semiconductor structure constitute a fourth transistor; the first transistor and the second transistor constitute a first stacked transistor, and the third transistor and the fourth transistor constitute a second stacked transistor.

2. The method according to claim 1, characterized in that The forming of the first gate structure and the second gate structure based on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and the forming of the third gate structure and the fourth gate structure based on the first active structure and the second active structure in the second semiconductor unit at the same time, comprises: Depositing a dielectric material on the first active structure, the gate isolation layer and the second active structure in the first semiconductor unit, and the first active structure and the second active structure in the second semiconductor unit to form a gate dielectric layer; Based on the second active structure covered with the gate dielectric layer, forming the second gate structure and the fourth gate structure respectively; Based on the first active structure covered with the gate dielectric layer, the first gate structure and the third gate structure are formed respectively.

3. The method according to claim 2, characterized in that The stacked transistor further comprises: a first carrier wafer; the first semiconductor unit and the second semiconductor unit further comprise: a first interlayer dielectric layer wrapping the first source-drain structure; the first interlayer dielectric layer is connected to the first carrier wafer; Wherein, the second gate structure and the fourth gate structure are formed based on the second active structure covered with the gate dielectric layer, respectively, including: Depositing a semiconductor material on the first carrier wafer to form a gate filling structure, wherein the gate filling structure encapsulates the first active structure in the first semiconductor unit, and the second active structure and the gate isolation layer in the first semiconductor unit are exposed outside the gate filling structure; the gate filling structure encapsulates the first active structure in the second semiconductor unit, and the second active structure in the second semiconductor unit is exposed outside the gate filling structure; A gate metal material is deposited on the gate isolation layer in the first semiconductor unit and the initial gate filling structure in the second semiconductor unit to form the second gate structure and the fourth gate structure respectively, wherein the second gate structure is connected to the gate isolation layer in the first semiconductor unit.

4. The method according to claim 3, characterized in that After forming the second gate structure and the fourth gate structure based on the second active structure covered with the gate dielectric layer, the method further includes: forming a back source-drain metal on the second source-drain structure; forming a back metal interconnection layer on the second gate structure, the fourth gate structure and the back source and drain metal; bonding the backside metal interconnect layer to a second carrier wafer; The first carrier wafer is flipped over and removed to expose the gate filling structure.

5. The method according to claim 3, characterized in that: The first semiconductor unit and the second semiconductor unit also include: a second interlayer dielectric layer wrapping the second source-drain structure; Wherein, after forming the second gate structure and the fourth gate structure respectively based on the second active structure covered with the gate dielectric layer, the method comprises: Forming a second carrier wafer on the second gate structure, the fourth gate structure and the second interlayer dielectric layer; The first carrier wafer is flipped over and removed to expose the gate filling structure.

6. The method according to claim 3, characterized in that After forming the second gate structure and the fourth gate structure based on the second active structure covered with the gate dielectric layer, the method further includes: Using a fin cutting process, etching the second gate structure and the fourth gate structure to form a back side isolation groove, wherein the back side isolation groove is at least located between the second gate structure and the fourth gate structure; An insulating material is deposited in the back isolation groove to form a back gate isolation structure.

7. The method according to any one of claims 3 or 6, characterized in that: The first gate structure and the third gate structure are formed based on the first active structure covered with the gate dielectric layer, respectively, including: removing the gate filling structure to expose the gate isolation layer and the fourth gate structure in the first semiconductor unit respectively; A gate metal material is deposited on the exposed gate isolation layer in the first semiconductor unit and the fourth gate structure to form the first gate structure and the third gate structure respectively, wherein the first gate structure is connected to the gate isolation layer in the first semiconductor unit.

8. The method according to claim 7, characterized in that After forming the first gate structure and the third gate structure based on the first active structure covered with the gate dielectric layer, the method further includes: forming a front source-drain metal on the first source-drain structure; A front metal interconnection layer is formed on the first gate structure, the third gate structure and the front source and drain metal.

9. The method according to claim 8, characterized in that In the case where a back metal interconnection layer is not formed, after forming the front metal interconnection layer, the method further comprises: Bonding the front metal interconnect layer to a third carrier wafer; Flipping and removing the second carrier wafer to expose the second gate structure, the fourth gate structure and the second interlayer dielectric layer; forming a back source-drain metal on the second source-drain structure; A back metal interconnection layer is formed on the second gate structure, the fourth gate structure and the back source and drain metal.

10. The method according to claim 7, characterized in that After forming the first gate structure and the third gate structure based on the first active structure covered with the gate dielectric layer, the method further includes: Using a fin cutting process, etching the first gate structure and the third gate structure to form a front isolation groove, wherein the front isolation groove is at least located between the first gate structure and the third gate structure; An insulating material is deposited in the front isolation groove to form a front gate isolation structure.

11. The method according to claim 1, characterized in that: The first semiconductor unit and the second semiconductor unit further include: a blocking layer, wherein the blocking layer is located on a side of the second source-drain structure away from the first active structure; The removing at least the gate isolation layer in the second semiconductor unit by a photolithography process comprises: Using the barrier layer as a mask, removing the gate isolation layer in the second semiconductor unit through an anisotropic etching process; Removing a first portion of the first dummy gate structure in the second semiconductor unit by an anisotropic etching process or an isotropic etching process, wherein the first portion corresponds to the gate isolation layer in the second semiconductor unit; The sequentially removing the first dummy gate structure and the photoresist comprises: Removing a second portion of the first dummy gate structure in the second semiconductor unit and the first dummy gate structure in the first semiconductor unit by an isotropic etching process, wherein the second portion and the first portion constitute the first dummy gate structure in the second semiconductor unit; The photoresist is removed.

12. The method according to claim 1, characterized in that Before removing the second dummy gate structure to expose the second source-drain structure and the gate isolation layer, the method further includes: The first semiconductor unit and the second semiconductor unit are formed.

13. The method according to claim 12, characterized in that The forming of the first semiconductor unit and the second semiconductor unit comprises: forming the first active structure and the second active structure on a semiconductor substrate, wherein the second active structure is closer to the semiconductor substrate than the first active structure; forming the second dummy gate structure, a gate isolation layer and the first dummy gate structure in sequence on the semiconductor substrate; Based on the first active structure, forming the first source-drain structure and the first interlayer dielectric layer in sequence; Forming a first carrier wafer on the first dummy gate structure and the first interlayer dielectric layer; Flipping and removing the semiconductor substrate; Based on the second active structure, the second source-drain structure and the second interlayer dielectric layer are formed in sequence.

14. The preparation method according to claim 1, characterized in that: Each of the first transistor, the second transistor, the third transistor and the fourth transistor is: Any of a fin field effect transistor, a gate-all-around field effect transistor, a vertical field effect transistor, a complementary field effect transistor, a fork plate transistor, and a planar field effect transistor.

15. A stacked transistor, prepared by the method according to any one of claims 1 to 14, characterized in that: include: A first stacked transistor and a second stacked transistor disposed adjacent to each other in a first direction; The first stacked transistor includes: a first transistor and a second transistor disposed opposite to each other along a second direction; a gate isolation layer is formed between a first gate structure of the first transistor and a second gate structure of the second transistor, and the gate isolation layer is used to electrically isolate the first gate structure from the second gate structure; The second stacked transistor includes: a third transistor and a fourth transistor which are arranged opposite to each other along a second direction; a third gate structure of the third transistor is connected to a fourth gate structure of the fourth transistor.

16. A semiconductor device, characterized in that: include: The stacked transistor of claim 15.

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