Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate is provided with a display area and a non-display area, the non-display area comprises a binding area, the binding area is located on the side, away from the display area, of the non-display area, and the binding area comprises a plurality of first pins arranged in the first direction; the first pins are arranged in the first direction, the second pins are arranged in the first direction, at least one second pin is located between every two adjacent first pins, signals transmitted by the first pins are different from signals transmitted by the second pins, and the second pins comprise data signal pins. According to the technical scheme, on the premise that the number of the pins is not changed, more data signal pins can be arranged, more data signal lines can be connected, the problem that the transverse arrangement space of the pins is insufficient under the condition of high resolution is effectively solved, and the display effect is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0002] With the development of display technology, the size of display panels is getting larger and larger, and the resolution is getting higher and higher, resulting in more and more data lines providing signals to each column of pixels. Correspondingly, the number of pins bound to the flexible circuit board is increasing, and the space required for the lateral arrangement of the pins is increasing, resulting in the problem of insufficient space for pin arrangement. Summary of the invention

[0003] In order to solve the above problems, embodiments of the present application provide an array substrate, a display panel and a display device.

[0004] In a first aspect, an embodiment of the present application provides an array substrate having a display area and a non-display area, the non-display area including a binding area, the binding area being located on a side of the non-display area away from the display area, the binding area including: a plurality of first pins, the plurality of first pins being arranged along a first direction; a plurality of second pins, the plurality of second pins being arranged along the first direction, at least one second pin being located between two adjacent first pins, wherein a signal transmitted by the first pin is different from a signal transmitted by the second pin, and the second pin includes a data signal pin.

[0005] In combination with the first aspect, the first pin includes a touch signal pin and a gate drive signal pin, at least one second pin is arranged between two adjacent touch signal pins, and at least one second pin is arranged between two adjacent gate drive signal pins; preferably, the multiple touch signal pins include a first group of touch signal pins and a second group of touch signal pins, and the multiple gate drive signal pins include a first group of gate drive signal pins and a second group of gate drive signal pins, and along the first direction, the first group of touch signal pins, the first group of gate drive signal pins, the second group of gate drive signal pins and the second group of touch signal pins are arranged in sequence.

[0006] In combination with the first aspect, the first pin also includes a test signal pin, and at least one second pin is provided between two adjacent test signal pins; preferably, a plurality of test signal pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins; preferably, during testing, the test signal pin is used to be electrically connected to the test equipment; after the test is completed, the signal of the test signal pin is set to a high potential. Since the data signal is an alternating current and is positive, after the signal of the test signal pin is set to a high potential, there will be no signal coupling between the test signal and the data signal, and no ESD problem will occur.

[0007] In combination with the first aspect, the binding area also includes: a plurality of third pins, the plurality of third pins are arranged along the first direction, the third pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins; preferably, the plurality of first pins also include a plurality of test signal pins, some test signal pins are arranged between the third pins and the first group of gate drive signal pins, and some test signal pins are arranged between the third pins and the second group of gate drive signal pins; preferably, the third pins include data signal pins.

[0008] In combination with the first aspect, the binding area includes: a plurality of third pins, the plurality of third pins are arranged along the first direction, the third pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins; preferably, the plurality of first pins also include a plurality of test signal pins, some test signal pins are arranged between the third pins and the first group of gate drive signal pins, and some test signal pins are arranged between the third pins and the second group of gate drive signal pins; preferably, the third pins include electronic signal pins.

[0009] In combination with the first aspect, the binding area includes: a plurality of fourth pins, the plurality of fourth pins are arranged along the first direction, the plurality of fourth pins include a first group of fourth pins and a second group of fourth pins, the first group of fourth pins are located on the side of the first group of touch signal pins away from the first group of gate drive signal pins, and the second group of fourth pins are located on the side of the second group of touch signal pins away from the second group of gate drive signal pins; preferably, the fourth pins include data signal pins. In the embodiment of the present application, the fourth pins are arranged on both sides of the binding area. When the fourth pins are connected to the data signal line, the connection length of the data signal line can be reduced, the voltage drop consumed on the route entering the display area is reduced, the overall impedance is reduced, the output voltage of the flexible circuit board is reduced, the overall power consumption is reduced, and the display uniformity can be improved.

[0010] In combination with the first aspect, the array substrate includes at least one of a touch signal line, a gate drive signal line, and a data signal line; the first pin is connected to at least one of the touch signal line and the gate drive signal line, and the second pin is connected to the data signal line; preferably, the binding area also includes a plurality of third pins, the third pins include data signal pins, and the third pins are connected to the data signal lines; or, the third pins include electronic signal pins, and the third pins are connected to the electronic signal lines; or, the binding area also includes a plurality of fourth pins, the fourth pins include data signal pins, and the fourth pins are connected to the data signal lines.

[0011] In combination with the first aspect, the first pin and the second pin are used to bind to the flexible circuit board; preferably, the binding area also includes a plurality of third pins, the third pins include data signal pins or electronic signal pins, and the third pins are used to bind to the flexible circuit board; or, the binding area also includes a plurality of fourth pins, the fourth pins include data signal pins, and the fourth pins are used to bind to the flexible circuit board.

[0012] In a second aspect, an embodiment of the present application provides a display panel, comprising the above-mentioned array substrate.

[0013] In a third aspect, an embodiment of the present application provides a display device, comprising the above-mentioned display panel.

[0014] Through the above technical solution, a data signal pin is set between two adjacent first pins, and the data signal pin occupies the position of a virtual pin (i.e., a dummy pin). On the one hand, the originally vacant dummy pin is utilized to improve space utilization; on the other hand, without changing the number of pins, more data signal pins can be set to connect more data signal lines, effectively solving the problem of insufficient lateral arrangement space of pins in the case of high resolution, and improving the display effect. In addition, a second pin 200 (i.e., a data signal pin) is set between two adjacent touch signal pins 110, and a second pin 200 (i.e., a data signal pin) is set between two adjacent gate drive signal pins 120, without setting a virtual pin, and signal transmission will not be affected. Since the touch signal is transmitted through the touch metal layer (TP-SY / TP-SX), and the data signal is transmitted through the first metal layer M1 and / or the second metal layer M2, the touch metal layer is far away from the film layer of the first metal layer M1 or the second metal layer M2, and signal coupling or interference problems will not occur. The gate drive signal is transmitted through the third metal layer M3. A thicker insulating layer is provided between the third metal layer M3 and the first metal layer M1 and the second metal layer M2, and signal coupling or interference problems will not occur. In addition, when performing signal testing, the touch signal pin needs to be led to the bottom of the array substrate to set the test pad, and the data signal pin does not need to be led to the bottom of the array substrate. Since a certain interval is provided between adjacent touch signal pins, after the test is completed, when the lead extending from the touch signal pin is cut, there will be no problem of cutting short circuit. In addition, there is no problem of pulling or coupling between the potential of the touch signal or the gate drive signal and the potential in the digital signal, and no electrostatic discharge (ESD) problem will occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of an array substrate provided in one embodiment of the present application.

[0016] Figure 2 yes Figure 1 Schematic diagram of the structure of part of the binding region is shown.

[0017] Figure 3 yes Figure 1 Schematic diagram of the structure of part of the binding region is shown.

[0018] Figure 4 yes Figure 1 Schematic diagram of the structure of part of the binding region is shown.

[0019] Figure 5 It is a structural schematic diagram of a binding area of ​​an array substrate provided in one embodiment of the present application.

[0020] Figure 6 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application.

[0021] Figure 7 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application.

[0022] Figure 8 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application.

[0023] Fig. 9 It is a schematic diagram of the structure of a display device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0025] At present, people have higher and higher requirements for the resolution of display panels, resulting in an increasing number of pins for binding flexible circuit boards. However, the increase in the width of the lower frame is limited. After growing to the limit value, there will be insufficient space for the pins to be arranged horizontally. The inventor has found that in the existing scheme, the arrangement of the pins for binding flexible circuit boards is divided into regions. For example, the touch signal pin and the gate drive signal pin are respectively arranged on both sides of the data signal pin, and there are virtual pins (i.e., dummy pins) inside the region due to high and low signal pressure differences, fixed intervals, etc. For example, between the sending signal pin (Tx pin) and the receiving signal pin (Rx pin) of the touch signal, due to the high and low signal pressure difference, a certain interval needs to be set, and a dummy pin is usually set between the Tx pin and the Rx pin; for another example, the gate drive signal pin sends multiple clock signals, and in order to avoid coupling between signals, a dummy pin is usually set between the clock signals. These virtual pins do not transmit signals, but occupy the space of the lower frame, resulting in space waste.

[0026] In the face of the technical problem of insufficient space for lateral arrangement of pins, an embodiment of the present application provides an array substrate, the array substrate having a display area and a non-display area, the non-display area including a binding area, the binding area being located on the side of the non-display area away from the display area, the binding area including: a plurality of first pins, the plurality of first pins being arranged along a first direction; a plurality of second pins, the plurality of second pins being arranged along a first direction, at least one second pin being located between two adjacent first pins, wherein the signal transmitted by the first pin is different from the signal transmitted by the second pin, and the second pin includes a data signal pin. In an embodiment of the present application, a data signal pin is arranged between two adjacent first pins, and the data signal pin occupies the position of a virtual pin (i.e., a dummy pin). On the one hand, the originally vacant dummy pin is utilized to improve the utilization space; on the other hand, without changing the number of pins, more data signal pins can be arranged to connect more data signal lines, effectively solving the problem of insufficient lateral arrangement space of pins under high resolution and improving the display effect.

[0027] Figure 1 It is a structural schematic diagram of an array substrate provided in one embodiment of the present application. Figure 2 yes Figure 1 The schematic diagram of the structure of the partial binding region is shown in FIG. Figure 1 As shown, the array substrate includes a display area AA and a non-display area NA. The non-display area NA includes a binding area BA. The binding area BA is located at a side of the non-display area away from the display area AA.

[0028] like Figure 2 As shown, the binding area BA includes a plurality of first pins 100 and a plurality of second pins 200, the plurality of first pins 100 are arranged along a first direction (i.e., the x direction), the plurality of second pins 200 are arranged along the first direction (i.e., the x direction), and the second pin 200 is located between two adjacent first pins 100, wherein the signal transmitted by the first pin 100 is different from the signal transmitted by the second pin 200, and the second pin 200 includes a data signal pin. Exemplarily, the first pin 100 includes at least one of a touch signal pin and a gate drive signal pin. It can be understood that the embodiment of the present application does not limit the number of second pins 200 set between two adjacent first pins 100. Figure 2 In the embodiment, a second pin 200 is arranged between two adjacent first pins 100, and a plurality of second pins 200 may be arranged between two adjacent first pins 100, for example, two second pins 200 (such as Figure 3 As shown), three second pins 200, four second pins 200, etc. Optionally, in different areas of the binding area BA, the number of second pins 200 provided between two adjacent first pins 100 may be different, for example, Figure 4As shown, in the first area, one second pin 200 is arranged between two adjacent first pins 100 , in the second area, two second pins 200 are arranged between two adjacent first pins 100 , in the third area, three second pins 200 are arranged between two adjacent first pins 100 , and so on.

[0029] The technical solution of the present application is explained below with reference to specific embodiments.

[0030] Figure 5 FIG. 1 is a schematic diagram of the structure of the binding area of ​​the array substrate provided by an embodiment of the present application. Figure 5 As shown, the first pin 100 includes a touch signal pin 110 and a gate drive signal (Gate In Panel, GIP) pin 120. The touch signal pin 110 is used to connect the touch signal line to transmit the touch signal, and the gate drive signal pin 120 is used to connect the gate drive signal line to transmit the gate drive signal. At least one second pin 200 is arranged between two adjacent touch signal pins 110, and at least one second pin 200 is arranged between two adjacent gate drive signal pins 120. Optionally, the plurality of touch signal pins 110 include a first group of touch signal pins 111 and a second group of touch signal pins 112, and the plurality of gate drive signal pins 120 include a first gate drive signal pin 121 and a second gate drive signal pin 122. Along the first direction (i.e., the x direction), the first group of touch signal pins 111, the first group of gate drive signal pins 121, the second group of gate drive signal pins 122, and the second group of touch signal pins 112 are arranged in sequence.

[0031] In the embodiment of the present application, a second pin 200 (i.e., a data signal pin) is set between two adjacent touch signal pins 110, and a second pin 200 (i.e., a data signal pin) is set between two adjacent gate drive signal pins 120. There is no need to set a virtual pin, and signal transmission will not be affected. Since the touch signal is transmitted through the touch metal layer (TP-SY / TP-SX), and the data signal is transmitted through the first metal layer M1 and / or the second metal layer M2, the touch metal layer is far away from the film layer of the first metal layer M1 or the second metal layer M2, and signal coupling or interference problems will not occur. The gate drive signal is transmitted through the third metal layer M3, and a thicker insulating layer is set between the third metal layer M3 and the first metal layer M1 and the second metal layer M2, and signal coupling or interference problems will not occur. In addition, when performing signal testing, the touch signal pins need to be wired to the bottom of the array substrate to set up the test pad, and the data signal pins do not need to be wired to the bottom of the array substrate. Since there is a certain interval between adjacent touch signal pins, when the wires extending from the touch signal pins are cut after the test is completed, there will be no problem of cutting short circuits. In addition, there is no problem of pulling or coupling between the potential of the touch signal or gate drive signal and the potential in the digital signal, and no electrostatic discharge (ESD) problem will occur.

[0032] exist Figure 5 In the figure, for the sake of illustration, the first group of touch signal pins 111 only shows two touch signal pins 110. It can be understood that the first group of touch signal pins 111 can include multiple Tx pins and Rx pins; similarly, the second group of touch signal pins 112 can also include multiple Tx pins and Rx pins. The first group of gate drive signal pins 121 only shows three gate drive signals. It can be understood that the first group of gate drive signal pins 121 can include multiple gate drive signal pins 120, for example, an input signal SIN pin, a first clock signal SCK1 pin, a second clock signal SCK2 pin, ... an nth clock signal SCKn pin. Similarly, the second group of gate drive signal pins 122 can include multiple gate drive signal pins 120, for example, an input signal SIN pin, a first clock signal SCK1 pin, a second clock signal SCK2 pin, ... an nth clock signal SCKn pin.

[0033] Continue to refer Figure 5 The binding area BA also includes a plurality of third pins 300 , which are arranged along the first direction (x direction) and are located between the first group of gate driving signal pins 121 and the second group of gate driving signal pins 122 . Figure 5The number of the third pins 300 in is only an example. It can be understood that the number of the third pins 300 is related to the size and resolution of the display panel. The larger the size of the display panel and the higher the resolution, the more the number of the third pins 300. In the embodiment of the present application, if the driver chip is arranged on a flexible circuit board (i.e., Chip On FPC, COP product), the third pin 300 includes a data signal pin for connecting a data signal line. If the driver chip is arranged on a display panel (i.e., Chip On Panel, COF product), the third pin 300 includes an electronic signal pin for connecting the driver chip to the electronic signal line of the flexible circuit board.

[0034] Figure 6 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application. Figure 6 The binding region shown is Figure 5 The difference of the binding area shown is that the first pin also includes a test signal pin 130, and at least one second pin 200 is provided between two adjacent test signal pins 130. In the embodiment of the present application, during the test, the test signal pin 130 is used to be electrically connected to the test equipment to test the signal line on the array substrate. After the test is completed, the signal of the test signal pin 130 is set to a high potential. Since the data signal is an alternating current and is positive, after the signal of the test signal pin 130 is set to a high potential, there will be no signal coupling between the test signal and the data signal, and no ESD problem will occur.

[0035] In the embodiment of the present application, the test signal pin 130 is located between the first group of gate drive signal pins 121 and the second group of gate drive signal pins 122. Specifically, part of the test signal pin 130 is located between the third pin 300 and the first group of gate drive signal pins 121; part of the test signal pin 130 is located between the third pin 300 and the second group of gate drive signal pins 122.

[0036] Figure 7 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application. Figure 8 It is a structural schematic diagram of a binding area of ​​an array substrate provided in yet another embodiment of the present application. Figure 7 The binding region shown is Figure 5 The differences in the binding regions shown, and Figure 8 The binding region shown is Figure 6The difference between the binding areas shown is that the binding area BA includes a plurality of fourth pins 400, and the plurality of fourth pins 400 are arranged along the first direction (i.e., the x direction). The plurality of fourth pins 400 include a first group of fourth pins 401 and a second group of fourth pins 402, the first group of fourth pins 401 is located on the side of the first group of touch signal pins 111 away from the first group of gate drive signal pins 121, and the second group of fourth pins 402 is located on the side of the second group of touch signal pins 112 away from the second group of gate drive signal pins 122. Optionally, the fourth pins 400 include data signal pins. In the embodiment of the present application, the fourth pins 400 are arranged on both sides of the binding area BA. When the fourth pins 400 are connected to the data signal line, the connection length of the data signal line can be reduced, the voltage drop consumed on the route entering the display area AA is reduced, the overall impedance is reduced, the output voltage of the flexible circuit board is reduced, the overall power consumption is reduced, and the display uniformity can be improved.

[0037] In an embodiment of the present application, the array substrate includes at least one of a touch signal line, a gate drive signal line, and a data signal line. The first pin 100 is connected to at least one of the touch signal line and the gate drive signal line, and the second pin 200 is connected to the data signal line. In an embodiment of the present application, the binding area BA includes a plurality of third pins 300, the third pin 300 includes a data signal pin, and the third pin 300 can also be connected to the data signal line. Alternatively, the third pin 300 includes an electronic signal pin, and the third pin 300 is connected to the electronic signal line to achieve electrical connection between the flexible circuit board and the driver chip. Alternatively, the binding area BA includes a plurality of fourth pins 400, the fourth pin 400 includes a data signal pin, and the fourth pin 400 is connected to the data signal line.

[0038] Optionally, the first pin 100 and the second pin 200 are used to bind with the flexible circuit board. Optionally, the binding area BA may include a plurality of third pins 300, the third pins 300 include data signal pins or electronic signal pins, and the third pins 300 are used to bind with the flexible circuit board. Alternatively, the binding area BA includes a plurality of fourth pins 400, the fourth pins 400 include data signal pins, and the fourth pins 400 are used to bind with the flexible circuit board.

[0039] In a second aspect, an embodiment of the present application provides a display panel, which includes the above-mentioned array substrate.

[0040] In a third aspect, an embodiment of the present application provides a display device, which includes the display panel described in the above embodiment.

[0041] Fig. 9 is a schematic diagram of the structure of a display device provided by an embodiment of the present application. Fig. 9As shown, the display device 900 is a product with an image display function. For example, the display device 900 can be used to display static images, such as pictures or photos. The display device 900 can also be used to display dynamic images, such as videos.

[0042] The display device 900 may be a laptop computer, a mobile phone, a handheld or portable computer, a camera, a camcorder, a vehicle-mounted smart central control screen, a calculator, a smart watch, a GPS navigator, an electronic photo, an electronic billboard or sign, a projector, etc.

[0043] The display device 900 includes a display panel provided by any of the above embodiments, which may be an organic light emitting diode display panel or a quantum dot electroluminescent display panel.

[0044] In addition, the display device 900 may also have functions such as taking pictures, recording videos, fingerprint recognition, and face recognition. Accordingly, the display device 900 also includes at least one functional module for implementing the above functions, such as an under-screen camera, an under-screen fingerprint recognition sensor, and the like.

[0045] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0046] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.

[0047] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.

[0048] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0049] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: The non-display area includes a display area and a non-display area. The non-display area includes a binding area. The binding area is located at a side of the non-display area away from the display area. The binding area includes: A plurality of first pins, wherein the plurality of first pins are arranged along a first direction; A plurality of second pins are arranged along the first direction, at least one of the second pins is located between two adjacent first pins, wherein the signal transmitted by the first pin is different from the signal transmitted by the second pin, and the second pin includes a data signal pin.

2. The array substrate according to claim 1, characterized in that: The first pins include a touch signal pin and a gate drive signal pin, at least one second pin is arranged between two adjacent touch signal pins, and at least one second pin is arranged between two adjacent gate drive signal pins; Preferably, the plurality of touch signal pins include a first group of touch signal pins and a second group of touch signal pins, and the plurality of gate drive signal pins include a first group of gate drive signal pins and a second group of gate drive signal pins, and along the first direction, the first group of touch signal pins, the first group of gate drive signal pins, the second group of gate drive signal pins and the second group of touch signal pins are arranged in sequence.

3. The array substrate according to claim 2, characterized in that: The first pins also include a test signal pin, and at least one second pin is arranged between two adjacent test signal pins; Preferably, the plurality of test signal pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins; Preferably, during testing, the test signal pin is used to be electrically connected to a test device; after the test is completed, the signal of the test signal pin is set to a high potential.

4. The array substrate according to claim 2, characterized in that: The binding area further includes: a plurality of third pins, the plurality of third pins are arranged along the first direction, the third pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins; the third pins include data signal pins; Preferably, the plurality of first pins further include a plurality of test signal pins, some of the test signal pins are arranged between the third pin and the first group of gate drive signal pins, and some of the test signal pins are arranged between the third pin and the second group of gate drive signal pins.

5. The array substrate according to claim 2, characterized in that: The binding area includes: a plurality of third pins, the plurality of third pins are arranged along the first direction, the third pins are located between the first group of gate drive signal pins and the second group of gate drive signal pins, and the third pins include electronic signal pins; Preferably, the plurality of first pins further include a plurality of test signal pins, some of the test signal pins are arranged between the third pin and the first group of gate drive signal pins, and some of the test signal pins are arranged between the third pin and the second group of gate drive signal pins.

6. The array substrate according to claim 2, characterized in that: The binding area comprises: a plurality of fourth pins, the plurality of fourth pins are arranged along the first direction, the plurality of fourth pins comprise a first group of fourth pins and a second group of fourth pins, the first group of fourth pins are located on a side of the first group of touch signal pins away from the first group of gate drive signal pins, and the second group of fourth pins are located on a side of the second group of touch signal pins away from the second group of gate drive signal pins; Preferably, the fourth pin comprises a data signal pin.

7. The array substrate according to claim 1, characterized in that: The array substrate includes at least one of a touch signal line, a gate drive signal line, and a data signal line; The first pin is connected to at least one of the touch signal line and the gate drive signal line, and the second pin is connected to the data signal line; Preferably, the binding area further comprises a plurality of third pins, wherein the third pins comprise data signal pins, and the third pins are connected to the data signal lines; or, the third pins comprise electronic signal pins, and the third pins are connected to the electronic signal lines; Alternatively, the binding area further includes a plurality of fourth pins, the fourth pins include data signal pins, and the fourth pins are connected to the data signal lines.

8. The array substrate according to claim 1, characterized in that: The first pin and the second pin are used to bind to the flexible circuit board; Preferably, the binding area further comprises a plurality of third pins, the third pins comprising data signal pins or electronic signal pins, and the third pins are used to bind to the flexible circuit board; or, The binding area further includes a plurality of fourth pins, wherein the fourth pins include data signal pins, and the fourth pins are used to bind to the flexible circuit board.

9. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 8.

10. A display device, characterized in that: Comprising the display panel as claimed in claim 9.

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