An integrated electrostatic surge protection circuit for a highly reliable high-voltage driver chip

Abstract

This invention belongs to the field of electrostatic discharge (ESD) and electrical overstress (EOS) pulse protection for integrated circuits. Specifically, it provides an integrated ESD and surge protection circuit for a high-reliability high-voltage driver chip, addressing issues such as easy latch-up, high trigger voltage, poor robustness, and slow turn-on speed in traditional high-voltage ESD / EOS protection solutions. This invention technically embeds an SCR structure, a Zener structure, and an LDMOS structure, integrating the voltage clamping capability of a Zener diode, the high withstand voltage capability of an LDMOS, the fast response characteristics of a composite transistor, and the strong current dissipation capability of an SCR. This achieves integrated ESD and surge protection. Under ESD / EOS electrical stress, the composite structure in this invention promotes the orderly turn-on of the Zener, SCR, and LDMOS structures through positive feedback, thereby meeting the ESD and EOS protection requirements for different pulse frequencies. This not only significantly reduces hysteresis and trigger voltage but also effectively avoids latch-up.

Description

Technical Field

[0001] This invention belongs to the field of electrostatic discharge (ESD) and electrical over-stress (EOS) pulse protection for integrated circuits (ICs). Specifically, it provides an integrated ESD / EOS protection circuit with high voltage resistance and low hysteresis characteristics, which can be applied to the electrostatic and surge protection of high voltage drive chips in complex electromagnetic environments, so as to improve the reliability, stability and service life of the chip and its application system. Background Technology

[0002] Electrostatic discharge (ESD), also known as surge, is a major cause of electronic equipment failure. High-voltage driver chips are widely used in industrial control, power electronics, and automotive electronics, and need to withstand high voltage and high power operating conditions in complex electromagnetic environments. This places higher demands on the transient overvoltage tolerance and long-term reliability of high-voltage driver chips; however, current ESD / EOS protection technologies for high-voltage driver chips still face many challenges.

[0003] Due to their simple structure and good process compatibility, traditional bijunction transistors, gate-grounded NMOS, and gate-connected power PMOS are widely used for high-voltage ESD / EOS protection. However, their poor current conduction uniformity and weak current discharge capacity per unit area make them difficult to meet the high reliability requirements of high-voltage driver chips. SCR structures exhibit advantages in high-voltage applications due to their excellent current discharge capability and high robustness. However, their high trigger voltage and large hysteresis voltage amplitude after turn-on may prevent timely response under transient stress, or trigger latch-up effects, leading to the burnout of the protected circuit or signal turbulence under ESD / EOS stress. Zener diodes, as a voltage regulator structure, have good voltage clamping characteristics and can effectively suppress large hysteresis, preventing circuit damage or latch-up. However, when using Zener structures alone, their voltage withstand and overcurrent capabilities are limited, making it difficult to meet the electrostatic discharge and surge protection requirements in high-voltage environments. Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in high-voltage drive circuits due to their excellent thermal stability and high withstand voltage characteristics. LDMOS devices not only maintain stable performance under high temperature and high power conditions, but also improve the switching efficiency, reduce on-resistance, and enhance the circuit's anti-interference capability. Based on this, this invention provides an integrated electrostatic discharge (ESD) surge protection circuit for a high-reliability high-voltage drive chip, to meet the high-reliability ESD / EOS integrated protection requirements of high-voltage drive chips in complex electromagnetic environments. Summary of the Invention

[0004] The purpose of this invention is to provide a highly reliable integrated electrostatic discharge (ESD) and surge protection circuit for high-voltage driver chips, addressing issues such as latch-up, high trigger voltage, poor robustness, and slow turn-on speed in traditional high-voltage ESD / EOS protection solutions. This invention technically embeds an SCR structure, a Zener structure, and an LDMOS structure to form a multi-composite transistor integrated ESD / EOS protection and discharge path, achieving rapid turn-on and anti-latch-up characteristics, and improving the circuit's discharge capability. Specifically, this invention integrates the voltage clamping capability of a Zener diode, the high withstand voltage capability of an LDMOS, the fast response characteristics of a composite transistor, and the strong discharge capability of an SCR, achieving integrated ESD and surge protection performance. Under ESD / EOS electrical stress, the composite structure in this invention promotes the orderly turn-on of the Zener, SCR, and LDMOS structures through positive feedback, thereby meeting the ESD and EOS protection requirements for different pulse frequencies. This not only significantly reduces hysteresis and trigger voltage but also effectively avoids latch-up. Furthermore, this composite structure can be flexibly adjusted according to different protection level requirements, providing an efficient and reliable solution and significantly improving the system reliability and operational stability of the high-voltage driver chip.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip is characterized in that the integrated electrostatic surge protection circuit for the high-reliability high-voltage driver chip is disposed on the same P-type silicon substrate (100).

[0007] The P-type silicon substrate (100) is provided with a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103) from left to right;

[0008] The first P-type epitaxial layer (101) is provided with a first deep P-well (104), the N-type buried layer (102) is provided with a deep N-well (105), and the second P-type epitaxial layer (103) is provided with a second deep P-well (106).

[0009] The first deep P-well (104) region is provided with a first P-well (111), and the first P-well (111) region is provided with a first P+ implantation region (113); the deep N-well (105) region is provided with a first N-well (107), a second P-well (108), and a second N-well (109) from left to right, and the second P-well (108) region is provided with a PB doped layer (110); the first N-well (107) region is provided with a first N+ implantation region (115); the second P-well (108) region is provided with a first P+ implantation region (115) from left to right. There are a second P+ implantation region (116), a second N+ implantation region (117), a third N+ implantation region (118), and a third P+ implantation region (119), and the third N+ implantation region (118) is located in the PB doped layer (110); the second N well (109) region is provided with a fourth P+ implantation region (120) and a fourth N+ implantation region (121) from left to right; the second deep P well (106) region is provided with a third P well (112), and the third P well (112) region is provided with a fifth P+ implantation region (114);

[0010] A polysilicon gate oxide layer (122) is provided between the third P+ implantation region (119) and the fourth P+ implantation region (120), and the polysilicon gate oxide layer (122) is connected across the surfaces of the second P well (108) and the second N well (109).

[0011] The first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the integrated electrostatic surge protection circuit. The first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the integrated electrostatic surge protection circuit.

[0012] Furthermore, in the integrated electrostatic surge protection circuit, the parasitic resistance of the second N-well (109) forms the first resistance R1, and the parasitic resistance of the P-well (108) forms the second resistance R2. The second N-well (109), the P-well (108), and the second N+ injection region (117) constitute an NPN transistor T. n1 The fourth P+ injection region (120), the second N-well (109), and the P-well (108) constitute a PNP transistor. The fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N-well (109), the P-well (108), and the third P+ injection region (119) constitute an LDMOS power transistor M1. The second N+ injection region (117), the PB doped layer (110), and the P-well (108) constitute a Zener transistor Z. D .

[0013] Furthermore, the Zener tube Z D The cathode is connected to the anode of the integrated electrostatic surge protection circuit, and the Zener diode Z... D The anode of the NPN transistor T n1 The base of the second resistor R2 is connected to the base of the PNP transistor T; one end of the second resistor R2 is connected to the anode of the integrated electrostatic surge protection circuit, and the other end is connected to the base of the PNP transistor T. p1 The base of the PNP transistor T is connected to the substrate electrode of the LDMOS power transistor M1. p1 The emitter of the PNP transistor is connected to the anode of the integrated electrostatic surge protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T is connected to the collector of the PNP transistor T. p1 The collector of the NPN transistor T n1 The base of the first resistor R1 is connected to the base of the NPN transistor T; one end of the first resistor R1 is connected to the base of the NPN transistor T. n1 One end is connected to the base, and the other end is connected to the cathode of the integrated electrostatic surge protection circuit; the NPN transistor T n1 The emitter of the LDMOS power transistor M1 is connected to the cathode of the integrated electrostatic surge protection circuit; the source and gate of the LDMOS power transistor M1 are connected to the anode of the integrated electrostatic surge protection circuit, and the drain of the LDMOS power transistor M1 is connected to the cathode of the integrated electrostatic surge protection circuit.

[0014] Furthermore, the integrated electrostatic surge protection circuit includes: a fast-opening path, an SCR main discharge path, and a voltage-regulating clamping path; the fast-opening path includes: a Zener diode Z-channel rectifier. D Second resistor R2, first resistor R1, PNP transistor T p1 With NPN transistor T n1 The SCR main discharge path includes: PNP transistor T p1 NPN transistor T n2 With the first resistor R1; the voltage regulation clamping path includes: Zener diode Z D With LDMOS power transistor M1.

[0015] Based on the above technical solution, the beneficial technical effects of the present invention are as follows:

[0016] This invention provides an integrated electrostatic discharge (ESD) surge protection circuit for a high-reliability high-voltage driver chip. By technically embedding SCR, Zener, and LDMOS structures, a multi-composite transistor ESD / EOS integrated protection and discharge path is formed, achieving fast turn-on and anti-latch-up characteristics, and improving the circuit's discharge capability. Specific advantages are as follows:

[0017] 1) When the ESD or EOS electrical stress is small, the leakage current caused by minority carrier drift in the integrated ESD / EOS protection circuit flows through the Zener diode Z. D The second resistor R2, and the NPN transistor T n1 and the PNP transistor T p1 The common collector junction converges on the first resistor R1 to form a first trigger current. The parasitic NPN transistor composed of the third N+ injection region (118), the PB doped layer (110), the P well (108) and the second N+ injection region (117) can form a second trigger current. The first trigger current and the second trigger current can improve the response speed of the ESD / EOS integrated protection circuit and reduce the trigger voltage.

[0018] 2) When the ESD or EOS electrical stress is large, the voltage across the first resistor R1 in the integrated ESD / EOS protection circuit continuously increases, and the voltage across the NPN transistor T... p1 and the second transistor T p1 Under the positive feedback, the voltage across the second resistor R2 increases continuously, forming an ESD or EOS current discharge channel for the SCR structure, thereby enhancing the robustness of the integrated ESD / EOS protection circuit.

[0019] 3) When the ESD or EOS electrical stress continues to increase, the LDMOS power transistor M1 in the integrated ESD / EOS protection circuit turns on and discharges current to achieve high voltage triggering performance.

[0020] 4) When the ESD or EOS electrical stress increases and triggers the activation of the integrated ESD / EOS protection circuit, the Zener diode Z... D It can suppress the large on-voltage sweepback phenomenon caused by large current discharge in the SCR structure, and enhance the latch-up resistance of the integrated ESD / EOS protection circuit.

[0021] 5) When the integrated ESD / EOS protection circuit is applied to high-voltage driver chips in different power domains, the Zener diode Z can be adjusted according to the power domain voltage and circuit operating characteristics requirements. D The number of cascaded circuits further enhances the withstand voltage and latch-up immunity of the integrated ESD / EOS protection circuit. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip in an embodiment of the present invention.

[0023] Figure 2This is a diagram showing the quick-start path of the electrostatic surge integrated protection circuit for the high-reliability high-voltage driver chip in this embodiment of the invention.

[0024] Figure 3 This is a diagram of the SCR main discharge path of the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in an embodiment of the present invention.

[0025] Figure 4 This is a voltage regulation clamping path diagram of the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the Zener diode cascade method in the electrostatic surge integrated protection circuit of the high-reliability high-voltage driver chip in an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0028] This embodiment provides an integrated electrostatic discharge (ESD / EOS) surge protection circuit for a high-reliability high-voltage driver chip, fabricated on the same P-type silicon substrate (100), with the specific structure as follows: Figure 1 As shown; the integrated ESD / EOS protection circuit is provided on the P-type silicon substrate (100) from left to right as follows: a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103); a first deep P-well (104) is provided on the first P-type epitaxial layer (101), a deep N-well (105) is provided on the N-type buried layer (102), and a second deep P-well (106) is provided on the second P-type epitaxial layer (103);

[0029] The first deep P-well (104) region is provided with a first P-well (111), and the first P-well (111) region is provided with a first P+ implantation region (113); the deep N-well (105) region is provided with a first N-well (107), a second P-well (108), and a second N-well (109) from left to right, and the second P-well (108) region is provided with a PB doped layer (110); the first N-well (107) region is provided with a first N+ implantation region (115); the second P-well (108) region is provided with a first P+ implantation region (115) from left to right. There are a second P+ implantation region (116), a second N+ implantation region (117), a third N+ implantation region (118), and a third P+ implantation region (119), and the third N+ implantation region (118) is located in the PB doped layer (110); from left to right, the second N well (109) region is provided with a fourth P+ implantation region (120) and a fourth N+ implantation region (121); the second deep P well (106) region is provided with a third P well (112), and the third P well (112) region is provided with a fifth P+ implantation region (114);

[0030] A polysilicon gate oxide layer (122) is provided between the third P+ injection region (119) and the fourth P+ injection region (120), and the polysilicon gate oxide layer (122) is connected across the surfaces of the second P-well (108) and the second N-well (109); the first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the ESD / EOS integrated protection circuit, and the first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the anode of the ESD / EOS integrated protection circuit.

[0031] The integrated ESD / EOS protection circuit of the high-reliability high-voltage driver chip includes: a Zener structure, a composite transistor structure, an SCR structure, an LDMOS structure, and metal lines, mainly composed of a first resistor R1, a second resistor R2, and an NPN transistor T. n1 PNP transistor T p1 LDMOS power transistor M1, Zener transistor Z D It consists of an anode and a cathode;

[0032] The first resistor R1 is the parasitic resistance of the second N-well (109), the second resistor R2 is the parasitic resistance of the P-well (108), and the NPN transistor T n1The PNP transistor is composed of the second N-well (109), the P-well (108), and the second N+ injection region (117); the PNP transistor is composed of the fourth P+ injection region (120), the second N-well (109), and the P-well (108); the LDMOS power transistor M1 is composed of the fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N-well (109), the P-well (108), and the third P+ injection region (119); the Zener transistor Z... D It is composed of the second N+ implantation region (117), the PB doped layer (110) and the P well (108).

[0033] In terms of working principle:

[0034] The integrated ESD / EOS protection circuit of the high-reliability high-voltage driver chip mainly includes: a fast-opening path, an SCR main discharge path, and a voltage regulation clamping path.

[0035] The quick start path is as follows: Figure 2 As shown, it includes: the Zener tube Z D The second resistor R2, the first resistor R1, and the PNP transistor T p1 and the NPN transistor T n1 The Zener tube Z D The cathode is connected to the anode of the ESD / EOS protection circuit, and the Zener diode Z... D The anode of the NPN transistor T n1 The base of the second resistor R2 is connected to the base of the PNP transistor T; one end of the second resistor R2 is connected to the anode of the ESD / EOS protection circuit, and the other end is connected to the base of the PNP transistor T. p1 The base of the PNP transistor T is connected; p1 The emitter of the PNP transistor is connected to the anode of the ESD / EOS protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T is connected to the collector of the PNP transistor T. p1 The collector of the NPN transistor T n1 The base of the first resistor R1 is connected to the base of the NPN transistor T; one end of the first resistor R1 is connected to the base of the NPN transistor T. n1 The base of the transistor is connected to the base of the transistor, and the other end is connected to the cathode of the ESD / EOS protection circuit; the NPN transistor T n1 The emitter of the Zener diode is connected to the cathode of the ESD / EOS protection circuit; wherein, the Zener diode Z... D Zener breakdown occurs, and the PNP transistor T p1Avalanche breakdown occurs at the base and collector of the NPN transistor, causing the voltage drop across the first resistor R1 to change faster than that across the second resistor R2. Therefore, the NPN transistor T... n1 Compared to the PNP transistor T p1 First, it is turned on, and positive feedback causes the integrated ESD / EOS protection circuit to turn on; the drift current when it is not turned on has a regulating effect on the turn-on speed, which can improve the response speed of the integrated ESD / EOS protection circuit and reduce the trigger voltage.

[0036] The SCR main discharge path is as follows: Figure 3 As shown, it includes: the PNP transistor T p1 The NPN transistor T n2 And the first resistor R1; when the voltage drop across the first resistor R1 reaches 0.7 or more, the voltage drop across the second resistor R2 also quickly reaches 0.7 or more, thus opening the main discharge path of the SCR and starting discharge;

[0037] The voltage stabilizing clamping path is as follows: Figure 4 As shown, it includes: the Zener tube Z D and the LDMOS power transistor M1; the Zener transistor Z D The clamping voltage can be used when the integrated ESD / EOS protection circuit is turned on to suppress the large current injection phenomenon caused by the large sweepback of the conduction voltage after the SCR main discharge path is triggered to turn on, thereby enhancing the withstand voltage and latch-up immunity of the integrated ESD / EOS protection circuit. The source and gate of the LDMOS power transistor M1 are respectively connected to the anode of the integrated ESD / EOS protection circuit, and the drain of the LDMOS power transistor M1 is connected to the cathode of the integrated ESD / EOS protection circuit. The substrate electrode of the LDMOS power transistor M1 is connected to the anode of the integrated ESD / EOS protection circuit through the second resistor R2. The LDMOS power transistor M1 turns on and discharges current when the ESD / EOS electrical stress continues to increase, realizing the high voltage triggering function.

[0038] When the ESD or EOS electrical stress is small, the leakage current formed by minority carrier drift in the integrated ESD / EOS protection circuit flows through the Zener transistor ZD, the second resistor R2, and the collector junction shared by the NPN transistor Tn1 and the PNP transistor Tp1, and converges on the first resistor R1 to form a first trigger current. The parasitic NPN transistor composed of the third N+ injection region (118), the PB doped layer (110), the P well (108), and the second N+ injection region (117) can form a second trigger current. The first trigger current and the second trigger current can improve the response speed of the integrated ESD / EOS protection circuit and reduce the trigger voltage.

[0039] When the ESD or EOS electrical stress is large, the voltage on the first resistor R1 in the integrated ESD / EOS protection circuit continuously increases, and under the positive feedback of the NPN transistor Tp1 and the second transistor Tp1, the voltage on the second resistor R2 continuously increases, which can form an ESD or EOS current discharge channel of the SCR structure, thereby enhancing the robustness of the integrated ESD / EOS protection circuit.

[0040] When the ESD or EOS electrical stress continues to increase, the LDMOS power transistor M1 in the integrated ESD / EOS protection circuit turns on and discharges current to achieve high voltage triggering performance.

[0041] When the ESD or EOS electrical stress increases and triggers the activation of the integrated ESD / EOS protection circuit, the Zener diode ZD can suppress the large current discharge in the SCR structure that causes a large sweepback of the conduction voltage, thereby enhancing the latch-up resistance of the integrated ESD / EOS protection circuit.

[0042] Furthermore, the integrated ESD / EOS protection circuit is applied to high-voltage driver chips in different power domains, and the Zener diode Z can be adjusted according to the power domain voltage and circuit operating characteristics requirements. D The number of cascaded circuits further enhances the withstand voltage and latch-up immunity of the integrated ESD / EOS protection circuit, such as... Figure 5 As shown.

[0043] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. An integrated electrostatic surge protection circuit for a high-reliability high-voltage driver chip, characterized in that, The integrated electrostatic surge protection circuit is disposed on the same P-type silicon substrate (100); The P-type silicon substrate (100) is provided with a first P-type epitaxial layer (101), an N-type buried layer (102), and a second P-type epitaxial layer (103) from left to right. The first P-type epitaxial layer (101) is provided with a first deep P-well (104), the N-type buried layer (102) is provided with a deep N-well (105), and the second P-type epitaxial layer (103) is provided with a second deep P-well (106). The first deep P-well (104) region is provided with a first P-well (111), and the first P-well (111) region is provided with a first P+ implantation region (113); the deep N-well (105) region is provided with a first N-well (107), a second P-well (108), and a second N-well (109) from left to right, and the second P-well (108) region is provided with a PB doped layer (110); the first N-well (107) region is provided with a first N+ implantation region (115); the second P-well (108) region is provided with a first P+ implantation region (115) from left to right. There are a second P+ implantation region (116), a second N+ implantation region (117), a third N+ implantation region (118), and a third P+ implantation region (119), and the third N+ implantation region (118) is located in the PB doped layer (110); the second N well (109) region is provided with a fourth P+ implantation region (120) and a fourth N+ implantation region (121) from left to right; the second deep P well (106) region is provided with a third P well (112), and the third P well (112) region is provided with a fifth P+ implantation region (114); A polysilicon gate oxide layer (122) is provided between the third P+ implantation region (119) and the fourth P+ implantation region (120), and the polysilicon gate oxide layer (122) is connected across the surfaces of the second P well (108) and the second N well (109); The first P+ injection region (113), the fifth P+ injection region (114), the second P+ injection region (116), the second N+ injection region (117), and the third P+ injection region (119) are all connected to the cathode of the electrostatic surge integrated protection circuit. The first N+ injection region (115), the third N+ injection region (118), the fourth P+ injection region (120), the fourth N+ injection region (121), and the polysilicon gate oxide layer (122) are all connected to the electrostatic surge integrated protection circuit. In the integrated electrostatic surge protection circuit, the parasitic resistance of the second N-well (109) forms the first resistance R1, the parasitic resistance of the second P-well (108) forms the second resistance R2, and the second N-well (109), the second P-well (108), and the second N+ injection region (117) constitute the NPN transistor T. n1 The fourth P+ injection region (120), the second N-well (109), and the second P-well (108) constitute a PNP transistor T. p1 The fourth P+ injection region (120), the polysilicon gate oxide layer (122), the second N-well (109), the second P-well (108), and the third P+ injection region (119) constitute the LDMOS power transistor M1; the second N+ injection region (117), the PB doped layer (110), and the second P-well (108) constitute the Zener transistor Z. D .

2. The electrostatic surge integrated protection circuit for the high-reliability high-voltage drive chip according to claim 1, characterized in that, The Zener tube Z D The cathode of the Zener diode is connected to the anode of the integrated electrostatic surge protection circuit. D The anode of the NPN transistor T n1 The base of the second resistor R2 is connected to the base of the PNP transistor T; one end of the second resistor R2 is connected to the anode of the integrated electrostatic surge protection circuit, and the other end is connected to the base of the PNP transistor T. p1 The base of the PNP transistor T is connected to the substrate electrode of the LDMOS power transistor M1. p1 The emitter of the PNP transistor is connected to the anode of the integrated electrostatic surge protection circuit. p1 The base of the NPN transistor T n1 The collector of the PNP transistor T is connected to the collector of the PNP transistor T. p1 The collector of the NPN transistor T n1 The base of the first resistor R1 is connected to the base of the NPN transistor T; one end of the first resistor R1 is connected to the base of the NPN transistor T. n1 One end is connected to the base, and the other end is connected to the cathode of the integrated electrostatic surge protection circuit; the NPN transistor T n1 The emitter of the LDMOS power transistor M1 is connected to the cathode of the integrated electrostatic surge protection circuit; the source and gate of the LDMOS power transistor M1 are connected to the anode of the integrated electrostatic surge protection circuit, and the drain of the LDMOS power transistor M1 is connected to the cathode of the integrated electrostatic surge protection circuit.

3. The electrostatic surge integrated protection circuit for the high-reliability high-voltage drive chip according to claim 1, characterized in that, The integrated electrostatic surge protection circuit includes: a fast-opening path, an SCR main discharge path, and a voltage regulator clamping path; the fast-opening path includes: a Zener diode Z-channel rectifier. D Second resistor R2, first resistor R1, PNP transistor T p1 With NPN transistor T n1 The SCR main discharge path includes: PNP transistor T p1 NPN transistor T n1 With the first resistor R1; the voltage regulation clamping path includes: Zener diode Z D With LDMOS power transistor M1.

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