Infrared enhanced single photon avalanche diode device

Abstract

The infrared-enhanced single-photon avalanche diode device comprises a P + photosensitive region located at the center of the surface of the device, a P-injection region surrounding the outer side of the P + photosensitive region, a deep N well surrounding the outer side of the P-injection region, and a P-type substrate surrounding the outer side of the deep N well; the P + photosensitive region, the P-injection region and the deep N well are flush with the upper surface of the P-type substrate; the P + photosensitive region is used as a photosensitive surface to absorb photons, and a metal anode is led out from the surface to form ohmic contact; a P-type charge layer is embedded in the P-injection region, an N-buried layer is embedded in the deep N well, the N-buried layer is located below the P-type charge layer, and the P-type charge layer and the N-buried layer are located at the central position of the device; and the N buried layer forms a main avalanche region with a deeper depth. According to the invention, the detection efficiency of the silicon-based single-photon avalanche diode in a near-infrared band can be effectively improved.

Description

Technical Field

[0001] The invention belongs to the technical field of single-photon detection, and in particular relates to an infrared-enhanced single-photon avalanche diode device. Background Art

[0002] For single-photon detection in the near-infrared band, traditional silicon-based single-photon detectors have certain limitations in detection efficiency and performance. In recent years, with the development of nanotechnology and new materials, researchers have begun to explore avalanche mechanism photoelectric detection technology based on new low-dimensional materials, in order to achieve detectors with high gain, room temperature operation and wide-band response. However, these new technologies are still in the research stage and have not yet been widely used.

[0003] The application of silicon-based avalanche photodiodes (SAPDs) in the visible light band is relatively mature, but the detection efficiency in the near-infrared band is relatively low. At present, near-infrared single-photon detection technology mainly relies on avalanche photodiodes made of materials such as indium gallium arsenide (InGaAs).

[0004] In response to the problem of limited SPAD detection range, although the existing solutions have expanded its detection wavelength range to a certain extent, they also have the following disadvantages:

[0005] High cost: Although the detection wavelength range can be expanded by introducing new materials, the complex preparation of InAsGa APD and the expensive materials such as silicon germanium and superconductors lead to additional cost expenditure and complexity.

[0006] Complex process: Optimizing the device structure by introducing reflective layers and diffraction layers requires high-precision nano-processing technology, and the high-voltage deep-well process also requires extremely high process control accuracy.

[0007] Non-room temperature operability: Materials such as silicon germanium and superconductors usually need to work under low temperature conditions, which increases their dependence on low temperature environments and limits their application at room temperature.

[0008] System complexity: Frequency up-conversion systems usually require additional pump light sources, nonlinear media, and precise optical alignment, increasing system complexity and cost.

[0009] In summary, although these solutions have solved the problem of limited detection range of SPAD to a certain extent, their respective shortcomings limit their widespread application. Summary of the invention

[0010] In order to overcome the deficiencies of the above-mentioned prior art, the object of the present invention is to provide an infrared enhanced single photon avalanche diode device, which can effectively improve the detection efficiency of silicon-based single photon avalanche diodes in the near-infrared band.

[0011] In order to achieve the above object, the technical solution adopted by the present invention is:

[0012] An infrared enhanced single photon avalanche diode device,

[0013] It comprises a P-type substrate, a deep N-well is sunken on the top surface of the P-type substrate, a P-injection region is sunken on the top surface of the deep N-well, a P+ photosensitive region is sunken on the top surface of the P-injection region, an N buried layer is arranged below the P-injection region in the deep N-well, and the N buried layer is not in contact with the P-injection region and the P-type substrate, and a P-type charge layer is arranged below the P+ photosensitive region in the P-injection region, and the P-type charge layer is not in contact with the P+ photosensitive region and the deep N-well;

[0014] N+ regions are arranged on both sides of the P-injection region in the deep N well, a metal cathode is arranged in the N+ region, and a metal anode is arranged in the P+ photosensitive region.

[0015] An N well is also provided in the deep N well, and the N well is located below the N+ region and contacts the N+ region;

[0016] An N+ region and an N-well are formed on the top by ion implantation, wherein the N+ region is a heavily doped region, forming an ohmic contact cathode, and the N-well is uniformly doped.

[0017] The deep N-well is flanked by N-wells and STI protection rings, and the virtual protection ring structure formed by the N-well and STI protection rings can effectively prevent edge breakdown.

[0018] An STI protection ring is also arranged in the P-type substrate, and the STI protection ring is in contact with the N+ region and the N well at the same time, forming a virtual protection ring structure.

[0019] The doping concentration of the P-type charge layer is higher than that of the P-injection region, so the electric field in the center region is stronger than that in the edge region, which effectively prevents edge breakdown effect.

[0020] The doping concentration of the P-implantation region is 10 15 cm -3 -10 16 cm -3 , the doping concentration of N+ region is 1*10 19 ~5*10 20 The N buried layer is a medium doping region, and the doping concentration of the N buried layer is 5*10 17 -5*10 18 The P-injection region does not need to be connected to the substrate, which greatly reduces the process difficulty.

[0021] The P+ photosensitive region is surrounded by a lightly doped P-injection region with a larger diameter, which acts as a light absorption region to absorb photons and can increase the depletion layer thickness to improve photon detection efficiency. Secondly, the larger diameter can also effectively prevent edge breakdown effects.

[0022] The P charge layer forms a single charge layer in the P-region, and forms a main PN junction with a thicker depletion layer with the deep N-well, and forms an edge PN junction with the deep N-well at the edge of the P-injection region.

[0023] The heavily doped N buried layer forms a single buried layer structure in the deep N well, making the drift electric field distribution in the middle more concentrated, serving as the main avalanche region of the device. The presence of the buried layer improves the uniformity of the electric field and effectively suppresses the edge breakdown effect.

[0024] P+ regions connected to the ground are added on both sides of the deep N well as grounding electrodes.

[0025] When the device is working, the voltage of the N+ region is set to 0 by default, and a reverse negative bias is applied to the P+ photosensitive region connected to the metal anode, so that the device works in Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. The hole-electron pair undergoes avalanche breakdown inside the device due to the multiplication effect, generating a large avalanche breakdown current, which can detect weak light signals and even single photon signals.

[0026] The P-type substrate is 20-50 microns wide and 6-15 microns high; the deep N-well is 12-18 microns wide and 0.8-1.4 microns high; the P-injection region is 8-14 microns wide and smaller than the deep N-well, and is 0.6-1.2 microns high; the P-type charge layer is 4-13 microns wide and smaller than the P-injection region, and is 0.1-0.2 microns high; the P+ photosensitive region is 0.8-1.2 microns wide and 0.05-0.1 microns high; the N+ region is 0.8-1.2 microns wide and 0.05-0.1 microns high; the N buried layer is 4-13 microns wide and smaller than the deep N-well, and is 0.1-0.2 microns high; the N-well is 0.8-1.2 microns wide and 0.6-1.2 microns high.

[0027] A method for preparing an infrared enhanced single photon avalanche diode device comprises the following steps:

[0028] Step (1): forming a P+ region and a deep N-well on a P-type silicon substrate using a CMOS process of photolithography, oxidation, diffusion, ion implantation, and annealing;

[0029] Step (2) forming an N+ region and an N-well by ion implantation above the deep N-well, wherein the N+ region is a heavily doped region, forming an ohmic contact cathode, and the N-well is uniformly doped;

[0030] Step (3): forming a medium-doped N buried layer in the center of the deep N well by Gaussian doping;

[0031] Step (4): using a diffusion process to perform P-type heavy doping in the center area of ​​the device to form a P+ photosensitive region and a P-injection region, wherein the P+ photosensitive region is connected to the metal anode of the SPAD;

[0032] Step (5): preparing a P-type charge layer in the P-injection region through ion implantation and annealing processes, and forming a PN junction with the deep N-well;

[0033] Step (6): making contact holes associated with the electrodes;

[0034] Step (7): Use photolithography, etching and metallization processes to prepare other high-level interconnect metals for leading the electrical signals of the SPAD to the contact pads; and prepare infrared-enhanced single-photon avalanche diode devices.

[0035] Step (8): Sequentially deposit silicon oxide / silicon nitride passivation layers on the chip surface to prevent the chip from being scratched and affected by the external environment.

[0036] The infrared enhanced silicon-based single-photon avalanche diode device is used in the fields of human eye safety, laser radar, etc. and can be integrated on a large scale.

[0037] Beneficial effects of the present invention:

[0038] The present invention widens the depletion layer thickness and improves device performance. Due to the presence of the low-doping concentration P-injection region and the P-type charge layer, a PN junction with a wider depletion layer can be formed with the deep N-well region. The wider the depletion layer, the larger the light absorption junction area, which improves the ability to absorb photons, thereby improving the detection efficiency of the SPAD device.

[0039] The avalanche probability is improved and premature edge breakdown is effectively suppressed. The edge breakdown effect refers to the phenomenon that after a reverse bias is applied to the SPAD, the electric field at the edge of the PN junction may be stronger than the central electric field, which eventually leads to premature avalanche in the edge area. The presence of the N buried layer 105 can concentrate the strong electric field in the center area of ​​the device, making the electric field in the center area higher than that in the edge area. The higher the electric field, the greater the probability of avalanche. Therefore, the probability of avalanche in the center area increases and the uniformity of the central electric field improves.

[0040] Reduce tunnel noise. The P-well doping concentration of the classic structure SPAD is high, so the PN junction tunnel noise formed with the deep N-well is high. However, the P-injection region and the P-type charge layer have low doping concentrations, which can effectively reduce tunnel noise.

[0041] Mature process and low manufacturing cost: The device is a silicon-based SPAD device based on the 180nm standard CMOS process. After years of development, the CMOS process has formed a mature process flow and manufacturing system. This makes the CMOS process have high stability and reliability in the production process, which is conducive to reducing production costs and improving production efficiency, and can achieve large-scale integration. Silicon materials are cheap and easy to obtain, which also greatly reduces the manufacturing cost.

[0042] Good environmental applicability: the device can work stably at room temperature without the need to create a low-temperature environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic diagram of the structure of the silicon-based SPAD device designed in Example 1 of the present invention.

[0044] Figure 2 It is a reference structural diagram of Example 2 of the present invention.

[0045] Figure 3 It is a graph of the avalanche probability of the SPAD device designed in Example 1 of the present invention under different over-bias voltages.

[0046] Figure 4 It is a graph showing the volt-ampere characteristic of the P-type charge layer of the SPAD device designed in Example 1 at different concentrations.

[0047] Figure 5 It is a detection efficiency curve diagram of the P-type charge layer of the SPAD device designed in Example 1 at different depths.

[0048] Figure 6 It is a detection efficiency curve diagram of the SPAD device designed in Example 1 when the N-type buried layer is located at different depths.

[0049] Figure 7 It is a graph showing the variation of PDE with wavelength for the SPAD device designed in Example 1 and the reference structure in Example 2. DETAILED DESCRIPTION

[0050] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0051] like Figure 1 As shown, a single charge layer and single buried layer silicon-based single photon avalanche diode structure includes a P+ photosensitive region 101, a P-injection region 102, a P-type charge layer 103, a deep N well 104, an N buried layer 105, a P-type substrate 106, an N+ region 107, an N well 108, a metal anode 109, a metal cathode 110, a P+ region 111 and a shallow trench STI protection ring 112.

[0052] The central area is a heavily doped P+ photosensitive region 101 with a diameter of 10μm, which absorbs photons as a photosensitive surface and leads to a metal anode 109 from the surface to form an ohmic contact. However, due to the high doping concentration of the P+ photosensitive region 101, the contact resistance does not respond significantly to light.

[0053] The doping concentration of the P-implantation region 102 is 10 15 cm -3The N buried layer 105 and the inverted doped deep N well 104 form a main avalanche region with a relatively deep depth. Since photons in the near-infrared band can still be absorbed at a relatively deep position of the device, the near-infrared detection efficiency can be improved. The N buried layer 105 is buried in the deep N well 104, which can concentrate the electric field in the central area, reduce the edge breakdown effect, and further improve the detection efficiency.

[0054] The P-injection region 102 is not connected to the substrate 106; the P-injection region 102 does not need to be connected to the substrate 106, which greatly reduces the process difficulty.

[0055] The P+ photosensitive region 101 is surrounded by a lightly doped P-injection region 102 with a larger diameter, which acts as a light absorption region to further absorb photons and increase the depletion layer thickness to improve photon detection efficiency. Secondly, the larger diameter can also effectively prevent edge breakdown effects.

[0056] The two sides of the deep N-well 104 are N-well 108 and STI guard ring 112. The virtual guard ring structure formed by the N-well 108 and the STI guard ring 112 can effectively prevent edge breakdown.

[0057] The doping concentration of the P-type charge layer 103 is higher than that of the P-injection region 102. Therefore, the electric field in the central region is stronger than that in the edge region, which effectively prevents edge breakdown effect. At the same time, the thick depletion layer also widens the device spectrum range toward the near-infrared direction.

[0058] A P charge layer 103 is inserted into the P-injection region 102 to form a single charge layer, and forms a main PN junction with a thick depletion layer with the deep N well 104. The P-injection region 102 and the deep N well 104 at the edge form an edge PN junction.

[0059] A heavily doped N buried layer 105 is buried in the deep N well 104 to form a single buried layer structure, so that the drift electric field distribution in the middle is more concentrated, serving as the main avalanche region of the device. The presence of the buried layer improves the uniformity of the electric field and effectively suppresses the edge breakdown effect.

[0060] P+ regions 111 connected to the ground are added on both sides of the deep N well 104 to serve as grounding electrodes.

[0061] When the device is working, the voltage of the N+ region 107 is set to 0 by default, and a reverse negative bias is applied to the P+ photosensitive region 101 connected to the metal anode 109, so that the device works in the Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. The hole-electron pair undergoes avalanche breakdown inside the device due to the multiplication effect, generating a large avalanche breakdown current, and detecting weak light signals or even single photon signals.

[0062] The near-infrared detection efficiency is optimized by structural modeling using TCAD software. As the doping concentration of the P-type charge layer 103 increases from 5×10 17 cm -3 Increased to 5×10 18 cm -3 , the volt-ampere characteristic curve gradually shifts to the left, and the avalanche breakdown voltage of the SPAD device also increases;

[0063] When other conditions remain unchanged, the longitudinal center positions of the P-type charge layer 103 are respectively taken as 0.7 μm, 0.8 μm, 0.9 μm and 1.0 μm from the device surface. It can be seen that the deeper the depth, the lower the detection efficiency in the short-wave range, and the long-wave detection efficiency first increases and then decreases;

[0064] The depths of the N buried layer 105 are set to 1.5 μm, 2 μm and 2.5 μm respectively;

[0065] Finally, the parameters of the P-type charge layer 103 are determined to be 0.9 μm in position and 1×10 18 cm-3, the position of N buried layer 105 is taken as 1.5μm, and the new SPAD device with the optimal structure has a detection efficiency of 15.6% at 850nm. Based on the established detection efficiency calculation model, the simulation results can be presented more intuitively.

[0066] Embodiment 1:

[0067] The device structure is simulated and modeled in two dimensions using TCAD software. Since the SPAD structure is a planar symmetrical SPAD, simulating half of the device will not affect the performance results, so the right half of the device is selected for simulation, and the two-dimensional simulation modeling process is as follows:

[0068] (1) Complete the initialization grid design, define a rectangular region 1 with a length of 10 μm in the x direction and a height of 6 μm in the y direction, and the material is silicon. Perform uniformly distributed light doping on the region 1 to form a P-type substrate 106.

[0069] (2) defining an STI guard ring structure 112 made of SiO2 and having a depth of 0.5 μm at 8 to 8.5 μm in the x direction;

[0070] (3) With 1.4 μm in the y direction as the position of the highest doping concentration, Gaussian doping is performed in the range of 0 to 8 μm in the x direction to form a deep N well 104, with the standard deviation set to 0.5 and the diffusion coefficient to 0.2.

[0071] (4) N-doping is performed in a region of 7 to 8 μm in the x direction and 0 to 1 μm in the y direction to form an N well 108 .

[0072] (5) In the region of 9 to 10 μm in the x direction, P-type Gaussian heavy doping is performed from the surface to form a P+ region 111 through diffusion.

[0073] (6) At 7 to 8 μm in the x direction, Gaussian-distributed N-type heavy doping is performed from the surface to diffuse and form an N+ region 107 .

[0074] (7) The P-type charge layer 103 is located in the x-direction from 0 to 5.5 μm, the doping peak is 0.8 μm in the y-direction, the standard deviation is 0.05, and the diffusion coefficient is 0.5;

[0075] (8) lightly doping the device surface to form a P-implantation region 102 in the range of 0 to 6 microns, with a standard deviation of 1.2 and a diffusion coefficient of 0.5;

[0076] (9) The N buried layer 105 is 0 to 4 microns in the x direction, the doping peak is 2 microns in the y direction, the standard deviation is 0.2, and the diffusion coefficient is 0.5.

[0077] (10) forming a P+ active region by heavy doping on the surface, with a doping range of 0 to 5 μm in the x direction, a standard deviation of 0.05, and a diffusion coefficient of 0.1;

[0078] (11) Finally, metal electrodes are set in the N+ region 107 and the P+ photosensitive region 101. The N+ region 107 is connected to the metal cathode 110, and the P+ region 101 is connected to the anode 109.

[0079] The temperature was set to 300 K, and the device was modeled based on the Geiger mode, impact ionization model, Fermi model, SRH model, mobility model, and Auger recombination model. Other process parameters are shown in Table 1. The final modeling results are consistent with the attached Figure 1 The design structure is consistent.

[0080] Table 1 SPAD process parameters of single charge layer and single buried layer structure

[0081]

[0082]

[0083] The device is compatible with 180nm CMOS process, and the main process steps for preparation are as follows:

[0084] P+ photosensitive region 101, P- region 102, P-type charge layer 103, deep N well 104, N buried layer 105, P-type substrate 106, N+ region 107, N well 108, metal anode 109, metal cathode 110, P+ region 111 and shallow trench STI protection ring 112;

[0085] (1) Using CMOS processes such as photolithography, oxidation, diffusion, ion implantation, and annealing, a P+ region 111 and a deep N well 104 are formed on a P-type silicon substrate 106. The deep N well 104 is retrograde doped;

[0086] (2) forming an N+ region 107 and an N-well region 108 on the deep N-well 104 by ion implantation, wherein the N+ region 107 is a heavily doped region, forming an ohmic contact cathode, and 108 is uniformly doped;

[0087] (3) forming a medium-doped N buried layer 105 region in the central deep N well 104 by Gaussian doping;

[0088] (4) P-type heavy doping is performed in the center area of ​​the device by diffusion process to form a P+ photosensitive region 101 and a P-injection region 102, wherein the P+ photosensitive region 101 is connected to the metal anode 109 of the SPAD;

[0089] (5) A P-type charge layer 103 is prepared in the P-implantation region 102 through ion implantation and annealing processes, and the P-type charge layer 103 forms a PN junction with the deep N-well 104;

[0090] (6) making contact holes associated with electrodes;

[0091] (7) using photolithography, etching and metallization processes to prepare other high-level interconnect metals for leading the electrical signals of the SPAD to the contact pads;

[0092] (8) Silicon oxide / silicon nitride passivation layers are sequentially deposited on the chip surface to prevent the chip from being scratched and affected by the external environment.

[0093] Photon detection efficiency (PDE) can be expressed as the product of quantum efficiency and avalanche triggering probability. To further quantify it and make it more intuitive and data-based in simulation results, a scientific and effective detection efficiency calculation model is needed.

[0094] Since the light absorption efficiency in different regions of the device is different, the calculation model of photon detection efficiency can be mainly divided into three parts: the top photon detection efficiency P Top , depletion layer photon detection efficiency P Dep and the bottom photon detection efficiency P Bot , then the total photon detection efficiency is PDE = P Top +P Dep +P Bot .

[0095] The top is a P-region neutral region composed of a P+ region 101 and a P-region 102. For the top photon detection efficiency, photons are absorbed at the top layer of the device to generate photogenerated carriers. These photogenerated carriers may trigger avalanche photocurrent after diffusing to the depletion layer. Therefore, the top photon detection efficiency P Top :

[0096]

[0097] Where α is the absorption coefficient of the device material for light with a wavelength of λ, L e is the electron diffusion length of the top layer, W1 is the thickness from the top to the upper boundary of the depletion layer, see the attached Figure 1 , then the probability of electron-triggered avalanche breakdown at the boundary of the depletion region is P e (W1) can be obtained by simulation.

[0098] The depletion layer is composed of the avalanche region formed between the P-type charge layer 103 and the deep N-well 104. It has a strong electric field and is therefore called the depletion layer. For this part of the photon detection efficiency, photons are absorbed in the depletion layer, and the generated electron-hole pairs drift in opposite directions under the action of the electric field, which may also trigger an avalanche photocurrent. The depletion layer photon detection efficiency P Dep :

[0099]

[0100] Where W2 is the depletion layer thickness, see the attached Figure 1 , α is the absorption coefficient of the device material for light with a wavelength of λ, and the probability of electrons and holes triggering avalanches at the longitudinal position x are P and e and P h ,

[0101] The bottom is the part of the deep N-well 104 below the depletion region. For the bottom photon detection efficiency, photons are absorbed in the well region below the depletion layer boundary, and the generated electron-hole pairs do not need to recombine and directly reach the lower boundary of the depletion layer. The bottom photon detection efficiency P Bot :

[0102]

[0103] Where α is the absorption coefficient of the device material for light with a wavelength of λ, W1+W2 is the distance from the lower boundary of the depletion layer to the device surface, see the attached Figure 1 , Lp is the diffusion length of holes in the N-well.

[0104] Embodiment 2:

[0105] In order to verify that the designed device structure has optimized detection efficiency in the near-infrared band, the classic P+ / deep N-well structure is modeled by TCAD software. The device structure is as follows Figure 2shown.

[0106] It includes: a second P+ region 201 , a second P well 202 , a second deep N well 203 , a second N+ region 204 , a second N well 205 , a second P substrate 206 , a second metal anode 207 , a second metal cathode 208 and a second STI protection ring 209 .

[0107] The two-dimensional simulation modeling process is as follows:

[0108] (1) Complete the initialization grid design, define a rectangular region 1 with a length of 10 μm in the x direction and a height of 6 μm in the y direction, and the material is silicon; define an STI guard ring structure 209 with a material of SiO2 and a depth of 0.5 μm at 6 to 7 μm and 8 to 10 μm in the x direction; and define the electrode.

[0109] (2) Evenly distribute light doping on region 1 to form P substrate 206.

[0110] (3) With 1.55 μm in the y direction as the position with the highest doping concentration, Gaussian doping is performed in the range of 0 to 8 μm in the x direction to form a deep N well 203 with a diffusion coefficient of 0.2.

[0111] (4) Uniform P-doping and N-doping are performed in the regions of 0 to 4 μm in the x direction, 0 to 0.49 μm in the y direction and 6 to 8 μm in the x direction, 0 to 0.7 μm in the y direction, respectively, to form a second P-well 202 and a second N-well 205.

[0112] (5) In the region of 0 to 3.5 μm in the x direction, P-type Gaussian heavy doping is performed from the surface to form a P+ region 201 through diffusion.

[0113] (6) At 7 to 8 μm in the x direction, N-type Gaussian heavy doping is performed from the surface to diffuse and form an N+ region 204.

[0114] (7) Setting the temperature and physical model. Other process parameters are shown in Table 2.

[0115] Table 2. Process parameters of classic structure SPAD

[0116]

[0117] Based on the above established model, the structural parameters of the designed SPAD device are changed through TCAD software, including: P-type charge layer concentration, P-type charge layer depth and N-type buried layer depth. The simulation results under different structural parameters are obtained respectively.

[0118] Over-bias voltage will also affect the device avalanche probability, thus causing changes in photon detection efficiency. Figure 3This is the total avalanche probability distribution when the over-bias voltage is 1V, 3V, 4.5V and 5V respectively when other parameters are the same. It can be seen that as the over-bias voltage continues to increase, the avalanche probability changes more slowly, that is, the total avalanche probability in the avalanche zone increases.

[0119] Using the Impact statement, the collision ionization model is set to the Selberrherr model, and the Models statement is used to set the band-to-band tunneling standard model; then, the cathode voltage value of the avalanche diode is set to 0V, and a reverse voltage of 0V to -20V is applied to the device through the metal anode, and the iterative voltage is -0.25V. After simulation, the corresponding volt-ampere characteristic curves under different P charge layer concentrations are output, such as Figure 4 As shown. The concentration of the P-type charge layer is 5×10 17 cm -3 , 1×10 18 cm -3 and 5×10 18 cm -3 As can be seen from the figure, as the concentration of the P-type charge layer increases, the volt-ampere characteristic curve gradually shifts to the left, and the avalanche breakdown voltage of the SPAD device also increases. When the concentration is 1×10 18 cm -3 When the SPAD breakdown voltage is about 11.8V.

[0120] like Figure 5 The PDE curves when the P-type charge layer is at different depths, the longitudinal center positions are taken as 0.7μm, 0.8μm, 0.9μm and 1.0μm from the device surface, and the over-bias voltage is taken as 30% of the respective breakdown voltages. It can be seen that as the depth of the center position of the P-type charge layer increases, the detection efficiency in the short-wave range continues to decrease, and the long-wave detection efficiency first increases and then decreases. Taking the P-type charge layer at 0.9μm as an example, its peak is still obtained in the short-wave range, but compared with the positions of 0.7μm and 0.8μm, the peak value decreases and shifts toward the long-wave direction; while in the near-infrared wavelength range, the detection efficiency is improved to a certain extent, such as at 850nm, its detection efficiency reaches 13.68%, which is not much different from the detection efficiency at 1.0μm.

[0121] like Figure 6The detection efficiency-wavelength curve of the SPAD structure under different buried layer conditions is shown. The PDE curves with or without buried layer and buried layer at 1.5μm, 2μm and 2.5μm are listed respectively when other conditions are the same. As can be seen from the figure, when there is no buried layer, the curve reaches a maximum value of 88% at 450nm. After adding the buried layer, the curve moves up as a whole, but the peak position is still at 450nm. As the buried layer depth increases, the detection efficiency curve in the near-infrared wavelength range gradually decreases. For example, when the buried layer depth is 1.5μm, the detection efficiency at 850nm wavelength is 14.5%, which is higher than the case when there is no buried layer and the buried layer depth is 2μm and 2.5μm. This is because the electric field distribution is more concentrated after adding the buried layer in the deep N well, and the PDE obtained after integration is larger. Therefore, when other conditions are the same, the buried layer depth is taken as the optimal solution of 1.5μm.

[0122] From the above analysis, it can be seen that under the working condition of 300K, the position of the P-type charge layer of the new structure should be taken as the optimal parameter 0.9μm, and the concentration should be taken as 1×10 18 cm-3, in order to obtain a smaller breakdown voltage and a suitable over-bias voltage. The buried layer position is taken as 1.5μm, and the buried layer diameter is 5μm, to ensure that the electric field is concentrated in the central avalanche region. Figure 7 Each curve shows the curve of the detection efficiency of the reference structure SPAD and the single charge layer single buried layer structure SPAD as a function of wavelength, and the over-bias voltage is 1V, 3V, and 5V, respectively. As can be seen from the figure, as the over-bias voltage increases, the detection efficiency gradually increases, and compared with the reference structure, the detection efficiency of the SPAD of the new structure has been greatly improved overall, the peak area moves toward the long-wave direction, and the spectral response range is also widened, especially in the near-infrared band. When the over-bias voltage is 3V, the detection efficiency of the reference structure SPAD at 850nm is about 4.3%, while the detection efficiency of the single charge layer single buried layer structure SPAD is increased to 15.6%, which can verify that the single charge layer and single buried layer structure SPAD proposed in the present invention effectively improves the detection efficiency in the near-infrared band, especially at 850nm.

Claims

1. An infrared enhanced single photon avalanche diode device, characterized in that: The invention comprises a P-type substrate (106), a deep N-well (104) is arranged under the top surface of the P-type substrate (106), a P-injection region (102) is arranged under the top surface of the deep N-well (104), a P+ photosensitive region (101) is arranged under the top surface of the P-injection region (102), an N-buried layer (105) is arranged below the P-injection region (102) in the deep N-well (104), and the N-buried layer (105) is not in contact with the P-injection region (102) and the P-type substrate (106), and a P-type charge layer (103) is arranged below the P+ photosensitive region (101) in the P-injection region (102), and the P-type charge layer (103) is not in contact with the P+ photosensitive region (101) and the deep N-well (104); An N+ region (107) is arranged on both sides of a P-injection region (102) in a deep N well (104), a metal cathode (110) is arranged in the N+ region (107), and a metal anode (109) is arranged in a P+ photosensitive region (101).

2. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: An N well (108) is also provided in the deep N well (104), and the N well (108) is located below the N+ region (107) and in contact with the N+ region (107); An N+ region (107) and an N well (108) are formed on the upper side by ion implantation, wherein the N+ region (107) is a heavily doped region, forming an ohmic contact cathode, and the N well (108) is uniformly doped.

3. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: The deep N-well (104) has an N-well (108) and an STI protection ring (112) on both sides, and a virtual protection ring structure formed by the N-well (108) and the STI protection ring (112); An STI protection ring (112) is also arranged in the P-type substrate (106), and the STI protection ring (112) is in contact with both the N+ region (107) and the N well (108) to form a virtual protection ring structure.

4. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: The doping concentration of the P-injection region (102) is 10 15 cm -3 -10 16 cm -3 , the doping concentration of N+ region (107) is 1*10 19 ~5*10 20 The N buried layer 105 is a medium doping region, and the doping concentration of the N buried layer 105 is 5*10 17 -5*10 18 .

5. The infrared enhanced single photon avalanche diode device according to claim 4, characterized in that: The doping concentration of the P-type charge layer (103) is higher than that of the P-injection region (102).

6. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: The P charge layer 103 forms a single charge layer in the P-region (102), forms a main PN junction with a thicker depletion layer with the deep N-well (104), and forms an edge PN junction with the deep N-well (104) at the edge of the P-injection region (102); The heavily doped N buried layer (105) forms a single buried layer structure in the deep N well 104.

7. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: P+ regions (111) connected to the ground are added to both sides of the deep N well (104) to serve as grounding electrodes.

8. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: When the device is working, the voltage of the N+ region (107) is set to 0 by default, and a reverse negative bias is applied to the P+ photosensitive region (101) connected to the metal anode (109), so that the device works in the Geiger mode. When a photon arrives and is absorbed by the device, a hole-electron pair is generated. The hole-electron pair undergoes avalanche breakdown inside the device due to the multiplication effect, generating a large avalanche breakdown current, thereby detecting weak light signals or even single photon signals.

9. The infrared enhanced single photon avalanche diode device according to claim 1, characterized in that: The P-type substrate (106) is 20-50 microns wide and 6-15 microns high; the deep N-well (104) is 12-18 microns wide and 0.8-1.4 microns high; the P-injection region (102) is 8-14 microns wide and smaller than the deep N-well (104) and 0.6-1.2 microns high; the P-type charge layer (103) is 4-13 microns wide and smaller than the P-injection region (102) and 0.1-0. 2 microns; the P+ photosensitive region (101) is 0.8-1.2 microns wide and 0.05-0.1 microns high; the N+ region (107) is 0.8-1.2 microns wide and 0.05-0.1 microns high; the N buried layer (105) is 4-13 microns wide and smaller than the deep N well (104), and is 0.1-0.2 microns high; the N well (108) is 0.8-1.2 microns wide and 0.6-1.2 microns high.

10. A method for preparing an infrared enhanced single photon avalanche diode device, characterized in that: The steps include: Step (1): forming a P+ region (111) and a deep N well (104) on a P-type silicon substrate (106) by using a CMOS process of photolithography, oxidation, diffusion, ion implantation, and annealing; Step (2) forming an N+ region (107) and an N well (108) above the deep N well (104) by ion implantation, wherein the N+ region (107) is a heavily doped region, forming an ohmic contact cathode, and the N well (108) is uniformly doped; Step (3): forming a medium-doped N buried layer (105) in the center of the deep N well (104) by Gaussian doping; Step (4): using a diffusion process to perform P-type heavy doping in the center region of the device to form a P+ photosensitive region (101) and a P-injection region (102), wherein the P+ photosensitive region (101) is connected to a metal anode (109) of the SPAD; Step (5): preparing a P-type charge layer (103) in the P-injection region (102) through ion implantation and annealing processes, and forming a PN junction between the P-type charge layer (103) and the deep N-well (104); Step (6): making contact holes associated with the electrodes; Step (7): Use photolithography, etching and metallization processes to prepare other high-level interconnect metals for leading the electrical signals of the SPAD to the contact pads; and prepare infrared-enhanced single-photon avalanche diode devices.

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