Solar cell preparation method and solar cell

Abstract

The invention discloses a solar cell preparation method and a solar cell, and relates to the technical field of solar cells. The method comprises the following steps: forming a first tunneling oxide layer, a function adjusting layer, a heat-resistant isolation layer and an N-type initial doping layer in an N-type doping region on the main surface of a silicon substrate from inside to outside, and forming a second tunneling oxide layer and a P-type initial doping layer in a P-type doping region on the main surface of the silicon substrate from inside to outside; and synchronously carrying out annealing treatment on the N-type doped region and the P-type doped region to diffuse the P-type doped element and the N-type doped element so as to convert the function adjustment layer into a first N-type doped layer, convert the N-type initial doped layer into a second N-type doped layer and convert the P-type initial doped layer into a P-type doped layer. According to the embodiment, synchronous diffusion of the N-type doping element and the P-type doping element can be realized through one-time high-temperature annealing.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a solar cell and a solar cell. Background Art

[0002] With the development of photovoltaic technology, more and more attention has been paid to the preparation efficiency of solar cells. For solar cells containing P-type doping regions and N-type doping regions, due to the different diffusion temperatures and diffusion rates of N-type doping elements and P-type doping elements, the diffusion temperature of P-type doping elements when preparing P-type doping layers is higher than that of N-type doping elements when preparing N-type doping layers. Therefore, P-type doping layers and N-type doping layers need to be prepared separately, resulting in a complicated and time-consuming process for preparing solar cells. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a method for preparing a solar cell and a solar cell, which can achieve synchronous diffusion of an N-type doping element and a P-type doping element through a single high-temperature annealing.

[0004] To achieve the above object, according to one aspect of an embodiment of the present invention, a method for preparing a solar cell is provided, comprising:

[0005] Step A1, forming a first tunneling oxide layer, a function adjustment layer, a heat-resistance insulating layer, and an N-type initial doping layer from inside to outside in the N-type doping region on the main surface of the silicon substrate, and forming a second tunneling oxide layer and a P-type initial doping layer from inside to outside in the P-type doping region on the main surface of the silicon substrate; wherein the N-type initial doping layer contains an N-type doping element, and the P-type initial doping layer contains a P-type doping element;

[0006] Step A2, simultaneously annealing the above-mentioned N-type doping area and the above-mentioned P-type doping area to diffuse the above-mentioned P-type doping elements and the N-type doping elements, wherein the above-mentioned annealing temperature meets the diffusion temperature of the above-mentioned P-type doping elements, and the above-mentioned N-type doping elements diffuse into the above-mentioned functional adjustment layer through the above-mentioned heat-resistant insulation layer to transform the above-mentioned functional adjustment layer into a first N-type doping layer, the above-mentioned N-type initial doping layer into a second N-type doping layer, and the above-mentioned P-type initial doping layer into a P-type doping layer.

[0007] To achieve the above object, according to another aspect of an embodiment of the present invention, there is provided a solar cell, comprising:

[0008] Silicon substrate;

[0009] A P-type doped region and an N-type doped region are provided on the main surface of the silicon substrate;

[0010] The N-type doping region is provided with a first tunneling oxide layer, a first N-type doping layer, a heat-resistance insulating layer, and a second N-type doping layer from inside to outside, wherein the N-type doping elements contained in the first N-type doping layer are partially or entirely derived from the second N-type doping layer;

[0011] The P-type doped region is provided with a second tunneling oxide layer and a P-type doped layer from inside to outside.

[0012] One embodiment of the above invention has the following advantages or beneficial effects: by forming a stacked structure including a first tunneling oxide layer, a function adjustment layer, a heat-resistant insulating layer, and an N-type initial doping layer from the inside to the outside in the N-type doping region, when the diffusion temperature of the N-type doping element and the diffusion temperature of the P-type doping element are different, the heat-resistant insulating layer can block part of the heat, so that the diffusion of the N-type doping element and the P-type doping element does not need to be carried out in steps, and the synchronous diffusion of the N-type doping element and the P-type doping element can be achieved through a single high-temperature annealing, thereby optimizing the preparation process of the solar cell, shortening the preparation time, and improving the production capacity. At the same time, by blocking part of the heat through the heat-resistant insulating layer, the N-type doping element is prevented from excessively penetrating the first tunneling oxide layer to reduce its passivation effect, thereby ensuring the yield rate and photoelectric conversion efficiency of the solar cell.

[0013] In addition, by setting the doping concentration of the N-type initial doping layer to be greater than the doping concentration of the function adjustment layer, gradient diffusion of the N-type doping element is achieved. By setting the third tunneling oxide layer and the fourth tunneling oxide layer, a tunneling channel is provided for the diffusion of the N-type doping element, the diffusion rate of the N-type doping element is increased, and the doping concentration of the first N-type doping layer after high-temperature annealing can further be guaranteed to meet the process requirements.

[0014] The further effects of the above-mentioned non-conventional optional manner will be described below in conjunction with the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to better understand the present invention and do not constitute an improper limitation of the present invention.

[0016] Figure 1 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present invention;

[0017] Figure 2 is a schematic structural diagram of a solar cell according to an embodiment of the present invention;

[0018] Figure 3 is another structural schematic diagram of a solar cell according to an embodiment of the present invention;

[0019] Figure 4 is a schematic structural diagram of a TOPCon battery according to Example 1 of the present invention;

[0020] Figure 5 Schematic diagram of the structure of a TBC battery according to Example 2 of the present invention.

[0021] Reference numerals:

[0022] 10-silicon substrate; 20-N-type doped region; 21-first tunneling oxide layer; 22-first N-type doped layer; 23-third tunneling oxide layer; 24-heat-blocking insulating layer; 25-fourth tunneling oxide layer; 26-second N-type doped layer; 27-second metal electrode; 30-P-type doped region; 31-second tunneling oxide layer; 32-P-type doped layer; 33-P+ layer; 34-first metal electrode; 40-passivation layer; 50-anti-reflection layer. DETAILED DESCRIPTION

[0023] The following is a description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, including various details of the embodiments of the present invention to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0024] It should be pointed out that the embodiments of the present invention and the technical features therein may be combined with each other without conflict.

[0025] Figure 1 FIG. 1 is a schematic diagram of the main steps of the method for preparing a solar cell according to an embodiment of the present invention. Figure 1 As shown, the solar cell manufacturing method of the embodiment of the present invention mainly includes the following steps A1 to A2:

[0026] Step A1, forming a first tunneling oxide layer 21, a function adjustment layer, a heat-resistant insulation layer 24, and an N-type initial doping layer from the inside to the outside in the N-type doping region 20 on the main surface of the above-mentioned silicon substrate 10, and forming a second tunneling oxide layer 31 and a P-type initial doping layer from the inside to the outside in the P-type doping region 30 on the main surface of the above-mentioned silicon substrate 10; wherein the above-mentioned N-type initial doping layer contains N-type doping elements, and the above-mentioned P-type initial doping layer contains P-type doping elements.

[0027] The N-type doping region 20 may be located on any surface of the silicon substrate 10. Optionally, according to the different types of solar cells to be prepared, the N-type doping region 20 and the P-type doping region 30 are respectively arranged on the two main surfaces of the silicon substrate 10; or, the N-type doping region 20 and the P-type doping region 30 are arranged on the same main surface of the silicon substrate 10. As an example, when a TOPCon (Tunnel Oxide Passivated Contact) battery needs to be prepared, according to the structure of the TOPCon battery, the N-type doping region 20 and the P-type doping region 30 should be arranged on the two main surfaces of the silicon substrate 10; when an interdigitated back contact (IBC) battery or a TBC (TOPCon-IBC) battery needs to be prepared, the N-type doping region 20 and the P-type doping region 30 should be arranged on the same main surface of the silicon substrate 10.

[0028] The function adjustment layer is a silicon film layer. The concentration of the N-type doping element contained in the silicon film layer is greater than or equal to 0. As an example, the silicon film layer can be a polycrystalline silicon layer containing an N-type doping element concentration equal to 0. As another example, the silicon film layer can be a polycrystalline silicon layer containing an N-type doping element concentration greater than 0.

[0029] It should be noted that the doping concentration of the above-mentioned functional adjustment layer is lower than the doping concentration of the above-mentioned N-type initial doping layer, so that during the annealing process, the N-type doping elements in the N-type initial doping layer can diffuse into the functional adjustment layer to achieve gradient diffusion of the N-type doping elements.

[0030] Among them, N-type doping elements include valence elements such as phosphorus or arsenic that can provide additional free electrons; P-type doping elements include trivalent elements such as aluminum or boron that can form holes.

[0031] A heat-resistant insulating layer 24 is disposed between the function adjustment layer and the N-type initial doping layer to block high temperature during annealing to prevent the function adjustment layer from being subjected to excessively high temperature, thereby affecting the diffusion of the N-type doping elements. The heat-resistant insulating layer 24 can be prepared by plasma enhanced chemical vapor deposition (PECVD), but is not limited thereto.

[0032] Furthermore, the heat-resistant insulating layer 24 may be a silicon carbide layer, which can block part of the heat while not blocking the diffusion of the N-type doping elements.

[0033] The N-type initial doping layer is a polysilicon layer with an N-type doping element concentration greater than 0, and the N-type doping element concentration contained therein is greater than the N-type doping element concentration contained in the function adjustment layer.

[0034] Step A2, simultaneously performing high-temperature annealing treatment on the above-mentioned N-type doping region 20 and the above-mentioned P-type doping region 30 to diffuse the above-mentioned P-type doping elements and the N-type doping elements, wherein the above-mentioned high-temperature annealing temperature meets the diffusion temperature of the above-mentioned P-type doping elements, and the above-mentioned N-type doping elements diffuse into the above-mentioned functional adjustment layer through the above-mentioned heat-resistant insulation layer 24, so as to transform the above-mentioned functional adjustment layer into the first N-type doping layer 22, the above-mentioned N-type initial doping layer into the second N-type doping layer 26, and the above-mentioned P-type initial doping layer into the P-type doping layer 32.

[0035] In the process of simultaneously performing high-temperature annealing treatment on the N-type doping region 20 and the P-type doping region 30, the annealing temperature should meet the diffusion temperature of the P-type doping element, so that the diffusion of the P-type doping element in the P-type doping region 30 and the diffusion of the N-type doping element in the N-type doping region 20 occur simultaneously, to avoid the annealing temperature being too low so that the diffusion of the P-type doping element cannot occur.

[0036] Optionally, the annealing temperature may be 870° C.-1100° C. As an example, the annealing temperature may be 870° C., 950° C., 1030° C., or 1100° C., etc.

[0037] Optionally, the high temperature annealing process may be performed in a tube furnace or a chain furnace, but is not limited thereto.

[0038] During the high-temperature annealing process, the heat-resistant insulating layer 24 can block part of the high temperature so that the temperature received by the functional adjustment layer is lower than the annealing temperature, thereby allowing the N-type doping elements in the N-type initial doping layer to diffuse into the functional adjustment layer, thereby realizing the diffusion of the N-type doping elements.

[0039] Furthermore, by adjusting the thickness of the heat-resistant insulating layer 24 to control the temperature received by the functional adjustment layer, only a small amount of N-type doping elements penetrate the first tunneling oxide layer 21 after high-temperature annealing, thereby avoiding excessive penetration of the N-type doping elements into the first tunneling oxide layer 21 at high temperature to reduce its passivation effect, so that the diffusion rate of the N-type doping elements and the concentration after diffusion meet the process requirements, thereby forming a first N-type doping layer 22, realizing the adjustment of the doping concentration of the N-type doping elements in the first N-type doping layer 22, and realizing the synchronous diffusion of P-type doping elements and N-type doping elements through one annealing treatment.

[0040] Optionally, during the annealing process, the temperature of the function adjustment layer may be 600° C.-800° C. As an example, during the annealing process, the temperature of the function adjustment layer may be 600° C., 650° C., 700° C., 750° C. or 800° C., etc.

[0041] Furthermore, the thickness of the heat-resistant insulating layer 24 can be 1-20 nm. By setting the thickness of the heat-resistant insulating layer 24 within a reasonable range, the heat-resistant insulating layer 24 can block part of the heat from reaching the functional adjustment layer, and can also allow the N-type doping elements of appropriate concentration to reach the functional adjustment layer, thereby promoting the functional adjustment layer to be converted into the first N-type doping layer 22 with appropriate doping concentration. As an example, the thickness of the heat-resistant insulating layer 24 can be 1 nm, 5 nm, 10 nm, 18 nm or 20 nm, etc.

[0042] In an optional embodiment, the above step A1 includes:

[0043] Step A11, forming a first tunneling oxide layer 21, a function adjustment layer and a heat-resistance insulating layer 24 from inside to outside on the N-type doped region 20 on the main surface of the silicon substrate 10;

[0044] Step A12: forming an N-type initial doping layer on the outer side of the heat-resistant insulating layer 24 by in-situ doping or high-temperature furnace tube diffusion doping.

[0045] The first tunnel oxide layer 21 may be prepared by a low pressure chemical vapor deposition (LPCVD) method, but is not limited thereto.

[0046] Forming the N-type initial doping layer by in-situ doping in step A12 includes: introducing N doping elements into the reaction material flow during the growth process of the N-type initial doping layer, thereby performing doping while growing, and finally forming the N-type initial doping layer.

[0047] The diffusion doping through the high-temperature furnace tube in step A12 mainly includes: forming a polysilicon layer on the outside of the heat-resistant insulating layer 24, placing the silicon substrate 10 in which the N-type doping area 20 on the main surface forms a first tunneling oxide layer 21, a functional adjustment layer, a heat-resistant insulating layer 24 and a polysilicon layer from the inside to the outside on a carrier such as a quartz boat, and placing the carrier in a high-temperature furnace tube, heating to the diffusion temperature of the N-type doping element, introducing an N-type doping source gas, and stopping the introduction of the N-type doping source gas after a preset doping time, and cooling the high-temperature furnace tube to obtain an N-type initial doping layer on the outside of the heat-resistant insulating layer 24.

[0048] It should be noted that when a high-temperature furnace tube diffusion doping is used to form an N-type initial doping layer, due to the high temperature conditions, in the process of forming the N-type initial doping layer, part of the N-type doping elements can diffuse into the functional adjustment layer through the heat-resistant insulating layer 24 to achieve the diffusion of the N-type doping elements. However, due to the limitations of the doping temperature and doping time of this step, the N-type doping elements diffused into the functional adjustment layer may not cause the functional adjustment layer to be completely converted into the first N-type doping layer 22. Therefore, a subsequent high-temperature annealing step is still required to cause the functional adjustment layer to be completely converted into the first N-type doping layer 22.

[0049] In a possible implementation of an optional embodiment, the above step A11 includes:

[0050] Step A111, forming a first tunneling oxide layer 21 at the location of the N-type doped region 20 on the main surface of the silicon substrate 10;

[0051] Step A112, forming the above-mentioned function adjustment layer outside the first tunneling oxide layer 21 by in-situ doping;

[0052] Step A113, forming a heat-resistant insulating layer 24 on the outside of the function adjustment layer.

[0053] The function adjustment layer is a silicon film layer whose N-type doping element concentration is greater than or equal to 0. Furthermore, the silicon film layer may be a polysilicon layer.

[0054] The forming of the function adjustment layer by in-situ doping in step A112 includes: introducing N doping elements into the reaction material flow during the growth process of the function adjustment layer, thereby performing doping while growing, and finally forming the function adjustment layer.

[0055] It can be understood that when the N-type doping element concentration in the functional adjustment layer is 0, a polysilicon layer can be directly grown outside the first tunneling oxide layer 21 without in-situ doping, and the polysilicon layer with an N-type doping element concentration of 0 can be directly used as the functional adjustment layer.

[0056] In an optional embodiment, the step A1 further includes: for the N-type doped region 20 on the main surface of the silicon substrate 10 , a third tunneling oxide layer 23 is formed between the function adjustment layer and the heat-resistance isolation layer 24 .

[0057] Specifically, step A1 includes: forming a first tunneling oxide layer 21, a function adjustment layer, a third tunneling oxide layer 23, a heat-resistance insulating layer 24, and an N-type initial doping layer from inside to outside in the N-type doping region 20 on the main surface of the silicon substrate 10.

[0058] By forming a third tunneling oxide layer 23 between the function adjustment layer and the heat-resistant insulating layer 24, a tunneling channel for the N-type doping element is formed. Due to the quantum tunneling effect, the tunneling channel is conducive to the passage of the N-type doping element and quickly reaches the function adjustment layer, thereby shortening the process time.

[0059] In an optional embodiment, the step A1 further comprises: for the N-type doped region 20 on the main surface of the silicon substrate 10 , a fourth tunneling oxide layer 25 is formed between the heat-resistant insulating layer 24 and the N-type initial doped layer.

[0060] Specifically, step A1 includes: forming a first tunneling oxide layer 21, a function adjustment layer, a heat-resistance insulating layer 24, a fourth tunneling oxide layer 25, and an N-type initial doping layer from inside to outside in the N-type doping region 20 on the main surface of the silicon substrate 10.

[0061] By forming the fourth tunneling oxide layer 25 between the heat-resistant insulating layer 24 and the N-type initial doping layer, a tunneling channel of the N-type doping element is formed to assist the diffusion of the N-type doping element during the annealing process.

[0062] Furthermore, the above-mentioned step A1 further includes: for the N-type doped region 20 on the main surface of the above-mentioned silicon substrate 10, a third tunneling oxide layer 23 is formed between the above-mentioned function adjustment layer and the above-mentioned heat-resistant insulation layer 24, and for the N-type doped region 20 on the main surface of the above-mentioned silicon substrate 10, a fourth tunneling oxide layer 25 is formed between the above-mentioned heat-resistant insulation layer 24 and the above-mentioned N-type initial doping layer.

[0063] Specifically, step A1 includes: forming a first tunneling oxide layer 21, a function adjustment layer, a third tunneling oxide layer 23, a heat-resistant insulation layer 24, a fourth tunneling oxide layer 25, and an N-type initial doping layer from inside to outside in the N-type doped region 20 on the main surface of the silicon substrate 10.

[0064] By forming a third tunneling oxide layer 23 between the function adjustment layer and the heat-resistant insulation layer 24, and forming a fourth tunneling oxide layer 25 between the heat-resistant insulation layer 24 and the N-type initial doping layer, a tunneling channel for the N-type doping element is formed to assist the diffusion of the N-type doping element during the annealing process.

[0065] According to the method for preparing a solar cell of an embodiment of the present invention, a stacked structure including a first tunneling oxide layer 21, a function adjustment layer, a heat-resistant insulating layer 24, and an N-type initial doping layer is formed from the inside to the outside of the N-type doping region 20. When the diffusion temperature of the N-type doping element and the diffusion temperature of the P-type doping element are different, the heat-resistant insulating layer 24 can block part of the heat, so that the diffusion of the N-type doping element and the P-type doping element does not need to be carried out in steps, and the synchronous diffusion of the N-type doping element and the P-type doping element can be achieved through a high-temperature annealing, thereby optimizing the preparation process of the solar cell, shortening the preparation time, and improving the production capacity. At the same time, by blocking part of the heat through the heat-resistant insulating layer 24, the N-type doping element is prevented from excessively penetrating the first tunneling oxide layer 21 to reduce its passivation effect, thereby ensuring the yield rate and photoelectric conversion efficiency of the solar cell.

[0066] In addition, by setting the doping concentration of the N-type initial doping layer to be greater than the doping concentration of the function adjustment layer, gradient diffusion of the N-type doping element is achieved. By setting the third tunneling oxide layer 23 and the fourth tunneling oxide layer 25, a tunneling channel is provided for the diffusion of the N-type doping element, the diffusion rate of the N-type doping element is increased, and the doping concentration of the first N-type doping layer 22 after high-temperature annealing can further be guaranteed to meet the process requirements.

[0067] Figure 2 Schematic diagram of the structure of a solar cell according to an embodiment of the present invention. Figure 2 , Figure 4 and Figure 5 As shown, the solar cell of the embodiment of the present invention includes: a silicon substrate 10; a P-type doping region 30 and an N-type doping region 20 arranged on the main surface of the above-mentioned silicon substrate 10; the above-mentioned N-type doping region 20 is provided with a first tunneling oxide layer 21, a first N-type doping layer 22, a heat-resistant insulation layer 24, and a second N-type doping layer 26 from the inside to the outside, wherein the N-type doping elements contained in the above-mentioned first N-type doping layer 22 are partially or completely derived from the above-mentioned second N-type doping layer 26; the above-mentioned P-type doping region 30 is provided with a second tunneling oxide layer 31 and a P-type doping layer 32 from the inside to the outside.

[0068] By providing the heat-blocking insulating layer 24 , part of the heat is blocked during the annealing process, so that the N-type doping element and the P-type doping element can be diffused synchronously.

[0069] The thickness of the first tunneling oxide layer 21 can be 1-2 nm, so as to ensure that the thinner first tunneling oxide layer 21 utilizes the quantum tunneling effect, allowing electrons to tunnel quickly when the solar cell is working, while blocking the recombination of holes, thereby improving the efficiency of the solar cell. As an example, the thickness of the first tunneling oxide layer 21 can be 1 nm, 1.3 nm, 1.5 nm or 2 nm, etc.

[0070] The thickness of the above-mentioned heat-resistant insulating layer 24 can be 1-20nm. By adjusting the thickness of the heat-resistant insulating layer 24, the amount of heat blocked can be controlled, and the temperature received by the functional layer between the heat-resistant insulating layer 24 and the silicon substrate 10 can be further controlled to be lower than the external annealing temperature. Even at a higher annealing temperature, the N-type doping element can diffuse to form the first N-type doping layer 22, and will not excessively penetrate the first tunneling oxide layer 21. As an example, the thickness of the heat-resistant insulating layer 24 can be 1nm, 5nm, 10nm or 20nm, etc.

[0071] In addition, the heat-resistant insulating layer 24 may be a silicon carbide layer, which can block part of the heat without blocking the diffusion of N-type doping elements.

[0072] The thickness of the first N-type doping layer 22 and the second N-type doping layer 26 may be 80-200 nm. It is understandable that the thickness of the first N-type doping layer 22 and the thickness of the second N-type doping layer 26 may be the same or different. By controlling the thickness of the first N-type doping layer 22 and the second N-type doping layer 26 within a reasonable thickness range, the open circuit voltage and fill factor of the solar cell are improved, the series resistance is reduced, and the performance of the solar cell is further improved. As an example, the thickness of the first N-type doping layer 22 may be 80 nm, 100 nm, 140 nm, 180 nm or 200 nm, etc.; the thickness of the second N-type doping layer 26 may be 80 nm, 110 nm, 140 nm, 190 nm or 200 nm, etc.

[0073] In an optional embodiment of the present invention, the doping concentration of the first N-type doping layer 22 is less than the doping concentration of the second N-type doping layer 26 .

[0074] It can be understood that, during the diffusion of the N-type doping element, the functional adjustment layer is converted into the first N-type doping layer 22, and the N-type initial doping layer is converted into the second N-type doping layer 26. At this time, since the doping concentration of the N-type initial doping layer is greater than the doping concentration of the functional adjustment layer, the N-type doping element diffuses from the N-type initial doping layer to the functional adjustment layer, thereby realizing the gradient diffusion of the N-type doping element. After the diffusion of the N-type doping element is completed, since the N-type doping element in the first N-type doping layer 22 is partially or entirely derived from the second N-type doping layer 26, the doping concentration of the first N-type doping layer 22 is less than the doping concentration of the second N-type doping layer 26. In the process of the N-type doping element diffusing from the N-type initial doping layer to the functional adjustment layer, the thickness of the heat-resistant insulation layer 24 is relatively thin, and the N-type doping element can find a diffusion path in the heat-resistant insulation layer 24. Moreover, since the diffusion temperature of the N-type doping element is relatively high, the atomic thermal motion is intense, and the N-type doping element can easily overcome the obstruction of the heat-resistant insulation layer 24 and diffuse into the functional adjustment layer.

[0075] Furthermore, the doping concentration of the first N-type doping layer 22 is less than or equal to 4×10 20 Pieces / cm 3 , and greater than or equal to 4×10 19 Pieces / cm 3 The doping concentration of the second N-type doping layer 26 is greater than or equal to 5×10 20 Pieces / cm 3 The doping concentration of the first N-type doping layer 22 is controlled to be less than the doping concentration of the second N-type doping layer 26 to form a concentration gradient. During the operation of the solar cell, the carriers diffuse from the high concentration area to the low concentration area under the action of the concentration gradient of the first N-type doping layer 22 and the second N-type doping layer 26. By controlling the doping concentrations of the first N-type doping layer 22 and the second N-type doping layer 26 within a reasonable range, the solar cell can more effectively collect photogenerated carriers. As an example, the doping concentration of the first N-type doping layer 22 can be 4×10 19 Pieces / cm 3 , 10×10 19 Pieces / cm 3 , 22×10 19 Pieces / cm 3 , 3×10 20 Pieces / cm 3 or 4×10 20 Pieces / cm 3 etc.; the doping concentration of the second N-type doping layer 26 may be 5×10 20 Pieces / cm 3 ,7×10 20 Pieces / cm 3 or 9×10 20 Pieces / cm 3 wait.

[0076] In an optional embodiment of the present invention, the N-type doping region 20 further includes: a third tunneling oxide layer 23, wherein the third tunneling oxide layer 23 is located between the first N-type doping layer 22 and the heat-resistant insulating layer 24, that is, the N-type doping region 20 is sequentially provided with the first tunneling oxide layer 21, the first N-type doping layer 22, the third tunneling oxide layer 23, the heat-resistant insulating layer 24, and the second N-type doping layer 26 from the inside to the outside. The third tunneling oxide layer 23 is provided to provide a tunneling channel for the diffusion of the N-type doping element, assist its diffusion, and improve the diffusion efficiency.

[0077] The thickness of the third tunnel oxide layer 23 may be 1-2 nm. By controlling the thickness of the third tunnel oxide layer 23 and setting a thinner third tunnel oxide layer 23, while providing a tunnel channel for the N-type doping element to increase the passing speed of the N-type doping element, other performances of the battery will not be affected. As an example, the thickness of the third tunnel oxide layer 23 may be 1 nm, 0.3 nm, 0.5 nm, 0.8 nm or 2 nm, etc.

[0078] In an optional embodiment of the present invention, the N-type doping region 20 further includes a fourth tunneling oxide layer 25, wherein the fourth tunneling oxide layer 25 is located between the heat-blocking and insulating layer 24 and the second N-type doping layer 26, that is, the N-type doping region 20 is sequentially provided with the first tunneling oxide layer 21, the first N-type doping layer 22, the heat-blocking and insulating layer 24, the fourth tunneling oxide layer 25, and the second N-type doping layer 26 from the inside to the outside. The fourth tunneling oxide layer 25 is provided to provide a tunneling channel for the diffusion of the N-type doping element, assist its diffusion, and improve the diffusion efficiency.

[0079] The thickness of the fourth tunnel oxide layer 25 may be 1-2 nm. By controlling the thickness of the fourth tunnel oxide layer 25 and setting a thinner fourth tunnel oxide layer 25, a tunnel channel is provided for the N-type doping element to increase the passing speed of the N-type doping element, while other performances of the battery are not affected. As an example, the thickness of the fourth tunnel oxide layer 25 may be 1 nm, 0.3 nm, 0.5 nm, 0.8 nm or 2 nm, etc.

[0080] In an optional embodiment of the present invention, Figure 3 As shown, the N-type doping region 20 is provided with a first tunneling oxide layer 21, a first N-type doping layer 22, a third tunneling oxide layer 23, a heat-resistant insulating layer 24, a fourth tunneling oxide layer 25, and a second N-type doping layer 26 in sequence from the inside to the outside. That is, a third tunneling oxide layer 23 is further provided between the first N-type doping layer 22 and the heat-resistant insulating layer 24, and a fourth tunneling oxide layer 25 is further provided between the heat-resistant insulating layer 24 and the second N-type doping layer 26. The third tunneling oxide layer 23 and the fourth tunneling oxide layer 25 provide a tunneling channel for the diffusion of the N-type doping element, assisting its diffusion and improving the diffusion efficiency.

[0081] It should be noted that Figure 2 and Figure 3 The schematic structural diagram of the solar cell shown only shows a partial structure of the solar cell, namely, the structure of the silicon substrate 10 in the solar cell and an N-type doped region 20 on its main surface.

[0082] According to the solar cell of the embodiment of the present invention, a stacked structure including a first tunneling oxide layer 21, a first N-type doping layer 22, a heat-resistant insulating layer 24, and a second N-type doping layer 26 is formed from the inside to the outside of the N-type doping region 20. The heat-resistant insulating layer 24 can block part of the heat. Even at a higher annealing temperature, the temperature received by the functional layer arranged between the heat-resistant insulating layer 24 and the silicon substrate 10 is lower than the external annealing temperature, which can prevent the N-type doping element from excessively penetrating the first tunneling oxide layer 21, improve the upper limit of the diffusion temperature of the N-type doping element that can be tolerated when the first N-type doping layer 22 is prepared, and the diffusion of the N-type doping element and the P-type doping element can be realized simultaneously, thereby ensuring the yield rate and photoelectric conversion efficiency of the solar cell.

[0083] In addition, by providing the third tunnel oxide layer 23 and the fourth tunnel oxide layer 25, tunnel channels are provided for the diffusion of N-type doping elements, the diffusion rate of the N-type doping elements is improved, and the doping concentration of the first N-type doping layer 22 after high-temperature annealing can further be ensured to meet the process requirements.

[0084] Example 1

[0085] This embodiment provides a preparation method and structure of a TOPCon battery, and its structure can be referred to Figure 4 , and its preparation method comprises the following steps B1 to B11:

[0086] Step B1, texturing the two main surfaces of the N-type silicon substrate 10 to form a silicon substrate 10 having a pyramid texture structure on the main surface;

[0087] Step B2, performing boron diffusion treatment on the N-type silicon substrate 10 to prepare a PN junction, thereby forming a P+ layer 33 and a borosilicate glass (BSG) layer from the inside to the outside on the first main surface, and at the same time, a P+ layer 33 and a BSG layer are formed on the second main surface due to the wrap-around plating phenomenon;

[0088] Among them, there is a PN junction in the P+ layer 33;

[0089] It should be noted that the first main surface of the N-type silicon substrate 10 refers to the side facing the sunlight when the solar cell is working, and correspondingly, the second main surface refers to the side facing away from the sunlight when the solar cell is working;

[0090] Step B3, etching the second main surface to remove the P+ layer 33 and the BSG layer produced by wrap-around plating; retaining the BSG layer on the first main surface;

[0091] Step B4, depositing a first tunneling oxide layer 21 on the second main surface of the N-type silicon substrate 10 by LPCVD, and forming a function adjustment layer outside the first tunneling oxide layer 21 by in-situ doping;

[0092] Step B5: depositing a third tunnel oxide layer 23, a heat-resistance insulating layer 24 and a fourth tunnel oxide layer 25 on the function adjustment layer in sequence by using an LPCVD method, and performing phosphorus doping treatment by an in-situ doping method to form an N-type initial doping layer outside the fourth tunnel oxide layer 25;

[0093] Wherein, the doping concentration of the N-type initial doping layer is greater than the doping concentration of the function adjustment layer;

[0094] Step B6, removing the P+ layer and the BSG layer on the first main surface and the side surface by etching;

[0095] Step B7, using a mask suitable for the TOPCon battery structure to cover the first main surface, using the LPCVD method to deposit the second tunneling oxide layer 31 on the P+ layer 33, and using the in-situ doping method to perform boron doping treatment to form a P-type initial doping layer outside the second tunneling oxide layer 31;

[0096] Step B8, simultaneously performing high temperature annealing treatment on the N-type doping region 20 and the P-type doping region 30 to achieve synchronous diffusion of boron and phosphorus;

[0097] The annealing temperature is 870° C. During the high-temperature annealing process, the heat-resistant insulating layer 24 can block part of the high temperature, so that the heat received by the functional adjustment layer is lower than the annealing temperature, so that the phosphorus element in the N-type initial doping layer can diffuse into the functional adjustment layer to achieve phosphorus diffusion; at the same time, because the annealing temperature meets the temperature of boron diffusion, boron diffusion and phosphorus diffusion occur simultaneously.

[0098] Before the high temperature annealing treatment, the P-type doped region 30 includes a P+ layer 33, a second tunneling oxide layer 31 and a P-type initial doped layer on the first main surface of the silicon substrate 10; the N-type doped region 20 includes a first tunneling oxide layer 21, a function adjustment layer, a third tunneling oxide layer 23, a heat-resistant insulating layer 24, a fourth tunneling oxide layer 25, and an N-type initial doped layer on the second main surface of the silicon substrate 10;

[0099] After the synchronous diffusion of the P-type doping element and the N-type doping element, the P-type initial doping layer is transformed into the P-type doping layer 32, the function adjustment layer is transformed into the first N-type doping layer 22, and the N-type initial doping layer is transformed into the second N-type doping layer 26. Therefore, after high-temperature annealing, the P-type doping region 30 includes the P+ layer 33, the second tunneling oxide layer 31 and the P-type doping layer 32 on the first main surface of the silicon substrate 10; the N-type doping region 20 includes the first tunneling oxide layer 21, the first N-type doping layer 22, the third tunneling oxide layer 23, the heat-resistant insulation layer 24, the fourth tunneling oxide layer 25, and the second N-type doping layer 26 on the second main surface of the silicon substrate 10.

[0100] Step B9, forming a passivation layer 40 on the P-type doped layer 32 on the first main surface; wherein the passivation layer 40 is an aluminum oxide layer;

[0101] Step B10, forming an anti-reflection layer 50 on the second N-type doped layer 26 on the second main surface and the passivation layer 40 on the first main surface respectively; wherein the material of the anti-reflection layer 50 includes but is not limited to silicon nitride, etc.;

[0102] Step B11, screen printing is performed on the first main surface and the second main surface to form a first metal electrode 34 on the first main surface and a second metal electrode 27 on the second main surface, and then the semi-finished battery cell with the electrodes formed is sintered and tested, etc., to obtain a battery cell having the following characteristics: Figure 4 The structure of the TOPCon battery is shown.

[0103] Example 2

[0104] This embodiment provides a method and structure for preparing a TBC battery. Figure 5 , and its preparation method comprises the following steps C1 to C10:

[0105] Step C1, polishing the two main surfaces of the N-type silicon substrate 10;

[0106] Step C2, depositing a second tunneling oxide layer 31 on the second main surface of the silicon substrate 10 by LPCVD, and performing boron doping by in-situ doping to form a P-type initial doping layer outside the second tunneling oxide layer 31;

[0107] Step C3, removing the N-type doped region 20 and the second tunnel oxide layer 31 and the P-type initial doped layer in the isolation region by laser; and cleaning the laser grooved region;

[0108] Step C4, using a mask suitable for the TBC battery structure to cover the second main surface, using LPCVD to deposit the first tunnel oxide layer 21 on the N-type doped region 20 and the isolation region, and performing phosphorus doping treatment on the second amorphous silicon layer by in-situ doping to form a functional adjustment layer;

[0109] Step C5: depositing a third tunneling oxide layer 23, a heat-resistant insulating layer 24 and a fourth tunneling oxide layer 25 on the function adjustment layer in sequence by using an LPCVD method, and performing phosphorus doping treatment by using a high-temperature furnace tube diffusion doping method to form an N-type initial doping layer outside the fourth tunneling oxide layer 25;

[0110] Wherein, the doping concentration of the N-type initial doping layer is greater than the doping concentration of the function adjustment layer;

[0111] Step C6, removing the first tunneling oxide layer 21, the function adjustment layer, the third tunneling oxide layer 23, the heat-resistance insulating layer 24, the fourth tunneling oxide layer 25 and the N-type initial doping layer in the isolation region by laser;

[0112] Step C7, simultaneously performing high temperature annealing treatment on the N-type doping region 20 and the P-type doping region 30 to achieve synchronous diffusion of boron and phosphorus;

[0113] The annealing temperature is 1100° C. During the high-temperature annealing process, the heat-resistant insulating layer 24 can block part of the high temperature, so that the heat received by the functional adjustment layer is lower than the annealing temperature, so that the phosphorus element in the N-type initial doping layer can diffuse into the functional adjustment layer to achieve phosphorus diffusion; at the same time, because the annealing temperature meets the temperature of boron diffusion, boron diffusion and phosphorus diffusion occur simultaneously.

[0114] Before the high temperature annealing treatment, the P-type doped region 30 includes the second tunneling oxide layer 31 and the P-type initial doped layer on the first main surface of the silicon substrate 10; the N-type doped region 20 includes the first tunneling oxide layer 21, the function adjustment layer, the third tunneling oxide layer 23, the heat-resisting isolation layer 24, the fourth tunneling oxide layer 25, and the N-type initial doped layer on the second main surface of the silicon substrate 10;

[0115] After the synchronous diffusion of the P-type doping element and the N-type doping element, the P-type initial doping layer is transformed into the P-type doping layer 32. At the same time, the surface of the P-type doping layer 32 away from the silicon substrate 10 forms a BSG layer, the function adjustment layer is transformed into the first N-type doping layer 22, and the N-type initial doping layer is transformed into the second N-type doping layer 26. At the same time, the surface of the second N-type doping layer 26 away from the silicon substrate 10 forms a phosphorosilicate glass (PSG) layer. Therefore, after high-temperature annealing, the P-type doping region 30 includes the second tunneling oxide layer 31, the P-type doping layer 32 and the BSG layer on the first main surface of the silicon substrate 10; the N-type doping region 20 includes the first tunneling oxide layer 21, the first N-type doping layer 22, the third tunneling oxide layer 23, the heat-resistant insulation layer 24, the fourth tunneling oxide layer 25, the second N-type doping layer 26 and the PSG layer on the second main surface of the silicon substrate 10.

[0116] Step C8, performing texturing on the isolation area, and removing the BSG and PSG layers by texturing;

[0117] Step C9, forming a passivation layer 40 and an anti-reflection layer 50 on both the first main surface and the second main surface; wherein the passivation layer 40 is a titanium oxide layer; and the anti-reflection layer 50 is a silicon nitride layer;

[0118] Step C10, screen printing is performed on the second main surface to form a first metal electrode 34 in the P-type doping area 30, and a second metal electrode 27 in the N-type doping area 20, and then the semi-finished battery cell with the electrodes formed is sintered and tested, etc., to obtain a battery cell having the following characteristics: Figure 5 The structure of the TBC battery is shown.

[0119] In summary, the embodiments of the present invention provide the following technical solutions:

[0120] Technical solution 1, a method for preparing a solar cell, comprising:

[0121] Step A1, forming a first tunneling oxide layer 21, a function adjustment layer, a heat-resistance insulating layer 24, and an N-type initial doping layer from inside to outside in the N-type doping region 20 on the main surface of the silicon substrate 10, and forming a second tunneling oxide layer 31 and a P-type initial doping layer from inside to outside in the P-type doping region 30 on the main surface of the silicon substrate 10; wherein the N-type initial doping layer contains an N-type doping element, and the P-type initial doping layer contains a P-type doping element;

[0122] Step A2, simultaneously annealing the N-type doping region 20 and the P-type doping region 30 to diffuse the P-type doping element and the N-type doping element, wherein the annealing temperature satisfies the diffusion temperature of the P-type doping element, and the N-type doping element diffuses into the functional adjustment layer through the heat-resistant insulation layer 24 to convert the functional adjustment layer into a first N-type doping layer 22, the N-type initial doping layer into a second N-type doping layer 26, and the P-type initial doping layer into a P-type doping layer 32.

[0123] Technical solution 2: A method for preparing a solar cell according to technical solution 1,

[0124] The function adjustment layer is a silicon film layer, wherein the concentration of the N-type doping element contained in the silicon film layer is greater than or equal to 0 and less than the doping concentration of the N-type initial doping layer.

[0125] Technical solution 3: A method for preparing a solar cell according to technical solution 1,

[0126] The annealing temperature in step A2 is 870°C-1100°C.

[0127] Technical solution 4: According to the method for preparing a solar cell according to technical solution 1, step A1 further comprises:

[0128] With respect to the N-type doped region 20 on the main surface of the silicon substrate 10, a third tunneling oxide layer 23 is formed between the function adjustment layer and the heat-resistance and insulation layer 24;

[0129] and / or,

[0130] With respect to the N-type doped region 20 on the main surface of the silicon substrate 10 , a fourth tunneling oxide layer 25 is formed between the heat-resistant insulating layer 24 and the N-type initial doped layer.

[0131] Technical solution 5: According to the method for preparing a solar cell according to technical solution 1, step A1 comprises:

[0132] Step A11, forming a first tunneling oxide layer 21, a function adjustment layer and a heat-resistance insulating layer 24 from inside to outside in the N-type doped region 20 on the main surface of the silicon substrate 10;

[0133] Step A12: forming an N-type initial doping layer on the outer side of the heat-resistant insulating layer 24 by in-situ doping or high-temperature furnace tube diffusion doping.

[0134] Technical solution 6: According to the method for preparing a solar cell according to technical solution 5, step A11 comprises:

[0135] Step A111, forming a first tunneling oxide layer 21 at a location of the N-type doped region 20 on the main surface of the silicon substrate 10;

[0136] Step A112, forming the function adjustment layer on the outer side of the first tunneling oxide layer 21 by in-situ doping;

[0137] Step A113, forming a heat-resistant insulating layer 24 on the outside of the function adjustment layer.

[0138] Technical solution 7: The method for preparing a solar cell according to technical solution 6,

[0139] The N-type doping region 20 and the P-type doping region 30 are respectively disposed on two main surfaces of the silicon substrate 10;

[0140] or,

[0141] The N-type doping region 20 and the P-type doping region 30 are disposed on the same main surface of the silicon substrate 10 .

[0142] Technical solution 8, a solar cell, comprising:

[0143] Silicon substrate 10;

[0144] A P-type doping region 30 and an N-type doping region 20 are disposed on the main surface of the silicon substrate 10;

[0145] The N-type doping region 20 is provided with a first tunneling oxide layer 21, a first N-type doping layer 22, a heat-resistance insulating layer 24, and a second N-type doping layer 26 from inside to outside;

[0146] The P-type doping region 30 is provided with a second tunneling oxide layer 31 and a P-type doping layer 32 from inside to outside.

[0147] Technical solution 9. The solar cell according to technical solution 8,

[0148] The N-type doped region 20 further includes a third tunneling oxide layer 23, wherein:

[0149] The third tunneling oxide layer 23 is located between the first N-type doping layer 22 and the heat-resistant insulating layer 24;

[0150] and / or,

[0151] The thickness of the first tunneling oxide layer 21 is 1-2 nm;

[0152] and / or,

[0153] The thickness of the heat-resistant insulating layer 24 is 1-20 nm;

[0154] and / or,

[0155] The thickness of the first N-type doping layer 22 and the second N-type doping layer 26 are both 80-200 nm.

[0156] Technical solution 10. The solar cell according to technical solution 9,

[0157] For the structure provided with the third tunnel oxide layer 23, the thickness of the third tunnel oxide layer 23 is 1-2 nm;

[0158] and / or,

[0159] The N-type doped region 20 further includes a fourth tunneling oxide layer 25, wherein:

[0160] The fourth tunneling oxide layer 25 is located between the heat-resistant insulating layer 24 and the second N-type doping layer 26 .

[0161] Technical solution 11. The solar cell according to technical solution 10,

[0162] For the structure provided with the fourth tunnel oxide layer 25 , the thickness of the fourth tunnel oxide layer 25 is 1-2 nm.

[0163] Technical solution 12. The solar cell according to technical solution 8,

[0164] The doping concentration of the first N-type doping layer 22 is lower than the doping concentration of the second N-type doping layer 26 .

[0165] Technical solution 13. The solar cell according to technical solution 8,

[0166] The heat-resistant insulating layer 24 includes a silicon carbide layer;

[0167] and / or,

[0168] The doping concentration of the first N-type doping layer 22 is less than or equal to 4×10 20 Pieces / cm 3 ;

[0169] and / or,

[0170] The doping concentration of the second N-type doping layer 26 is greater than or equal to 5×10 20 Pieces / cm 3 , and less than or equal to 5×10 25 Pieces / cm 3 .

[0171] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions may occur depending on design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: Step A1, forming a first tunneling oxide layer (21), a function adjustment layer, a heat-resistance insulating layer (24), and an N-type initial doping layer from inside to outside in an N-type doping region (20) on the main surface of a silicon substrate (10), and forming a second tunneling oxide layer (31) and a P-type initial doping layer from inside to outside in a P-type doping region (30) on the main surface of the silicon substrate (10); wherein the N-type initial doping layer contains an N-type doping element, and the P-type initial doping layer contains a P-type doping element; Step A2, simultaneously annealing the N-type doping region (20) and the P-type doping region (30) to diffuse the P-type doping element and the N-type doping element, wherein the annealing temperature satisfies the diffusion temperature of the P-type doping element, and the N-type doping element diffuses through the heat-resistance insulating layer (24) to the functional adjustment layer, so as to transform the functional adjustment layer into a first N-type doping layer (22), transform the N-type initial doping layer into a second N-type doping layer (26), and transform the P-type initial doping layer into a P-type doping layer (32).

2. The method for preparing a solar cell according to claim 1, characterized in that: The function adjustment layer is a silicon film layer, wherein the concentration of the N-type doping element contained in the silicon film layer is greater than or equal to 0 and less than the doping concentration of the N-type initial doping layer.

3. The method for preparing a solar cell according to claim 1, characterized in that: The annealing temperature in step A2 is 870°C-1100°C.

4. The method for preparing a solar cell according to claim 1, characterized in that: The step A1 further comprises: With respect to the N-type doped region (20) on the main surface of the silicon substrate (10), a third tunneling oxide layer (23) is formed between the function adjustment layer and the heat-resistance isolation layer (24); and / or, With respect to the N-type doped region (20) on the main surface of the silicon substrate (10), a fourth tunneling oxide layer (25) is formed between the heat-resistance isolation layer (24) and the N-type initial doped layer.

5. The method for preparing a solar cell according to claim 1, characterized in that: The step A1 comprises: Step A11, forming a first tunneling oxide layer (21), a function adjustment layer and a heat-resistance isolation layer (24) from the inside to the outside of the N-type doped region (20) on the main surface of the silicon substrate (10); Step A12: forming an N-type initial doping layer on the outside of the heat-resistant insulating layer (24) by in-situ doping or high-temperature furnace tube diffusion doping.

6. The method for preparing a solar cell according to claim 5, characterized in that: The step A11 comprises: Step A111, forming a first tunneling oxide layer (21) at the location of the N-type doped region (20) on the main surface of the silicon substrate (10); Step A112, forming the function adjustment layer on the outside of the first tunneling oxide layer (21) by in-situ doping; Step A113, forming a heat-resistant insulating layer (24) outside the function adjustment layer.

7. The method for preparing a solar cell according to claim 6, characterized in that: The N-type doping region (20) and the P-type doping region (30) are respectively arranged on two main surfaces of the silicon substrate (10); or, The N-type doping region (20) and the P-type doping region (30) are arranged on the same main surface of the silicon substrate (10).

8. A solar cell, characterized in that: include: Silicon substrate (10); A P-type doped region (30) and an N-type doped region (20) disposed on a main surface of the silicon substrate (10); The N-type doping region (20) is provided with a first tunneling oxide layer (21), a first N-type doping layer (22), a heat-resistance insulating layer (24), and a second N-type doping layer (26) from the inside to the outside; The P-type doped region (30) is provided with a second tunneling oxide layer (31) and a P-type doped layer (32) from the inside to the outside.

9. The solar cell according to claim 8, characterized in that The N-type doped region (20) further comprises: a third tunneling oxide layer (23), wherein: The third tunneling oxide layer (23) is located between the first N-type doped layer (22) and the heat-resistant isolation layer (24); and / or, The thickness of the first tunneling oxide layer (21) is 1-2 nm; and / or, The thickness of the heat-resistant insulating layer (24) is 1-20 nm; and / or, The thickness of the first N-type doping layer (22) and the second N-type doping layer (26) are both 80-200 nm.

10. The solar cell according to claim 9, characterized in that: For a structure provided with the third tunneling oxide layer (23), the thickness of the third tunneling oxide layer (23) is 1-2 nm; and / or, The N-type doped region (20) further comprises: a fourth tunneling oxide layer (25), wherein: The fourth tunneling oxide layer (25) is located between the heat-resistance and isolation layer (24) and the second N-type doping layer (26); Preferably, for the structure provided with the fourth tunneling oxide layer (25), the thickness of the fourth tunneling oxide layer (25) is 1-2 nm; Preferably, the doping concentration of the first N-type doping layer (22) is less than the doping concentration of the second N-type doping layer (26); Preferably, the heat-resistant insulating layer (24) comprises a silicon carbide layer; and / or, The doping concentration of the first N-type doping layer (22) is less than or equal to 4×10 20 Pieces / cm 3 ; and / or, The doping concentration of the second N-type doping layer (26) is greater than or equal to 5×10 20 Pieces / cm 3 , and less than or equal to 5×10 25 Pieces / cm 3 .

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