Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and relates to the technical field of solar cell manufacturing, and the method comprises the steps: preparing a first tunneling oxide layer, an intrinsic amorphous silicon layer and a shielding layer on a first main surface of a silicon substrate from inside to outside in a stacked manner; heating the first tunneling oxide layer and the intrinsic amorphous silicon layer at a first temperature, so that the first tunneling oxide layer is converted into a second tunneling oxide layer, and the intrinsic amorphous silicon layer is converted into an intrinsic polycrystalline silicon layer; wherein the pore size of a pore channel contained in the first tunneling oxide layer is 0.001 nm to 0.2 nm and is smaller than the pore size of a pore channel contained in the second tunneling oxide layer; removing the shielding layer; and carrying out boron doping on the intrinsic polycrystalline silicon layer to form a doped polycrystalline silicon layer. According to the embodiment, the aperture of the pore channel in the first tunneling oxide layer is increased by using the shielding layer, the second tunneling oxide layer which is more beneficial to boron diffusion is obtained, and the recombination of boron atoms on the interface of the tunneling oxide layer is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] In the existing solar cell preparation process, a passivation contact structure is usually formed by preparing a stacked tunneling oxide layer and a doped polysilicon layer. Specifically, according to the different doping types, it can be divided into P-TOPCon (boron doping) and N-TOPCon structures (phosphorus doping). Compared with phosphorus doping, the passivation performance of the passivation contact structure obtained by boron doping is usually poor. This is because the solid solubility of boron atoms in the tunneling oxide layer is large, much higher than the solid solubility in the doped polysilicon layer, causing boron atoms to accumulate near the interface between the tunneling oxide layer and the doped polysilicon layer, causing a large amount of interface recombination and Auger recombination, affecting the overall performance of the solar cell. Summary of the invention

[0003] In view of this, an embodiment of the present invention provides a solar cell and a method for preparing the same, which utilizes a shielding layer stacked on the outside of an intrinsic amorphous silicon layer to prevent the escape of atomic hydrogen in the intrinsic amorphous silicon layer at a first temperature, so that during the annealing process, atomic hydrogen can be enriched in the first tunneling oxide layer to increase the aperture of the pores in the first tunneling oxide layer, thereby obtaining a second tunneling oxide layer that is more conducive to boron diffusion, thereby reducing the interface recombination of boron atoms between the tunneling oxide layer and the doped polycrystalline silicon layer.

[0004] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0005] In a first aspect, the present invention provides a method for preparing a solar cell, comprising: step 1, preparing a first tunneling oxide layer, an intrinsic amorphous silicon layer and a shielding layer by stacking from the inside to the outside on a first main surface of a silicon substrate; step 2, heating the first tunneling oxide layer and the intrinsic amorphous silicon layer at a first temperature, so that the first tunneling oxide layer is transformed into a second tunneling oxide layer, and the intrinsic amorphous silicon layer is transformed into an intrinsic polycrystalline silicon layer; wherein the pore size of the channel included in the first tunneling oxide layer is smaller than the pore size of the channel included in the second tunneling oxide layer; the pore size of the channel included in the second tunneling oxide layer is 0.001 nm ~ 0.2 nm; step 3, removing the shielding layer; step 4, boron-doping the intrinsic polycrystalline silicon layer to form a doped polycrystalline silicon layer.

[0006] Optionally, the first temperature is 800°C~900°C; and / or, the time for heating the first tunneling oxide layer and the intrinsic amorphous silicon layer is 1min~30min; and / or, step 4 includes: boron doping the intrinsic polycrystalline silicon layer at a second temperature; wherein the second temperature is higher than the first temperature.

[0007] Optionally, the second temperature is 900°C~1000°C.

[0008] Optionally, a density of channels included in the first tunnel oxide layer is smaller than a density of channels included in the second tunnel oxide layer.

[0009] Optionally, the hole density in the first tunnel oxide layer is 1×10 6 Pieces / cm 3 ~1×10 8 Pieces / cm 3 ; and / or, the pore density in the second tunneling oxide layer is 5×10 6 Pieces / cm 3 ~5×10 8 Pieces / cm 3 .

[0010] Optionally, step 1 includes: step 11, preparing a first tunneling oxide layer on the first main surface of the silicon substrate under low-pressure oxygen conditions; step 12, cooling to a third temperature, and preparing an intrinsic amorphous silicon layer on the first tunneling oxide layer; step 13, coating a liquid polymer on the outside of the intrinsic amorphous silicon layer, and obtaining the shielding layer by cross-linking and shaping.

[0011] Optionally, the liquid polymer includes at least one of polymethyl methacrylate, organic polybutylene succinate, polystyrene and organic-inorganic hybrid polybutylene succinate; and / or the molecular weight of the liquid polymer is 100,000 to 5,000,000; and / or the coating method of the liquid polymer is at least one of spin coating and scraping coating.

[0012] Optionally, the thickness of the shielding layer is 0.1 μm to 500 μm; and / or, the step 3 comprises: removing the shielding layer by using cyclohexanone or chloroform.

[0013] Optionally, the third temperature is 450°C~560°C.

[0014] In a second aspect, the present invention provides a solar cell comprising: a silicon substrate, and a second tunneling oxide layer and a doped polysilicon layer sequentially arranged from the inside to the outside on a first main surface of the silicon substrate; wherein the doped polysilicon layer is doped with boron atoms; and the pore size of the channel contained in the second tunneling oxide layer is 0.001 nm ~ 0.2 nm.

[0015] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: a shielding layer stacked on the outside of the intrinsic amorphous silicon layer is used to avoid the escape of atomic hydrogen in the intrinsic amorphous silicon layer at the first temperature, so that during the annealing process, atomic hydrogen can be enriched in the first tunneling oxide layer to increase the aperture of the pores in the first tunneling oxide layer, thereby obtaining a second tunneling oxide layer that is more conducive to boron diffusion, thereby reducing the interface recombination of boron atoms between the tunneling oxide layer and the doped polycrystalline silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to better understand the present invention and do not constitute an improper limitation of the present invention.

[0017] Figure 1 is a schematic flow chart of a method for preparing a solar cell according to an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a specific preparation process of step S101 according to an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of the cross-sectional structure of the silicon substrate prepared in step S203 according to an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a cross-sectional structure of a silicon substrate obtained after removing the shielding layer 4 according to an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of a cross-sectional structure of a silicon substrate obtained after step S104 according to an embodiment of the present invention;

[0022] Figure 6 It is the ×10CV curve analysis result obtained according to Example 1 and Comparative Example 1 of the present invention.

[0023] The reference numerals are as follows:

[0024] 1-silicon substrate; 2-first tunneling oxide layer; 21-second tunneling oxide layer; 3-intrinsic amorphous silicon layer; 31-intrinsic polysilicon layer; 32-doped polysilicon layer; 4-shielding layer; 5-passivation layer. DETAILED DESCRIPTION

[0025] A solar cell is a photoelectric semiconductor sheet that uses sunlight to generate electricity directly. It is also called a "solar chip" or "photovoltaic cell". As long as it is illuminated by light that meets certain illumination conditions, it can instantly output voltage and generate current in the presence of a circuit. In physics, it is called solar photovoltaic (PV), or photovoltaic for short. In order to conveniently and clearly describe the method for preparing a solar cell and the solar cell of the present invention, the following exemplary embodiments of the present invention are described in conjunction with the accompanying drawings, which include various details of the embodiments of the present invention to facilitate understanding, and they should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present invention. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0026] In recent years, with the development of monocrystalline solar cells, especially the successful industrialization of passivated emitter and back field (PERC) technology, the efficiency improvement of mass-produced cells on P-type silicon wafers has reached a bottleneck. More attention has been paid to N-type cells with higher body minority carrier lifetime and lower attenuation. Three types of cell structures, including N-type PERT, heterojunction (HJT) and tunneling oxide passivated contact (TOPCon), have also gradually attracted attention from the industry. Among them, TOPCon cells, or passivated contact cells, have a structure in which an ultra-thin silicon oxide layer and a highly doped polysilicon layer are prepared on the silicon surface. The selective permeability of ultra-thin silicon oxide to carriers and the good field passivation effect of highly doped polysilicon and the substrate are used to effectively suppress the recombination of minority carriers on the silicon surface and increase the cell opening voltage.

[0027] However, since the solid solubility of boron atoms in the tunneling oxide layer is relatively large, much higher than that in the doped polysilicon layer, during the boron doping process, boron atoms will accumulate near the interface between the tunneling oxide layer and the doped polysilicon layer, causing a large amount of interfacial recombination and Auger recombination, affecting the overall performance of the solar cell. Therefore, how to reduce the Auger recombination in the boron doping process has become a technical problem that needs to be solved urgently.

[0028] In the prior art, there are usually two methods to reduce Auger recombination: the first is to set the thickness of the tunneling oxide layer to be thinner. Since there are more pores in the tunneling oxide layer itself, it is convenient for boron atoms to pass through well during the diffusion process when the thickness is thin. However, the thin thickness of the tunneling oxide layer will result in a very small process window, and the tunneling oxide layer is easily damaged during the boron diffusion process, resulting in passivation failure. The other is to increase the pore density in the tunneling oxide layer by high-temperature heating (1000℃-1200℃) on the basis of ensuring the original thickness of the tunneling oxide layer, but too high a temperature will affect the passivation performance of the silicon substrate itself, and the heating requires a significant increase in the process time, affecting the process capacity. Therefore, an embodiment of the present invention aims to provide a method for preparing a solar cell that does not require high-temperature heating while ensuring the thickness of the tunneling oxide layer.

[0029] In one embodiment of the present invention, Figure 1 As shown, this embodiment provides a method for preparing a solar cell, and the preparation method may include the following steps:

[0030] Step S101, preparing a first tunneling oxide layer 2, an intrinsic amorphous silicon layer 3 and a shielding layer 4 by stacking from inside to outside on a first main surface of a silicon substrate 1;

[0031] Step S102, heating the first tunnel oxide layer 2 and the intrinsic amorphous silicon layer 3 at a first temperature, so that the first tunnel oxide layer 2 is transformed into the second tunnel oxide layer 21, and the intrinsic amorphous silicon layer 3 is transformed into the intrinsic polycrystalline silicon layer 31; wherein the aperture of the pores included in the first tunnel oxide layer 2 is smaller than the aperture of the pores included in the second tunnel oxide layer 21; the aperture size of the pores included in the second tunnel oxide layer 21 is 0.001 nm to 0.2 nm, for example, it can be 0.001 nm, 0.005 nm, 0.01 nm, 0.05 nm, 0.1 nm or 0.2 nm, etc.;

[0032] Step S103, removing the shielding layer 4;

[0033] Step S104 , boron-doping the intrinsic polysilicon layer 31 to form a doped polysilicon layer 32 .

[0034] The first tunnel oxide layer 2 and the second tunnel oxide layer 21 are actually the same layer structure, but after being heated at the first temperature in step S102, the aperture of the channel changes, so the embodiment of the present invention uses different names to distinguish the layer structures with different apertures before and after heating. The aperture size of the first tunnel oxide layer 2 is basically the same as the aperture size of the conventional tunnel oxide layer, which is 0.0001nm~0.1nm, for example 0.0001nm, 0.001nm, 0.01nm, 0.1nm, etc.

[0035] In addition, the shielding layer 4 does not exist in the final solar cell layer structure. Its purpose is to prevent the escape of hydrogen atoms in the intrinsic amorphous silicon layer 3 during the heating and annealing of the first tunneling oxide layer 2 and the intrinsic amorphous silicon layer 3 in step S102, so as to achieve the effect of hydrogen atoms enriching in the first tunneling oxide layer 2 and obtaining the second tunneling oxide layer 21 with an increased aperture. It should be noted that at the first temperature, hydrogen atoms will be slowly released from the intrinsic amorphous silicon layer 3, but the released hydrogen atoms do not have a regular movement direction, so the shielding layer 4 is needed to block them, so that the hydrogen atoms can only move to the inner first tunneling oxide layer 2, thereby achieving the combination of atomic hydrogen and silicon oxide, and reducing the formation energy barrier of the first tunneling oxide layer 2. Therefore, after step S102, the shielding layer 4 needs to be removed before boron doping can be performed to obtain the doped polysilicon layer 32.

[0036] The above steps S101 to S104 are described in detail below:

[0037] For step S101, in an optional embodiment, as Figure 2 As shown, including:

[0038] Step S201, forming a first tunneling oxide layer 2 on a first main surface of a silicon substrate 1 under low-pressure oxygen flow conditions;

[0039] Step S202, cooling to a third temperature, and forming an intrinsic amorphous silicon layer 3 on the first tunnel oxide layer 2;

[0040] Step S203 , coating a liquid polymer on the outside of the intrinsic amorphous silicon layer 3 , and forming the shielding layer 4 through cross-linking.

[0041] For example, the cross-sectional structure of the silicon substrate prepared from the above steps S201 to S203 is as follows: Figure 3 As shown, specifically, the first tunneling oxide layer 2, the intrinsic amorphous silicon layer 3 and the shielding layer 4 can be prepared simultaneously on both sides of the silicon substrate 1, or can be prepared only on one side of the silicon substrate 1 according to actual needs, and the present invention does not make specific limitations on this.

[0042] The temperature for preparing the first tunnel oxide layer 2 is usually higher than the temperature for preparing the intrinsic amorphous silicon layer in step S202. Specifically, in step S201, the dried silicon substrate 1 can be placed in a quartz boat, heated to 600°C to 700°C, such as 600°C, 650°C, 700°C, etc., under low pressure conditions, and 2000 sccm of oxygen is introduced to prepare a tunnel oxide layer 2 with a thickness of 1.5nm to 2.0nm. The preparation thickness of the tunnel oxide layer 2 is related to the process parameters. Under different temperatures and different pressure conditions, the thickness of the prepared tunnel oxide layer 2 is also different, and the present invention does not make specific limitations on this.

[0043] In an optional embodiment, the third temperature is 450°C to 560°C, such as 450°C, 480°C, 520°C, 560°C, etc., that is, step S202 may specifically include: cooling the temperature from 600°C to 700°C to 500°C, and introducing 8000 sccm of silane to grow an intrinsic amorphous silicon layer 3 with a thickness of 300nm. It can be understood that as the temperature increases, when the temperature is higher than 560°C, the movement of silicon atoms increases, and an ordered crystal structure will be formed. Therefore, the embodiment of the present invention sets the third temperature to 450°C to 560°C, which can ensure that the disordered amorphous silicon structure is prepared in step S202.

[0044] For the liquid polymer in step S203, in an optional embodiment, it includes at least one of polymethyl methacrylate (PMMA), organic polybutylene succinate (PBS), polystyrene (EPS) and organic-inorganic hybrid polybutylene succinate. Among them, the organic-inorganic hybrid polybutylene succinate may include PBS grafted with calcium fluoride nanoparticles. In the present application, the shielding layer 4 is used to block the escape of hydrogen atoms on the one hand, and on the other hand, it is necessary to ensure that no physical or chemical reaction occurs at the first temperature, so as to smoothly increase the aperture of the pores in the first tunneling oxide layer 2 to obtain the second tunneling oxide layer 21. Therefore, the shielding layer 4 in the embodiment of the present invention needs to ensure a certain density and high temperature resistance. The above-mentioned multiple polymers are relatively stable under high temperature conditions, and the multiple branched structures present in the polymer can have good density after cross-linking and finalization. Among them, as the number of branches increases, the density is better.

[0045] In a further optional embodiment, the molecular weight of the liquid polymer is 100,000 to 5 million, for example, it can be 100,000, 500,000, 1 million, 2 million, 3 million, 4 million or 5 million, etc. It can be understood that as the number of branches increases, the molecular weight of the liquid polymer will also increase, that is, the number of branches is positively correlated with the molecular weight, so the higher the molecular weight of the liquid polymer, the better the density.

[0046] In an optional embodiment, the coating method of the liquid polymer in step S203 may be at least one of spin coating and scraping coating. Specifically, during the coating process, the coating thickness and coating uniformity are ensured, and other coating methods may be selected, which are not further limited in the present invention.

[0047] In an optional embodiment, the thickness of the shielding layer 4 is 0.1 μm to 500 μm, for example, 0.1 μm, 1 μm, 20 μm, 50 μm, 120 μm, 200 μm, 250 μm, 350 μm, 400 μm, 500 μm, etc. If the thickness is too thin, the blocking effect on hydrogen atoms will be weakened, thereby affecting the effect of changing the aperture in the first tunneling oxide layer 2. If the thickness is too thick, it will not only increase the difficulty of subsequent removal of the shielding layer 4, but also cause waste of liquid polymer materials.

[0048] For step S102, in an optional embodiment, the first temperature is 800°C to 900°C, such as 800°C, 820°C, 850°C, 900°C, etc. After the intrinsic amorphous silicon layer 3 and the first tunneling oxide layer 2 are prepared by step S10, a high-temperature annealing process is required to transform the intrinsic amorphous silicon layer 3 into an intrinsic polycrystalline silicon layer 31, and at the same time, the hydrogen atoms in the intrinsic amorphous silicon layer 3 are directed to transfer to the first tunneling oxide layer 2 to obtain a second tunneling oxide layer 21 with a larger pore size. Normally, when the temperature reaches 300°C to 400°C, hydrogen atoms begin to migrate, but the migration speed is slow. In order to shorten the migration time of hydrogen atoms, we set the temperature to 800°C to 900°C, which can not only ensure the transformation of amorphous silicon to polycrystalline silicon, but also improve the migration efficiency of hydrogen atoms. At the same time, the annealing process also needs to last for a certain period of time to ensure that the first tunneling oxide layer 2 can be smoothly transformed into the second tunneling oxide layer 21. In an optional embodiment, the time for heating the first tunneling oxide layer 2 and the intrinsic amorphous silicon layer 3 is 1min~30min, for example 1min, 10min, 20min, 30min, etc.

[0049] In an optional embodiment, the density of the pores included in the first tunnel oxide layer 2 is less than the density of the pores included in the second tunnel oxide layer 21. It can be understood that at the first temperature, not only the pore size of the pores in the first tunnel oxide layer 2 is increased, but also the density of the pores is changed. In a further optional embodiment, the density of the pores in the first tunnel oxide layer 2 is 1×10 6 Pieces / cm 3 ~1×10 8 Pieces / cm 3 , for example 1×10 6 Pieces / cm 3 , 1×10 7 Pieces / cm 3 , 1×10 8 Pieces / cm 3 etc.; the hole density in the second tunnel oxide layer 21 is 5×10 6 Pieces / cm 3 ~5×10 8 Pieces / cm 3, for example 5×10 6 Pieces / cm 3 , 5×10 7 Pieces / cm 3 , 5×10 8 Pieces / cm 3 It should be noted that, although the pore size and density of the pores will change, they generally will not change greatly in magnitude, that is, the pore density in the first tunnel oxide layer 2 is 1×10 6 Pieces / cm 3 When the annealing process is carried out at the first temperature, the pore density of the second tunnel oxide layer 21 may be 5×10 6 Pieces / cm 3 , but will not become 5×10 8 Pieces / cm 3 .

[0050] Through the above process, during the annealing process of transforming the intrinsic amorphous silicon layer 3 into the intrinsic polycrystalline silicon layer 31, the shielding layer 4 is simultaneously used to increase the aperture and density of the channels in the first tunneling oxide layer 2 to obtain the second tunneling oxide layer 21, thereby achieving the deposition of boron atoms on the silicon substrate through larger apertures and more channels, avoiding the accumulation problem on the surface of the tunneling oxide layer, and reducing interface recombination and Auger recombination.

[0051] In an optional embodiment, step S103 includes: using cyclohexanone or chloroform to remove the shielding layer 4. Cyclohexanone or chloroform, as a solvent, can dissolve the aforementioned multiple liquid polymers well and will not chemically react with the second tunneling oxide layer 21.

[0052] For example, after the shielding layer 4 is removed in step S103, the cross-sectional structure of the silicon substrate is obtained as follows: Figure 4 As shown. Since the second tunnel oxide layer 21 is obtained by the first tunnel oxide layer 2 through internal aperture transformation, and the intrinsic polysilicon layer 31 is obtained by annealing the intrinsic amorphous silicon layer 3, in an optional embodiment, the second tunnel oxide layer 21 and the first tunnel oxide layer 2 have the same thickness, and the intrinsic polysilicon layer 31 and the intrinsic amorphous silicon layer 3 have the same thickness.

[0053] After removing the shielding layer 4, the boron doping process of step S104 can be carried out. Specifically, in an optional embodiment, step S104 further includes: boron doping the intrinsic polysilicon layer 31 at a second temperature; wherein the second temperature is higher than the first temperature. It should be noted here that the second temperature is set higher than the first temperature because the solid solubility of boron atoms is positively correlated with temperature, and when the boron diffusion temperature is less than 900°C, a large number of boron atoms will not be activated, resulting in composite losses, and too high a temperature will cause the oxide layer to be destroyed and affect body passivation, etc. Therefore, the boron diffusion temperature range of the present invention is more suitable in the range of 900°C to 950°C, for example, it can be 900°C, 910°C, 920°C, 930°C, 940°C or 950°C, etc.

[0054] In the actual preparation process, as the doped polysilicon layer 32 is formed, a borosilicate glass layer is simultaneously formed outside the doped polysilicon layer 32 while the boron diffuses. In an optional embodiment, the silicon substrate is cleaned with a hydrofluoric acid solution to remove the extra borosilicate glass layer.

[0055] In a further optional embodiment, after step S104, the process further includes: laminating and preparing a passivation anti-reflection layer 5 on the outer side of the doped polysilicon layer 32. For example, the cross-sectional structure of the prepared silicon substrate is as follows: Figure 5 The passivation anti-reflection layer 5 includes a passivation layer and an anti-reflection layer. Specifically, the passivation layer may be an Al2O3 anti-reflection layer with a thickness of 5nm to 8nm, or may be a SiN3 anti-reflection layer with a thickness of 50nm to 100nm. x film.

[0056] In summary, the method for preparing a solar cell provided in an embodiment of the present invention utilizes a shielding layer stacked on the outside of the intrinsic amorphous silicon layer to prevent the escape of atomic hydrogen in the intrinsic amorphous silicon layer at a first temperature, so that during the annealing process, atomic hydrogen can be enriched in the first tunneling oxide layer to increase the aperture of the pores in the first tunneling oxide layer, thereby obtaining a second tunneling oxide layer that is more conducive to boron diffusion, thereby reducing the interface recombination of boron atoms between the tunneling oxide layer and the doped polycrystalline silicon layer.

[0057] Below is still Figure 5 Taking the example of FIG. 1 as an example, the specific structure of the solar cell provided by the embodiment of the present invention is described. Figure 5 As shown, the solar cell provided by the present invention includes: a silicon substrate 1, and a second tunneling oxide layer 21 and a doped polysilicon layer 32 arranged in sequence from the inside to the outside on the first main surface of the silicon substrate 1; wherein the doped polysilicon layer 32 is doped with boron atoms; the pore size of the channel contained in the second tunneling oxide layer 21 is 0.001 nm ~ 0.2 nm.

[0058] It should be noted that although the existing solar cell structure also includes a tunneling oxide layer and a doped polysilicon layer, the apertures of the pores in the tunneling oxide layer in the existing structure and the pores in the second tunneling oxide layer 21 in the present invention are different. The second tunneling oxide layer 21 in the present invention has an increased aperture based on the first tunneling oxide layer 2. Therefore, there will be no problem of boron atom accumulation on the surface of the second tunneling oxide layer 2 in the solar cell provided by the present invention.

[0059] Specifically, the size of the aperture in the second tunnel oxide layer 21 is always larger than the size of the aperture in the first tunnel oxide layer 2 (ie, the size of the aperture in the tunnel oxide layer in the prior art).

[0060] In an optional embodiment, the thickness of the doped polysilicon layer 32 is 100nm~500nm, for example, 100nm, 200nm, 300nm, 400nm, 500nm, etc.; the thickness of the second tunneling oxide layer 21 is 1.5nm~2.0nm, for example, 1.5nm, 1.6nm, 1.7nm, 1.8nm, 2.0nm, etc.

[0061] In a further optional embodiment, a passivation anti-reflection layer 5 is further provided outside the doped polysilicon layer 32. The passivation anti-reflection layer 5 includes a passivation layer and an anti-reflection layer. Specifically, the passivation layer may be Al2O3 with a thickness of 5nm to 8nm, and the anti-reflection layer may be SiN with a thickness of 50nm to 100nm. x film.

[0062] In some embodiments, the hole density in the second tunnel oxide layer 21 is 5×10 6 Pieces / cm 3 ~5×10 8 Pieces / cm 3 The pore density of the second tunnel oxide layer 21 is greater than that of the first tunnel oxide layer 2, that is, greater than that of the first tunnel oxide layer 2 in the prior art. This allows boron atoms to be deposited on the silicon substrate through larger pores and more pores, avoiding the accumulation problem on the surface of the tunnel oxide layer and reducing interface recombination and Auger recombination.

[0063] In summary, the solar cell provided in the embodiment of the present invention utilizes the second tunneling oxide layer obtained by increasing the aperture of the pores in the first tunneling oxide layer, which is more conducive to the smooth diffusion of boron atoms into the silicon substrate, and does not produce boron atom accumulation at the interface of the second tunneling oxide layer, thereby reducing the interface recombination of boron atoms between the tunneling oxide layer and the doped polysilicon layer.

[0064] Example 1

[0065] A method for preparing a solar cell, comprising:

[0066] Step a, performing texturing and polishing treatment on an N-type silicon wafer having a resistivity of 20 Ω cm and a thickness of 150 μm;

[0067] Step b, placing the dried silicon wafer in a quartz boat, heating it to 600°C under low pressure, introducing 2000 sccm of oxygen to grow a 1.5 nm SiO2 layer, then cooling it to 500°C, introducing 8000 sccm of silane to grow a 300 nm thick intrinsic amorphous silicon;

[0068] Step c, spin coating a PMMA layer with a molecular weight of 500,000 on the amorphous silicon layer at a rotation speed of 3000 rpm, and annealing at 800° C. for 10 minutes; wherein the PMMA thickness is 500 nm;

[0069] Step d, removing the PMMA layer on the surface using a cyclohexanone solution;

[0070] Step e, raising the temperature to 900° C., introducing a boron source to complete boron diffusion, and obtaining a doped polysilicon layer and a BSG layer located outside the doped polysilicon layer;

[0071] Step f, removing the BSG layer on the surface using hydrofluoric acid;

[0072] Step g, Al2O3 coating is performed on the outside of the doped polysilicon layer to grow an Al2O3 layer with a thickness of 6 nm, and silane and ammonia are introduced into a plasma enhanced chemical vapor deposition device at 540°C to deposit a SiN layer with a thickness of 75 nm. x film.

[0073] Example 2

[0074] A method for preparing a solar cell, the difference from Example 1 is that the molecular weight of PMMA is 50,000.

[0075] Example 3

[0076] A method for preparing a solar cell, the difference from Example 1 is that the thickness of PMMA is 10 nm.

[0077] Comparative Example 1

[0078] A method for preparing a solar cell, comprising:

[0079] Step a, performing texturing and polishing treatment on an N-type silicon wafer having a resistivity of 20 Ω cm and a thickness of 150 μm;

[0080] Step b, placing the dried silicon wafer in a quartz boat, heating it to 600°C under low pressure, introducing 2000 sccm of oxygen to grow a 1.5 nm SiO2 layer, then cooling it to 500°C, introducing 8000 sccm of silane to grow a 300 nm thick intrinsic amorphous silicon;

[0081] Step c, raising the temperature to 900° C., introducing a boron source to complete boron diffusion, and obtaining a doped polysilicon layer and a BSG layer located outside the doped polysilicon layer;

[0082] Step d, removing the BSG layer on the surface using hydrofluoric acid;

[0083] Step e: Al2O3 is coated on the outside of the doped polysilicon layer to grow an Al2O3 layer with a thickness of 6 nm, and silane and ammonia are introduced into a plasma enhanced chemical vapor deposition device at 540 °C to deposit a SiN layer with a thickness of 75 nm. x film.

[0084] The solar cells prepared in the above-mentioned Examples 1 to 3 and Comparative Example 1 were subjected to performance tests, and the test results are shown in Table 1 below:

[0085]

[0086] From the above results, it can be seen that compared with Example 1, the molecular weight of the shielding layer PMMA in Example 2 is reduced, so the implicit open circuit voltage (iVoc) is lower, the life (Lifetime) is shorter, and the composite current density (J0) is larger. This is because the molecular weight of the shielding layer is too small and the structure is not dense enough, resulting in the shielding effect on hydrogen is not as good as in Example 1. Therefore, the adjustment range of the pore size and density in the tunneling oxide layer is small, so that the pore size in the tunneling oxide layer is still small, and it is impossible to allow enough diffusion elements to diffuse inward, which eventually leads to the increase of the square resistance Rsheet and the formation of a larger surface composite; similarly, the thickness of the PMMA layer in Example 3 is thinner than that in Example 1. Although the molecular weight is the same as that in Example 1, the difference in thickness also leads to a poor shielding effect on hydrogen, so the surface composite is also greater than that in Example 1. In other words, by comparing the test data between Example 2 and Example 3 and Example 1, it can be seen that the thinning of the thickness of the shielding layer 4 and the reduction of the molecular weight will affect the overall passivation performance of the solar cell to a certain extent.

[0087] In addition, ECV curve analysis was performed on Example 1 and Comparative Example 1, and the results are as follows: Figure 6 As shown in Table 1 and Figure 6It can be seen from the test results that the embodiment of the present invention effectively increases the density of the holes in the tunnel oxide layer during the annealing process at the first temperature by setting the shielding layer 4, so that the doping concentration and peak concentration of boron atoms after boron doping ( Figure 6 The maximum value of the doping concentration in the silicon matrix) is reduced, and the doping concentration of the boron atoms in the silicon matrix varies ( Figure 6 The slope of the change in doping concentration in the middle depth range of 0.26μm-0.35μm) is also relatively reduced, the square resistance is correspondingly smaller, and the implicit open circuit voltage (iVoc) of Example 1 is significantly higher than the open circuit voltage of Comparative Example 1, indicating that increasing the pore density effectively reduces interface recombination and Auger recombination.

[0088] The introduction provided in the above steps is only used to help understand the structure, method and core idea of ​​the present invention. For ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also belong to the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: include: Step 1, preparing a first tunneling oxide layer (2), an intrinsic amorphous silicon layer (3) and a shielding layer (4) by stacking from inside to outside on a first main surface of a silicon substrate (1); Step 2, heating the first tunneling oxide layer (2) and the intrinsic amorphous silicon layer (3) at a first temperature, so that the first tunneling oxide layer (2) is transformed into a second tunneling oxide layer (21), and the intrinsic amorphous silicon layer (3) is transformed into an intrinsic polycrystalline silicon layer (31); wherein the pore size of the pores contained in the first tunneling oxide layer (2) is smaller than the pore size of the pores contained in the second tunneling oxide layer (21); and the pore size of the pores contained in the second tunneling oxide layer (21) is 0.001 nm to 0.2 nm; Step 3, removing the shielding layer (4); Step 4: boron-doping the intrinsic polysilicon layer (31) to form a doped polysilicon layer (32).

2. The preparation method according to claim 1, characterized in that: The first temperature is 800° C. to 900° C.; and / or, The time for heating the first tunnel oxide layer (2) and the intrinsic amorphous silicon layer (3) is 1 minute to 30 minutes; and / or, The step 4 comprises: The intrinsic polysilicon layer (31) is doped with boron at a second temperature; wherein the second temperature is higher than the first temperature.

3. The preparation method according to claim 2, characterized in that: The second temperature is 900°C to 1000°C.

4. The preparation method according to claim 1, characterized in that: The density of the channels included in the first tunneling oxide layer (2) is smaller than the density of the channels included in the second tunneling oxide layer (21).

5. The preparation method according to claim 4, characterized in that: The hole density in the first tunneling oxide layer (2) is 1×10 6 Pieces / cm 3 ~1×10 8 Pieces / cm 3 ; and / or, The pore density in the second tunneling oxide layer (21) is 5×10 6 Pieces / cm 3 ~5×10 8 Pieces / cm 3 .

6. The preparation method according to claim 1, characterized in that: The step 1 comprises: Step 11, preparing a first tunneling oxide layer (2) on the first main surface of the silicon substrate (1) under low-pressure oxygen flow conditions; Step 12, cooling the layer to a third temperature, and preparing an intrinsic amorphous silicon layer (3) on the first tunneling oxide layer (2); Step 13, coating a liquid polymer on the outside of the intrinsic amorphous silicon layer (3), and forming the shielding layer (4) by cross-linking.

7. The preparation method according to claim 6, characterized in that: The liquid polymer includes at least one of polymethyl methacrylate, organic polybutylene succinate, polystyrene and organic-inorganic hybrid polybutylene succinate; and / or, The molecular weight of the liquid polymer is 100,000 to 5,000,000; and / or, The liquid polymer is coated by at least one of spin coating and blade coating.

8. The preparation method according to claim 1, characterized in that: The thickness of the shielding layer (4) is 0.1 μm to 500 μm; and / or, The step 3 comprises: removing the shielding layer (4) by using cyclohexanone or chloroform; Preferably, the third temperature is 450°C-560°C.

9. A solar cell, characterized in that: include: A silicon substrate (1), and a second tunneling oxide layer (21) and a doped polysilicon layer (32) arranged in sequence from the inside to the outside on a first main surface of the silicon substrate (1); wherein: The doped polysilicon layer (32) is doped with boron atoms; The pore size of the pores contained in the second tunneling oxide layer (21) is 0.001 nm to 0.2 nm.

10. The solar cell according to claim 9, characterized in that: The thickness of the doped polysilicon layer (32) is 100 nm to 500 nm; and / or, The thickness of the second tunneling oxide layer (21) is 1.5 nm to 2.0 nm; And / or, the pore density in the second tunneling oxide layer (21) is 5×10 6 Pieces / cm 3 ~5×10 8 Pieces / cm 3 .

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