Low-power-consumption infrared strain illuminator for GIS fault detection and preparation method of low-power-consumption infrared strain illuminator

Abstract

The invention discloses a low-power-consumption infrared strain illuminator for GIS fault detection and a preparation method. The illuminator sequentially comprises a substrate layer, a pseudo substrate layer, a relaxation layer, an n + type SiGeSn layer, an intrinsic GeSn layer and a p + type SiGeSn layer from bottom to top. The n + type SiGeSn layer, the intrinsic GeSn layer and the p + type SiGeSn layer form an active region; a first metal electrode is deposited on the top surface of the p + type SiGeSn layer, and a second metal electrode is deposited on the top end of the relaxation layer and the outer side of the n + type SiGeSn layer. According to the low-power-consumption infrared strain light emitter, the light emission spectrum can be adjusted at will within the infrared range of 350 cm <-1 >-650 cm <-1 >.

Description

Technical Field

[0001] The invention belongs to the technical field of silicon-based optoelectronics and relates to a low-power infrared strain illuminator for GIS fault detection. Background Art

[0002] The insulation and arc extinguishing performance of sulfur hexafluoride SF6 gas is far superior to that of air under the same environment, which makes SF6 widely used as the insulating medium of fully enclosed gas-insulated switchgear GIS equipment. Statistics show that insulation failure accounts for a large proportion of GIS failures. In the case of partial discharge, arc discharge, overheating, etc., SF6 gas will decompose. The decomposed gas will produce SF6 under the action of trace water and trace oxygen. x (x < 6), SO2, H2S, SOF2, SO2F2 and other gases. The generation of impurity gases will seriously weaken the insulation performance of SF6 gas, thus causing insulation failure. Therefore, the detection of SF6 decomposition gas is an important means of GIS fault detection.

[0003] With the rapid development of integrated circuits, driven by the post-Moore era, GIS fault infrared spectroscopy detection compatible with CMOS (complementary metal oxide semiconductor) technology has attracted widespread attention from researchers. The spectral characteristic peak of SF6 decomposition gas is distributed at 480 cm -1 -580 cm -1 The traditional infrared detection light source is TeCdHg (mercury cadmium telluride) laser, which is not only highly toxic, but also has a lattice constant of about 6.5 Å, which cannot match the lattice constant of Si (silicon) of 5.4 Å. Ge has a lattice constant of about 5.6 Å and is a Group VI element like Si. It has the same cubic crystal structure as Si and is compatible with CMOS technology, making it the focus of attention. However, Ge is an indirect bandgap semiconductor, and the energy of the bottom of its direct bandgap conduction band Γ energy valley is 136 meV higher than that of the bottom of the indirect bandgap L energy valley. Even if a silicon-based Ge laser is realized by large current injection, its light emission boundary is only 650 cm -1 But it cannot cover 480 cm -1 - 580 cm -1 In addition, the huge power consumption makes it impossible to become an infrared light source for GIS fault detection. Summary of the invention

[0004] The technical problem to be solved by the present invention is that the emission spectrum of the silicon-based infrared Ge light source used for GIS fault detection cannot cover 480 cm -1 -580 cm -1In order to solve the problems of infrared range and high power consumption, how to transform Ge into direct bandgap semiconductor GeSn by introducing another main group VI tin (Sn) and tensile strain to achieve a light emission spectrum of 350 cm -1 -650 cm -1 Any adjustment within the infrared range and the purpose of reducing power consumption at one time.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A low-power infrared strain illuminator for GIS fault detection, which consists of a substrate layer, a pseudo-substrate layer, a relaxation layer, and a n + type SiGeSn layer, intrinsic GeSn layer, p + Type SiGeSn layer; + type SiGeSn layer, intrinsic GeSn layer, p + The type SiGeSn layer constitutes the active region;

[0007] The p + The first metal electrode is deposited on the top of the SiGeSn layer, and the top of the relaxation layer and the n + A second metal electrode is deposited outside the SiGeSn layer.

[0008] In the aforementioned low-power infrared strain emitter for GIS fault detection, the substrate layer is a single-crystal Si substrate layer, the pseudo-substrate layer is a single-crystal Ge layer, and the relaxation layer is n + Style 0.95 Sn 0.05 .

[0009] In the aforementioned low-power infrared strain illuminator for GIS fault detection, the lattice constant of the relaxation layer is greater than the lattice constant of the pseudo substrate layer, and the lattice constant of the relaxation layer is smaller than the lattice constant of the active region material.

[0010] The aforementioned low-power infrared strain illuminator for GIS fault detection, n + type SiGeSn layer and p + The maximum positive energy difference is formed between the Γ energy valley bottom of the conduction band of the type SiGeSn layer material and the Γ energy valley bottom of the conduction band of the intrinsic GeSn layer material.

[0011] The aforementioned low-power infrared strain emitter for GIS fault detection,

[0012] The + The type SiGeSn layer is SiGeSn heavily doped with phosphorus;

[0013] The Sn component of the intrinsic GeSn layer material is less than 20%, and the intrinsic GeSn layer material is selected from intrinsic Ge 0.94Sn 0.06 ;

[0014] The p + The material of the SiGeSn layer is boron heavily doped SiGeSn.

[0015] The aforementioned low-power infrared strain emitter for GIS fault detection has an active area of ​​n + The heterojunction structure formed at the interface of the p-type SiGeSn layer and the intrinsic GeSn layer is a type I heterojunction. + The heterojunction structure formed at the interface of the SiGeSn layer is also a type I heterojunction, forming a double I-type heterojunction.

[0016] The aforementioned low-power infrared strain illuminator for GIS fault detection has a tensile strain source wrapped around the intrinsic GeSn layer. + The p+ type SiGeSn layer is wrapped with a compressive strain source one, and the p+ type SiGeSn layer is wrapped with a compressive strain source two; the tensile strain source is a Si3N4 film with residual compressive strain deposited by a PECVD method, and the compressive strain source one and the compressive strain source two are SiC films with residual tensile strain deposited by an MOCVD method.

[0017] In the aforementioned low-power infrared strain illuminator for GIS fault detection, the thickness of the tensile strain source in the middle along the Z-axis direction is greater than the thickness on the upper and lower sides; the thickness of the compressive strain source 1 and the compressive strain source 2 is the smallest on the side close to the tensile strain source, and the thickness increases linearly away from the tensile strain source.

[0018] A method for preparing a low-power infrared strain illuminator for GIS fault detection comprises the following steps:

[0019] Step 1: On the single crystal Si substrate layer, the pseudo substrate Ge layer, the relaxed n + Style 0.95 Sn 0.05 Layer, n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer, intrinsic Ge 0.94 Sn 0.06 Layer, p + Type Si 0.359 Ge 0.483 Sn 0.158 layer;

[0020] Step 2: Use photolithography to etch the n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer, intrinsic Ge0.94 Sn 0.06 Layer, p + Type Si 0.359 Ge 0.483 Sn 0.158 The layer is etched into a truncated cone of a set diameter;

[0021] Step 3: Intrinsic Ge 0.94 Sn 0.06 A Si3N4 tensile strain source film with residual compressive stress is deposited on the side surface of the layer by PECVD process;

[0022] Step 4: In n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer and p + Type Si 0.359 Ge 0.483 Sn 0.158 The SiC compressive strain source 108 and the compressive strain source 2 with residual tensile stress are deposited on the side surface of the layer by MOCVD process;

[0023] Step 5: After the residual stress of the strain source is released, the adhesive stripping method is used to remove the residual stress of the strain source. + Type Si 0.359 Ge 0.483 Sn 0.158 Layer top and relaxation n + Style 0.95 Sn 0.05 A first metal electrode and a second metal electrode are formed on the top of the layer, respectively, wherein the second metal electrode is outside the SiC compressive strain source.

[0024] In the above-mentioned method for preparing a low-power infrared strain illuminator for GIS fault detection, in step 1, p + The type SiGeSn material adopts the boron ion implantation process, + The SiGeSn type material is made by phosphorus ion implantation process.

[0025] In the aforementioned method for preparing a low-power infrared strain light emitter for GIS fault detection, in step 3, the thickness of the tensile strain source in the middle along the Z-axis direction is not less than the thickness on the upper and lower sides.

[0026] In the aforementioned method for preparing a low-power infrared strain light emitter for GIS fault detection, in step 4, the thickness of the compressive strain source along the Z-axis direction remains unchanged or gradually decreases, and the thickness of the compressive strain source along the Z-axis direction remains unchanged or gradually increases.

[0027] The beneficial effects achieved by the present invention are as follows: the low-power infrared strain illuminator of the present invention is well compatible with silicon-based CMOS technology, which is beneficial to the integration of GIS fault detection system. By introducing Sn and tensile strain to transform Ge into a direct bandgap semiconductor GeSn, a luminescence spectrum of 350 cm -1 - 650 cm -1 Any adjustment within the infrared range.

[0028] The present invention realizes low power consumption of the light-emitting device by designing a lattice-matched SiGeSn / GeSn / SiGeSn double I-type heterojunction band structure, and utilizes the structural design of tensile strain sources and compressive strain sources to further increase the barrier difference of the I-type heterojunction, enhance the carrier restriction capability of the light-emitting region, and further reduce the power consumption of the light-emitting device.

[0029] Through the design of the energy band structure, the SiGeSn / GeSn / SiGeSn double I-type heterostructure is used to reduce power consumption for the second time; the device structure design of the tensile strain source and the compressive strain source is used to increase the barrier difference of the I-type heterojunction, thereby reducing the power consumption of the light source device again. In addition, through the design of the components of the heterojunction materials SiGeSn and GeSn, the lattice matching of SiGeSn and GeSn is achieved, and the material quality of the light emission area (intrinsic GeSn layer in the active area) is guaranteed, which is conducive to further reducing the power consumption of the light source device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a three-dimensional schematic diagram of a low-power infrared strain illuminator for GIS fault detection in Example 1;

[0031] Figure 2 It is an XZ cross-sectional view of a low-power infrared strain illuminator for GIS fault detection in Example 1;

[0032] Figure 3 This is a processing schematic diagram of step 1 of a method for preparing a low-power infrared strain illuminator for GIS fault detection in Example 4;

[0033] Figure 4 This is a processing schematic diagram of step 2 of a method for preparing a low-power infrared strain illuminator for GIS fault detection in Example 4;

[0034] Figure 5 This is a processing schematic diagram of step 3 of a method for preparing a low-power infrared strain illuminator for GIS fault detection in Example 4;

[0035] Figure 6 This is a processing schematic diagram of step 4 of a method for preparing a low-power infrared strain illuminator for GIS fault detection in Example 4;

[0036] Figure 7 This is a processing schematic diagram of step 5 of the method for preparing a low-power infrared strain illuminator for GIS fault detection in Example 4;

[0037] Figure 8 is Ge under relaxation condition in Example 1 0.94 Sn 0.06 / Si 0.359 Ge 0.483 Sn 0.158 The energy band diagram of

[0038] Fig. 9 is a strain distribution diagram of the XZ section of the device under the action of the strain source in Example 2;

[0039] Fig.10 is Ge under strain in Example 2 0.94 Sn 0.06 / Si 0.359 Ge 0.483 Sn 0.158 The energy band diagram of

[0040] Fig.11 An XZ cross-sectional view of a low-power infrared strain illuminator for GIS fault detection with irregular strain source thickness in Example 3;

[0041] Numbers in the accompanying drawings: 101 - substrate layer, 102 - pseudo substrate layer, 103 - relaxed layer, 104 - n + type SiGeSn layer, 105—intrinsic GeSn layer, 106—p + type SiGeSn layer, 107—tensile strain source, 108—compressive strain source one, 109—compressive strain source two, 110—first metal electrode, 111—second metal electrode, 11—XZ cross section. DETAILED DESCRIPTION

[0042] The present invention is described in more detail below through specific implementation modes to facilitate understanding of the technical solution of the present invention, but is not intended to limit the protection scope of the present invention.

[0043] Example 1

[0044] like Figure 1 As shown, this embodiment provides a low-power infrared strain emitter for GIS fault detection, which comprises, from bottom to top, a substrate layer 101, a pseudo substrate layer 102, a relaxation layer 103, and a + type SiGeSn layer 104, intrinsic GeSn layer 105, p + Type SiGeSn layer 106; + type SiGeSn layer 104, intrinsic GeSn layer 105, p+ The SiGeSn layer 106 forms an active region;

[0045] The p + The first metal electrode 110 is deposited on the top surface of the SiGeSn layer 106, and the top of the relaxation layer 103 and the n + A second metal electrode 111 is deposited outside the SiGeSn layer 104 .

[0046] The substrate layer 101 is a single crystal Si substrate layer, which is compatible with CMOS technology and is more easily implemented for large-scale integration.

[0047] The pseudo substrate layer 102 is a single crystal Ge layer, which acts as a preliminary buffer to make it easier to grow GeSn material with a larger lattice constant.

[0048] The relaxation layer 103 is n + Style 0.95 Sn 0.05 The lattice constant of the relaxation layer 103 is greater than that of the pseudo substrate layer 102, in order to further release the compressive stress introduced by the substrate to improve the quality of the single crystal grown by the active region material; the lattice constant of the relaxation layer 103 is smaller than that of the active region material, which is conducive to the growth of n + The SiGeSn layer 104 introduces a certain amount of compressive strain.

[0049] The active region is a vertically distributed and lattice-matched p + -in + Double I-type heterojunction strain structure, the vertical distribution is n from bottom to top of the active area + type SiGeSn layer 104, intrinsic GeSn layer 105 and p + The stacked structure of the SiGeSn layer 106 is more conducive to the wrapping of the strain source and the introduction of more uniform strain.

[0050] n + type SiGeSn layer 104 and p + The maximum positive energy difference is formed between the Γ energy valley bottom of the conduction band of the SiGeSn layer 106 material and the Γ energy valley bottom of the conduction band of the intrinsic GeSn layer 105 material.

[0051] The + The SiGeSn layer 104 is phosphorus heavily doped SiGeSn;

[0052] The Sn component of the intrinsic GeSn layer 105 material is less than 20%. The intrinsic GeSn layer 105 material can be selected from intrinsic Ge 0.94 Sn 0.06 ;

[0053] The p +The material of the SiGeSn layer 106 is boron heavily doped SiGeSn.

[0054] The lattice matching refers to the active area n + type SiGeSn layer, intrinsic GeSn layer and p + The lattice constant of the SiGeSn type layer material is the same, and the same lattice constant is conducive to reducing line defects and forming high-quality crystals, which is conducive to improving the light emission efficiency of the light-emitting device.

[0055] Active area n + The heterojunction structure formed at the interface of the p-type SiGeSn layer and the intrinsic GeSn layer is a type I heterojunction. + The heterojunction structure formed at the interface of the SiGeSn layer is also a type I heterojunction, forming a double type I heterojunction; the above SiGeSn component selection is similar to Ge 0.94 Sn 0.06 Lattice matching, forming a double I-type heterojunction, and the Si with the largest heterojunction barrier difference 0.359 Ge 0.483 Sn 0.158 Under the premise of lattice matching, the barrier difference of type I heterojunction is maximized by adjusting the composition ratio of the three elements of SiGeSn; the double type I heterojunction is beneficial for electron and hole carriers to be simultaneously confined to the intrinsic GeSn layer of light emission, which is beneficial for reducing the amount of carrier injection, thereby achieving the purpose of reducing power consumption.

[0056] like Figure 8 As shown, this embodiment is an infrared illuminator in a relaxed state without a strain source. 0.94 Sn 0.06 It is still an indirect bandgap semiconductor, with a direct bandgap of 0.593 eV, and the energy difference between the Γ energy valley and the L energy valley is E L -E Г = -0.007 eV, direct bandgap emission wavelength is 478 cm -1 ; Si in the relaxation state 0.359 Ge 0.483 Sn 0.158 The direct band gap is 0.703 eV, which is similar to the relaxed Ge 0.94 Sn 0.06 The potential barrier difference ΔE of the conduction band Γ energy valley formed Г = E Г, SiGeSn -E Г, GeSn is 0.061 eV, and the potential barrier difference between the valence band and the hole top is ΔE V = E V, GeSn -E V, SiGeSn is 0.050 eV.

[0057] Example 2

[0058] A low-power infrared strain illuminator for GIS fault detection, comprising, from bottom to top, a substrate layer 101, a pseudo-substrate layer 102, a relaxation layer 103, and a + type SiGeSn layer 104, intrinsic GeSn layer 105, p + Type SiGeSn layer 106;

[0059] The substrate layer 101 is a single crystal Si substrate layer with a 100 crystal orientation, the pseudo substrate layer 102 is a single crystal Ge layer, and the relaxation layer 103 is n + Style 0.95 Sn 0.05 , the n + The SiGeSn layer 104 is heavily doped with phosphorus, and the intrinsic GeSn layer 105 is intrinsic Ge 0.94 Sn 0.06 , the p + The SiGeSn layer 106 is boron heavily doped SiGeSn;

[0060] The p + The first metal electrode 110 is deposited on the top surface of the SiGeSn layer 106, and the top of the relaxation layer 103 and the n + A second metal electrode 111 is deposited outside the SiGeSn layer 104 .

[0061] The difference between this embodiment and Example 1 is that the intrinsic GeSn layer 105 is surrounded by a tensile strain source 107, n + The SiGeSn layer 104 is surrounded by a compressive strain source 108, + The type SiGeSn layer 106 is surrounded by a compressive strain source 109; the tensile strain source 107 is a 200 nm Si3N4 film with residual compressive strain deposited by a PECVD method, and the compressive strain source 1 108 and the compressive strain source 2 109 are 200 nm SiC films with residual tensile strain deposited by a MOCVD method.

[0062] The active area is wrapped by strain sources to form a strain structure, in which the light-emitting intrinsic GeSn layer is wrapped by tensile strain sources, which lowers the energy of the conduction band Γ energy valley and increases the energy of the valence band LH top, thereby achieving the purpose of adjusting the light emission wavelength; the heavily doped SiGeSn layer is wrapped by compressive strain sources, which increases the energy of the conduction band Γ energy valley and reduces the energy of the valence band LH top, thereby achieving the purpose of increasing the I-type heterojunction barrier difference.

[0063] like Fig. 9As shown, in this case, the tensile strain source 107 introduces biaxial tensile strains of about 0.6%, 0.6%, and -0.4% into the intrinsic GeSn layer 105, and the compressive strain source 1 108 and the compressive strain source 2 109 are in the n + type SiGeSn layer 104 and p + A biaxial compressive strain of approximately −0.4%, −0.4%, and 0.2% is introduced into the SiGeSn layer 106 .

[0064] like Fig.10 As shown, in this embodiment, Ge under tensile strain 0.94 Sn 0.06 The indirect band gap semiconductor is transformed into a direct band gap semiconductor. The direct band gap is reduced to 0.484 eV, and the energy difference between the Γ energy valley and the L energy valley is E L -E Г = 0.073 eV, the emission wavelength is stretched to 390 cm -1 ; Si under compressive strain 0.359 Ge 0.483 Sn 0.158 The direct band gap increases to 0.792 eV, which is similar to the tensile strained Ge 0.94 Sn 0.06 The potential barrier difference ΔE of the conduction band Γ energy valley formed Г = E Г, SiGeSn -E Г, GeSn is 0.212 eV, and the potential barrier difference between the valence band and the hole top is ΔE V = E V, GeSn -E V, SiGeSn is 0.096 eV.

[0065] Example 3

[0066] The difference between this embodiment and the second embodiment is that the thickness of the tensile strain source 107 in the middle along the Z-axis direction is greater than the thickness on the upper and lower sides; the thickness of the compressive strain source 108 and the compressive strain source 2 109 close to the tensile strain source 107 is the smallest, and the thickness increases linearly away from the tensile strain source 107, such as Fig.11 The effect of this embodiment is to avoid the tearing of the heterojunction interface caused by the sudden change of strain to produce interface defects, thereby reducing the luminous efficiency of the light-emitting device and increasing power consumption.

[0067] Example 4

[0068] A method for preparing a low-power infrared strain illuminator for GIS fault detection is provided, comprising the following steps:

[0069] Step 1: Figure 3As shown in FIG. 1 , on the single crystal Si substrate layer 101, a 50 nm pseudo substrate Ge layer 102, a 300 nm relaxed Ge layer 103, and a 300 nm Ge layer 104 are sequentially grown by molecular beam epitaxy. + Style 0.95 Sn 0.05 Layer 103, 500 nm n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer 104, 1000 nm intrinsic Ge 0.94 Sn 0.06 Layer 105, 500 nm p + Type Si 0.359 Ge 0.483 Sn 0.158 Layer 106;

[0070] Step 2: If Figure 4 As shown, the photolithography process is used to + Type Si 0.359 Ge 0.483 Sn 0.158 Layer 104, intrinsic Ge 0.94 Sn 0.06 Layer 105, p + Type Si 0.359 Ge 0.483 Sn 0.158 Layer 106 is etched into a truncated cone with a diameter of 600 nm;

[0071] Step 3: If Figure 5 As shown, in the intrinsic Ge 0.94 Sn 0.06 A 200 nm Si3N4 tensile strain source film 107 with residual compressive stress is deposited on the side surface of the layer 105 by a PECVD process;

[0072] Step 4: Figure 6 As shown, in n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer 104 and p + Type Si 0.359 Ge 0.483 Sn 0.158 The side surface of layer 106 is deposited with 200 nm SiC compressive strain sources 108 and 109 having residual tensile stress by MOCVD process;

[0073] Step 5: Figure 7 As shown in the figure, after the residual stress of the strain source is released, the adhesive stripping method is used to remove the residual stress of the strain source. + Type Si 0.359 Ge 0.483 Sn0.158 Layer top 106 and relaxation n + Style 0.95 Sn 0.05 A first metal electrode 110 and a second metal electrode 111 are formed on the top of the layer 103 , respectively, wherein the second metal electrode is outside the SiC compressive strain source 108 .

[0074] In step 1, the p+ type SiGeSn material is implanted with boron ions, and the n+ type SiGeSn material is implanted with phosphorus ions.

[0075] In step 3, the thickness of the tensile strain source 107 in the middle along the Z-axis direction is not less than the thickness of the upper and lower sides.

[0076] In step 4, the thickness of the compressive strain source 108 along the Z-axis direction remains unchanged or gradually decreases, and the thickness of the compressive strain source 109 along the Z-axis direction remains unchanged or gradually increases.

[0077] The embodiments described above are only preferred embodiments of the present invention and are not intended to limit the scope of implementation of the present invention. Therefore, any equivalent changes or modifications made according to the structures, features and principles described in the patent scope of the present invention should be included in the scope of the patent application of the present invention.

Claims

1. A low-power infrared strain illuminator for GIS fault detection, characterized in that: From bottom to top, they are substrate layer (101), pseudo substrate layer (102), relaxation layer (103), n + type SiGeSn layer (104), intrinsic GeSn layer (105), p + type SiGeSn layer (106); + The p+ type SiGeSn layer (104), the intrinsic GeSn layer (105), and the p+ type SiGeSn layer (106) constitute an active region; The p + A first metal electrode (110) is deposited on the top surface of the type SiGeSn layer (106), and a top surface of the relaxation layer (103) and a n + A second metal electrode (111) is deposited outside the SiGeSn layer (104).

2. A low-power infrared strain emitter for GIS fault detection according to claim 1, characterized in that: The substrate layer (101) is a single crystal Si substrate layer, the pseudo substrate layer (102) is a single crystal Ge layer, and the relaxation layer (103) is n + Type 0.95 Sn 0.05 .

3. The low-power infrared strain emitter for GIS fault detection according to claim 1 is characterized in that: The lattice constant of the relaxation layer (103) is greater than the lattice constant of the pseudo substrate layer (102), and the lattice constant of the relaxation layer (103) is less than the lattice constant of the active region material.

4. The low-power infrared strain emitter for GIS fault detection according to claim 1 is characterized in that: n + type SiGeSn layer (104) and p + The maximum positive energy difference is formed between the Γ energy valley bottom of the conduction band of the type SiGeSn layer (106) material and the Γ energy valley bottom of the conduction band of the intrinsic GeSn layer (105) material.

5. The low-power infrared strain emitter for GIS fault detection according to claim 1 is characterized in that: The + The SiGeSn layer (104) is phosphorus heavily doped SiGeSn; the Sn component of the intrinsic GeSn layer (105) material is less than 20%, and the intrinsic GeSn layer (105) material is selected from intrinsic Ge 0.94 Sn 0.06 ; said p + The material of the SiGeSn layer (106) is boron-heavily doped SiGeSn.

6. The low-power infrared strain emitter for GIS fault detection according to claim 1 is characterized in that: Active area n + The heterojunction formed at the interface of the p-type SiGeSn layer and the intrinsic GeSn layer is a type I heterojunction. + The heterojunction formed at the interface of the SiGeSn layer is also a type I heterojunction, that is, a double I-type heterojunction is formed in the active region.

7. The low-power infrared strain emitter for GIS fault detection according to claim 1, characterized in that: The intrinsic GeSn layer (105) is surrounded by a tensile strain source (107). + The SiGeSn layer (104) is surrounded by a compressive strain source (108), p + The SiGeSn layer (106) is surrounded by a second compressive strain source (109); the tensile strain source (107) is a Si3N4 film with residual compressive strain deposited by a PECVD method, and the first compressive strain source (108) and the second compressive strain source (109) are SiC films with residual tensile strain deposited by a MOCVD method.

8. The low-power infrared strain emitter for GIS fault detection according to claim 7, characterized in that: The thickness of the tensile strain source (107) in the middle along the Z-axis direction is greater than the thickness on the upper and lower sides; the thickness of the compressive strain source 1 (108) and the compressive strain source 2 (109) is the smallest on the side close to the tensile strain source (107), and the thickness increases linearly in the direction away from the tensile strain source (107).

9. A method for preparing a low-power infrared strain illuminator for GIS fault detection, characterized in that: The following steps are involved: Step 1: On the single crystal Si substrate layer (101), a pseudo substrate Ge layer (102), a relaxation n + Style 0.95 Sn 0.05 Layer (103), n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer (104), intrinsic Ge 0.94 Sn 0.06 Layer (105), p + Type Si 0.359 Ge 0.483 Sn 0.158 layer(106); Step 2: Use photolithography to etch the n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer (104), intrinsic Ge 0.94 Sn 0.06 Layer (105), p + Type Si 0.359 Ge 0.483 Sn 0.158 The layer (106) is etched into a truncated cone with a set diameter; Step 3: Intrinsic Ge 0.94 Sn 0.06 A Si3N4 tensile strain source film (107) having residual compressive stress is deposited on the side surface of the layer (105) by a PECVD process; Step 4: In n + Type Si 0.359 Ge 0.483 Sn 0.158 Layer (104) and p + Type Si 0.359 Ge 0.483 Sn 0.158 A first SiC compressive strain source (108) and a second SiC compressive strain source (109) having residual tensile stress are deposited on the side surface of the layer (106) by MOCVD process; Step 5: After the residual stress of the strain source is released, the adhesive stripping method is used to remove the residual stress of the strain source. + Type Si 0.359 Ge 0.483 Sn 0.158 Layer top (106) and relaxation n + Style 0.95 Sn 0.05 A first metal electrode (110) and a second metal electrode (111) are respectively formed on the top of the layer (103), wherein the second metal electrode is outside the SiC compressive strain source (108).

10. The method for preparing a low-power infrared strain illuminator for GIS fault detection according to claim 9, characterized in that: In step 1, p + The type SiGeSn material adopts the boron ion implantation process, + The SiGeSn type material is made by phosphorus ion implantation process.

11. The method for preparing a low-power infrared strain illuminator for GIS fault detection according to claim 9, characterized in that: In step 3, the thickness of the tensile strain source (107) in the middle along the Z-axis direction is not less than the thickness of the upper and lower sides.

12. The method for preparing a low-power infrared strain illuminator for GIS fault detection according to claim 9, characterized in that: In step 4, the thickness of the compressive strain source (108) along the Z-axis direction remains unchanged or gradually decreases, and the thickness of the compressive strain source (109) along the Z-axis direction remains unchanged or gradually increases.

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