Display device

Abstract

A display device includes: a first electrode; a pixel defining layer on the first electrode; a spacer layer on the pixel defining layer; an emission structure on the first electrode and the spacer layer; and a second electrode on the emission structure, in which the spacer layer includes a first spacer layer on the pixel defining layer and having a first width and a second spacer layer on the first spacer layer and having a second width greater than the first width, the emission structure includes a first layer having a first thickness and a second layer having a second thickness greater than the first thickness, and wherein the second spacer layer is between the first layer and the second layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0156653, filed on November 13, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device. Background Art

[0004] Recently, as interest in information display increases, research and development of display devices are being conducted.

[0005] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure include a display device having relatively improved reliability and a method of manufacturing the display device.

[0007] According to some embodiments of the present disclosure, a display device includes: a first electrode; a pixel defining layer on the first electrode; a spacer layer on the pixel defining layer; an emission structure on the first electrode and the spacer layer; and a second electrode on the emission structure. According to some embodiments, the spacer layer may include a first spacer layer on the pixel defining layer and having a first width and a second spacer layer on the first spacer layer and having a second width greater than the first width. According to some embodiments, the emission structure includes a first layer having a first thickness and a second layer having a second thickness greater than the first thickness. According to some embodiments, the second spacer layer may be between the first layer and the second layer.

[0008] According to some embodiments, the thickness of the first separation layer may be greater than the first thickness.

[0009] According to some embodiments, the thickness of the first separation layer may be less than the sum of the first thickness and the second thickness.

[0010] According to some embodiments, the first layer may be between the pixel defining layer and the second spacer layer.

[0011] According to some embodiments, the spacer layer may further include a third spacer layer on the second spacer layer and having a third width smaller than the second width, and a fourth spacer layer on the third spacer layer and having a fourth width larger than the third width.

[0012] According to some embodiments, the second layer may be between the second spacer layer and the fourth spacer layer.

[0013] According to some embodiments, the emission structure may further include a third layer having a third thickness smaller than the second thickness and a fourth layer having a fourth thickness larger than the third thickness.

[0014] According to some embodiments, a fourth spacer layer may be between the third layer and the fourth layer.

[0015] According to some embodiments, the third layer may be between the second layer and the fourth spacer layer.

[0016] According to some embodiments, the thickness of the third spacer layer may be greater than the third thickness.

[0017] According to some embodiments, the thickness of the third spacer layer may be less than the sum of the third thickness and the fourth thickness.

[0018] According to some embodiments of the present disclosure, a display device includes: a first electrode; a pixel defining layer on the first electrode; a spacer layer on the pixel defining layer; an emission structure on the first electrode and the spacer layer; and a second electrode on the emission structure. According to some embodiments, the spacer layer may include a first spacer layer having a first width and a second spacer layer having a second width greater than the first width. According to some embodiments, the emission structure may include a first layer between a first surface of the pixel defining layer and the second spacer layer and a second layer on a second surface of the second spacer layer. According to some embodiments, the conductivity of the first layer may be higher than the conductivity of the second layer.

[0019] According to some embodiments, the first spacer layer may be between the pixel defining layer and the second spacer layer.

[0020] According to some embodiments, the spacer layer may further include a third spacer layer having a third width smaller than the second width.

[0021] According to some embodiments, the third spacer layer may be on the second surface of the second spacer layer.

[0022] According to some embodiments, the spacer layer may further include a fourth spacer layer having a fourth width greater than the third width.

[0023] According to some embodiments, the third spacer layer may be between the second spacer layer and the fourth spacer layer.

[0024] According to some embodiments, the emission structure may further include a third layer between the second surface of the second spacer layer and the first surface of the fourth spacer layer.

[0025] According to some embodiments, the emission structure may further include a fourth layer on the second surface of the fourth spacer layer.

[0026] According to some embodiments, the electrical conductivity of the third layer may be higher than the electrical conductivity of the fourth layer.

[0027] Details of various embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects and features according to embodiments of the present disclosure will become more apparent by further describing aspects of some embodiments of the present disclosure in detail with reference to the accompanying drawings, in which:

[0029] Figure 1 is a block diagram of a display device according to some embodiments.

[0030] Figure 2 According to some embodiments Figure 1 A block diagram of any one of the sub-pixels.

[0031] Figure 3 According to some embodiments Figure 2 Circuit diagram of a sub-pixel.

[0032] Figure 4 According to some embodiments Figure 1 A plan view of the display panel.

[0033] Figure 5 According to some embodiments Figure 4 An exploded perspective view of a portion of a display panel.

[0034] Figure 6 According to some embodiments Figure 5 The plan view of any one of the pixels.

[0035] Figure 7 According to some embodiments, Figure 6 A cross-sectional view taken along line II'.

[0036] Figure 8 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure.

[0037] Fig. 9 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure.

[0038] Fig.10 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure.

[0039] Fig.11 According to some embodiments Figure 7 A cross-sectional view of an emission structure included in any one of the first to third light emitting elements.

[0040] Fig.12 According to some embodiments Figure 7 A cross-sectional view of an emission structure included in any one of the first to third light emitting elements.

[0041] Fig.13 According to some embodiments Figure 5 The plan view of any one of the pixels.

[0042] Fig.14 According to some embodiments Figure 5 The plan view of any one of the pixels.

[0043] Fig.15 is a block diagram of a display system according to some embodiments.

[0044] Fig.16 According to some embodiments Fig.15 A perspective view of an example application of the display system.

[0045] Fig.17 is worn on a user according to some embodiments Fig.16 Schematic diagram of a head-mounted display device. DETAILED DESCRIPTION

[0046] Aspects of some embodiments of the present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments of the present disclosure are shown. However, the present disclosure may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided so that the present disclosure will be more thorough and complete, and will more fully convey the scope of the embodiments according to the present disclosure to those skilled in the art.

[0047] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. When an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. For example, when a first element is described as being "coupled to" or "connected to" a second element, the first element may be directly coupled to or directly connected to the second element, or the first element may be indirectly coupled to or indirectly connected to the second element through one or more intervening elements.

[0048] In the accompanying drawings, for the clarity of illustration, the sizes of various elements, layers, etc. may be exaggerated. The same reference numerals represent the same elements. As used herein, the term "and / or" includes any combination and all combinations of one or more of the items listed in association. In addition, when describing the embodiments of the present disclosure, the use of "may" relates to "one or more embodiments of the present disclosure". When after the list of elements, expressions such as "at least one of ... " and "any one of ... " modify the entire list of elements, and do not modify the individual elements of the list. For example, the statement "at least one of a, b and c" indicates only a, only b, only c, a and b, a and c, b and c, a, b and c, all or a, b and / or c in a. As used herein, the terms "use", "in use" and "used" can be considered to be synonymous with the terms "utilize", "in use" and "used" respectively. As used herein, the terms "substantially", "approximately" and similar terms are used as approximate terms rather than terms of degree, and are intended to consider the inherent deviations of the measured values ​​or calculated values ​​recognized by those of ordinary skill in the art.

[0049] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or portion from another element, component, region, layer or portion. Therefore, the first element, component, region, layer or portion discussed below may be referred to as a second element, component, region, layer or portion without departing from the teachings of the exemplary embodiments.

[0050] For ease of description, spatially relative terms such as "below," "below," "down," "above," and "on" may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, elements described as being "below" or "below" other elements or features will then be oriented as being "above" or "on" other elements or features. Therefore, the term "below" can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or oriented in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0051] The terms used herein are for the purpose of describing embodiments of the present disclosure and are not intended to limit the present disclosure. As used herein, the singular form "one" is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" indicate the existence of stated features, integral bodies, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0053] Hereinafter, aspects of some embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0054] Figure 1 is a block diagram of a display device according to some embodiments.

[0055] refer to Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0056] The display panel 110 may include subpixels SP. The subpixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm, where m is an integer equal to or greater than 1. The subpixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn, where n is an integer equal to or greater than 1.

[0057] Each of the sub-pixels SP may include at least one light emitting element configured to generate light. Therefore, each of the sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the sub-pixels SP may form one pixel PXL. For example, Figure 1 As shown in the figure, three sub-pixels SP may form one pixel PXL.

[0058] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output a gate signal to the first to m-th gate lines GL1 to GLm in response to a gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame and a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0059] According to some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may be further provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0060] The gate driver 120 may be located on one side of the display panel 110. However, the embodiment is not limited to the above example. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically distinguished from each other. The driver may be located on a first side of the display panel 110 and a second side of the display panel 110 opposite to the first side. Therefore, depending on the embodiment, the gate driver 120 may be arranged around the display panel 110 in various forms.

[0061] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first to nth data lines DL1 to DLn. The data driver 130 may receive image data DATA and a data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0062] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to nth data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to mth gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the data lines DL1 to DLm. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. As a result, an image may be displayed on the display panel 110.

[0063] According to some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0064] The voltage generator 140 may operate in response to a voltage control signal VCS provided from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external device provided outside the display device 100, adjust the received voltage, and adjust the adjusted voltage, thereby generating a plurality of voltages.

[0065] The voltage generator 140 may generate a first power voltage VDD and a second power voltage VSS. The generated first power voltage VDD and second power voltage VSS may be provided to the sub-pixel SP. The first power voltage VDD may have a relatively high voltage level. The second power voltage VSS may have a lower voltage level than the first power voltage VDD. According to some embodiments, the first power voltage VDD or the second power voltage VSS may be provided by an external device of the display device 100.

[0066] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a specific reference voltage may be applied to each of the first to nth data lines DL1 to DLn. The voltage generator 140 may generate the reference voltage.

[0067] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling an operation of displaying the input image data IMG from an external device. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0068] Controller 150 may convert input image data IMG to be suitable for display device 100 or display panel 110 and thus output image data DATA. According to some embodiments, controller 150 may align input image data IMG on a row basis to be suitable for sub-pixels SP and then output image data DATA.

[0069] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted in a single integrated circuit. Figure 1As illustrated in FIG. 1 , the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be components functionally separated from each other in a single driver integrated circuit DIC. According to some embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component separate from the driver integrated circuit DIC.

[0070] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense a peripheral temperature and generate temperature data TEP indicating the sensed temperature. According to some embodiments, the temperature sensor 160 may be placed adjacent to the display panel 110 and / or the driver integrated circuit DIC.

[0071] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to some embodiments, the controller 150 may adjust the brightness of an image output from the display panel 110 in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140, thereby adjusting the data signal and the first power voltage VDD and the second power voltage VSS.

[0072] Figure 2 According to some embodiments Figure 1 A block diagram of any one of the sub-pixels. Figure 2 , a sub-pixel SPij located in an i-th row (where i is an integer equal to or greater than 1 and equal to or less than m) and a j-th column (where j is an integer equal to or greater than 1 and equal to or less than n) is illustrated.

[0073] refer to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0074] The light emitting element LD may be connected between a first power voltage node VDDN and a second power voltage node VSSN. The first power voltage node VDDN is provided to transmit Figure 1 The second power voltage node VSSN is a node provided to transmit the second power voltage VSS.

[0075] The anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected to the second power voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0076] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first to m-th gate lines GL1 to GLm, Figure 1 The i-th emission control line ELi among the first to m-th emission control lines EL1 to ELm and Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD in response to a signal received through the above-mentioned signal line.

[0077] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in the figure, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Therefore, in the case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0078] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. According to some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0079] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light-emitting element LD may emit light at a brightness corresponding to the data signal.

[0080] Figure 3 According to some embodiments Figure 2 Circuit diagram of a sub-pixel.

[0081] refer to Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0082] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared with the i-th emission control line ELi, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0083] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0084] The first transistor T1 may be connected between the first power voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2. Therefore, the first transistor T1 may be turned on depending on the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0085] The second transistor T2 may be connected between the j-th data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1. Therefore, the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0086] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2. Therefore, the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0087] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub emission control line SEL2. Therefore, the fourth transistor T4 may be turned on in response to the emission control signal of the second sub emission control line SEL2.

[0088] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. According to some embodiments, the initialization voltage may be Figure 1 The initialization voltage may be provided by the voltage generator 140 of the display device 100. According to some embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. Therefore, the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0089] The sixth transistor T6 may be connected between the first power voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub emission control line SEL1. Therefore, the sixth transistor T6 may be turned on in response to the emission control signal of the first sub emission control line SEL1.

[0090] The first capacitor C1 may be connected between the second transistor T2 and the second node N2. The second capacitor C2 may be connected between the first power voltage node VDDN and the second node N2.

[0091] Therefore, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and a first capacitor C1 and a second capacitor C2. However, the embodiment is not limited to the above example. The sub-pixel circuit SPC may be implemented as any of various forms of circuits each including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may vary.

[0092] The first to sixth transistors T1 to T6 may be formed by a P-type transistor. Each of the first to sixth transistors T1 to T6 may be formed by a metal oxide silicon field effect transistor (MOSFET). However, the embodiment is not limited to the above example. For example, at least one of the first to sixth transistors T1 to T6 may be replaced by an N-type transistor.

[0093] According to some embodiments, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0094] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and an emission layer. The emission layer may be located between the anode electrode AE ​​and the cathode electrode CE. When the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to be low levels after the data signal transmitted through the jth data line DLj is reflected in the voltage of the second node N2, the fourth transistor T4 and the sixth transistor T6 may be turned on. The first transistor T1 may be turned on in response to the voltage of the second node N2 so that current may flow from the first power voltage node VDDN to the second power voltage node VSSN. The light emitting element LD may emit light corresponding to the amount of current.

[0095] Figure 4 According to some embodiments Figure 1 A plan view of the display panel.

[0096] refer to Figure 4 ,and Figure 1 The display panel DP of the example corresponding to the display panel 110 depicted in FIG. 1 may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be arranged around the display area DA (e.g., in the periphery of the display area DA or outside the coverage area of ​​the display area DA).

[0097] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0098] In the case where the display panel DP is used as a display screen of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be placed very close to the user's eyes. In this case, a relatively high density of sub-pixels SP may be required. In order to increase the pixel density of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB that is a silicon substrate. A display device 100 (refer to FIG. 1 ) including a display panel DP formed on a substrate SUB that is a silicon substrate Figure 1 ) can be called an OLED on silicon (OLEDoS) display device.

[0099] The sub-pixels SP may be located on the substrate SUB in the display area DA. The sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited to the above example. For example, the sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. The first direction DR1 may refer to a row direction, and the second direction DR2 may refer to a column direction.

[0100] Two or more sub-pixels among the sub-pixels SP may form one pixel PXL.

[0101] Components for controlling the sub-pixels SP may be located on the substrate SUB in the non-display area NDA. Figure 1 Lines of the first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn connected to the sub-pixels SP may be located in the non-display area NDA.

[0102] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA of the display panel DP. According to some embodiments, Figure 1The gate driver 120 may be mounted on the display panel DP and placed in the non-display area NDA. According to some embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. According to some embodiments, the temperature sensor 160 may be placed in the non-display area NDA to sense the temperature of the display panel DP.

[0103] The pad PD may be located on the substrate SUB in the non-display area NDA. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0104] The pad PD can connect the display panel DP to the display device 100 (see Figure 1 According to some embodiments, voltages and signals required for the operation of components included in the display panel DP may be connected to the display panel DP through the pads PD. Figure 1 For example, the first to nth data lines DL1 to DLn (reference Figure 1 ) can be connected to the driver integrated circuit DIC through the pad PD. For example, the first power voltage VDD (reference Figure 1 ) and the second power voltage VSS (reference Figure 1 ) can be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS (reference Figure 1 ) can be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0105] According to some embodiments, the circuit board may be electrically connected to the pad PD through a conductive adhesive member such as an anisotropic conductive film. Here, the circuit board may be a flexible circuit board (FPCB) or a flexible film made of a flexible material. The driver integrated circuit DIC may be mounted on the circuit board and electrically connected to the pad PD.

[0106] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape including linear and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, and an ellipse.

[0107] According to some embodiments, the display panel DP may have a flat display surface. According to some embodiments, the display panel DP may have a display surface that is at least partially rounded. According to some embodiments, the display panel DP may be bendable, foldable, or rollable. In the above case, the display panel DP and / or the substrate SUB may include a material having flexible properties.

[0108] Figure 5According to some embodiments Figure 4 An exploded perspective view of a portion of a display panel. Figure 5 In the embodiment, for the sake of clarity and simplicity of explanation, the display panel DP (refer to Figure 4 ) and Figure 4 The remaining portions of the display panel DP corresponding to other pixels may also be configured in the same manner.

[0109] refer to Figure 4 and Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 may include first to third sub-pixels SP1, SP2 and SP3. However, the embodiment is not limited to the above example. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0110] exist Figure 5 , it is illustrated that when viewed in a third direction DR3 crossing the first direction DR1 and the second direction DR2, the first to third sub-pixels SP1, SP2, and SP3 have a rectangular shape and the same size. However, the embodiment is not limited to the above example. The first to third sub-pixels SP1, SP2, and SP3 may be modified to have various shapes.

[0111] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0112] According to some embodiments, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer, etc. According to some embodiments, the substrate SUB may include a glass substrate. According to some embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0113] The pixel circuit layer PCL may be located on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern located between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of the circuit components and lines, etc. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0114] The circuit element may include corresponding sub-pixel circuits SPC of the first to third sub-pixels SP1, SP2 and SP3 (refer to Figure 2). The sub-pixel circuit SPC may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. According to some embodiments, in the case where the substrate SUB is formed of a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, in the case where the substrate SUB is formed of a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined in the first direction DR1 and the second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, with an insulating layer interposed between the electrodes.

[0115] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first to third sub-pixels SP1, SP2, and SP3, such as gate lines, emission control lines, and data lines. These lines may further include lines connected to Figure 2 The lines may further include lines connected to the first power voltage node VDDN. Figure 2 A line to the second power voltage node VSSN.

[0116] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0117] The anode electrode AE ​​may be located on the pixel circuit layer PCL. The anode electrode AE ​​may be electrically connected to the circuit elements of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0118] The pixel defining layer PDL may be located on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a corresponding portion of the anode electrode AE. The opening OP in the pixel defining layer PDL may be understood as a corresponding emission region corresponding to the first to third sub-pixels SP1 to SP3.

[0119] According to some embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of inorganic layers stacked together. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x According to some embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited to the above examples.

[0120] The emission structure EMS may be located on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0121] According to some embodiments, the emission structure EMS may fill the opening OP in the pixel defining layer PDL and be arranged on the entire surface of the upper portion of the pixel defining layer PDL. The emission structure EMS may extend over the first to third sub-pixels SP1 to SP3. In this case, at least some of the layers in the emission structure EMS may be separated (interrupted) or bent at the boundaries between the first to third sub-pixels SP1 to SP3. However, the embodiments are not limited to the above examples. For example, portions of the emission structure EMS corresponding to the first to third sub-pixels SP1 to SP3 may be separated from each other, and each of the separated portions of the emission structure EMS may be located in a corresponding opening OP in the pixel defining layer PDL.

[0122] The cathode electrode CE may be located on the emission structure EMS. The cathode electrode CE may extend throughout the first to third sub-pixels SP1 to SP3. Thus, the cathode electrode CE may be provided as a common electrode of the first to third sub-pixels SP1 to SP3.

[0123] The cathode electrode CE may be a thin film metal layer having a thickness that allows light emitted from the emission structure EMS to pass through. The cathode electrode CE may be made of a metal material or a transparent conductive material having a relatively small thickness. According to some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. According to some embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a compound thereof. However, the material of the cathode electrode CE is not limited to the above examples.

[0124] Any one of the anode electrode AE, the portion of the emission structure EMS overlapping with any anode electrode AE, and the portion of the cathode electrode CE overlapping with the portion of the emission structure EMS may be understood as constituting one light emitting element LD (refer to Figure 2). Each of the light-emitting elements of the first to third sub-pixels SP1 to SP3 may include an anode electrode AE, a portion of the emission structure EMS overlapping the anode electrode AE, and a portion of the cathode electrode CE overlapping the portion of the emission structure EMS. In each of the first to third sub-pixels SP1 to SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the emission layer of the emission structure EMS, thereby forming excitons. When the excitons transition from an excited state to a ground state, light may be generated. Depending on the amount of current flowing through the emission layer, the brightness of the light may be determined. Depending on the configuration of the emission layer, the wavelength range of the light to be generated may be determined.

[0125] The encapsulation layer TFE may be located on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce the penetration of pollutants such as oxygen and / or water into the light emitting element layer LDL. According to some embodiments, the encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer may include silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ) etc. For example, the organic layer may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited to the above examples.

[0126] The encapsulation layer TFE may further include aluminum oxide (AlO x ) film to improve the encapsulation efficiency of the encapsulation layer TFE. The film including aluminum oxide can be placed on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or under the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0127] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited to the above example. The encapsulation layer TFE may further include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0128] The optical function layer OFL may be located on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0129] The color filter layer CFL may be located between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the emission structure EMS to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the color filters CF allows light within a wavelength range corresponding to the associated sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the emission structure EMS of each sub-pixel, at least some of the color filters CF may be omitted.

[0130] The lens array LA may be located on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the lenses LS may output and guide the light emitted from the emission structure EMS along an intended path, thereby improving the light output efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a higher refractive index than the overcoat layer OC. According to some embodiments, the lens LS may include an organic material. According to some embodiments, the lens LS may include an acrylic material. However, the material of the lens LS is not limited to the above examples.

[0131] According to some embodiments, compared to the opening OP of the pixel defining layer PDL, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be offset in a direction parallel to the plane defined in the first direction DR1 and the second direction DR2. For example, in the central area of ​​the display area DA, the center of each color filter CF and the center of each lens LS may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, each opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter CF and the center of the lens LS may be offset from the center of the corresponding opening OP of the pixel defining layer PDL in the plane direction. For example, in the display area DA, in the area adjacent to the non-display area NDA, each opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, light emitted from the emission structure EMS in the central portion of the display area DA can be effectively output in the normal direction of the display surface. Light emitted from the emission structure EMS around the outer edge of the display area DA can be effectively output in a direction inclined at a specific angle relative to the normal direction of the display surface.

[0132] The outer coating layer OC may be located on the lens array LA. The outer coating layer OC may cover the optical function layer OFL, the encapsulation layer TFE, the light emitting element layer LDL and / or the pixel circuit layer PCL. The outer coating layer OC may include various materials suitable for protecting the lower layer from foreign matter such as dust or water. For example, the outer coating layer OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating layer OC may include epoxy resin, but is not limited thereto. The outer coating layer OC may have a lower refractive index than the lens array LA.

[0133] The cover window CW may be located on the outer coating layer OC. The cover window CW may be configured to protect the lower layer. The cover window CW may have a higher refractive index than the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass layer configured to protect the components located thereunder. According to some embodiments, the cover window CW may be omitted.

[0134] Figure 6 According to some embodiments Figure 5 The plane diagram of any one of the pixels. Figure 6 In the example, for the sake of clarity and simplicity of explanation, the Figure 5The first pixel PXL1 of the first pixel PXL1 and the second pixel PXL2 may be configured in the same manner as the first pixel PXL1.

[0135] refer to Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0136] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0137] The first emission area EMA1 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. Figure 5 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0138] Figure 7 According to some embodiments, Figure 6 A cross-sectional view taken along line II'. Figure 8 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure. Fig. 9 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure. Fig.10 According to some embodiments Figure 7 Cross-sectional view of the spacer layer and emission structure.

[0139] refer to Figure 7 , a substrate SUB and a pixel circuit layer PCL located on the substrate SUB are provided.

[0140] The substrate SUB may include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon germanium.

[0141] The pixel circuit layer PCL may be located on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first to third sub-pixels SP1 to SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (refer to Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2 may be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for clear and concise explanation, one of the transistors of each sub-pixel is illustrated, and the remaining circuit elements are omitted.

[0142] The transistor T_SP1 of the first subpixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0143] The source region SRA and the drain region DRA may be located in the substrate SUB. The well WL formed by the ion implantation process may be located in the substrate SUB. The source region SRA and the drain region DRA may be arranged to be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0144] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be located in the pixel circuit layer PCL. The gate electrode GE may be separated from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0145] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern located between the insulating layers. The conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connector DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connector SRC passing through one or more insulating layers.

[0146] As the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the transistors of the first subpixel SP1.

[0147] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured in the same manner as the transistor T_SP1 of the first subpixel SP1.

[0148] Therefore, the substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first to third sub-pixels SP1 to SP3 .

[0149] The via layer VIAL may be located on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The via layer VIAL may be configured to flatten the stepped portion on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and at least one of silicon carbon nitride (SiCN), but the embodiment is not limited thereto.

[0150] The light emitting element layer LDL may be on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3, a planarization layer PLNL, first to third anode electrodes AE1 to AE3, a pixel defining layer PDL, a separation layer SPR, an emission structure EMS, and a cathode electrode CE.

[0151] The first to third reflective electrodes RE1 to RE3 may be located in the first to third sub-pixels SP1 to SP3, respectively, on the via layer VIAL. Each of the first to third reflective electrodes RE1 to RE3 may be electrically connected to a circuit element located in the pixel circuit layer PCL through a corresponding via hole passing through the via layer VIAL.

[0152] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors provided to reflect light emitted from the emission structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from the above materials, but the embodiment is not limited thereto.

[0153] According to some embodiments, the connection electrode may be located under each of the first to third reflective electrodes RE1 to RE3. The connection electrode may enhance the electrical connection characteristics between the corresponding reflective electrode and the corresponding circuit element of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. According to some embodiments, the corresponding reflective electrode may be placed between the multiple layers of the connection electrode.

[0154] The buffer pattern BFP may be located under at least one of the first to third reflective electrodes RE1 to RE3. The buffer pattern BFP may include an inorganic material such as silicon carbon nitride, but the embodiment is not limited thereto. As the buffer pattern BFP is placed, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted. For example, the buffer pattern BFP may be located between the first reflective electrode RE1 and the via layer VIAL, thereby adjusting the height of the first reflective electrode RE1.

[0155] The first to third reflective electrodes RE1 to RE3 can be used as full reflectors, and the cathode electrode CE can be used as a half reflector. By reciprocating between the corresponding reflective electrodes and the cathode electrode CE, the light emitted from the emission layer of the emission structure EMS can be at least partially amplified. The amplified light can be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the emission layer of the corresponding emission structure EMS.

[0156] Due to the buffer pattern BFP, the first subpixel SP1 can have a shorter resonance distance than other subpixels. Therefore, the adjusted resonance distance enables light in a specific wavelength range (e.g., red) to be effectively amplified. Therefore, the first subpixel SP1 can effectively and efficiently output light in the corresponding wavelength range.

[0157] exist Figure 7 , a case where the buffer pattern BFP is provided in the first sub-pixel SP1 but not in the second sub-pixel SP2 and the third sub-pixel SP3 is illustrated, but the embodiment is not limited thereto. The buffer pattern may also be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 so that the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3 can be adjusted. For example, the first to third sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE may be smaller than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be smaller than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0158] In order to planarize the stepped portions between the first to third reflective electrodes RE1 to RE3, a planarization layer PLNL may be located on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The planarization layer PLNL may cover the entire surfaces of the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and have a flat surface. According to some embodiments, the planarization layer PLNL may be omitted.

[0159] On the planarization layer PLNL, the first to third anode electrodes AE1 to AE3 may be disposed overlapping the first to third reflective electrodes RE1 to RE3, respectively. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may overlap with the first to third reflective electrodes RE1 to RE3. Figure 6 The first to third emission areas EMA1 to EMA3 have similar shapes. The first to third anode electrodes AE1 to AE3 are respectively connected to the first to third reflective electrodes RE1 to RE3. The first anode electrode AE1 can be connected to the first reflective electrode RE1 through a first through hole VIA1 passing through the planarization layer PLNL. The second anode electrode AE2 can be connected to the second reflective electrode RE2 through a second through hole VIA2 passing through the planarization layer PLNL. The third anode electrode AE3 can be connected to the third reflective electrode RE3 through a third through hole VIA3 passing through the planarization layer PLNL.

[0160] According to some embodiments, the first to third anode electrodes AE1 to AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited to the above examples. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0161] An insulating layer may be further provided to adjust the height of one or more of the first to third anode electrodes AE1 to AE3. The insulating layer may be located between one or more of the first to third anode electrodes AE1 to AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first to third sub-pixels SP1 to SP3 may correspond to red, green, and blue, respectively. The distance between the first anode electrode AE1 and the cathode electrode CE may be smaller than the distance between the second anode electrode AE2 and the cathode electrode CE. The distance between the second anode electrode AE2 and the cathode electrode CE may be smaller than the distance between the third anode electrode AE3 and the cathode electrode CE.

[0162] The pixel defining layer PDL may be located on a portion of the first to third anode electrodes AE1 to AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP exposing respective portions of the first to third anode electrodes AE1 to AE3. The opening OP in the pixel defining layer PDL may define respective emission regions of the first to third sub-pixels SP1 to SP3. Thus, the pixel defining layer PDL may be placed Figure 6 The non-emitting area NEA is defined as Figure 6 The first to third emission areas EMA1 to EMA3.

[0163] According to some embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of. For example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked in succession. The first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited thereto. The first to third insulating layers may have a stepped shape in a region adjacent to each of the openings OP, but the embodiment is not limited thereto.

[0164] The partition layer SPR may be provided in the boundary area BDA between adjacent sub-pixels. For example, the partition layer SPR may be provided in Figure 4 The partition layer SPR may be provided on the pixel defining layer PDL.

[0165] The partition layer SPR may cause a discontinuous portion to be generated in the emission structure EMS in the boundary area BDA. For example, the emission structure EMS may be separated (interrupted) or bent by the partition layer SPR in the boundary area BDA. Therefore, during operation of the display panel DP, current leaking from each of the first to third sub-pixels SP1 to SP3 through the layer included in the emission structure EMS to the adjacent sub-pixel may be reduced. As a result, the first to third light-emitting elements LD1 to LD3 may operate with relatively high reliability.

[0166] refer to Figure 8 The spacer layer SPR may be composed of a plurality of layers. For example, the spacer layer SPR may include a first spacer layer S1, a second spacer layer S2, a third spacer layer S3 and / or a fourth spacer layer S4.

[0167] The first spacer layer S1 may be placed on the pixel defining layer PDL. The first spacer layer S1 may be located between the pixel defining layer PDL and the second spacer layer S2. The first spacer layer S1 may be located between the first surfaces of the pixel defining layer PDL and the second spacer layer S2. The first surface of the first spacer layer S1 may contact the pixel defining layer PDL, and the second surface of the first spacer layer S1 may contact the first surface of the second spacer layer S2.

[0168] The second separator layer S2 may be located on the first separator layer S1. The second separator layer S2 may be located between the first separator layer S1 and the third separator layer S3. The second separator layer S2 may be located between the second surface of the first separator layer S1 and the first surface of the third separator layer S3. The first surface of the second separator layer S2 may contact the second surface of the first separator layer S1, and the second surface of the second separator layer S2 may contact the first surface of the third separator layer S3.

[0169] The third separator layer S3 may be located on the second separator layer S2. The third separator layer S3 may be located between the second separator layer S2 and the fourth separator layer S4. The third separator layer S3 may be located between the second surface of the second separator layer S2 and the first surface of the fourth separator layer S4. The first surface of the third separator layer S3 may contact the second surface of the second separator layer S2, and the second surface of the third separator layer S3 may contact the first surface of the fourth separator layer S4.

[0170] The fourth spacer layer S4 may be located on the third spacer layer S3. A first surface of the fourth spacer layer S4 may contact a second surface of the third spacer layer S3.

[0171] The first width of the first spacer layer S1 with respect to the first direction DR1 may be different from the second width of the second spacer layer S2 with respect to the first direction DR1. For example, the first width of the first spacer layer S1 with respect to the first direction DR1 may be smaller than the second width of the second spacer layer S2 with respect to the first direction DR1.

[0172] The second width of the second spacer layer S2 relative to the first direction DR1 may be different from the third width of the third spacer layer S3 relative to the first direction DR1. For example, the second width of the second spacer layer S2 relative to the first direction DR1 may be greater than the third width of the third spacer layer S3 relative to the first direction DR1.

[0173] The third width of the third spacer layer S3 with respect to the first direction DR1 may be different from the fourth width of the fourth spacer layer S4 with respect to the first direction DR1. For example, the third width of the third spacer layer S3 with respect to the first direction DR1 may be smaller than the fourth width of the fourth spacer layer S4 with respect to the first direction DR1.

[0174] According to some embodiments, the first width of the first spacer layer S1 with respect to the first direction DR1 may be the same as the third width of the third spacer layer S3 with respect to the first direction DR1. The second width of the second spacer layer S2 with respect to the first direction DR1 may be the same as the fourth width of the fourth spacer layer S4 with respect to the first direction DR1. However, embodiments are not limited to the above examples. Fig. 9 As shown in FIG, the first width of the first spacer layer S1 relative to the first direction DR1 may be smaller than the third width of the third spacer layer S3 relative to the first direction DR1. The second width of the second spacer layer S2 relative to the first direction DR1 may be smaller than the fourth width of the fourth spacer layer S4 relative to the first direction DR1.

[0175] The first to fourth spacer layers S1, S2, S3, and S4 may each include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials.

[0176] The first spacer layer S1 and the second spacer layer S2 may include different materials. The second spacer layer S2 and the third spacer layer S3 may include different materials. The third spacer layer S3 and the fourth spacer layer S4 may include different materials. The first spacer layer S1 and the third spacer layer S3 may have the same material. The second spacer layer S2 and the fourth spacer layer S4 may have the same material. For example, the first spacer layer S1 and the third spacer layer S3 may be made of silicon oxide (SiO x ), and the second spacer layer S2 and the fourth spacer layer S4 may be made of silicon nitride (SiN x ) is formed, but the embodiment is not limited thereto.

[0177] The emission structure EMS may be located on the anode electrode AE ​​and the partition layer SPR. The emission structure EMS may be located on the anode electrode AE ​​exposed from the pixel defining layer PDL. The emission structure EMS may be located as a whole in the first to third sub-pixels SP1 to SP3. Some or all of the multiple layers included in the emission structure EMS may be separated or bent by the partition layer SPR in the boundary area BDA.

[0178] The emission structure EMS may be composed of a plurality of layers. For example, the emission structure EMS may include a first layer L1, a second layer L2 and / or a third layer L3. The second layer L2 may be located between the first layer L1 and the third layer L3.

[0179] The first layer L1 may be located on the anode electrode AE. The first layer L1 may be located between the anode electrode AE ​​and the second layer L2. A first surface of the first layer L1 may contact the anode electrode AE. A second surface of the first layer L1 may contact a first surface of the second layer L2.

[0180] The first layer L1 may be placed on the pixel defining layer PDL. The first layer L1 may be located between the pixel defining layer PDL and the second spacer layer S2. For example, the first layer L1 may overlap the pixel defining layer PDL and the second spacer layer S2 in the third direction DR3. The first layer L1 may be located between the first surfaces of the pixel defining layer PDL and the second spacer layer S2. The first surface of the first layer L1 may contact the pixel defining layer PDL. The second surface of the first layer L1 may be spaced apart from the first surface of the second spacer layer S2. The space between the second surface of the first layer L1 and the first surface of the second spacer layer S2 may form a gap.

[0181] The second layer L2 may be located on the first layer L1. The second layer L2 may be located between the first layer L1 and the third layer L3. The second layer L2 may be located between the second surface of the first layer L1 and the first surface of the third layer L3. The first surface of the second layer L2 may contact the second surface of the first layer L1, and the second surface of the second layer L2 may contact the first surface of the third layer L3.

[0182] The second layer L2 may be located on the second spacer layer S2. The second layer L2 may be located between the second spacer layer S2 and the fourth spacer layer S4. For example, the second layer L2 may overlap the second spacer layer S2 and the fourth spacer layer S4 in the third direction DR3. The second layer L2 may be located between the second surface of the second spacer layer S2 and the first surface of the fourth spacer layer S4. According to some embodiments, the first pattern L1' may be further located between the second spacer layer S2 and the second layer L2. The first pattern L1' located on the second spacer layer S2 may be a pattern separated from the first layer L1 by the second spacer layer S2 during the process of forming the first layer L1. In this case, the first surface of the second layer L2 may contact the first pattern L1'. According to some embodiments, the first pattern L1' may also be located on the fourth spacer layer S4. The first pattern L1' located on the fourth spacer layer S4 may be a pattern separated from the first layer L1 by the fourth spacer layer S4. The second pattern L2' may be further located on the first pattern L1'. The second pattern L2' on the fourth spacer layer S4 may be a pattern separated from the second layer L2 by the fourth spacer layer S4. The third pattern L3' may be further on the second pattern L2'. The third pattern L3' on the fourth spacer layer S4 may be a pattern separated from the third layer L3 by the fourth spacer layer S4.

[0183] The third layer L3 may be located on the second layer L2. The third layer L3 may be located between the second layer L2 and the fourth separator S4. For example, the third layer L3 may overlap the second layer L2 and the fourth separator S4 in the third direction DR3. The third layer L3 may be located between the second surface of the second layer L2 and the first surface of the fourth separator S4. The first surface of the third layer L3 may contact the second surface of the second layer L2. The second surface of the third layer L3 may be spaced apart from the first surface of the fourth separator S4. The space between the second surface of the third layer L3 and the first surface of the fourth separator S4 may form a gap.

[0184] The third layer L3 may be located on the second separator layer S2. The third layer L3 may be located between the second separator layer S2 and the fourth separator layer S4. For example, the third layer L3 may overlap the second separator layer S2 and the fourth separator layer S4 in the third direction DR3. The third layer L3 may be located between the second surface of the second separator layer S2 and the first surface of the fourth separator layer S4.

[0185] The first thickness of the first layer L1 relative to the third direction DR3 may be different from the second thickness of the second layer L2 relative to the third direction DR3. For example, the first thickness of the first layer L1 relative to the third direction DR3 may be less than the second thickness of the second layer L2 relative to the third direction DR3. The thickness of the first spacer layer S1 relative to the third direction DR3 may be greater than the first thickness of the first layer L1 relative to the third direction DR3. The thickness of the first spacer layer S1 relative to the third direction DR3 may be less than the sum of the first thickness of the first layer L1 relative to the third direction DR3 and the second thickness of the second layer L2 relative to the third direction DR3. The length of the second spacer layer S2 protruding from the first spacer layer S1 relative to the third direction DR3 may be greater than the second thickness of the second layer L2 relative to the third direction DR3.

[0186] The conductivity of the first layer L1 may be different from the conductivity of the second layer L2. For example, the conductivity of the first layer L1 may be higher than the conductivity of the second layer L2. For example, the first layer L1 may correspond to the first charge generation layer CGL1' (refer to Fig.12 ), and the second layer L2 may correspond to a second hole transport component HTU2' (reference Fig.12 ), but the embodiment is not limited thereto.

[0187] The second thickness of the second layer L2 relative to the third direction DR3 may be different from the third thickness of the third layer L3 relative to the third direction DR3. For example, the second thickness of the second layer L2 relative to the third direction DR3 may be greater than the third thickness of the third layer L3 relative to the third direction DR3. The thickness of the third spacer layer S3 relative to the third direction DR3 may be greater than the third thickness of the third layer L3 relative to the third direction DR3.

[0188] The conductivity of the second layer L2 may be different from the conductivity of the third layer L3. For example, the conductivity of the second layer L2 may be less than the conductivity of the third layer L3. For example, the second layer L2 may correspond to the second hole transport component HTU2' (refer to Fig.12 ), and the third layer L3 may correspond to the second charge generation layer CGL2' (reference Fig.12 ), but the embodiment is not limited thereto.

[0189] According to some embodiments, the second separation layer S2 may be located between the first layer L1 and the second layer L2, whereby the first layer L1 and the second layer L2 may be separated from each other. Therefore, the third layer L3 may be located on the second layer L2 separated from the first layer L1, so that a short circuit defect occurring between the first layer L1 and the third layer L3 corresponding to a relatively highly conductive layer may be prevented or reduced. As a result, the reliability of the sub-pixel may be relatively improved.

[0190] According to some embodiments, the spacer layer SPR may further include a fifth spacer layer S5 and / or a sixth spacer layer S6. Fig.10 , the fifth spacer layer S5 may be located on the fourth spacer layer S4. The fifth spacer layer S5 may be located between the fourth spacer layer S4 and the sixth spacer layer S6. The fifth spacer layer S5 may be located between the second surface of the fourth spacer layer S4 and the first surface of the sixth spacer layer S6. The first surface of the fifth spacer layer S5 may contact the second surface of the fourth spacer layer S4, and the second surface of the fifth spacer layer S5 may contact the first surface of the sixth spacer layer S6.

[0191] The sixth spacer layer S6 may be located on the fifth spacer layer S5. A first surface of the sixth spacer layer S6 may contact a second surface of the fifth spacer layer S5.

[0192] The fifth width of the fifth spacer layer S5 with respect to the first direction DR1 may be different from the fourth width of the fourth spacer layer S4 with respect to the first direction DR1. For example, the fifth width of the fifth spacer layer S5 with respect to the first direction DR1 may be smaller than the fourth width of the fourth spacer layer S4 with respect to the first direction DR1.

[0193] The sixth width of the sixth spacer layer S6 with respect to the first direction DR1 may be different from the fifth width of the fifth spacer layer S5 with respect to the first direction DR1. For example, the sixth width of the sixth spacer layer S6 with respect to the first direction DR1 may be greater than the fifth width of the fifth spacer layer S5 with respect to the first direction DR1.

[0194] The fifth spacer layer S5 and the sixth spacer layer S6 may each include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y), aluminum nitride (AlN x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), hafnium oxide (HfO x ) and titanium oxide (TiO x ) various inorganic materials.

[0195] The fifth spacer layer S5 and the sixth spacer layer S6 may include different materials, respectively. The first spacer layer S1, the third spacer layer S3, and / or the fifth spacer layer S5 may have the same material. The second spacer layer S2, the fourth spacer layer S4, and / or the sixth spacer layer S6 may have the same material, but are not necessarily limited thereto. For example, the fifth spacer layer S5 may be made of silicon oxide (SiO x ) is formed, and the sixth separation layer S6 may be made of silicon nitride (SiN x ) is formed, but is not necessarily limited to this.

[0196] According to some embodiments, the emission structure EMS may include a fourth layer L4 and / or a fifth layer L5.

[0197] The fourth layer L4 may be located on the third layer L3. The fourth layer L4 may be located between the third layer L3 and the fifth layer L5. The fourth layer L4 may be located between the second surface of the third layer L3 and the first surface of the fifth layer L5. The first surface of the fourth layer L4 may contact the second surface of the third layer L3, and the second surface of the fourth layer L4 may contact the first surface of the fifth layer L5.

[0198] The fourth layer L4 may be located on the fourth spacer layer S4. The fourth layer L4 may be located between the fourth spacer layer S4 and the sixth spacer layer S6. For example, the fourth layer L4 may overlap the fourth spacer layer S4 and the sixth spacer layer S6 in the third direction DR3. The fourth layer L4 may be located between the second surface of the fourth spacer layer S4 and the first surface of the sixth spacer layer S6. According to some embodiments, the first pattern L1', the second pattern L2' and / or the third pattern L3' may be further located between the fourth spacer layer S4 and the fourth layer L4. The first pattern L1' located on the fourth spacer layer S4 may be a pattern separated from the first layer L1 by the fourth spacer layer S4 during the process of forming the first layer L1. The second pattern L2' located on the fourth spacer layer S4 may be a pattern separated from the second layer L2 by the fourth spacer layer S4 during the process of forming the second layer L2. The third pattern L3' located on the fourth spacer layer S4 may be a pattern separated from the third layer L3 by the fourth spacer layer S4 during the process of forming the third layer L3. The first pattern L1', the second pattern L2', and / or the third pattern L3' may be continuously stacked on the fourth spacer layer S4. In this case, the first surface of the fourth layer L4 may contact the third pattern L3'.

[0199] According to some embodiments, the first pattern L1' may be further located on the sixth spacer layer S6. The first pattern L1' located on the sixth spacer layer S6 may be a pattern separated from the first layer L1 by the sixth spacer layer S6. The second pattern L2' may be further located on the first pattern L1'. The second pattern L2' located on the sixth spacer layer S6 may be a pattern separated from the second layer L2 by the sixth spacer layer S6. The third pattern L3' may be further located on the second pattern L2'. The third pattern L3' located on the sixth spacer layer S6 may be a pattern separated from the third layer L3 by the sixth spacer layer S6. The fourth pattern L4' may be further located on the third pattern L3'. The fourth pattern L4' located on the sixth spacer layer S6 may be a pattern separated from the fourth layer L4 by the sixth spacer layer S6. The fifth pattern L5' may be further located on the fourth pattern L4'. The fifth pattern L5' located on the sixth spacer layer S6 may be a pattern separated from the fifth layer L5 by the sixth spacer layer S6.

[0200] The fifth layer L5 may be located on the fourth layer L4. The fifth layer L5 may be located between the fourth layer L4 and the sixth separator S6. For example, the fifth layer L5 may overlap the fourth layer L4 and the sixth separator S6 in the third direction DR3. The fifth layer L5 may be located between the second surface of the fourth layer L4 and the first surface of the sixth separator S6. The first surface of the fifth layer L5 may contact the second surface of the fourth layer L4. The second surface of the fifth layer L5 may be spaced apart from the first surface of the sixth separator S6. The space between the second surface of the fifth layer L5 and the first surface of the sixth separator S6 may form a gap.

[0201] The fifth layer L5 may be located on the fourth spacer layer S4. The fifth layer L5 may be located between the fourth spacer layer S4 and the sixth spacer layer S6. For example, the fifth layer L5 may overlap the fourth spacer layer S4 and the sixth spacer layer S6 in the third direction DR3. The fifth layer L5 may be located between the second surface of the fourth spacer layer S4 and the first surface of the sixth spacer layer S6.

[0202] The fourth thickness of the fourth layer L4 relative to the third direction DR3 may be different from the third thickness of the third layer L3 relative to the third direction DR3. For example, the fourth thickness of the fourth layer L4 relative to the third direction DR3 may be greater than the third thickness of the third layer L3 relative to the third direction DR3.

[0203] The fifth thickness of the fifth layer L5 relative to the third direction DR3 may be different from the fourth thickness of the fourth layer L4 relative to the third direction DR3. For example, the fifth thickness of the fifth layer L5 relative to the third direction DR3 may be less than the fourth thickness of the fourth layer L4 relative to the third direction DR3.

[0204] The thickness of the third spacer layer S3 relative to the third direction DR3 may be less than the sum of the third thickness of the third layer L3 relative to the third direction DR3 and the fourth thickness of the fourth layer L4 relative to the third direction DR3. The length of the fourth spacer layer S4 protruding from the third spacer layer S3 relative to the third direction DR3 may be greater than the fourth thickness of the fourth layer L4 relative to the third direction DR3. The thickness of the fifth spacer layer S5 relative to the third direction DR3 may be greater than the fifth thickness of the fifth layer L5 relative to the third direction DR3.

[0205] The conductivity of the fourth layer L4 may be different from the conductivity of the third layer L3. For example, the conductivity of the fourth layer L4 may be less than the conductivity of the third layer L3. The conductivity of the fifth layer L5 may be different from the conductivity of the fourth layer L4. For example, the conductivity of the fifth layer L5 may be higher than the conductivity of the fourth layer L4.

[0206] According to some embodiments, the fourth separation layer S4 may be located between the third layer L3 and the fourth layer L4, whereby the third layer L3 and the fourth layer L4 may be separated from each other. Therefore, the fifth layer L5 may be located on the fourth layer L4 separated from the third layer L3, so that a short circuit defect occurring between the third layer L3 and the fifth layer L5 corresponding to a relatively high conductive layer may be prevented or reduced. As a result, the reliability of the sub-pixel may be relatively improved.

[0207] Reference again Figure 7 , the cathode electrode CE may be located on the emission structure EMS. The cathode electrode CE may be commonly provided in the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a semi-reflective mirror that partially transmits and partially reflects light emitted from the emission structure EMS.

[0208] The cathode electrode CE may be connected in the boundary area BDA and thus be commonly provided in the first to third sub-pixels SP1 to SP3 .

[0209] The first anode electrode AE1, the portion of the emission structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2, the portion of the emission structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3, the portion of the emission structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may form a third light emitting element LD3.

[0210] The encapsulation layer TFE may be located on the cathode electrode CE. The encapsulation layer TFE may prevent or reduce the penetration of pollutants such as oxygen and / or water into the light emitting element layer LDL.

[0211] The optical function layer OFL may be located on the encapsulation layer TFE. According to some embodiments, the optical function layer OFL may be attached to the encapsulation layer TFE by an adhesive layer APL. For example, the optical function layer OFL may be manufactured by a separate process and attached to the encapsulation layer TFE by an adhesive layer APL. The adhesive layer APL may further perform the function of protecting the lower layer including the encapsulation layer TFE.

[0212] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may transmit light in different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red light, green light, and blue light, respectively.

[0213] According to some embodiments, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. According to some embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0214] The lens array LA may be located on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may guide the light emitted from the first to third light emitting elements LD1 to LD3 to the intended paths, respectively, thereby improving light output efficiency.

[0215] Fig.11 According to some embodiments Figure 7 A cross-sectional view of an emission structure included in any one of the first to third light emitting elements.

[0216] refer to Fig.11 , the emission structure EMS may have a series structure in which the first emission unit EU1 and the second emission unit EU2 are stacked. Figure 7 In each of the first to third light emitting elements LD1 to LD3 , the emission structure EMS may have substantially the same configuration.

[0217] Each of the first emission component EU1 and the second emission component EU2 may include at least one emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be located between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be located between the second electron transport component ETU2 and the second hole transport component HTU2.

[0218] Each of the first hole transport component HTU1 and the second hole transport component HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and an electron blocking layer, etc. as needed. The first hole transport component HTU1 and the second hole transport component HTU2 may have the same configuration or different configurations.

[0219] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer, etc. as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0220] A connection layer, which may be provided in the form of a charge generation layer CGL, may be located between the first emission component EU1 and the second emission component EU2 to connect the first emission component EU1 and the second emission component EU2 to each other. According to some embodiments, the charge generation layer CGL may have a stacked structure including a P dopant layer and an N dopant layer. For example, the P dopant layer may include a P-type dopant such as dipyrazino[2,3-f:2',3'-h]quinoxaline-2,3,6,7,10,11-hexacarbonitrile (HAT-CN), tetracyanoquinodimethane (TCNQ), or 4-[[2,3-bis[cyano-(4-cyano-2,3,5,6-tetrafluorophenyl)methylene]cyclopropylene]-cyanomethyl]-2,3,5,6-tetrafluorobenzonitrile (NDP-9), and the N dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, embodiments are not limited to the above examples.

[0221] According to some embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors. The light emitted from the first emission layer EML1 and the second emission layer EML2 may be mixed into visible white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may generate yellow light. According to some embodiments, the second emission layer EML2 may include a stacked structure including a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light. Red light and green light may be mixed to provide yellow light. In this case, an intermediate layer configured to perform the function of transporting holes and / or blocking the transport of electrons may be further located between the first sub-emission layer and the second sub-emission layer. According to some embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of the same color.

[0222] The emission structure EMS may be formed through a scheme such as vacuum deposition or inkjet printing, but the embodiment is not limited thereto.

[0223] Fig.12 According to some embodiments Figure 7 A cross-sectional view of an emission structure included in any one of the first to third light emitting elements.

[0224] refer to Fig.12 , the emission structure EMS' may have a series structure in which the first to third emission elements EU1' to EU3' are stacked. Figure 7 In each of the first to third light emitting elements LD1 to LD3 , the emission structure EMS′ may have substantially the same configuration.

[0225] Each of the first to third emission components EU1' to EU3' may include an emission layer configured to generate light in response to a current applied thereto. The first emission component EU1' may include a first emission layer EML1', a first electron transport component ETU1', and a first hole transport component HTU1'. The first emission layer EML1' may be located between the first electron transport component ETU1' and the first hole transport component HTU1'. The second emission component EU2' may include a second emission layer EML2', a second electron transport component ETU2', and a second hole transport component HTU2'. The second emission layer EML2' may be located between the second electron transport component ETU2' and the second hole transport component HTU2'. The third emission component EU3' may include a third emission layer EML3', a third electron transport component ETU3', and a third hole transport component HTU3'. The third emission layer EML3' may be located between the third electron transport component ETU3' and the third hole transport component HTU3'.

[0226] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and an electron blocking layer, etc. as needed. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0227] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and a hole blocking layer, etc. as needed. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0228] The first charge generation layer CGL1' may be located between the first emission part EU1' and the second emission part EU2'. The second charge generation layer CGL2' may be located between the second emission part EU2' and the third emission part EU3'.

[0229] According to some embodiments, the first to third emission layers EML1' to EML3' may generate light of different colors. The light emitted from the first to third emission layers EML1' to EML3' may be mixed into visible white light. For example, the first emission layer EML1' may generate blue light, the second emission layer EML2' may generate green light, and the third emission layer EML3' may generate red light. According to some embodiments, two or more emission layers among the first to third emission layers EML1' to EML3' may generate light of the same color.

[0230] and Fig.11 and Fig.12 The situation shown in the figure is different. Figure 7 The emission structure EMS may include an emission component in each of the first to third light emitting elements LD1 to LD3. Here, the corresponding emission components included in the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the emission component of the first light emitting element LD1 may emit red light, the emission component of the second light emitting element LD2 may emit green light, and the emission component of the third light emitting element LD3 may emit blue light. In this case, the emission components of the first to third sub-pixels SP1 to SP3 may be separated from each other, and each may be located in a corresponding opening OP of the pixel defining layer PDL. In this case, at least some of the color filters CF1 to CF3 may be omitted.

[0231] Fig.13 According to some embodiments Figure 5 The plan view of any one of the pixels.

[0232] refer to Fig.13 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0233] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' formed around the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' formed around the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' formed around the third emission area EMA3'.

[0234] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be located in the first direction DR1 with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0235] The second sub-pixel SP2' may have a larger surface area than the first sub-pixel SP1'. The third sub-pixel SP3' may have a larger surface area than the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have a larger surface area than the first emission area EMA1'. The third emission area EMA3' may have a larger surface area than the second emission area EMA2'. However, the embodiments are not limited to the above examples. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same surface area. The third sub-pixel SP3' may have a larger surface area than each of the first sub-pixel SP1' and the second sub-pixel SP2'. Therefore, depending on the embodiment, the surface areas of the first to third sub-pixels SP1' to SP3' may be changed in various ways.

[0236] Fig.14 According to some embodiments Figure 5 The plan view of any one of the pixels.

[0237] refer to Fig.14 , the first pixel PXL1" may include first to third sub-pixels SP1" to SP3". The first sub-pixel SP1" may include a first emission area EMA1" and a non-emission area NEA" formed around the first emission area EMA1". The second sub-pixel SP2" may include a second emission area EMA2" and a non-emission area NEA" formed around the second emission area EMA2". The third sub-pixel SP3" may include a third emission area EMA3" and a non-emission area NEA" formed around the third emission area EMA3".

[0238] Each of the first to third sub-pixels SP1 ″ to SP3 ″ may have a polygonal shape in the third direction DR3 . For example, the shape of the first to third sub-pixels SP1 ″ to SP3 ″ may be a hexagon.

[0239] Each of the first to third emission areas EMA1 ″ to EMA3 ″ may have a circular shape in the third direction DR3 . However, the embodiment is not limited to the above example. For example, each of the first to third emission areas EMA1 ″ to EMA3 ″ may have a polygonal shape.

[0240] The first and third sub-pixels SP1 ″ and SP3 ″ may be arranged in the first direction DR1 . The second sub-pixel SP2 ″ may be arranged in a direction (or an oblique direction) inclined at an acute angle with respect to the first sub-pixel SP1 ″ based on the second direction DR2 .

[0241] Figure 6 , Fig.13 and Fig.14 The arrangement of the sub-pixels illustrated in the figure is exemplary, and the embodiment is not limited thereto. Each pixel may include two or more sub-pixels, and the sub-pixels may be arranged in various ways. Each of the sub-pixels may have various shapes. Each of the emission regions of the sub-pixels may also have various shapes.

[0242] Fig.15 is a block diagram of a display system according to some embodiments.

[0243] refer to Fig.15 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220 .

[0244] The processor 1100 may perform various tasks and operations. According to some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control these components.

[0245] exist Fig.15 , it is illustrated that the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0246] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1The display device 100 described above is configured in the same manner. In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0247] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 The display device 100 described above is configured in the same manner. In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0248] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a portable multimedia player, a navigation system, and an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0249] Fig.16 According to some embodiments Fig.15 A perspective view of an example application of the display system.

[0250] refer to Fig.16 , Fig.15 The display system 1000 may be applied to a head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that may be worn on a user's head.

[0251] The head-mounted display device 2000 may include a head-mounted band 2100 and a display device housing 2200. The head-mounted band 2100 may be connected to the display device housing 2200. The head-mounted band 2100 may include a horizontal band and / or a vertical band to fix the head-mounted display device 2000 to the user's head. The horizontal band may surround the side of the user's head, and the vertical band may surround the top of the user's head. However, the embodiment is not limited to the above example. For example, the head-mounted band 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0252] The display device receiving housing 2200 can receive Fig.15The first display device 1210 and the second display device 1220. The display device receiving housing 2200 may further receive Fig.15 Processor 1100.

[0253] Fig.17 is worn on a user according to some embodiments Fig.16 Schematic diagram of a head-mounted display device.

[0254] refer to Fig.17 , the first display device 1210 (reference Fig.15 ) of the first display panel DP1 and the second display device 1220 (reference Fig.15 ) is located in the head mounted display device 2000. The head mounted display device 2000 may further include one or more lenses LLNS and RLNS.

[0255] In the display device receiving container 2200, the right eye lens RLNS may be placed between the first display panel DP1 and the right eye of the user. In the display device receiving container 2200, the left eye lens LLNS may be placed between the second display panel DP2 and the left eye of the user.

[0256] The image output from the first display panel DP1 may be viewed by the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light emitted from the first display panel DP1 toward the right eye of the user. The right eye lens RLNS may perform an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user.

[0257] The image output from the second display panel DP2 may be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light emitted from the second display panel DP2 toward the user's left eye. The left eye lens LLNS may perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0258] According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In this case, each display panel may output images corresponding to the sub-regions of the multi-channel lens, respectively. The output images may be viewed by a user through the corresponding sub-regions.

[0259] According to some embodiments, a portion of the emission structure may be separated from each other by a separation layer formed in a boundary region between adjacent sub-pixels. Thus, current leakage to adjacent sub-pixels may be minimized or reduced.

[0260] However, the aspects and features of the present disclosure are not limited to the above-described aspects and features, and a person of ordinary skill in the art will appreciate that various other aspects and features are within the spirit and scope of the present disclosure.

[0261] The embodiments described in detail above are provided to explain the present disclosure, but these embodiments are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that various changes, substitutions and modifications can be made in the present disclosure without departing from the scope of the present disclosure defined by the claims and their equivalents.

[0262] The scope of the embodiments according to the present disclosure is not limited by the detailed description of this specification, and should be defined by the claims and their equivalents. In addition, all changes or modifications derived from the claims and their equivalents of the present disclosure should be interpreted as being included in the scope of the embodiments according to the present disclosure. The embodiments can be combined to form additional embodiments.

Claims

1. A display device, comprising: a first electrode; a pixel defining layer, on the first electrode; a separation layer, on the pixel defining layer; an emission structure on the first electrode and the separation layer; as well as a second electrode, on the emitting structure, The partition layer includes a first partition layer on the pixel defining layer and having a first width, and a second partition layer on the first partition layer and having a second width greater than the first width. wherein the emitting structure comprises a first layer having a first thickness and a second layer having a second thickness greater than the first thickness, and Wherein, the second separation layer is between the first layer and the second layer.

2. The display device according to claim 1, wherein: The thickness of the first separation layer is greater than the first thickness.

3. The display device according to claim 1, wherein: The thickness of the first separation layer is less than the sum of the first thickness and the second thickness.

4. The display device according to claim 1, wherein: The first layer is between the pixel defining layer and the second spacer layer.

5. The display device according to any one of claims 1 to 4, wherein: The spacer layer further includes a third spacer layer on the second spacer layer and having a third width smaller than the second width, and a fourth spacer layer on the third spacer layer and having a fourth width larger than the third width.

6. The display device according to claim 5, wherein: The second layer is between the second spacer layer and the fourth spacer layer.

7. The display device according to claim 5, wherein: The emitting structure further includes a third layer having a third thickness smaller than the second thickness and a fourth layer having a fourth thickness larger than the third thickness.

8. The display device according to claim 7, wherein: The fourth spacer layer is between the third layer and the fourth layer.

9. The display device according to claim 7, wherein: The third layer is between the second layer and the fourth spacer layer.

10. The display device according to claim 9, wherein: The thickness of the third separation layer is greater than the third thickness.

11. The display device according to claim 9, wherein: The thickness of the third separation layer is less than the sum of the third thickness and the fourth thickness.

12. A display device, comprising: a first electrode; a pixel defining layer, on the first electrode; a separation layer, on the pixel defining layer; an emission structure on the first electrode and the separation layer; as well as a second electrode, on the emitting structure, The separation layer includes a first separation layer having a first width and a second separation layer having a second width greater than the first width. wherein the emission structure comprises a first layer between the pixel defining layer and the first surface of the second spacer layer and a second layer on the second surface of the second spacer layer, and The electrical conductivity of the first layer is higher than the electrical conductivity of the second layer.

13. The display device according to claim 12, wherein: The first spacer layer is between the pixel defining layer and the second spacer layer.

14. The display device according to claim 12 or 13, wherein: The spacer layer further includes a third spacer layer having a third width smaller than the second width.

15. The display device according to claim 14, wherein: The third spacer layer is on the second surface of the second spacer layer.

16. The display device according to claim 14, wherein: The spacer layer further includes a fourth spacer layer having a fourth width greater than the third width.

17. The display device according to claim 16, wherein: The third spacer layer is between the second spacer layer and the fourth spacer layer.

18. The display device according to claim 16, wherein: The emitting structure further includes a third layer between the second surface of the second spacer layer and the first surface of the fourth spacer layer.

19. The display device according to claim 18, wherein: The emitting structure further includes a fourth layer on the second surface of the fourth spacer layer.

20. The display device according to claim 19, wherein: The electrical conductivity of the third layer is higher than the electrical conductivity of the fourth layer.

Images