Display device

Abstract

The display device comprises a first data line, a second data line, a first voltage line, a second voltage line and a plurality of pixels, the plurality of pixels includes: a first sub-pixel including a first pixel circuit and a first light emitting element; the second sub-pixel comprises a second pixel circuit and a second light-emitting element; the first voltage line includes a 1-1 portion extending in a first direction and a 1-2 portion electrically connected to the 1-1 portion and extending in a second direction intersecting the first direction. The second voltage line includes a 2-1 portion extending in the first direction and a 2-2 portion electrically connected to the 2-1 portion and extending in the second direction.

Description

Technical Field

[0001] The present invention relates to a display device with improved display quality. Background Art

[0002] Generally speaking, a display device includes a display panel for displaying an image and a driving circuit for driving the display panel. The display panel includes: a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The driving circuit includes: a data driving circuit that outputs a data driving signal to the data line; a scanning driving circuit that outputs a scanning signal for driving the scanning line; and a driving controller that controls the data driving circuit and the scanning driving circuit.

[0003] Such a display device can display an image by outputting a scan signal using a scan line connected to a pixel to be displayed, and supplying a data voltage corresponding to the display image to a data line connected to the pixel.

[0004] Furthermore, the plurality of pixels may respectively provide one of a plurality of color lights such as red light, green light, and blue light. Each of the plurality of pixels may include a light emitting element and a pixel circuit for driving the light emitting element. The size and arrangement of each of the plurality of pixels may be varied. Summary of the invention

[0005] An object of the present invention is to provide a display device with improved display quality.

[0006] According to an embodiment of the present invention, a display device may include: a first data line and a second data line, each extending in a first direction; a first voltage line and a second voltage line, providing initialization voltages different from each other; and a plurality of pixels, the plurality of pixels including: a first sub-pixel, electrically connected to the first data line and the first voltage line, and including a first pixel circuit and a first light-emitting element; and a second sub-pixel, adjacent to the first sub-pixel, electrically connected to the second data line and the second voltage line, and including a second pixel circuit and a second light-emitting element, the first voltage line including a 1-1 portion extending in the first direction and a 1-2 portion electrically connected to the 1-1 portion and extending in a second direction intersecting the first direction, the second voltage line including a 2-1 portion extending in the first direction and a 2-2 portion electrically connected to the 2-1 portion and extending in the second direction.

[0007] The 1-1 part and the 2-1 part may be arranged on the same layer, or the 1-1 part and the 1-2 part may be arranged on different layers.

[0008] The first data line, the second data line, the 1-1 portion, and the 2-1 portion may be arranged on the same layer.

[0009] The first pixel circuit may include a 1-1th initialization transistor connected between the first voltage line and the first light emitting element, and the second pixel circuit may include a 1-2th initialization transistor connected between the second voltage line and the second light emitting element.

[0010] The first pixel circuit may include a first driving transistor and a 2-1 initialization transistor connected between a gate electrode of the first driving transistor and the first voltage line, and the second pixel circuit may include a second driving transistor and a 2-2 initialization transistor connected between a gate electrode of the second driving transistor and the second voltage line.

[0011] The present invention may also include a third data line and a third voltage line provided with a voltage different from the first voltage line and the second voltage line. The multiple pixels also include a third sub-pixel, which is adjacent to the second sub-pixel and includes a third pixel circuit and a third light-emitting element. The third sub-pixel can be electrically connected to the third voltage line.

[0012] The third voltage line may include: a portion 3-1 extending in the first direction; and a portion 3-2 electrically connected to the portion 3-1 and extending in the second direction.

[0013] The first to third data lines may be provided with color data different from each other.

[0014] A plurality of the first pixel circuits and the second pixel circuits may be provided, the plurality of the first pixel circuits may be arranged along the first direction, the plurality of the second pixel circuits may be arranged along the first direction, and the plurality of the first pixel circuits and the plurality of the second pixel circuits may be spaced apart in the second direction.

[0015] A plurality of the first light-emitting elements may be provided, and the plurality of the first light-emitting elements may be electrically connected to the plurality of the first pixel circuits respectively. When observed from a plane, a portion of the plurality of the first light-emitting elements may overlap with the corresponding first pixel circuits, and when observed from the plane, the remaining plurality of the first light-emitting elements do not overlap with the corresponding first pixel circuits.

[0016] When viewed from a plane, the second data line may overlap with the first light emitting element and may not overlap with the second light emitting element.

[0017] The first data line and the second data line may be spaced apart in the second direction.

[0018] When viewed from a plane, the first voltage line, the second voltage line, and the third voltage line may each have a mesh structure.

[0019] According to an embodiment of the present invention, a display device may include: a data line extending in a first direction; a voltage line providing an initialization voltage; and a pixel electrically connected to the data line and the voltage line, the pixel including a pixel circuit and a light-emitting element, the voltage line including: a first portion extending in the first direction; and a second portion electrically connected to the first portion and extending in a second direction intersecting the first direction, the first portion and the second portion being arranged on different layers, and the data line and the first portion being arranged on the same layer.

[0020] The pixel circuit may include: a first initialization transistor connected between the voltage line and the light emitting element.

[0021] The pixel circuit may include: a driving transistor; and a second initialization transistor connected between a gate electrode of the driving transistor and the voltage line.

[0022] A plurality of the pixel circuits may be provided, and the plurality of the pixel circuits may be arranged along the first direction.

[0023] A plurality of the light emitting elements may be provided, and the plurality of the light emitting elements may be electrically connected to a plurality of the pixel circuits, respectively.

[0024] When viewed from a plane, a portion of the plurality of light emitting elements may overlap with corresponding pixel circuits.

[0025] When viewed from the plane, the remaining light emitting elements among the plurality of light emitting elements may not overlap with the corresponding pixel circuits.

[0026] (Effects of the Invention)

[0027] As described above, the first to third voltage lines may have a mesh structure. Thus, compared with the voltage lines extending in the second direction in the past, the first to third voltage lines may further include a second portion extending in the first direction. The area of ​​the wiring for providing the initialization voltage may be increased, and the resistance may be reduced. As the first to third voltage lines transmit the initialization voltage, the load (Load) applied to the first to third voltage lines may be reduced. Therefore, a display device with improved reliability may be provided.

[0028] Furthermore, as described above, the first to third voltage lines can be connected to the first to third sub-pixels, respectively. Thus, the phenomenon that the charge flows to other adjacent sub-pixels during the driving of a certain sub-pixel can be prevented or eliminated. The color difference that may occur due to horizontal leakage can be prevented or eliminated. Therefore, a display device with improved display quality can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram of a display device according to an embodiment of the present invention.

[0030] Figure 2 A partial structure of a display panel according to an embodiment of the present invention is exemplarily shown.

[0031] Figure 3 A partial structure of a display panel according to an embodiment of the present invention is exemplarily shown.

[0032] FIG. 4A to FIG. 4C is a circuit diagram of first to third sub-pixels according to an embodiment of the present invention.

[0033] FIG. 5A to FIG. 5C is a circuit diagram of first to third sub-pixels according to an embodiment of the present invention.

[0034] Figure 6 An embodiment of the present invention is along Figure 3 A cross-sectional view of the display panel taken along line II'.

[0035] Figure 7 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0036] Figure 8 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0037] Fig. 9 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0038] Fig.10 A partial structure of a display panel according to an embodiment of the present invention is exemplarily shown.

[0039] Description of Reference Numerals

[0040] DD: display device; DP: display panel; PX: multiple pixels; PXR: first sub-pixel; L1: first voltage line; L1-1: first part; L1-2: second part; PXG: second sub-pixel; L2: second voltage line; L2-1: first part; L2-2: second part; PXB: third sub-pixel; L3: third voltage line; L3-1: first part; L3-2: second part DETAILED DESCRIPTION

[0041] In this specification, when referring to a certain constituent element (or region, layer, part, etc.) being "on" another constituent element, "connected" or "combined with" another constituent element, it means that the certain constituent element can be directly configured / connected / combined on the other constituent element, or a third-party constituent element can be configured between them.

[0042] The same reference numerals represent the same components. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated for effective description of the technical content. "And / or" includes all of the combinations of more than one that can be defined for the components related to each other.

[0043] The terms first, second, etc. may be used to describe a plurality of constituent elements, but the constituent elements are not limited to the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element may be referred to as the second constituent element, and similarly, the second constituent element may be referred to as the first constituent element. Unless a different meaning is clearly indicated in the context, a singular expression includes a plural expression.

[0044] In addition, the terms such as “below”, “lower side”, “above”, and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0045] The terms "including" or "having" should be understood as intending to specify the existence of the features, numbers, steps, actions, constituent elements, parts or their combinations recorded in the specification, but are not intended to preclude the existence or additional possibilities of one or more other features, numbers, steps, actions, constituent elements, parts or their combinations.

[0046] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. Furthermore, terms that are the same as those defined in generally used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, wherein, unless explicitly defined, they should not be interpreted as having overly ideal or overly formal meanings.

[0047] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0048] Figure 1 is a block diagram of a display device according to an embodiment of the present invention.

[0049] Reference Figure 1 , the display device DD may include: a driving controller 100, a data driving circuit 200, a voltage generator 500 and a display panel DP.

[0050] The driving controller 100 may receive an input image signal RGB and a control signal CTRL. The driving controller 100 may generate an output image signal DS that converts the input image signal RGB into an image type suitable for the display panel DP. The driving controller 100 may output a scan control signal SCS and a data control signal DCS.

[0051] The display panel DP of one embodiment of the present invention may be a light-emitting display panel, which is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer of the quantum dot light-emitting display panel may include quantum dots and quantum rods, etc. The light-emitting layer of the micro-LED display panel may include micro-LEDs. The light-emitting layer of the nano-LED display panel may include nano-LEDs.

[0052] The display panel DP may include scan lines GL1 -GLn, data lines DL1 ˜DLm, and a plurality of pixels PX.

[0053] The display panel DP may be defined with a display area DA and a non-display area NDA. Through the display area DA, the display panel DP may display an image in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may surround the display area DA.

[0054] The display panel DP may further include a scan driving circuit 300 and a light emitting driving circuit 400. The pixels PX may be disposed in the display area DA, and the scan driving circuit 300 and the light emitting driving circuit 400 may be disposed in the non-display area NDA.

[0055] The scan lines GL1-GLn may extend from the scan driving circuit 300 in the first direction DR1 and be arranged at intervals from each other in a second direction DR2 intersecting the first direction DR1. The light emission control lines EML1-EMLn may extend from the light emission driving circuit 400 in the opposite direction of the first direction DR1 and be arranged at intervals from each other in the second direction DR2. The data lines DL1-DLm may extend from the data driving circuit 200 in the second direction DR2 and be arranged at intervals from each other in the first direction DR1.

[0056] Each pixel in the plurality of pixels PX may be connected to a corresponding scan line among the scan lines GL1 -GLn, to a corresponding data line among the data lines DL1 -DLm, and to a corresponding light emission control line among the light emission control lines EML1 -EMLn. Figure 1 , each pixel in the plurality of pixels PX is connected to one scanning line, but the present invention is not limited thereto. For example, each pixel in the plurality of pixels PX may be electrically connected to two or more scanning lines.

[0057] Each of the plurality of pixels PX may include a light emitting element and a pixel circuit for controlling the light emitting element to emit light. The light emitting element and the pixel circuit will be described later.

[0058] The data driving circuit 200 may receive a data control signal DCS and an output image signal DS from the driving controller 100. The data driving circuit 200 converts the output image signal DS into first to third color data signals, and outputs the first to third color data signals to the data lines DL1 to DLm, respectively. Each of the first to third color data signals may have a voltage level corresponding to a grayscale level of the output image signal DS.

[0059] The data driving circuit 200 may be implemented by an integrated circuit (IC) and directly mounted on a specified area of ​​the display panel DP or mounted on an additional printed circuit board in a chip on film (COF) manner to be electrically connected to the display panel DP. In one embodiment, the data driving circuit 200 may be formed on the display panel DP using the same process as the pixel circuit of each pixel in the plurality of pixels PX.

[0060] The scan driving circuit 300 may receive a scan control signal SCS from the driving controller 100. The scan driving circuit 300 may output a scan signal to the scan lines GL1-GLn in response to the scan control signal SCS. In one embodiment, the scan driving circuit 300 may be formed in the same process as a pixel circuit of each pixel in the plurality of pixels PX.

[0061] The light emitting driving circuit 400 may receive a light emitting driving signal ECS from the driving controller 100. The light emitting driving circuit 400 may output a light emitting control signal to the light emitting control lines EML1 to EMLn in response to the light emitting driving signal ECS. In one embodiment, the light emitting driving circuit 400 may be formed in the same process as the pixel circuit of each pixel PX. Figure 1 4. The light emitting driving circuit 400 is shown in FIG. 3 , but the present invention is not limited thereto. In one embodiment, the light emitting driving circuit 400 may be included in the scanning driving circuit 300.

[0062] The driving controller 100 , the data driving circuit 200 , the scanning driving circuit 300 , and the light emitting driving circuit 400 may be driving circuits for providing first to third color data signals corresponding to the input image signal RGB to the pixel PX.

[0063] The voltage generator 500 may generate voltages required for the display panel DP to operate. The voltage generator 500 may provide the voltages to the display panel DP. In an embodiment of the present invention, the voltages may include: a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage Vint, and a second initialization voltage Vaint.

[0064] The first initialization voltage Vint may have a higher voltage level than the second initialization voltage Vaint. However, this is merely exemplary, and the voltage levels of the first initialization voltage Vint and the second initialization voltage Vaint of an embodiment of the present invention are not limited thereto. For example, the first initialization voltage Vint may also have the same voltage level as the second initialization voltage Vaint.

[0065] Figure 2 A partial structure of a display panel according to an embodiment of the present invention is exemplarily shown.

[0066] Reference Figure 2 , the display panel DP may include: a plurality of first sub-pixels PXR, a plurality of second sub-pixels PXG, a plurality of third sub-pixels PXB, a first voltage line L1, a second voltage line L2, and a third voltage line L3.

[0067] A plurality of pixels PX (refer to Figure 1 ) may include: a first sub-pixel PXR, a second sub-pixel PXG and a third sub-pixel PXB.

[0068] The first subpixel PXR may be electrically connected to the first voltage line L1. The first subpixel PXR may emit a first light.

[0069] The second subpixel PXG may be adjacent to the first subpixel PXR. The second subpixel PXG may be electrically connected to the second voltage line L2. The second subpixel PXG may emit a second light.

[0070] The third subpixel PXB may be adjacent to the second subpixel PXG. The third subpixel PXB may be electrically connected to the third voltage line L3. The third subpixel PXB may emit a third light.

[0071] In one embodiment, the first to third lights may be lights of different colors from each other. In another embodiment, the first to third lights may be lights of different colors from each other.

[0072] In one embodiment, the first to third lights may be red light, green light, and blue light, respectively. However, the present invention is not limited thereto. In another embodiment, the first to third lights may be not only blue, green, and red, but also white, cyan, magenta, and yellow.

[0073] The first subpixel PXR, the second subpixel PXG, and the third subpixel PXB may be arranged along the first direction DR1.

[0074] Each of the first sub-pixel PXR, the second sub-pixel PXG, and the third sub-pixel PXB may be provided in plurality.

[0075] Each of the plurality of first sub-pixels PXR, the plurality of second sub-pixels PXG, and the plurality of third sub-pixels PXB may be arranged in the second direction DR2.

[0076] in addition, Figure 2 The arrangement of the first to third sub-pixels PXR, PXG, and PXB is shown by way of example, but is not limited thereto and may be arranged in a variety of forms. In one embodiment, the first to third sub-pixels PXR, PXG, and PXB may have a pendent tile. TM Alternatively, the first to third sub-pixels PXR, PXG, PXB may also have a stripe arrangement or a diamond arrangement. TM ) arrangement form.

[0077] The first voltage line L1 may be provided with a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ). This will be described later.

[0078] The first voltage line L1 may include a 1-1 portion P1-1 and a 1-2 portion P1-2. The 1-1 portion P1-1 may extend in the second direction DR2. The 1-2 portion P1-2 may be electrically connected to the 1-1 portion P1-1. The 1-2 portion P1-2 may extend in the first direction DR1. The first voltage line L1 may have a mesh shape.

[0079] The 1-1 portion P1-1 and the 1-2 portion P1-2 may be disposed in different layers. The 1-1 portion P1-1 and the 1-2 portion P1-2 may be electrically connected to each other through the contact hole CNT.

[0080] The 1-1 portion P1-1 may be provided in plurality. The plurality of 1-1 portions P1-1 may be disposed adjacent to the first sub-pixel PXR and electrically connected.

[0081] The second voltage line L2 can provide a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ). This will be described later.

[0082] The second voltage line L2 may include a 2-1 portion P2-1 and a 2-2 portion P2-2. The 2-1 portion P2-1 may extend in the second direction DR2. The 2-2 portion P2-2 may be electrically connected to the 2-1 portion P2-1. The 2-2 portion P2-2 may extend in the first direction DR1. The second voltage line L2 may have a mesh shape.

[0083] The 2-1 portion P2-1 and the 2-2 portion P2-2 may be disposed in different layers. The 2-1 portion P2-1 and the 2-2 portion P2-2 may be electrically connected to each other through the contact hole CNT.

[0084] The 2-1 portion P2-1 may be provided in plurality, and the plurality of 2-1 portions P2-1 may be disposed adjacent to and electrically connected to the second sub-pixel PXG.

[0085] The third voltage line L3 can provide a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ). This will be described later.

[0086] The third voltage line L3 may include a 3-1 portion P3-1 and a 3-2 portion P3-2. The 3-1 portion P3-1 may extend in the second direction DR2. The 3-2 portion P3-2 may be electrically connected to the 3-1 portion P3-1. The 3-2 portion P3-2 may extend in the first direction DR1. The third voltage line L3 may have a mesh shape.

[0087] The 3-1 portion P3-1 and the 3-2 portion P3-2 may be disposed in different layers. The 3-1 portion P3-1 and the 3-2 portion P3-2 may be electrically connected to each other through the contact hole CNT.

[0088] The 3-1 portion P3-1 may be provided in plurality. The plurality of 3-1 portions P3-1 may be disposed adjacent to and electrically connected to the third sub-pixel PXB.

[0089] According to the present invention, the first to third voltage lines L1, L2, L3 may have a mesh structure. Thus, compared with the conventional voltage lines extending in the second direction DR2, the first to third voltage lines L1, L2, L3 may further include second portions P1-2, P2-2, P3-2 extending in the first direction DR1. Figure 1 ) can increase the wiring area and reduce the resistance. As the first to third voltage lines L1, L2, L3 transmit the initialization voltages Vint, Vaint (refer to Figure 1 ), the load (Load) applied to the first to third voltage lines L1, L2, L3 can be reduced. Therefore, a display device DD with improved reliability can be provided (refer to Figure 1 ).

[0090] Furthermore, unlike the present invention, initialization voltages Vint and Vaint (see Figure 1 ), when driving the first to third sub-pixels PXR, PXG, PXB, the common wiring can be used as a charge movement channel. Horizontal leakage current may occur through the common wiring, so that when driving a certain sub-pixel, the charge flows to another adjacent sub-pixel. However, according to the present invention, the first to third voltage lines L1, L2, L3 can be connected to the first to third sub-pixels PXR, PXG, PXB, respectively. Thereby, the phenomenon that the charge flows to other adjacent sub-pixels when driving a certain sub-pixel can be prevented or eliminated. The color difference that may occur due to the horizontal leakage current can be prevented or eliminated. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0091] Figure 3 A partial structure of a display panel according to an embodiment of the present invention is exemplarily shown.

[0092] Reference Figure 3 The display panel DP may include: a plurality of data lines DL1~DL8, a plurality of first pixel circuits PC11, PC15, PC21, PC25, a plurality of second pixel circuits PC12, PC14, PC16, PC18, PC22, PC24, PC26, PC28, a plurality of third pixel circuits PC13, PC17, PC23, PC27, a plurality of first light emitting elements RE11, RE13, RE22, RE24, a plurality of second light emitting elements GE15~GE18, GE25~GE28 and a plurality of third light emitting elements BE12, BE14, BE21, BE23.

[0093] A plurality of first pixel circuits PC11, PC15, PC21, PC25 and a plurality of first light emitting elements RE11, RE13, RE22, RE24 corresponding thereto may be respectively included in the first sub-pixel PXR (refer to Figure 2 ).

[0094] The plurality of second pixel circuits PC12, PC14, PC16, PC18, PC22, PC24, PC26, PC28 and the plurality of second light emitting elements GE15-GE18, GE25-GE28 corresponding thereto may be respectively included in the second sub-pixel PXG (refer to Figure 2 )middle.

[0095] A plurality of third pixel circuits PC13, PC17, PC23, PC27 and a plurality of third light emitting elements BE12, BE14, BE21, BE23 corresponding thereto may be respectively included in a third sub-pixel PXB (refer to Figure 2 )middle.

[0096] A portion of the first pixel circuits PC11, PC15 among multiple first pixel circuits PC11, PC15, PC21, PC25, a portion of the second pixel circuits PC12, PC14, PC16, PC18, PC22, PC24, PC26, PC28 and a portion of the third pixel circuits PC13, PC17 among multiple third pixel circuits PC13, PC17, PC23, PC27 can be arranged in the first row ROW1 and arranged sequentially in the first direction DR1.

[0097] A portion of the first pixel circuits PC21, PC25 among the plurality of first pixel circuits PC11, PC15, PC21, PC25, a portion of the second pixel circuits PC22, PC24, PC26, PC28 among the plurality of second pixel circuits PC12, PC14, PC16, PC18, PC22, PC24, PC26, PC28, and a portion of the third pixel circuits PC23, PC27 among the plurality of third pixel circuits PC13, PC17, PC23, PC27 may be arranged in the second row ROW2 and sequentially arranged in the first direction DR1. The second row ROW2 may be spaced apart from the first row ROW1 in the second direction DR2.

[0098] Each of the plurality of data lines DL1 to DL8 may extend in the second direction DR2. The plurality of data lines DL1 to DL8 may be arranged at intervals from each other in the first direction DR1.

[0099] The plurality of data lines DL1 ˜ DL8 may include a first data line DL1 , a second data line DL2 , a third data line DL3 , a fourth data line DL4 , a fifth data line DL5 , a sixth data line DL6 , a seventh data line DL7 and an eighth data line DL8 .

[0100] Part of the plurality of data lines DL1 to DL8 may be arranged adjacent to each other in pairs, that is, the second data line DL2 and the third data line DL3 may be arranged adjacent to each other, the fourth data line DL4 and the fifth data line DL5 may be arranged adjacent to each other, and the sixth data line DL6 and the seventh data line DL7 may be arranged adjacent to each other.

[0101] The pixel circuits PC11 to PC18 arranged in the first row ROW1 may be connected to corresponding data lines among the plurality of data lines DL1 to DL8 , respectively.

[0102] The pixel circuits PC21 to PC28 arranged in the second row ROW2 may be connected to corresponding data lines among the plurality of data lines DL1 to DL8 , respectively.

[0103] When viewed from a plane, the first data line DL1 may overlap the first light emitting element RE11 and the third light emitting element BE21.

[0104] When viewed from a plane, the second data line DL2 may not overlap with the second light emitting elements GE15 and GE25.

[0105] When viewed from a plane, the second data line DL2 and the third data line DL3 may overlap the third light emitting element BE12 and the first light emitting element RE22 .

[0106] When viewed from a plane, the fourth data line DL4 may not overlap with the second light emitting elements GE16 and GE26.

[0107] When viewed from a plane, the fourth data line DL4 and the fifth data line DL5 may overlap the first light emitting element RE13 and the third light emitting element BE23 .

[0108] When viewed from a plane, the sixth data line DL6 may not overlap with the second light emitting elements GE17 and GE27.

[0109] When viewed from a plane, the sixth data line DL6 and the seventh data line DL7 may overlap the third light emitting element BE14 and the first light emitting element RE24.

[0110] When viewed from a plane, the eighth data line DL8 may not overlap with the second light emitting elements GE18 and GE28.

[0111] In the first row ROW1, the first light emitting element RE11, the second light emitting element GE15, the third light emitting element BE12, the second light emitting element GE16, the first light emitting element RE13, the second light emitting element GE17, the third light emitting element BE14 and the second light emitting element GE18 may be sequentially arranged along the first direction DR1.

[0112] In the second row ROW2, the third light emitting element BE21, the second light emitting element GE25, the first light emitting element RE22, the second light emitting element GE26, the third light emitting element BE23, the second light emitting element GE27, the first light emitting element RE24 and the second light emitting element GE28 may be sequentially arranged in the first direction DR1.

[0113] When observed from a plane, the first light-emitting elements RE11 and RE13 arranged in the first row ROW1 may overlap with the corresponding first pixel circuits PC11 and PC15 respectively, and the first light-emitting elements RE22 and RE24 arranged in the second row ROW2 may not overlap with the corresponding first pixel circuits PC21 and PC25 respectively.

[0114] When viewed from a plane, the second light emitting elements GE15 to GE18 and GE25 to GE28 may overlap with corresponding second pixel circuits PC12, PC14, PC16, PC18, PC22, PC24, PC26 and PC28, respectively.

[0115] When observed from a plane, the third light-emitting elements BE12 and BE14 arranged in the first row ROW1 may overlap with the corresponding third pixel circuits PC13 and PC17 respectively, and the third light-emitting elements BE21 and BE23 arranged in the second row ROW2 may not overlap with the corresponding third pixel circuits PC23 and PC27 respectively.

[0116] Figure 3 The size, shape and arrangement order of each light emitting element among the multiple first light emitting elements RE11, RE13, RE22, RE24, the multiple second light emitting elements GE15-GE18, GE25-GE28 and the multiple third light emitting elements BE12, BE14, BE21, BE23 shown are merely examples to facilitate understanding of the description, and the present invention is not limited thereto.

[0117] Figure 3 The first light emitting elements RE11, RE13, RE22, RE24, a plurality of second light emitting elements GE15-GE18, GE25-GE28, and a plurality of third light emitting elements BE12, BE14, BE21, BE23 are exemplarily shown to have a pantile (PENTILE TM) arrangement form, but the arrangement form of the light emitting element can also have a stripe arrangement form or a diamond arrangement form. TM ) arrangement form.

[0118] Each of the plurality of first light emitting elements RE11, RE13, RE22, RE24 may emit a first light, for example, red light.

[0119] Each of the plurality of second light emitting elements GE15-GE18, GE25-GE28 may emit a second light different from the first light, for example, green light.

[0120] Each of the plurality of third light emitting elements BE12, BE14, BE21, and BE23 may emit a third light different from the first light and the second light, for example, the third light may be blue light.

[0121] The first light emitting elements RE11, RE13, the second light emitting elements GE15-GE18 and the third light emitting elements BE12, BE14 of the first row ROW1 can be electrically connected to a corresponding one of the pixel circuits PC11-PC18 of the first row ROW1 through a plurality of extended wirings (or a plurality of extended electrodes) EL11-EL18.

[0122] The plurality of extension wirings EL11 to EL18 may include a first extension wiring EL11 , a second extension wiring EL12 , a third extension wiring EL13 , a fourth extension wiring EL14 , a fifth extension wiring EL15 , a sixth extension wiring EL16 , a seventh extension wiring EL17 , and an eighth extension wiring EL18 .

[0123] The first extension wiring EL11 may extend in the first direction DR1 and be electrically connected between the first light emitting element RE11 and the first pixel circuit PC11 through the first contact hole CT11 .

[0124] The second extension wiring EL12 may extend in the first direction DR1 and be electrically connected between the third light emitting element BE12 and the third pixel circuit PC13 through the second contact hole CT12 .

[0125] The extension wiring EL13 may extend in the first direction DR1 and be electrically connected between the first light emitting element RE13 and the first pixel circuit PC15 through the third contact hole CT13 .

[0126] The extension wiring EL14 may extend in the first direction DR1 and be electrically connected between the third light emitting element BE14 and the third pixel circuit PC17 through the fourth contact hole CT14 .

[0127] The extension wiring EL15 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE15 and the second pixel circuit PC12 through the fifth contact hole CT15 .

[0128] The extension wiring EL16 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE16 and the second pixel circuit PC14 through the sixth contact hole CT16 .

[0129] The extension wiring EL17 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE17 and the second pixel circuit PC16 through the seventh contact hole CT17 .

[0130] The extension wiring EL18 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE18 and the second pixel circuit PC18 through the eighth contact hole CT18 .

[0131] The first light emitting elements RE22 and RE24 , the second light emitting elements GE25 to GE28 and the third light emitting elements BE21 and BE23 of the second row ROW2 may be electrically connected to corresponding ones of the pixel circuits PC21 to PC28 of the second row ROW2 through a plurality of extension wirings EL21 to EL28 .

[0132] The plurality of extension wirings EL21 to EL28 may include a ninth extension wiring EL21 , a tenth extension wiring EL22 , an eleventh extension wiring EL23 , a twelfth extension wiring EL24 , a thirteenth extension wiring EL25 , a fourteenth extension wiring EL26 , a fifteenth extension wiring EL27 , and a sixteenth extension wiring EL28 .

[0133] The extension wiring EL21 may extend in the first direction DR1 and be electrically connected between the third light emitting element BE21 and the third pixel circuit (not shown) through a third contact hole (not shown).

[0134] The extension wiring EL22 may extend in the first direction DR1 and be electrically connected between the first light emitting element RE22 and the second pixel circuit PC21 through the second contact hole CT22 .

[0135] The extension wiring EL23 may extend in the first direction DR1 and be electrically connected between the third light emitting element BE23 and the third pixel circuit PC23 through the third contact hole CT23 .

[0136] The extension wiring EL24 may extend in the first direction DR1 and be electrically connected between the first light emitting element RE24 and the first pixel circuit PC25 through the first contact hole CT24 .

[0137] The extension wiring EL25 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE25 and the second pixel circuit PC22 through the second contact hole CT25 .

[0138] The extension wiring EL26 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE26 and the second pixel circuit PC24 through the second contact hole CT26 .

[0139] The extension wiring EL27 may extend in the second direction DR2 and be electrically connected between the second light emitting element GE27 and the second pixel circuit PC26 through the second contact hole CT27 .

[0140] The extension wiring EL28 may extend in the second direction DR2 and electrically connect the second light emitting element GE28 and the second pixel circuit PC28 through the second contact hole CT28 .

[0141] Data driving circuit 200 (see Figure 1 ) can output first color data signals RD1 and RD5 to the data lines DL1 and DL5, respectively, output second color data signals GD2, GD4, GD6, GD8 to the data lines DL2, DL4, DL6, DL8, respectively, and output third color data signals BD3 and BD7 to the data lines DL3 and DL7, respectively.

[0142] In one embodiment, each first color data signal RD1, RD5 may be a red data signal, each second color data signal GD2, GD4, GD6, GD8 may be a green data signal, and each third color data signal BD3, BD7 may be a blue data signal.

[0143] Data driving circuit 200 (see Figure 1 ) Only data signals corresponding to specific colors are output to each data line DL1 to DL8, thereby reducing power consumption.

[0144] For example, a current corresponding to the first color data signal RD1 provided to the first data line DL1 may be transferred to the first light emitting elements RE11 and RE22 through the first pixel circuits PC11 and PC21 .

[0145] A current corresponding to the second color data signal GD2 provided to the second data line DL2 may be transmitted to the second light emitting elements GE15 and GE25 through the second pixel circuits PC12 and PC22 .

[0146] A current corresponding to the third color data signal BD3 provided to the third data line DL3 may be transferred to the third light emitting elements BE12 and BE23 through the third pixel circuits PC13 and PC23.

[0147] A current corresponding to the second color data signal GD4 provided to the data line DL4 may be transmitted to the second light emitting elements GE16 and GE26 through the second pixel circuits PC14 and PC24.

[0148] A current corresponding to the first color data signal RD5 provided to the data line DL5 may be transferred to the first light emitting elements RE13 and RE24 through the first pixel circuits PC15 and PC25 .

[0149] A current corresponding to the second color data signal GD6 provided to the data line DL6 may be transmitted to the second light emitting elements GE17 and GE27 through the second pixel circuits PC16 and PC26 .

[0150] A current corresponding to the third color data signal BD7 supplied to the data line DL7 may be transferred to the third light emitting element GE14 through the third pixel circuit PC17 .

[0151] A current corresponding to the second color data signal GD8 provided to the data line DL8 may be transmitted to the second light emitting elements GE18 and GE28 through the second pixel circuits PC18 and PC28 .

[0152] FIG. 4A to FIG. 4C is a circuit diagram of first to third sub-pixels according to an embodiment of the present invention.

[0153] Reference Figures 3 to 4C , the first sub-pixel PXR may include a first pixel circuit PC11 and a first light emitting element RE11.

[0154] The second sub-pixel PXG may include a second pixel circuit PC12 and a second light emitting element GE15 .

[0155] The third subpixel PXB may include a third pixel circuit PC13 and a third light emitting element BE12 .

[0156] The first light emitting element RE11 , the second light emitting element GE15 , and the third light emitting element BE12 may be light emitting diodes.

[0157] Each pixel circuit in the first pixel circuit PC11, the second pixel circuit PC12, and the third pixel circuit PC13 may include at least one transistor and at least one capacitor. Each pixel circuit in the first pixel circuit PC11, the second pixel circuit PC12, and the third pixel circuit PC13 may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8, and a capacitor Cst. For example, each pixel circuit in the first pixel circuit PC11, the second pixel circuit PC12, and the third pixel circuit PC13 may be defined as having an 8T1C structure.

[0158] In this embodiment, the third and fourth transistors T3 and T4 of the first to eighth transistors T1 to T8 can be N-type transistors with oxide semiconductor as the semiconductor layer, and each transistor of the first, second, fifth, sixth, seventh, and eighth transistors T1, T2, T5, T6, T7, and T8 can be a P-type transistor with a low-temperature polycrystalline silicon (LTPS) semiconductor layer. However, the present invention is not limited to this. In one embodiment, all of the first to eighth transistors T1 to T8 can be P-type transistors or N-type transistors. In another embodiment, at least one transistor of the first to eighth transistors T1 to T8 can be an N-type transistor, and the remaining transistors can be P-type transistors.

[0159] In one embodiment, each pixel circuit in the first pixel circuit PC11, the second pixel circuit PC12 and the third pixel circuit PC13 may be electrically connected to a data line DL1, DL2, DL3, four scan lines GIL1, GCL1, GWL1, GBL1 and a light emitting control line EML1. Figure 1 The scan lines GL1-GLn shown may each include a plurality of scan lines. Figure 1 The scan line GL1 shown may include four scan lines GIL1 , GCL1 , GWL1 , and GBL1 .

[0160] The scanning lines GIL1, GCL1, GWL1, and GBL1 can transmit scanning signals GI1, GC1, GW1, and GB1, respectively, and the emission control line EML1 transmits the emission control signal EM1. The first data line DL1 can transmit the first color data signal RD1. The second data line DL2 can transmit the second color data signal GD2. The third data line DL3 can transmit the third color data signal BD3. The first color data signal RD1 can have a certain value that is different from the value input to the display device DD (refer to FIG. 1 ). Figure 1 ) image signal RGB (refer to Figure 1 ) The first to third driving voltage lines VL1, VL2, VL3 can transmit the first driving voltage ELVDD, the second driving voltage ELVSS and the first initialization voltage Vint.

[0161] The first voltage line L1 may transfer a 2-1st initialization voltage Vaint1 .

[0162] The second voltage line L2 may transfer the 2-2nd initialization voltage Vaint2. The 2-2nd initialization voltage Vaint2 may have a different voltage from the 2-1st initialization voltage Vaint1.

[0163] The third voltage line L3 may transmit the 2-3rd initialization voltage Vaint3. The 2-3rd initialization voltage Vaint3 may have voltages different from the 2-1st initialization voltage Vaint1 and the 2-2nd initialization voltage Vaint2.

[0164] The first transistor T1 includes: a first electrode S1 connected to the first driving voltage line VL1 via a fifth transistor T5; a second electrode D1; and a gate electrode G1 connected to one end of the capacitor Cst. The first transistor T1 may be referred to as a driving transistor T1.

[0165] The second transistor T2 includes: a first electrode connected to the data lines DL1, DL2, and DL3; a second electrode connected to the first electrode S1 of the first transistor T1; and a gate electrode connected to the scan line GWL1. The second transistor T2 can be turned on according to the scan signal GW1 received through the scan line GWL1 to transfer the first color data signal GD1 transmitted from the data line DL1 to the first electrode S1 of the first transistor T1. The first color data signal GD1 transmitted from the data line DL1 can correspond to the second color.

[0166] The third transistor T3 includes: a first electrode connected to the gate electrode G1 of the first transistor T1; a second electrode connected to the second electrode D1 of the first transistor T1; and a gate electrode connected to the scan line GCL1. The third transistor T3 can be turned on according to the scan signal GC1 received through the scan line GCL1 to connect the gate electrode G1 and the second electrode of the first transistor T1 to each other, thereby making the first transistor T1 diode-connected.

[0167] The fourth transistor T4 includes a first electrode connected to the gate electrode G1 of the first transistor T1, a second electrode connected to the third driving voltage line VL3 transmitting the first initialization voltage Vint1, and a gate electrode connected to the scanning line GIL1. The fourth transistor T4 may be referred to as a second initialization transistor T4.

[0168] The second electrodes of the fourth transistors T4 of the respective first, second, and third subpixels PXR, PXG, and PXB may be connected to the same third driving voltage line VL3.

[0169] The fourth transistor T4 may be turned on according to the scan signal GI1 received through the scan line GIL1 to transmit the first initialization voltage Vint1 to the gate electrode G1 of the first transistor T1 , thereby performing an initialization action of initializing the voltage of the gate electrode G1 of the first transistor T1 .

[0170] The fifth transistor T5 includes: a first electrode connected to the first driving voltage line VL1; a second electrode connected to the first electrode S1 of the first transistor T1; and a gate electrode connected to the light emission control line EML1.

[0171] The sixth transistor T6 includes a first electrode S6 connected to the second electrode D1 of the first transistor T1, a second electrode D6 connected to the anode of the first light emitting element RE11, and a gate electrode G6 connected to the light emitting control line EML1. The second electrode D6 of the sixth transistor T6 can be connected to the anodes of the light emitting elements RE11, GE15, and BE12.

[0172] The fifth transistor T5 and the sixth transistor T6 can be turned on at the same time according to the light emitting control signal EM1 received through the light emitting control line EML1. As the fifth transistor T5 and the sixth transistor T6 are turned on, a current path can be formed from the first driving voltage line VL1 to the light emitting elements RE11, GE15, and BE12 through the fifth transistor T5, the first transistor T1, and the sixth transistor T6. At this time, the current flowing through the first transistor T1 can correspond to the charge charged in the capacitor Cst. Therefore, the current corresponding to the data signals RD1, GD2, and BD3 can be transmitted to the light emitting elements RE11, GE15, and BE12.

[0173] The seventh transistor T7 includes a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to a corresponding one of the first to third voltage lines L1, L2, L3, and a gate electrode connected to the scan line GBL1. The seventh transistor T7 may be referred to as a first initialization transistor T7.

[0174] That is, the second electrode of the seventh transistor T7 of the first subpixel PXR can be connected to the first voltage line L1, the second electrode of the seventh transistor T7 of the second subpixel PXG is connected to the second voltage line L2, and the second electrode of the seventh transistor T7 of the third subpixel PXB is connected to the third voltage line L3.

[0175] The seventh transistor T7 may be turned on according to the scan signal GB1 received through the scan line GBL1 , so as to initialize the anode of each of the light emitting elements RE11 , GE15 , BE12 to a corresponding initialization voltage among the second initialization voltages Vaint1 , Vaint2 , Vaint3 .

[0176] According to the present invention, the anode of the first light emitting element RE11 emitting red light can be initialized to the 2-1st initialization voltage Vaint1 by the seventh transistor T7, the anode of the second light emitting element GE15 emitting green light can be initialized to the 2-2nd initialization voltage Vaint2 by the seventh transistor T7, and the anode of the third light emitting element BE12 emitting blue light can be initialized to the 2-3rd initialization voltage Vaint3 by the seventh transistor T7. That is, considering the aperture ratio of the light emitting element corresponding to the light emitting color and the initialization voltage based on the light emitting layer EML (refer to Figure 6 ) formed between the anode and cathode of the material can provide different initialization voltages Vaint1, Vaint2, and Vaint3 according to different luminescent colors. The time for the anode to be charged with the initialization voltages Vaint1, Vaint2, and Vaint3 can be supplemented, and the color difference phenomenon caused by the color being misaligned due to the difference in the time can be prevented or eliminated. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0177] Furthermore, according to the present invention, the initialization voltages Vaint1, Vaint2, and Vaint3 can be provided respectively through the first to third voltage lines L1, L2, and L3, rather than providing the same initialization voltage to each pixel in the plurality of pixels PX through one wiring. When initializing the anode of each light-emitting element RE11, GE15, and BE12, the applied load (Load) can be reduced. Therefore, the color difference between the light-emitting elements RE11, GE15, and BE12 caused by the load can be improved. Therefore, a display device DD with improved display quality can be provided (see Figure 1 ).

[0178] The eighth transistor T8 includes a first electrode connected to the first electrode S1 of the first transistor T1 , a second electrode connected to a bias voltage line VBL to which a bias voltage Vbias is transmitted, and a gate electrode connected to the scan line GBL1 .

[0179] The eighth transistor T8 may be turned on according to the scan signal GB1 received through the scan line GBL1 to transfer the bias voltage Vbias to the first electrode S1 of the first transistor T1 , thereby initializing the voltage of the first electrode S1 of the first transistor T1 .

[0180] As mentioned above, one end of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other end is connected to the first driving voltage line VL1. The cathode of the first light emitting element RE11 may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS.

[0181] FIG. 5A to FIG. 5C 1 is a circuit diagram of the first to third sub-pixels of an embodiment of the present invention. FIG. 5A to FIG. 5C During the explanation, FIG. 4A to FIG. 4C The constituent elements described are given the same reference numerals, and description thereof will be omitted.

[0182] Reference FIG. 5A to FIG. 5C , the first sub-pixel PXR- 1 may include a first pixel circuit PC11 - 1 and a first light emitting element RE11 .

[0183] The second subpixel PXG- 1 may include a second pixel circuit PC12 - 1 and a second light emitting element GE15 .

[0184] The third subpixel PXB- 1 may include a third pixel circuit PC13 - 1 and a third light emitting element BE12 .

[0185] Each of the first pixel circuit PC11 - 1 , the second pixel circuit PC12 - 1 , and the third pixel circuit PC13 - 1 may include first to seventh transistors T1 , T2 , T3 , T4 - 1 , T5 , T6 , and T7 - ​​1 and a capacitor Cst.

[0186] The first voltage line L1_1 may transfer a 1-1th initialization voltage Vint1 .

[0187] The second voltage line L2_1 may transfer the 1-2nd initialization voltage Vint2. The 1-2nd initialization voltage Vint2 may have a different voltage from the 1-1st initialization voltage Vint1.

[0188] The third voltage line L3_1 may transmit the 1-3rd initialization voltage Vint3. The 1-3rd initialization voltage Vint3 may have voltages different from the 1-1st initialization voltage Vint1 and the 1-2nd initialization voltage Vint2, respectively.

[0189] The fourth transistor T4-1 may include: a first electrode connected to the gate electrode G1 of the first transistor T1; a second electrode connected to a corresponding one of the first to third voltage lines L1_1, L2_1, L3_1; and a gate electrode connected to the scan line GIL1. The fourth transistor T4-1 may be referred to as a second initialization transistor T4-1.

[0190] That is, the second electrode of the fourth transistor T4-1 of the first subpixel PXR-1 can be connected to the first voltage line L1_1, the second electrode of the fourth transistor T4-1 of the second subpixel PXG-1 is connected to the second voltage line L2_1, and the second electrode of the fourth transistor T4-1 of the third subpixel PXB-1 is connected to the third voltage line L3_1.

[0191] The fourth transistor T4 - 1 can be turned on by the scan signal GI1 received by the scan line GIL1 to transmit the first initialization voltages Vint1 , Vint2 , and Vint3 to the gate electrode G1 of the first transistor T1 , thereby performing an initialization operation of initializing the voltage of the gate electrode G1 of the first transistor T1 .

[0192] The gate electrode G1 of the first transistor T1 of the first subpixel PXR-1 can be initialized to the 1-1th initialization voltage Vint1 by the fourth transistor T4-1, the gate electrode G1 of the first transistor T1 of the second subpixel PXG-1 is initialized to the 1-2nd initialization voltage Vint2 by the fourth transistor T4-1, and the gate electrode G1 of the first transistor T1 of the third subpixel PXB-1 is initialized to the 1-3rd initialization voltage Vint3 by the fourth transistor T4-1.

[0193] According to the present invention, the initialization voltages Vint1, Vint2, and Vint3 can be provided respectively through the first to third voltage lines L1_1, L2_1, and L3_1, rather than providing the same initialization voltage to each pixel in the plurality of pixels PX through one wiring. When the gate electrode G1 of the first transistor T1 is initialized, the applied load (Load) can be reduced. Therefore, the gate electrode G1 of the first transistor T1 can be easily initialized, and a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0194] The seventh transistor T7-1 may include a first electrode connected to the second electrode of the sixth transistor T6, a second electrode connected to the fourth driving voltage line VL4 providing the second initialization voltage Vaint, and a gate electrode connected to the scan line GBL1. The seventh transistor T7-1 may be referred to as a first initialization transistor T7-1.

[0195] The second electrode of the seventh transistor T7 - ​​1 of each of the first subpixel PXR- 1 , the second subpixel PXG- 1 , and the third subpixel PXB- 1 may be connected to the same fourth driving voltage line VL4 .

[0196] Figure 6 An embodiment of the present invention is along Figure 3 A cross-sectional view of the display panel taken along line II'. Figure 6 A cross section of a part of the second light emitting element GE15 and the second pixel circuit PC12 is exemplarily shown.

[0197] Reference Figure 3 and Figure 6, the display panel DP may include: a base layer BL, a circuit element layer DP-CL, a display element layer DP-ED and a thin film encapsulation layer TFE. The display panel DP may also include a functional layer such as a refractive index adjustment layer. The circuit element layer DP-CL includes at least a plurality of insulating layers and circuit elements. Hereinafter, the insulating layer may include an organic layer and / or an inorganic layer.

[0198] The insulating layer, the semiconductor layer and the conductive layer are formed by coating, deposition and other processes. Subsequently, the insulating layer, the semiconductor layer and the conductive layer can be selectively patterned by photolithography and etching processes. Semiconductor patterns, conductive patterns, signal lines, etc. are formed by such processes. Patterns configured on the same layer are formed by the same process.

[0199] The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. In particular, the synthetic resin layer may be a polyimide resin layer, and the material thereof is not particularly limited. The synthetic resin layer may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin. In addition, the base layer may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate, etc.

[0200] At least one inorganic layer is formed on the upper surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed into multiple layers. At least one of the multiple inorganic layers may constitute a buffer layer BFL.

[0201] The buffer layer BFL provides a bonding force between the base layer BL and the semiconductor pattern and / or the conductive pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0202] A semiconductor pattern is disposed on the buffer layer BFL. The semiconductor pattern may be directly disposed on the buffer layer BFL. The semiconductor pattern may include a silicon semiconductor. The semiconductor pattern may include LTPS (low-temperature polycrystalline silicon). However, the present invention is not limited thereto, and the semiconductor pattern may also include amorphous silicon.

[0203] The electrical properties of the semiconductor pattern are different depending on whether it is doped or not. The semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor includes a doped region doped with a P-type dopant.

[0204] The conductivity of the doped region is greater than that of the non-doped region, and it substantially functions as an electrode or a signal line. The non-doped region is substantially equivalent to the active region (or channel) of the transistor. In other words, a portion of the semiconductor pattern may be the active region of the transistor, another portion may be the first electrode (or source) or the second electrode (or drain) of the transistor, and another portion may be a connecting electrode or a connecting signal line (or a connecting electrode).

[0205] like Figure 6 As shown, in the second pixel circuit PC12, the first electrode S1, the active electrode A1, and the second electrode D1 of the first transistor T1 are formed from a semiconductor pattern. The first electrode S1 and the second electrode D1 of the first transistor T1 can extend from the active electrode A1 in opposite directions to each other. In addition, the first electrode S6, the active electrode A6, and the second electrode D6 of the sixth transistor T6 can be formed from a semiconductor pattern. The first electrode S6 and the second electrode D6 of the sixth transistor T6 extend from the active electrode A6 in opposite directions to each other. Although not shown separately, the first electrode S6 of the sixth transistor T6 can be connected to the second electrode D1 of the first transistor T1.

[0206] like FIG. 4A to FIG. 4C As shown, the first electrode S6 of the sixth transistor T6 may be electrically connected to the second electrode D1 of the first transistor T1.

[0207] A first insulating layer 10 is disposed on the buffer layer BFL. The first insulating layer 10 may overlap the pixel circuits PC11 to PC28 together and cover the semiconductor pattern. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only the first insulating layer 10, but also the insulating layer of the circuit element layer DP-CL described later may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned substances.

[0208] The gate electrode G1 of the first transistor T1 is disposed on the first insulating layer 10. The gate electrode G1 may be a part of the metal pattern. The gate electrode G1 of the first transistor T1 overlaps the active electrode A1 of the first transistor T1. In the process of doping the semiconductor pattern, the gate electrode G1 of the first transistor T1 is equivalent to a mask.

[0209] A second insulating layer 20 covering the gate electrode G1 is disposed on the first insulating layer 10. The second insulating layer 20 may overlap the pixel circuits PC11 to PC28. The second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer or multi-layer structure. In the present embodiment, the second insulating layer 20 may be a single-layer silicon oxide layer.

[0210] A third insulating layer 30 is disposed on the second insulating layer 20. In this embodiment, the third insulating layer 30 may be a single-layer silicon oxide layer.

[0211] A first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the second electrode D6 of the sixth transistor T6 through a contact hole CNT1 penetrating the first to third insulating layers 10 to 30.

[0212] A fourth insulating layer 40 covering the first connection electrode CNE1 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be a single-layer silicon oxide layer. A fifth insulating layer 50 is disposed on the fourth insulating layer 40. The fifth insulating layer 50 may be an organic layer. A second connection electrode CNE2 may be disposed on the fifth insulating layer 50. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT2 penetrating the fourth insulating layer 40 and the fifth insulating layer 50.

[0213] In one embodiment, the data lines DL1 ˜ DL8 may be disposed on the fifth insulating layer 50 similarly to the second link electrode CNE2 .

[0214] A sixth insulating layer 60 covering the second connection electrode CNE2 is disposed on the fifth insulating layer 50. The sixth insulating layer 60 may be an organic layer.

[0215] The connection wiring CL15 can be connected to the second connection electrode CNE2 through a contact hole CT15a penetrating the sixth insulating layer 60. A seventh insulating layer 70 is disposed on the sixth insulating layer 60. An anode GAE15 is disposed on the seventh insulating layer 70. The anode GAE15 is connected to the connection wiring CL15 through a contact hole CT15 penetrating the seventh insulating layer 70.

[0216] The pixel definition film PDL defines an opening OP. The opening OP of the pixel definition film PDL exposes at least a portion of the anode GAE15.

[0217] The light emitting layer EML is disposed on the anode GAE15. The light emitting layer EML may be disposed only in a region corresponding to the opening OP. The light emitting layer EML may be formed separately in each of the pixel circuits PC11 to PC28.

[0218] In this embodiment, although the patterned light-emitting layer EML is illustratively shown, the light-emitting layer EML can be configured in common in the pixel circuits PC11 to PC28. In this case, the light-emitting layer EML can generate white light or blue light. In addition, the light-emitting layer EML can have a multilayer structure. A cathode CE is configured on the light-emitting layer EML. The cathode CE is configured in common in the pixel circuits PC11 to PC28.

[0219] Although not shown, a hole control layer may be disposed between the anode GAE15 and the light-emitting layer EML, and an electron control layer may be disposed between the light-emitting layer EML and the cathode CE.

[0220] A thin film encapsulation layer TFE is disposed on the cathode CE. The thin film encapsulation layer TFE is commonly disposed on the pixel circuits PC11 to PC28. In this embodiment, the thin film encapsulation layer TFE directly covers the cathode CE. In one embodiment of the present invention, a capping layer directly covering the cathode CE may also be disposed.

[0221] The thin film encapsulation layer TFE includes at least an inorganic layer or an organic layer. In one embodiment of the present invention, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed therebetween. In one embodiment of the present invention, the thin film encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0222] The encapsulation inorganic layer protects the second light emitting element GE15 from moisture / oxygen, and the encapsulation organic layer protects the second light emitting element GE15 from foreign matter such as dust particles. The encapsulation inorganic layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer or an aluminum oxide layer, etc., which are not particularly limited. The encapsulation organic layer may include an acrylic series organic layer, which are not particularly limited.

[0223] Figure 7 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0224] Reference Figure 2 , Figure 6 as well as Figure 7 The first layer LY1 may be a layer disposed on the first insulating layer 10 and covered by the second insulating layer 20 .

[0225] The gate electrode G1 of the first transistor T1 , the second portion P2 - 2 of the second voltage line L2 , the plurality of scan lines GWL1 , GWL2 , and the plurality of scan lines GBL1 , GBL2 may be disposed on the same layer.

[0226] The gate electrode G1 of the first transistor T1 may be disposed on the first insulating layer 10. The second portion P2-2 of the second voltage line L2 may be disposed on the first insulating layer 10. The second portion P2-2 may extend in the first direction DR1.

[0227] The second portion P2 - 2 may be electrically connected to the first portion P1 - 1 of the second voltage line L2 through the contact hole CNTa.

[0228] The second portion P2-2 may be provided in plurality, and the plurality of second portions P2-2 may be arranged in the second direction DR2.

[0229] The plurality of scanning lines GWL1 and GWL2 may be disposed on the first insulating layer 10. Each of the plurality of scanning lines GWL1 and GWL2 may extend in the first direction DR1. The plurality of scanning lines GWL1 and GWL2 may be arranged in the second direction DR2.

[0230] The plurality of scanning lines GBL1 and GBL2 may be disposed on the first insulating layer 10. Each of the plurality of scanning lines GBL1 and GBL2 may extend in the first direction DR1. The plurality of scanning lines GBL1 and GBL2 may be arranged in the second direction DR2.

[0231] When viewed from a planar perspective, the gate electrode G1 may be disposed between the scanning lines GWL1 and GBL1 .

[0232] Figure 8 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0233] Reference Figure 2 , Figure 6 as well as Figure 8 The second layer LY2 may be a layer disposed on the fifth insulating layer 50 and covered by the sixth insulating layer 60 .

[0234] The second portion P1-2 of the first voltage line L1, the plurality of scan lines GCL1, GCL2, the plurality of emission control lines EML1, EML2, the bias voltage line VBL, the second portion L1-2 of the first voltage line L1 and the second portion L3-2 of the third voltage line L3 may be arranged on the same layer.

[0235] The second portion P1-2 of the first voltage line L1 may be disposed on the fifth insulating layer 50. The second portion P1-2 may extend in the first direction DR1.

[0236] The second portion P1 - 2 may be electrically connected to the first portion P1 - 1 of the first voltage line L1 through the contact hole CNTb.

[0237] The second portion P1-2 may be provided in plurality, and the plurality of second portions P1-2 may be arranged in the second direction DR2.

[0238] The plurality of scan lines GCL1 and GCL2 may be disposed on the fifth insulating layer 50. Each of the plurality of scan lines GCL1 and GCL2 may extend in the first direction DR1. The plurality of scan lines GCL1 and GCL2 may be arranged in the second direction DR2.

[0239] A plurality of light emitting control lines EML1 and EML2 may be disposed on the fifth insulating layer 50. Each of the plurality of light emitting control lines EML1 and EML2 may extend in the first direction DR1. The plurality of light emitting control lines EML1 and EML2 may be arranged in the second direction DR2.

[0240] The bias voltage line VBL may be disposed on the fifth insulating layer 50. The bias voltage line VBL may extend in the first direction.

[0241] The second portion L3-2 of the third voltage line L3 may be disposed on the fifth insulating layer 50. The second portion P3-2 may extend in the first direction DR1.

[0242] The second portion P3 - 2 may be electrically connected to the first portion L3 - 1 of the third voltage line L3 through the contact hole CNTc.

[0243] The second portion P3-2 may be provided in plurality, and the plurality of second portions P3-2 may be arranged in the second direction DR2.

[0244] That is, the second portion L1 - 2 of the first voltage line L1 and the second portion L2 - 2 of the second voltage line L2 may be disposed at different layers.

[0245] The second portion L1 - 2 of the first voltage line L1 and the second portion L3 - 2 of the third voltage line L3 may be disposed on the same layer.

[0246] Fig. 9 FIG. 1 is a top view showing one layer of a display panel according to an embodiment of the present invention.

[0247] Reference Figure 2 , Figure 6 as well as Fig. 9 The third layer LY3 may be a layer disposed on the sixth insulating layer 60 and covered by the seventh insulating layer 70 .

[0248] The first portion P1-1 of the first voltage line L1, the second data line DL2, the third data line DL3, the first portion P2-1 of the second voltage line L2, the first portion P3-1 of the third voltage line L3, the fourth data line DL4 and the fifth data line DL5 may be disposed on the same layer.

[0249] The first portion P1-1 of the first voltage line L1 may be disposed on the sixth insulating layer 60. The first portion P1-1 may extend in a second direction DR2 crossing the first direction DR1.

[0250] The first portion P1-1 may be provided in plurality. The plurality of first portions P1-1 may be arranged in the first direction DR1.

[0251] When viewed from a plane, the contact hole CNTd of the third layer LY3 can be aligned with the second layer LY2 (see Figure 8 ) of the contact hole CNTb (refer to Figure 8 )overlapping.

[0252] The first portion P1 - 1 may be electrically connected to the second portion P1 - 2 through the contact hole CNTd.

[0253] The second data line DL2 may be disposed on the sixth insulating layer 60. The second data line DL2 may extend in the second direction DR2. The second data line DL2 may be spaced apart from the first portion P1-1 in the first direction DR1.

[0254] The third data line DL3 may be disposed on the sixth insulating layer 60. The third data line DL3 may extend in the second direction DR2. The third data line DL3 may be spaced apart from the second data line DL2 in the first direction DR1.

[0255] The first portion P2-1 of the second voltage line L2 may be disposed on the sixth insulating layer 60. The first portion P2-1 may extend in the second direction DR2.

[0256] The first portion P2 - 1 may be provided in plurality, and the plurality of first portions P2 - 1 may be arranged in the first direction DR1 .

[0257] When viewed from a plane, the contact hole CNTe of the third layer LY3 may be aligned with the first layer LY1 (refer to Figure 7 ) overlaps with the contact hole CNTa.

[0258] The first portion P2 - 1 may be electrically connected to the second portion P2 - 2 through the contact hole CNTe.

[0259] The first portion P3-2 of the third voltage line L3 may be disposed on the sixth insulating layer 60. The first portion P3-1 may extend in the second direction DR2.

[0260] The first portion P3 - 1 may be provided in plurality, and the plurality of first portions P3 - 1 may be arranged in the first direction DR1 .

[0261] When viewed from a plane, the contact hole CNTf of the third layer LY3 can be aligned with the second layer LY2 (see Figure 8 ) contact hole CNTc (refer to Figure 8 )overlapping.

[0262] The first portion P3 - 1 may be electrically connected to the second portion P3 - 2 through the contact hole CNTf.

[0263] The fourth data line DL4 may be disposed on the sixth insulating layer 60. The fourth data line DL4 may extend in the second direction DR2. The fourth data line DL4 may be spaced apart from the first portion P3-1 in the first direction DR1.

[0264] The fifth data line DL5 may be disposed on the sixth insulating layer 60. The fifth data line DL5 may extend in the second direction DR2. The fifth data line DL5 may be spaced apart from the fourth data line DL4 in the first direction DR1.

[0265] That is, the first part L1-1 of the first voltage line L1, the first part L2-1 of the second voltage line L2, and the first part L3-1 of the third voltage line L3 can be configured in different layers with the second part L1-2 of the first voltage line L1, the second part L2-2 of the second voltage line L2, and the second part L3-2 of the third voltage line L3.

[0266] However, this is merely illustrative, and the first to third layers LY1 , ​​LY2 , and LY3 of one embodiment of the present invention are not limited to the layers in which they are arranged, as long as they satisfy the characteristic of being arranged in different layers.

[0267] Fig.10 The following is an exemplary diagram showing a part of the structure of a display panel according to an embodiment of the present invention. Fig.10 During the explanation, Figure 2 The constituent elements described are given the same reference numerals, and description thereof will be omitted.

[0268] Reference Fig.10 , the display panel DPa may include: a plurality of first sub-pixels PXRa, a plurality of second sub-pixels PXGa, a plurality of third sub-pixels PXBa, a first voltage line L1a, a second voltage line L2a, and a third voltage line L3a.

[0269] Each of the plurality of first sub-pixels PXRa may be electrically connected to the first voltage line L1 a .

[0270] The first voltage line L1a may provide a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ).

[0271] The first voltage line L1a may include a 1-1 portion P1-1a and a 1-2 portion P1-2a. The 1-1 portion P1-1a may extend in the second direction DR2. The 1-1 portion P1-1a may be adjacent to a plurality of first sub-pixels PXRa in the first direction DR1. The 1-2 portion P1-2a may extend in the first direction DR1. The 1-2 portion P1-2a may be electrically connected to the 1-1 portion P1-1a. When viewed from a plane, the first voltage line L1a may have a mesh shape.

[0272] The 1-1 portion P1-1a and the 1-2 portion P1-2a may be disposed in different layers. The 1-1 portion P1-1a and the 1-2 portion P1-2a may be electrically connected to each other through the contact hole CNT.

[0273] Each of the plurality of second sub-pixels PXGa may be electrically connected to the second voltage line L2 a .

[0274] The second voltage line L2a can provide a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ).

[0275] The second voltage line L2a may include a 2-1 portion P2-1a and a 2-2 portion P2-2a. The 2-1 portion P2-1a may extend in the second direction DR2. The 2-1 portion P2-1a may be adjacent to a plurality of second sub-pixels PXGa in the first direction DR1. The 2-2 portion P2-2a may extend in the first direction DR1. The 2-2 portion P2-2a may be electrically connected to the 2-1 portion P2-1a. When viewed from a plane, the second voltage line L2a may have a mesh shape.

[0276] The 2-1 portion P2-1a and the 2-2 portion P2-2a may be disposed in different layers. The 2-1 portion P2-1a and the 2-2 portion P2-2a may be electrically connected to each other through the contact hole CNT.

[0277] Each of the plurality of third sub-pixels PXBa may be electrically connected to the third voltage line L3 a .

[0278] The third voltage line L3a can provide a first initialization voltage Vint (refer to Figure 1 ) or the second initialization voltage Vaint (refer to Figure 1 ).

[0279] The third voltage line L3a may include a 3-1 portion P3-1a and a 3-2 portion P3-2a. The 3-1 portion P3-1a may extend in the second direction DR2. The 3-1 portion P3-1a may be adjacent to a plurality of third sub-pixels PXBa in the first direction DR1. The 3-2 portion P3-2a may extend in the first direction DR1. The 3-2 portion P3-2a may be electrically connected to the 3-1 portion P3-1a. When viewed from a plane, the third voltage line L3a may have a mesh shape.

[0280] The 3-1 portion P3-1a and the 3-2 portion P3-2a may be disposed in different layers. The 3-1 portion P3-1a and the 3-2 portion P3-2a may be electrically connected to each other through the contact hole CNT.

[0281] According to the present invention, the first to third voltage lines L1a, L2a, L3a may have a mesh structure. Therefore, compared with the conventional voltage lines extending in the second direction DR2, the first to third voltage lines L1a, L2a, L3a may further include second portions P1-2a, P2-2a, P3-2a extending in the first direction DR1. Figure 1 ) can increase the wiring area and reduce the resistance. As the first to third voltage lines L1a, L2a, L3a transmit the initialization voltages Vint, Vaint (refer to Figure 1 ), the load (Load) applied to the first to third voltage lines L1a, L2a, L3a can be reduced. As a result, the voltage drop phenomenon may be reduced or eliminated. Therefore, a display device DD with improved reliability and improved power consumption can be provided (refer to Figure 1 ).

[0282] Furthermore, unlike the present invention, the initialization voltages Vint and Vaint (see Figure 1 ), when driving the first to third sub-pixels PXRa, PXGa, PXBa, the common wiring can be used as a charge movement channel. Horizontal leakage current may occur through the common wiring, so that in the drive of a certain sub-pixel, the charge flows to another adjacent sub-pixel. However, according to the present invention, the first to third voltage lines L1a, L2a, L3a can be connected to the first to third sub-pixels PXRa, PXGa, PXBa, respectively. Thereby, the phenomenon that the charge flows to other adjacent sub-pixels in the drive of a certain sub-pixel can be prevented or eliminated. The color difference or color contrast that may occur due to the horizontal leakage current can be prevented or eliminated. Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0283] According to the present invention, when viewed from a plane, the second portions P1-2a, P2-2a, and P3-2a may be spaced apart from each other in the second direction DR2. Figure 1 ) may be disposed between two pixels adjacent to each other in the second direction DR2. Figure 1 ) can achieve high pixel density (PPI: Pixels Per Inch). Therefore, a display device DD with improved display quality can be provided (refer to Figure 1 ).

[0284] Although the above description is made with reference to the preferred embodiments of the present invention, it is understood by a person skilled in the art or a person of ordinary skill in the art that various modifications and changes may be made to the present invention without departing from the scope of the concept and technical field of the present invention as described in the attached claims. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the attached claims.

Claims

1. A display device, in, include: The first data line and the second data line extend in a first direction respectively. The first voltage line and the second voltage line are provided with different initialization voltages, and Multiple pixels; The plurality of pixels comprises: a first sub-pixel, electrically connected to the first data line and the first voltage line, and comprising a first pixel circuit and a first light emitting element, and a second sub-pixel, adjacent to the first sub-pixel, electrically connected to the second data line and the second voltage line, and comprising a second pixel circuit and a second light emitting element; The first voltage line includes a 1-1 portion extending in the first direction and a 1-2 portion electrically connected to the 1-1 portion and extending in a second direction intersecting the first direction. The second voltage line includes a 2-1 portion extending in the first direction and a 2-2 portion electrically connected to the 2-1 portion and extending in the second direction.

2. The display device according to claim 1, wherein: The 1-1 part and the 2-1 part are arranged on the same layer, The 1-1 part and the 1-2 part are arranged in different layers.

3. The display device according to claim 1, wherein: The first data line, the second data line, the 1-1 portion, and the 2-1 portion are arranged in the same layer.

4. The display device according to claim 1, wherein: The first pixel circuit includes a 1-1th initialization transistor connected between the first voltage line and the first light emitting element, The second pixel circuit includes a 1-2th initialization transistor connected between the second voltage line and the second light emitting element.

5. The display device according to claim 1, wherein: The first pixel circuit includes a first driving transistor and a 2-1st initialization transistor connected between a gate electrode of the first driving transistor and the first voltage line. The second pixel circuit includes a second driving transistor and a 2-2 th initialization transistor connected between a gate electrode of the second driving transistor and the second voltage line.

6. The display device according to claim 1, wherein: further comprising a third data line and a third voltage line provided with a voltage different from the first voltage line and the second voltage line, The plurality of pixels further include a third sub-pixel, the third sub-pixel being adjacent to the second sub-pixel and including a third pixel circuit and a third light emitting element, The third sub-pixel is electrically connected to the third voltage line.

7. The display device according to claim 6, wherein: The third voltage line comprises: Part 3-1, extending in the first direction; and Part 3-2 is electrically connected to the part 3-1 and extends toward the second direction.

8. The display device according to claim 6, wherein: The first to third data lines are provided with color data different from each other.

9. The display device according to claim 1, wherein: A plurality of the first pixel circuits and the second pixel circuits are provided, A plurality of the first pixel circuits are arranged along the first direction, A plurality of the second pixel circuits are arranged along the first direction, The plurality of first pixel circuits and the plurality of second pixel circuits are spaced apart from each other in the second direction.

10. The display device according to claim 9, wherein: A plurality of the first light emitting elements are provided, The plurality of first light emitting elements are electrically connected to the plurality of first pixel circuits respectively. When viewed from a plane, a portion of the plurality of first light-emitting elements overlaps with the corresponding first pixel circuit. When viewed from the plane, the remaining light emitting elements among the plurality of the first light emitting elements do not overlap with the corresponding first pixel circuits.

11. The display device according to claim 1, wherein: When viewed from a plane, the second data line overlaps with the first light emitting element and does not overlap with the second light emitting element.

12. The display device according to claim 1, wherein: The first data line and the second data line are spaced apart in the second direction.

13. The display device according to claim 6, wherein: When viewed from a plane, the first voltage line, the second voltage line, and the third voltage line each have a mesh structure.

14. A display device, in, include: A data line extending in a first direction, voltage line, providing an initialization voltage, and A pixel, electrically connected to the data line and the voltage line; The pixel includes a pixel circuit and a light emitting element. The voltage line comprises: a first portion extending in the first direction, and a second portion electrically connected to the first portion and extending in a second direction intersecting the first direction; The first part and the second part are arranged on different layers, The data line and the first portion are configured on the same layer.

15. The display device according to claim 14, wherein: The pixel circuit comprises: A first initialization transistor is connected between the voltage line and the light emitting element.

16. The display device according to claim 14, wherein: The pixel circuit comprises: a driver transistor; and The second initialization transistor is connected between the gate electrode of the driving transistor and the voltage line.

17. The display device according to claim 14, wherein: A plurality of pixel circuits are provided, The plurality of pixel circuits are arranged along the first direction.

18. The display device according to claim 14, wherein: A plurality of the light emitting elements are provided, The plurality of light emitting elements are electrically connected to the plurality of pixel circuits, respectively.

19. The display device according to claim 18, wherein: When viewed from a plane, a portion of the plurality of light emitting elements overlaps with corresponding pixel circuits.

20. The display device according to claim 19, wherein: When viewed from the plane, the remaining light-emitting elements among the plurality of light-emitting elements do not overlap with the corresponding pixel circuits.

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