Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises: a substrate; the multiple light-emitting elements are located in the first display area and the second display area and comprise multiple sets of light-emitting elements, the light-emitting elements in each set of the multiple sets of light-emitting elements are arranged in the first direction, the multiple sets of light-emitting elements are arranged in the second direction, and at least one set of the multiple sets of light-emitting elements comprises multiple first area light-emitting elements and multiple second area light-emitting elements; the plurality of pixel circuits comprise a plurality of groups of pixel circuits, the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along a first direction, the plurality of groups of pixel circuits are arranged along a second direction, and at least one group of the plurality of groups of pixel circuits comprises a plurality of pixel circuits of a first type and a plurality of pixel circuits of a second type; among the at least one group of light emitting elements and the at least one group of pixel circuits, a plurality of first pixel circuits connected to the plurality of first light emitting elements are closer to the second display area than each of a plurality of second pixel circuits connected to the plurality of second light emitting elements.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application is a divisional application with application date of March 12, 2021 and application number 202180000474.4. The patent application with application number 202180000474.4 is an application entering the Chinese national phase of PCT patent application No. PCT / CN2021 / 080494 filed on March 12, 2021. The application entering the Chinese national phase claims priority to PCT patent application No. PCT / CN2020 / 119673 filed on September 30, 2020. The contents disclosed in the above-mentioned PCT patent application are hereby quoted in full as part of this application. Technical Field

[0003] At least one embodiment of the present disclosure relates to a display panel and a display device. Background Art

[0004] With the continuous development of display technology, active-matrix organic light-emitting diode (AMOLED) display technology has been increasingly used in display devices such as mobile phones, tablet computers, digital cameras, etc. due to its advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed.

[0005] The under-screen camera technology is a new technology proposed to increase the screen-to-body ratio of display devices. Summary of the invention

[0006] At least one embodiment of the present disclosure relates to a display panel and a display device.

[0007] At least one embodiment of the present disclosure provides a display panel, comprising: a substrate, having a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; a plurality of light-emitting elements, located in the first display area and the second display area, wherein the plurality of light-emitting elements include a plurality of groups of light-emitting elements, wherein the light-emitting elements in each group of the plurality of groups of light-emitting elements are arranged along a first direction, wherein the plurality of groups of light-emitting elements are arranged along a second direction, wherein at least one group of the plurality of groups of light-emitting elements includes a plurality of first-region light-emitting elements and a plurality of second-region light-emitting elements, wherein the plurality of first-region light-emitting elements are located in the first display area, and wherein the plurality of second-region light-emitting elements are located in the second display area; a plurality of pixel circuits, located in the first display area, wherein the plurality of pixel circuits include a plurality of groups of pixel circuits, wherein the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along the first direction, wherein the plurality of groups of pixel circuits are arranged along the second direction, wherein at least one group of the plurality of groups of pixel circuits includes a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, wherein the plurality of second-type pixel circuits are distributed between the plurality of first-type pixel circuits at intervals; and At least one first-region light-emitting element is connected, and the orthographic projection of the at least one first-type pixel circuit on the substrate substrate at least partially overlaps with the orthographic projection of the at least one first-region light-emitting element on the substrate substrate; at least one second-type pixel circuit among the plurality of second-type pixel circuits is connected to at least one second-region light-emitting element among the plurality of second-region light-emitting elements through a conductive line; the plurality of second-region light-emitting elements include a plurality of first light-emitting elements and a plurality of second light-emitting elements, the first light-emitting elements are configured to emit a first color light, the second light-emitting elements are configured to emit a second color light, the plurality of second-type pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits, the conductive lines include a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first light-emitting elements are connected to the plurality of first pixel circuits through the plurality of first conductive lines, the plurality of second light-emitting elements are connected to the plurality of second pixel circuits through the plurality of second conductive lines, and in the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first light-emitting elements are closer to the second display area than each of the plurality of second pixel circuits connected to the plurality of second light-emitting elements.

[0008] For example, in the at least one group of light-emitting elements and the at least one group of pixel circuits, no other second-type pixel circuits are arranged between two first pixel circuits connected to two adjacent first conductive lines.

[0009] For example, one end of the conductive line is connected to the second-region light-emitting element, and the other end of the conductive line is connected to the second-type pixel circuit through a connecting element.

[0010] For example, in the at least one group of light emitting elements and the at least one group of pixel circuits, at least one of the plurality of first-type pixel circuits is disposed between two adjacent second-type pixel circuits.

[0011] For example, in the at least one group of light-emitting elements and the at least one group of pixel circuits, the multiple first pixel circuits connected to the multiple first conductive lines are arranged at intervals among the multiple first-type pixel circuits, and the multiple second pixel circuits connected to the multiple second conductive lines are arranged at intervals among the multiple first-type pixel circuits.

[0012] For example, the orthographic projection of a portion of one of the plurality of first conductive lines extending along the first direction on the substrate substrate at least partially overlaps with the orthographic projection of a portion of another first conductive line of a different layer from the first conductive line extending along the first direction on the substrate substrate, or the orthographic projection of a portion of one of the plurality of first conductive lines extending along the first direction on the substrate substrate at least partially overlaps with the orthographic projection of a portion of one of the plurality of fourth conductive lines of a different layer from the first conductive line extending along the first direction on the substrate substrate.

[0013] For example, the multiple second-area light-emitting elements also include multiple third light-emitting elements, and the third light-emitting elements are configured to emit a third color light. The multiple second-type pixel circuits also include multiple third pixel circuits. The conductive wires also include multiple third conductive wires. The multiple third light-emitting elements are connected to the multiple third pixel circuits through the multiple third conductive wires. Among the at least one group of light-emitting elements and the at least one group of pixel circuits, the multiple first pixel circuits connected to the multiple first conductive wires are closer to the second display area than each of the multiple third pixel circuits connected to the multiple third conductive wires.

[0014] For example, in the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of second pixel circuits connected to the plurality of second conductive lines and the plurality of third pixel circuits connected to the plurality of third conductive lines are alternately arranged.

[0015] For example, the multiple second-area light-emitting elements also include multiple fourth light-emitting elements, and the fourth light-emitting elements are configured to emit a fourth color light. The multiple second-type pixel circuits also include multiple fourth pixel circuits. The conductive wires also include multiple fourth conductive wires. The multiple fourth light-emitting elements are connected to the multiple fourth pixel circuits through the multiple fourth conductive wires. Among the at least one group of light-emitting elements and the at least one group of pixel circuits, the multiple fourth pixel circuits connected to the multiple fourth conductive wires are closer to the second display area than each of the multiple second pixel circuits connected to the multiple second conductive wires.

[0016] For example, the plurality of fourth pixel circuits connected to the plurality of fourth conductive lines and the plurality of first pixel circuits connected to the plurality of first conductive lines are alternately arranged.

[0017] For example, the orthographic projection of a portion of one of the plurality of second conductive lines extending along the first direction on the substrate at least partially overlaps with the orthographic projection of a portion of one of the plurality of third conductive lines of a different layer from the second conductive line extending along the first direction on the substrate.

[0018] For example, at least one of the multiple groups of light-emitting elements includes a first subgroup of light-emitting elements, a second subgroup of light-emitting elements, and a third subgroup of light-emitting elements sequentially arranged along the first direction, at least one of the multiple groups of pixel circuits includes a first subgroup of pixel circuits to a seventh subgroup of pixel circuits sequentially arranged along the first direction, the seventh subgroup of pixel circuits is closer to the second display area than the first subgroup of pixel circuits, the conductive lines connected to the first subgroup of light-emitting elements are located in the third pattern layer, the conductive lines connected to the second subgroup of light-emitting elements are located in the second pattern layer, the conductive lines connected to the third subgroup of light-emitting elements include conductive lines located in the first pattern layer and also include conductive lines formed in segments, the conductive lines formed in segments include a first conductive portion located in the first pattern layer and a second conductive portion located in the second pattern layer, the second light-emitting elements in the first subgroup of light-emitting elements and the The third light-emitting element is connected to the second sub-group pixel circuit, the second light-emitting element and the third light-emitting element in the second sub-group light-emitting elements are connected to the first sub-group pixel circuit, the second light-emitting element and the third light-emitting element close to the second sub-group light-emitting element in the third sub-group light-emitting elements are connected to the fourth sub-group pixel circuit, the second light-emitting element and the third light-emitting element far from the second sub-group light-emitting element in the third sub-group light-emitting elements are connected to the fifth sub-group pixel circuit, the first light-emitting element and the fourth light-emitting element in the first sub-group light-emitting elements are connected to the seventh sub-group pixel circuit, the first light-emitting element and the fourth light-emitting element in the second sub-group light-emitting elements are connected to the sixth sub-group pixel circuit, and the first light-emitting element and the fourth light-emitting element in the third sub-group light-emitting elements are connected to the third sub-group pixel circuit.

[0019] For example, an orthographic projection of a portion of the second conductive line extending along the first direction on the substrate at least partially overlaps with an orthographic projection of a portion of a third conductive line located in a different layer from the second conductive line extending along the first direction on the substrate.

[0020] For example, a portion of the conductive line connected to the second subset of light emitting elements extending along the first direction does not overlap with a portion of other conductive lines extending along the first direction.

[0021] For example, the portion of the conductive line connected to the second sub-group pixel circuit extending along the first direction overlaps with the portion of the conductive line connected to the fourth sub-group pixel circuit extending along the first direction, and the portion of the conductive line connected to the first sub-group pixel circuit extending along the first direction does not overlap with the portion of the conductive line connected to the second sub-group pixel circuit extending along the first direction, and does not overlap with the portion of the conductive line connected to the fourth sub-group pixel circuit extending along the first direction.

[0022] For example, the fourth light emitting element and the first light emitting element are configured to emit light of the same color.

[0023] For example, the fourth light-emitting element and the first light-emitting element are configured to emit green light, the second light-emitting element and one of the third light-emitting elements are configured to emit red light, and the other of the second light-emitting element and the third light-emitting element is configured to emit blue light.

[0024] For example, at least one of the first conductive lines, the second conductive lines, the third conductive lines, and the fourth conductive lines is formed entirely of one conductive line or is formed of conductive parts located in different layers.

[0025] For example, at least one of the first conductive line, the second conductive line, the third conductive line, and the fourth conductive line is made of a transparent conductive material.

[0026] For example, the second display area is axisymmetric, having a first symmetry axis extending along the first direction and a second symmetry axis extending along the second direction, and the conductive lines are arranged in a plurality, and the plurality of conductive lines are axisymmetric with respect to the first symmetry axis and axisymmetric with respect to the second symmetry axis.

[0027] For example, the plurality of second-region light-emitting elements are axisymmetric with respect to the first symmetry axis and are axisymmetric with respect to the second symmetry axis.

[0028] For example, the first display area includes an auxiliary area, the plurality of second-type pixel circuits are located in the auxiliary area, and an area of ​​the auxiliary area is smaller than an area of ​​a region of the first display area excluding the auxiliary area.

[0029] For example, a size of the first type of pixel circuit in the first direction is smaller than a size of the first area light emitting element in the first direction.

[0030] For example, in the auxiliary area, an orthographic projection of the conductive line on the base substrate partially overlaps with an orthographic projection of the first type of pixel circuit on the base substrate.

[0031] For example, the light-emitting area of ​​the light-emitting elements in the first area is larger than the light-emitting area of ​​the light-emitting elements in the second area, the second display area includes a light-transmitting area, the resolution of the first display area is the same as the resolution of the second display area, and the density of the light-emitting elements in the first area is the same as the density of the light-emitting elements in the second area.

[0032] For example, the pixel circuit includes a driving transistor and a reset transistor, the display panel also includes a reset control signal line, the gate of the reset transistor is connected to the reset control signal line, the first electrode of the reset transistor is connected to the initialization signal line, the second electrode of the reset transistor is connected to the first electrode of the light-emitting element, and the initialization signal line is configured to provide a constant voltage, and the constant voltage is greater than or equal to -2V.

[0033] At least one embodiment of the present disclosure further provides a display device, comprising any one of the above-mentioned display panels.

[0034] For example, the display device further includes a photosensor, and the photosensor is located on one side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0036] Figure 1A It is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0037] Figure 1B It is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0038] Figure 2 is a schematic diagram of a pixel unit of a display panel provided in one embodiment of the present disclosure.

[0039] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.

[0040] Figure 4 A schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure.

[0041] FIG. 5A to FIG. 5C A partial plan view of a display panel provided according to an embodiment of the present disclosure.

[0042] FIG. 5D to FIG. 5F is a schematic diagram of the structure of a display panel provided in some embodiments of the present disclosure.

[0043] Fig. 6A The present invention is a schematic diagram of a row of light-emitting elements located in a second display area of ​​a display panel and a second type of pixel circuit connected thereto.

[0044] Figure 6B A schematic diagram of the capacitance of a conductive line in a display panel.

[0045] Figure 6C A schematic diagram of a display defect of a display panel.

[0046] FIG. 6D to FIG. 6F They are schematic diagrams of poor display at low grayscale.

[0047] Fig. 7A A schematic diagram of a row of light-emitting elements located in a second display area of ​​a display panel and a second type of pixel circuit connected thereto is provided in an embodiment of the present disclosure.

[0048] Figure 7B A schematic diagram of the capacitance of light-emitting elements emitting light of different colors in the same row of light-emitting elements in a second display area of ​​a display panel provided by an embodiment of the present disclosure.

[0049] Figure 7C A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0050] Fig. 8A A schematic diagram of a light-emitting element located in a second display area and a second type of pixel circuit connected thereto in a display panel provided in one embodiment of the present disclosure.

[0051] Figure 8B for Fig. 8A Schematic diagram of the first conductive line and the fourth conductive line in FIG.

[0052] Figure 8C for Fig. 8A Schematic diagram of the second conductive line in .

[0053] Fig.8D for Fig. 8A Schematic diagram of the third conductive line in .

[0054] Fig. 8E A schematic diagram of a row of light-emitting elements of a display panel provided in accordance with another embodiment of the present disclosure.

[0055] Fig.9A A schematic diagram of another display panel provided according to an embodiment of the present disclosure.

[0056] Fig. 9B A schematic diagram of a display panel provided according to another embodiment of the present disclosure.

[0057] FIG. 10A to FIG. 10E A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0058] Fig.10F A schematic diagram of connection elements in a column of second-type pixel circuits in a display panel provided according to an embodiment of the present disclosure.

[0059] Figure 10GA schematic diagram of a conductive line connected to a column of second-region light-emitting elements in a display panel provided by an embodiment of the present disclosure.

[0060] Fig. 10H A schematic diagram of connection elements in a column of second-type pixel circuits in a display panel provided according to an embodiment of the present disclosure.

[0061] Fig.11 A schematic diagram of a display panel provided according to an embodiment of the present disclosure.

[0062] Fig. 12A Detailed description of the invention The invention is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.

[0063] Fig. 12B It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure.

[0064] Fig. 12C for Fig. 12B A cross-sectional view along line AB.

[0065] Fig.12D It is a layout diagram of a pixel circuit in a display panel provided by another embodiment of the present disclosure.

[0066] Fig.12E It is a layout diagram of a pixel circuit in a display panel provided by another embodiment of the present disclosure.

[0067] Fig.13A and Fig. 13B A schematic diagram of a display device provided in accordance with an embodiment of the present disclosure.

[0068] Fig.14 for Fig. 12A The working timing diagram of the pixel circuit shown.

[0069] Fig.15 A schematic structural diagram of a display panel provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0071] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0072] With the development of display technology, the existing notch screen or water drop screen design is gradually unable to meet the user's demand for a high screen-to-body ratio of display panels, and a series of display panels with a light-transmitting display area have emerged. In this type of display panel, hardware such as light sensors (such as cameras) can be set in the light-transmitting display area. Since there is no need to punch holes, a true full screen becomes possible while ensuring the practicality of the display panel.

[0073] In the related art, a display panel with an under-screen camera generally includes a first display area for normal display and a second display area for setting the camera. The second display area generally includes: a plurality of light-emitting elements and a plurality of pixel circuits, each pixel circuit is connected to a light-emitting element and is used to drive the light-emitting element to emit light, and the interconnected pixel circuits and light-emitting elements overlap in a direction perpendicular to the display panel.

[0074] Since a pixel circuit is also disposed in the second display area in the related art, the light transmittance of the second display area is poor, and accordingly, the display effect of the display panel is poor.

[0075] Figure 1A It is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 1B is a schematic diagram of the structure of a display panel provided by an embodiment of the present disclosure. Figure 1A and Figure 1BAs shown, the display panel may include: a substrate BS. The display panel includes a first display area R1 and a second display area R2, and the first display area R1 may be located on at least one side of the second display area R2. For example, in some embodiments, the first display area R1 surrounds the second display area R2. That is, the second display area R2 may be surrounded by the first display area R1. The second display area R2 may also be set at other positions, and the setting position of the second display area R2 may be determined as required. For example, the second display area R2 may be located at the top center of the substrate BS, or at the upper left corner or upper right corner of the substrate BS. For example, hardware such as a photosensitive sensor (such as a camera) is set in the second display area R2 of the display panel. For example, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area. For example, the first display area R1 is opaque and is only used for display. Figure 1B It is shown that the first display area R1 includes the auxiliary area Ra.

[0076] Figure 2 FIG. 1 is a schematic diagram of a pixel unit of a display panel provided by an embodiment of the present disclosure. The display panel includes a pixel unit 100, and the pixel unit 100 is located on a substrate. Figure 2 As shown, the pixel unit 100 includes a pixel circuit 100a and a light emitting element 100b, and the pixel circuit 100a is configured to drive the light emitting element 100b. For example, the pixel circuit 100a is configured to provide a driving current to drive the light emitting element 100b to emit light. For example, the light emitting element 100b is an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light under the drive of its corresponding pixel circuit 100a. The color of the light emitted by the light emitting element 100b can be determined as required.

[0077] In order to improve the light transmittance of the second display area R2, only a light emitting element may be provided in the second display area R2, and a pixel circuit driving the light emitting element of the second display area R2 may be provided in the first display area R1. That is, the light transmittance of the second display area R2 is improved by separately providing the light emitting element and the pixel circuit. That is, the pixel circuit 100a is not provided in the second display area R2.

[0078] Figure 3 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel includes: a plurality of first-type pixel circuits 10, a plurality of second-type pixel circuits 20 and a plurality of first-region light-emitting elements 30 located in the first display area R1, and a plurality of second-region light-emitting elements 40 located in the second display area R2. For example, the plurality of second-type pixel circuits 20 may be distributed between the plurality of first-type pixel circuits 10 at intervals.

[0079] For example, Figure 3As shown, at least one first-type pixel circuit 10 among the plurality of first-type pixel circuits 10 may be connected to at least one first-region light-emitting element 30 among the plurality of first-region light-emitting elements 30, and the orthographic projection of at least one first-type pixel circuit 10 on the substrate BS may at least partially overlap with the orthographic projection of at least one first-region light-emitting element 30 on the substrate BS. The at least one first-type pixel circuit 10 may be used to provide a driving signal to the connected first-region light-emitting element 30 to drive the first-region light-emitting element 30 to emit light.

[0080] For example, Figure 3 As shown, at least one second type of pixel circuit 20 among the plurality of second type pixel circuits 20 can be connected to at least one second area light emitting element 40 among the plurality of second area light emitting elements 40 through a conductive line L1, and the at least one second type of pixel circuit 20 can be used to provide a driving signal to the connected second area light emitting element 40 to drive the second area light emitting element 40 to emit light. Figure 3 As shown, since the second-region light-emitting element 40 and the second-type pixel circuit 20 are located in different regions, the orthographic projection of at least one second-type pixel circuit 20 on the substrate BS does not overlap with the orthographic projection of at least one second-region light-emitting element 40 on the substrate BS.

[0081] For example, in the embodiment of the present disclosure, the first display area R1 can be set as a non-light-transmitting display area, and the second display area R2 can be set as a light-transmitting display area. For example, the first display area R1 is not light-transmitting, and the second display area R2 is light-transmitting. In this way, the display panel provided by the embodiment of the present disclosure does not need to be processed by digging holes on the display panel, and the required hardware structures such as the photosensitive sensor can be directly set at the position corresponding to the second display area R2 on one side of the display panel, laying a solid foundation for the realization of a true full screen. In addition, since the second display area R2 only includes light-emitting elements but not pixel circuits, it is beneficial to improve the transmittance of the second display area R2, so that the display panel has a better display effect.

[0082] like Figure 3As shown, the pixel unit 100 includes a first pixel unit 101 and a second pixel unit 102, the pixel circuit 100a and the light-emitting element 100b of the first pixel unit 101 are both located in the first display area R1, the pixel circuit 100a of the second pixel unit 101 is located in the first display area R1, and the light-emitting element 100b of the second pixel unit 102 is located in the second display area R2. In the embodiment of the present disclosure, the pixel circuit 100a of the first pixel unit 101 is a first-type pixel circuit 10, the light-emitting element 100b of the first pixel unit 101 is a first-region light-emitting element 30, the pixel circuit 100a of the second pixel unit 101 is a second-type pixel circuit 20, and the light-emitting element 100b of the second pixel unit 102 is a second-region light-emitting element 40. For example, the first-region light-emitting element 30 can be referred to as an in-situ light-emitting element. For example, the first-type pixel circuit 10 can be referred to as an in-situ pixel circuit, and the second-type pixel circuit 20 can be referred to as a non-in-situ pixel circuit.

[0083] For example, Figure 3 As shown, the second region light emitting element 40 and the second type of pixel circuit 20 connected to the second region light emitting element 40 are located in the same row. That is, the light emitting signal of the second region light emitting element 40 comes from the second type of pixel circuit in the same row. For example, the pixel circuits of the pixel units in the same row are connected to the same gate line.

[0084] like Figure 3 As shown, the pixel circuit of the second pixel unit 102 (the second type of pixel circuit 20) is connected to the light-emitting element (the second region light-emitting element 40) of the second pixel unit 102 through the conductive line L1. For example, the conductive line L1 is made of a transparent conductive material. For example, the conductive line L1 is made of a conductive oxide material. For example, the conductive oxide material includes indium tin oxide (ITO), but is not limited thereto.

[0085] like Figure 3 As shown, one end of the conductive line L1 is connected to the second type pixel circuit 20, and the other end of the conductive line L1 is connected to the second area light emitting element 40. Figure 3 As shown, the conductive line L1 extends from the first display region R1 to the second display region R2.

[0086] like Figure 1B and Figure 3As shown, in some embodiments, the first display area R1 may include an auxiliary area Ra, and the auxiliary area Ra may be provided for a second type of pixel circuit 20 connected to the second area light-emitting element 40. For example, a plurality of dummy pixel circuits may be provided in an area other than the auxiliary area Ra of the first display area R1. The dummy pixel circuit is not connected to any light-emitting element. The provision of a dummy pixel circuit is beneficial to improving the uniformity of the components of each film layer in the etching process. For example, the dummy pixel circuit has the same structure as the second type of pixel circuit 20 in its row or column, except that it is not connected to any light-emitting element. For example, in the first display area R1, the auxiliary area Ra and the area (non-auxiliary area) of the first display area R1 other than the auxiliary area Ra have the same pixel density, or the same resolution, but is not limited thereto.

[0087] Figure 3 Three rows of light emitting elements 100b are shown. Figure 3 The light emitting elements 100 b in the first row shown pass through the first display area R1 and the second display area R2 , that is, a row of light emitting elements 100 b passes through two areas. Figure 3 The light emitting elements 100 b in the second row shown pass through the first display area R1 and the second display area R2 , that is, the light emitting elements 100 b in one row pass through two areas. Figure 3 The third row of light emitting elements 100b shown only passes through the first display area R1, but not the second display area R2, and is a row of light emitting elements 100b passing through one area. For example, in some embodiments, the light emitting elements 100b are divided into two types of rows of light emitting elements, that is, a row of light emitting elements passing through two areas and a row of light emitting elements passing through one area.

[0088] Figure 4 Schematic diagram of a first display area and a second display area in a display panel provided in an embodiment of the present disclosure. Figure 4 As shown, in the second display area R2, a light-transmitting area R0 is provided between adjacent second-region light-emitting elements 40. Figure 4 As shown, a plurality of light-transmitting regions R0 are connected to each other to form a continuous light-transmitting region separated by a plurality of second-region light-emitting elements 40. The conductive line L1 is made of a transparent conductive material to increase the light transmittance of the light-transmitting region R0 as much as possible. Figure 4 As shown, the second display region R2 except for the second region light emitting element 40 can be a light-transmitting region.

[0089] FIG. 5A to FIG. 5C This is a partial plan view of a display panel provided by an embodiment of the present disclosure. FIG. 5A to FIG. 5C Give a description.

[0090] Figure 5A Schematic diagram of a first display area and a second display area of ​​a display panel provided in one embodiment of the present disclosure. Figure 5A As shown, the second display area R2 is a light-transmitting display area, and the first display area R1 is a display area.

[0091] Figure 5B A schematic diagram of a first-region light-emitting element in a first display region and a second-region light-emitting element in a second display region of a display panel provided in one embodiment of the present disclosure. Figure 5B A first area light emitting element 30 and a second area light emitting element 40 are shown.

[0092] refer to Figure 5A , Figure 5B and Figure 3 In order to improve the display effect, the density of the second region light emitting elements 40 may be equal to the density of the first region light emitting elements 30. That is, the resolution of the second display region R2 is the same as the resolution of the first display region R1. Of course, in other embodiments, the density of the second region light emitting elements 40 may be greater than or less than the density of the first region light emitting elements 30. That is, the resolution of the second display region R2 may be greater than or less than the resolution of the first display region R1. For example, Figure 5B and Figure 4 As shown, the light emitting area of ​​the second region light emitting element 40 is smaller than the light emitting area of ​​the first region light emitting element 30. That is, the light emitting area of ​​the first region light emitting element 30 is larger than the light emitting area of ​​the second region light emitting element 40. Figure 4 The dotted lines show the light emitting area of ​​the second region light emitting element 40 and the light emitting area of ​​the first region light emitting element 30. For example, the light emitting area of ​​the light emitting element may correspond to the area of ​​the opening of the pixel definition layer.

[0093] Figure 5C The first region light emitting element 30, the second region light emitting element 40, the first type of pixel circuit 10, the second type of pixel circuit 20, the connecting element CE0, and the conductive line L1 are shown. Each pixel circuit is connected to the light emitting element through the connecting element CE0. That is, each pixel unit has a connecting element CE0. That is, the first type of pixel circuit 10 is connected to the first region light emitting element 30 through the connecting element CE0, and the second type of pixel circuit 20 is connected to the second region light emitting element 40 through the connecting element CE0.

[0094] For example, Figure 5CAs shown, one end of the conductive line L1 is connected to the second region light emitting element 40, and the other end of the conductive line L1 is connected to the second type of pixel circuit 20 through the connecting element CE0. For example, the connecting element CE0 is connected to the pixel circuit 100a and the light emitting element 100b respectively. For example, the connecting element CE0 is connected to the light emitting control transistor in the pixel circuit 100a and the first electrode of the light emitting element 100b respectively. For example, the connecting element CE0 can be formed by a single conductive component, or it can be formed by two different conductive components located in different layers. For example, the connecting element CE0 can include a conductive component located in one conductive layer and another conductive component located in another conductive layer.

[0095] like Figure 5C As shown, a conductive line L1 passes through the area where the pixel circuit of the pixel unit is located to respectively connect the second type of pixel circuit 20 and the second area light emitting element 40 on both sides of the pixel unit. For example, the area where the pixel circuit of the pixel unit is located overlaps with a plurality of conductive lines L1 passing through the area. The area where the second type of pixel circuit 20 is arranged in the first display area R1 can be called an auxiliary area Ra (such as Figure 1B and Figure 3 As shown), the auxiliary area Ra can also be called a transition area. Figure 5C Taking the example that a first type pixel circuit 10 overlaps with at most two conductive lines L1, in other embodiments, a first type pixel circuit 10 may also overlap with more conductive lines L1. For example, in some embodiments, a first type pixel circuit 10 may overlap with 10-15 conductive lines L1. The number of conductive lines L1 overlapped by a first type pixel circuit 10 may be determined as needed. Figure 5C As shown, the second type pixel circuit 20 may also overlap with the conductive line L1 that is not connected thereto.

[0096] In some embodiments, the size of the first type of pixel circuit 10 can be compressed in the first direction X to obtain an area for arranging the second type of pixel circuit 20. Figure 5C As shown, in the auxiliary area, a column of second type pixel circuits 20 is provided for every set column of first type pixel circuits 10. For example, the number of columns of first type pixel circuits 10 between two adjacent columns of second type pixel circuits 20 can be determined as required.

[0097] For example, in some embodiments, the area for setting the second type of pixel circuit 20 can be obtained by reducing the size of the first type of pixel circuit 10 in the first direction X. For example, the size of the first type of pixel circuit 10 in the first direction X is smaller than the size of the first area light emitting element 30 in the first direction X. The first direction X is, for example, a row direction, but is not limited thereto. In other embodiments, the first direction X may also be a column direction. The embodiments of the present disclosure are described by taking the first direction X as a row direction as an example.

[0098] FIG. 5D to FIG. 5F is a schematic diagram of the structure of a display panel provided by some embodiments of the present disclosure. In order to further reflect that after compressing the pixel circuit, there are more columns of pixel circuits, Figure 5D A schematic diagram of the structure of a first-region light-emitting element in the first display region R1 is shown. Figure 5E Shows Figure 5A Schematic diagram of part of the structure (including only the pixel circuit), Fig. 5F Shows Figure 5A Schematic diagram of part of the structure (including only the light-emitting element).

[0099] refer to FIG. 5D to FIG. 5F It can be seen that the width of the pixel circuit is smaller than the width of the light-emitting element. Thus, the pixel circuits in the second and ninth columns from the right to the left are not connected to any first-region light-emitting element 30, and belong to extra-column pixel circuits, which can be used as the second type of pixel circuit 20 to connect to the second-region light-emitting element 40 in the second display area R2. Fig. 5F As shown, the first region light emitting element 30 may include the first electrode E1 of four types of light emitting elements, RG1, B, and G2, and the first electrode E1 of the light emitting element is connected to the first type of pixel circuit 10 through the connecting element CE0. R represents a light emitting element that emits red light, G1 represents a light emitting element that emits green light, B represents a light emitting element that emits blue light, and G2 represents a light emitting element that emits green light. For example, the connecting element CE0 includes two connecting electrodes, which may be the connecting electrode CE01 mentioned later (such as Figure 5E or Fig. 12B as shown) and connecting electrode CE02 (as Fig. 5F or Fig. 12B For example, in order to have sufficient space for arranging the conductive line L1, the axes of the connection electrodes CE01 in the same row of pixel units may be located on a straight line.

[0100] Fig. 5F Four rows of connection elements CE0 / connection electrodes CE02 are shown, namely, Fig. 5FFour rows of light emitting elements are shown. For example, the light emitting elements in each row are arranged in sequence along the first direction X in the manner of RGBG or BGRG. Of course, the light emitting colors of the light emitting elements are not limited to RGB, and the arrangement of the light emitting elements is not limited to Fig. 5F As shown, the embodiments of the present disclosure are described by taking the light emitting elements including RGBG as an example. Fig. 5F As shown, G includes G1 or G2. For example, Fig. 5F In the pixel arrangement shown, a repeating unit RP includes two Gs arranged in the second direction Y and R and B arranged on both sides of the two Gs in the first direction X, wherein R and G constitute a pixel, and use B in another adjacent repeating unit to constitute a virtual pixel for display, and B and G constitute a pixel, and use R in another adjacent repeating unit to constitute a virtual pixel for display, but not limited to this.

[0101] refer to Figure 3 , Figure 4 , FIG. 5A to FIG. 5C The display panel provided by some embodiments of the present disclosure includes: a base substrate BS, a plurality of light emitting elements 100b, and a plurality of pixel circuits 100a. The base substrate BS has a first display area R1 and a second display area R2, and the first display area R1 is located at least on one side of the second display area R2. The plurality of light emitting elements 100b are arranged in a plurality of rows and a plurality of columns.

[0102] refer to Figure 3 , Figure 4 , Figure 5C and Fig. 5F The plurality of light emitting elements 100b include a plurality of groups of light emitting elements, the light emitting elements in each of the plurality of groups of light emitting elements are arranged along a first direction X, and the plurality of groups of light emitting elements are arranged along a second direction Y. Figure 3 and Figure 5C Three groups of light emitting elements GP are shown, which are respectively a group of light emitting elements GPx, a group of light emitting elements GPy and a group of light emitting elements GPz; one group of light emitting elements GPx and a group of light emitting elements GPy pass through the first display area R1 and the second display area R2, and a group of light emitting elements GPz only passes through the first display area R1. Figure 4 At least four groups of light emitting elements GP arranged in the second direction Y are shown. Fig. 5F At least four groups of light emitting elements GP are shown arranged in the second direction Y. In the display panel, the number of groups of light emitting elements passing through the first display area R1 and the second display area R2 and the number of groups of light emitting elements passing through only the first display area R1 can be determined as required.

[0103] For example, in some embodiments, a group of light emitting elements may be a row of light emitting elements. Of course, a group of light emitting elements may not completely correspond to a column of light emitting elements. In other embodiments, a group of light emitting elements may be a column of light emitting elements. Of course, a group of light emitting elements may not completely correspond to a column of light emitting elements. The embodiments of the present disclosure are described by taking a group of light emitting elements as a row of light emitting elements as an example.

[0104] For example, refer to Figure 3 and Figure 5C At least one of the plurality of groups of light emitting elements includes a plurality of first-region light emitting elements 30 and a plurality of second-region light emitting elements 40. That is, at least one of the plurality of groups of light emitting elements passes through the first display area R1 and the second display area R2.

[0105] For example, refer to Figure 3 , Figure 4 ,as well as Figure 5C The multiple light-emitting elements 100b include at least one row of light-emitting elements 100b passing through the first display area R1 and the second display area R2, and any one of the at least one row of light-emitting elements 100b passing through the two areas includes multiple first area light-emitting elements 30 and multiple second area light-emitting elements 40.

[0106] For example, refer to Figure 3 , Figure 4 ,as well as Figure 5C , a plurality of first-region light-emitting elements 30 are located in the first display region R1 , and a plurality of second-region light-emitting elements 40 are located in the second display region R2 .

[0107] For example, refer to Figure 3 , Figure 5C and Figure 5E The plurality of pixel circuits include a plurality of groups of pixel circuits GR, the pixel circuits in each group of the plurality of groups of pixel circuits are arranged along a first direction X, and the plurality of groups of pixel circuits are arranged along a second direction Y. For example, at least one group of the plurality of groups of pixel circuits 100a includes a plurality of first-type pixel circuits 10 and a plurality of second-type pixel circuits 20. Figure 3 and Figure 5C Three groups of pixel circuits GR are shown respectively. Figure 5E Four groups of pixel circuits GR are shown. Figure 3 and Figure 5C As shown, the pixel circuit is only located in the first display area R1, and no pixel circuit is arranged in the second display area R2.

[0108] For example, refer to Figure 3 and Figure 5C, a plurality of pixel circuits 100a are arranged in a plurality of rows and a plurality of columns, and the plurality of pixel circuits 100a include a plurality of first-type pixel circuits 10 and a plurality of second-type pixel circuits 20 located in the same row. In other words, at least one of the plurality of groups of pixel circuits includes a plurality of first-type pixel circuits 10 and a plurality of second-type pixel circuits 20.

[0109] For example, refer to Figure 3 and Figure 5C , a plurality of first-type pixel circuits 10 and a plurality of second-type pixel circuits 20 are all located in the first display area R1, and a plurality of second-type pixel circuits 20 are spaced and distributed between the plurality of first-type pixel circuits 10. At least one first-type pixel circuit 10 among the plurality of first-type pixel circuits 10 is connected to at least one first-region light-emitting element 30 among the plurality of first-region light-emitting elements 30, and the orthographic projection of at least one first-type pixel circuit 10 on the substrate BS at least partially overlaps with the orthographic projection of at least one first-region light-emitting element 30 on the substrate BS; at least one second-type pixel circuit 20 among the plurality of second-type pixel circuits 20 is connected to at least one second-region light-emitting element 40 among the plurality of second-region light-emitting elements 40 through a conductive line.

[0110] Fig. 6A The present invention is a schematic diagram of a row of light-emitting elements located in a second display area of ​​a display panel and a second type of pixel circuit connected thereto. Figure 6B A schematic diagram of the capacitance of a conductive line in a display panel. Figure 6C A schematic diagram of a display defect of a display panel. FIG. 6D to FIG. 6F They are schematic diagrams of poor display at low grayscale. Fig. 7A A schematic diagram of a row of light-emitting elements located in a second display area of ​​a display panel and a second type of pixel circuit connected thereto is provided in an embodiment of the present disclosure. Figure 7B A schematic diagram of the capacitance of light-emitting elements emitting light of different colors in the same row of light-emitting elements in a second display area of ​​a display panel provided by an embodiment of the present disclosure.

[0111] For example, in an embodiment of the present disclosure, a row of light-emitting elements may refer to that the pixel circuits connected to the row of light-emitting elements are all connected to the same gate line, but is not limited thereto. For example, in an embodiment of the present disclosure, a row of pixel circuits may refer to that the pixel circuits connected to the row are all connected to the same gate line, but is not limited thereto. For example, in an embodiment of the present disclosure, a row of pixel units may refer to that the pixel circuits connected to the row of pixel units are all connected to the same gate line, but is not limited thereto.

[0112] For example, Fig. 6A and Fig. 7AAs shown, in at least one group of light-emitting elements 100b, the plurality of second-region light-emitting elements 40 include a plurality of first light-emitting elements 41 and a plurality of second light-emitting elements 42, the first light-emitting elements 41 are configured to emit a first color light, and the second light-emitting elements 42 are configured to emit a second color light. The plurality of second-type pixel circuits 20 include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22, the conductive line L1 includes a plurality of first conductive lines La and a plurality of second conductive lines Lb, the plurality of first light-emitting elements 41 are connected to the plurality of first pixel circuits 21 through the plurality of first conductive lines La, and the plurality of second light-emitting elements 42 are connected to the plurality of second pixel circuits 22 through the plurality of second conductive lines Lb. For example, one first light-emitting element 41 is connected to one first pixel circuit 21 through one first conductive line La, and one second light-emitting element 42 is connected to one second pixel circuit 22 through one second conductive line Lb.

[0113] For example, Fig. 6A and Fig. 7A As shown, the plurality of second-region light-emitting elements 40 further include a plurality of third light-emitting elements 43, the third light-emitting elements 43 are configured to emit light of a third color, the plurality of second-type pixel circuits 20 further include a plurality of third pixel circuits 23, the conductive line L1 further includes a plurality of third conductive lines Lc, and the plurality of third light-emitting elements 43 are connected to the plurality of third pixel circuits 23 through the plurality of third conductive lines Lc. For example, one third light-emitting element 43 is connected to one third pixel circuit 23 through one third conductive line Lc.

[0114] For example, Fig. 6A and Fig. 7A As shown, the plurality of second-region light-emitting elements 40 further include a plurality of fourth light-emitting elements 44, the fourth light-emitting elements 44 are configured to emit fourth color light, the plurality of second-type pixel circuits 20 further include a plurality of fourth pixel circuits 24, the conductive line L1 further includes a plurality of fourth conductive lines Ld, and the plurality of fourth light-emitting elements 44 are connected to the plurality of fourth pixel circuits 24 through the plurality of fourth conductive lines Ld. For example, one fourth light-emitting element 44 is connected to one fourth pixel circuit 24 through one fourth conductive line Ld.

[0115] For example, the first color light and the fourth color light are both green light, one of the second color light and the third color light is red light, and the other of the second color light and the third color light is blue light.

[0116] For example, the fourth light-emitting element 44 and the first light-emitting element 41 are configured to emit light of the same color. For example, the fourth light-emitting element 44 and the first light-emitting element 41 are configured to emit green light, one of the second light-emitting element 42 and the third light-emitting element 43 is configured to emit red light, and the other of the second light-emitting element 42 and the third light-emitting element 43 is configured to emit blue light. The embodiment of the present disclosure is described by taking the fourth light-emitting element 44 and the first light-emitting element 41 emitting green light, the second light-emitting element 42 emitting red light, and the third light-emitting element 43 emitting blue light as an example. In other embodiments, the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43 and the fourth light-emitting element 44 may also emit light of other colors, not limited to the three colors of red, green and blue. The colors of the light emitted by the first light-emitting element 41, the second light-emitting element 42, the third light-emitting element 43 and the fourth light-emitting element 44 may be determined as needed.

[0117] like Figure 6B As shown, the horizontal axis represents the position of the second display area of ​​the display panel in the first direction, and the vertical axis represents the ratio of the capacitance of the conductive wire connected to the light-emitting element at this position to the total capacitance. In the display panel, the capacitance of the conductive wires varies greatly. Since the lengths of the conductive wires connecting the light-emitting elements located in the second display area are different, the capacitance differences of the light-emitting elements emitting different colors vary differently. Compared with the capacitance difference of the conductive wires connected to the light-emitting elements emitting red light and the capacitance difference of the conductive wires connected to the light-emitting elements emitting blue light, the capacitance difference of the conductive wires connected to the light-emitting elements emitting green light is greater. Because the capacitance difference of the conductive wires connected to the light-emitting elements emitting green light is greater, the light-emitting time of the light-emitting elements emitting green light is reduced, resulting in brightness differences in the display panel, causing poor display. For example, if Figure 6C As shown in the figure, stripes appear when the display panel is displayed. Figure 6C As shown, purple stripes appear when the display panel is displayed ( Figure 6C (The image is in grayscale and not colored). For example, purple vertical stripes appear when the display panel is displayed. FIG. 6D to FIG. 6F As shown, at low grayscale, the defective degree of the light-emitting element emitting green light is greater than that of the light-emitting element emitting red light, and the defective degree of the light-emitting element emitting red light is greater than that of the light-emitting element emitting blue light. For example, at the same grayscale, the driving current driving the light-emitting element emitting blue light is greater than the driving current driving the light-emitting element emitting red light, and the driving current driving the light-emitting element emitting red light is greater than the driving current driving the light-emitting element emitting green light.

[0118] Figure 7B for Fig. 7A A schematic diagram of the distribution of the capacitance of the conductive wires connected to the light-emitting elements emitting light of different colors in a row of light-emitting elements in the second display area. Figure 7BAs shown, the capacitance of the conductive line connected to the green light-emitting element is the smallest, and as Figure 7B As shown in the left half of the figure, the capacitance of the conductive line connected to the green light-emitting element shows a trend of gradually increasing, so the capacitance difference between the two conductive lines connected to the adjacent green light-emitting elements is small. Figure 7B The right half shown will not be described in detail. Figure 7B As shown, the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the red light-emitting element, and the capacitance of the conductive wire connected to the green light-emitting element is smaller than that of the conductive wire connected to the blue light-emitting element. Figure 7B As shown, the capacitance of the conductive wire connected to the red light-emitting element shows a gradually increasing trend, and the capacitance of the conductive wire connected to the blue light-emitting element shows a gradually increasing trend, and the capacitance of the conductive wire connected to the red light-emitting element and the capacitance of the conductive wire connected to the blue light-emitting element are not much different.

[0119] In order to improve display defects, the display panel provided by the embodiment of the present disclosure adjusts the arrangement order of the second type of pixel circuits connected to the light-emitting elements emitting light of different colors, so as to reduce or eliminate the display defects caused by the large difference in the length of the conductive wire. That is, when designing the second type of pixel circuit connected to the first light-emitting element, the length of the conductive wire and the difference in the length of the conductive wire are considered, for example, the order of G priority is adopted. For example, G priority means that the second type of pixel circuit connected to the light-emitting element emitting green light is preferentially arranged close to the second display area.

[0120] like Fig. 7A As shown, in at least one group of light-emitting elements and at least one group of pixel circuits, the plurality of first pixel circuits 21 connected to the plurality of first light-emitting elements 41 are closer to the second display area R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second light-emitting elements 42. That is, Fig. 7A The display panel shown is Fig. 6A Compared with the display panel shown in the figure, the setting position of the first pixel circuit 21 connected to the first light-emitting element 41 is adjusted, so that the first pixel circuit 21 connected to the first light-emitting element 41 is closer to the second display area R2 than other second-type pixel circuits, so that the length difference of the first conductive line La connected to the first light-emitting element 41 is reduced, thereby alleviating or avoiding poor display.

[0121] For example, in the embodiment of the present disclosure, at least one group of light emitting elements and at least one group of pixel circuits may refer to a row of light emitting elements 100b passing through two regions, or may refer to a row of pixel units passing through two regions, but is not limited thereto.

[0122] For example, Fig. 7A As shown, in at least one group of light-emitting elements and at least one group of pixel circuits, no other second-type pixel circuit 20 is arranged between two first pixel circuits 21 connected to two adjacent first conductive lines La. This arrangement is conducive to reducing the length of the first conductive lines La, and also conducive to reducing the length difference between the first conductive lines La.

[0123] It should be noted that, in the display panel provided in the embodiments of the present disclosure, element A and element B are adjacent, or adjacent elements A and element B means that there are no other elements A and other elements B between element A and element B, but there may be other elements besides element A and element B. Element A and element B may be the same element or different elements.

[0124] For example, Figure 5C , Figure 5E and Fig. 7A As shown, in at least one group of light emitting elements and at least one group of pixel circuits, at least one of the plurality of first type pixel circuits 10 is arranged between two adjacent second type pixel circuits 20 .

[0125] For example, Fig. 7A As shown, in at least one group of light-emitting elements and at least one group of pixel circuits, a plurality of first pixel circuits 21 connected to a plurality of first conductive lines La are arranged at intervals in a plurality of first-type pixel circuits 10, and a plurality of second pixel circuits 22 connected to a plurality of second conductive lines Lb are arranged at intervals in a plurality of first-type pixel circuits 10.

[0126] Fig. 7A Only one row of light emitting elements passing through two regions is shown. It can be understood that Fig. 7A The upper side, lower side, or upper side and lower side of the row of light-emitting elements shown may also include multiple rows of light-emitting elements that are the same as the row of light-emitting elements shown. Fig. 7A Each light emitting element shown in is one of a column of light emitting elements, Fig. 7A Each pixel circuit shown in FIG. 1 is one of a column of pixel circuits.

[0127] For example, Fig. 7A As shown, in at least one group of light emitting elements and at least one group of pixel circuits, a plurality of first pixel circuits 21 connected to a plurality of first conductive lines La are closer to the second display area R2 than each of a plurality of third pixel circuits 23 connected to a plurality of third conductive lines Lc.

[0128] For example, Fig. 7AAs shown, in order to make the second conductive line Lb have a smaller capacitance difference and in order to make the third conductive line Lc have a smaller capacitance difference, in at least one group of light-emitting elements and at least one group of pixel circuits, a plurality of second pixel circuits 22 connected to a plurality of second conductive lines Lb and a plurality of third pixel circuits 23 connected to a plurality of third conductive lines Lc are alternately arranged.

[0129] For example, Fig. 7A As shown, in at least one group of light-emitting elements and at least one group of pixel circuits, the plurality of fourth pixel circuits 24 connected to the plurality of fourth conductive lines Ld are closer to the second display area R2 than each of the plurality of second pixel circuits 22 connected to the plurality of second conductive lines Lb. In the embodiment of the present disclosure, the fourth light-emitting element 44 and the first light-emitting element 41 emit light of the same color, so that the plurality of fourth pixel circuits 24 are also preferentially arranged, that is, the plurality of fourth pixel circuits 24 are arranged closer to the second display area. Of course, in other embodiments, the fourth light-emitting element 44 may not be arranged, so that the fourth pixel circuit 24 does not need to be arranged. For example, in this case, the pixel may be in the form of real RGB, but is not limited thereto.

[0130] For example, Fig. 7A As shown, in order to make the first conductive line La have a smaller capacitance difference and to make the fourth conductive line Ld have a smaller capacitance difference, in at least one group of light-emitting elements and at least one group of pixel circuits, a plurality of fourth pixel circuits 24 connected to a plurality of fourth conductive lines Ld and a plurality of first pixel circuits 21 connected to a plurality of first conductive lines La are alternately arranged.

[0131] For example, at least one of the first conductive line La, the second conductive line Lb, the third conductive line Lc, and the fourth conductive line Ld is made of a transparent conductive material.

[0132] Figure 7C Schematic diagram of a display panel provided by an embodiment of the present disclosure. Figure 7C As shown, the second display area R2 of the display panel is axially symmetrical, having a first symmetric axis X1 extending along the first direction X and a second symmetric axis X2 extending along the second direction Y. Figure 7C As shown, a plurality of conductive lines L1 are provided, and the plurality of conductive lines L1 are axisymmetric with respect to the first symmetry axis X1 and are axisymmetric with respect to the second symmetry axis X2. Figure 7C Only four conductive lines L1 are schematically shown. Figure 7CIt is shown that the second display area R2 includes a first sub-area R21, a second sub-area R22, a third sub-area R23, and a fourth sub-area R24. The first sub-area R21 and the second sub-area R22 are axially symmetrical with respect to the second symmetry axis X2, the third sub-area R23 and the fourth sub-area R24 are axially symmetrical with respect to the second symmetry axis X2, the first sub-area R21 and the third sub-area R23 are axially symmetrical with respect to the first symmetry axis X1, and the second sub-area R22 and the fourth sub-area R24 are axially symmetrical with respect to the first symmetry axis X1. For example, a plurality of second-region light-emitting elements are axially symmetrical with respect to the first symmetry axis X1 and axially symmetrical with respect to the second symmetry axis X2. Fig. 7A The row of light emitting elements shown may be located in the first sub-region R21 or the third sub-region R23.

[0133] Fig. 8A A schematic diagram of a light-emitting element located in a second display area and a second type of pixel circuit connected thereto in a display panel provided in one embodiment of the present disclosure. Fig. 8A Part of the light-emitting elements located in the second display area is shown. For the sake of clarity, the light-emitting elements located in the first display area are omitted, and the first type of pixel circuit is omitted. Fig. 7A and Fig. 8A It can be understood that one or more first-type pixel circuits and a first-region light-emitting element connected to the first-type pixel circuits are arranged between two adjacent second-type pixel circuits.

[0134] Fig. 8A Two rows of light emitting elements located in the left half of the second display area R2 are shown. The structure in the second display area R2 is vertically symmetrical with respect to the axis X1 and is left-right symmetrical with respect to the second symmetry axis X2. Fig. 8A Two rows of light emitting elements r1 and r2 are shown, with Fig. 8A For example, the two rows of light emitting elements r1 and r2 are symmetrical with respect to the first symmetry axis X1. For example, Fig. 8A The two rows of light emitting elements r1 and r2 are located at Figure 7C The first sub-region R21 or the third sub-region R23 shown.

[0135] Figure 8B for Fig. 8A Schematic diagram of the first conductive line La and the fourth conductive line Ld in FIG. Figure 8C for Fig. 8A Schematic diagram of the second conductive line Lb in . Fig.8D for Fig. 8A Schematic diagram of the third conductive line Lc in FIG.

[0136] For example, in some embodiments, the first conductive line La and the fourth conductive line Ld are located in the same pattern layer, the second conductive line Lb is located in one pattern layer, and the third conductive line Ld is located in another pattern layer, thereby forming three pattern layers. For example, in some embodiments, the first conductive line La and the fourth conductive line Ld are located in the third pattern layer, the second conductive line Lb is located in the second pattern layer, and the third conductive line Ld is located in the first pattern layer. For example, the third pattern layer, the second pattern layer, and the first pattern layer are sequentially arranged in a direction perpendicular to the substrate, and the first pattern layer is closer to the substrate than the second pattern layer, and the second pattern layer is closer to the substrate than the third pattern layer. In the case where the number of conductive lines required to be arranged in each group of light-emitting elements is small, the conductive lines required to be arranged in the group of light-emitting elements can be arranged in one layer. In the case where the number of conductive lines required to be arranged in each group of light-emitting elements is large, the conductive lines can be arranged in different layers. According to needs, some conductive lines can be formed in segments, that is, formed by conductive parts located in different layers. When there are many conductive lines to be arranged, a segmented arrangement method is adopted.

[0137] For example, Fig. 8A , FIG. 8B to FIG. 8D As shown, the conductive lines connected to two rows of adjacent light emitting elements 100 b passing through two regions are axisymmetric.

[0138] For example, Fig. 8A , FIG. 8B to FIG. 8D As shown, the structure in the second display area R2 is axisymmetric.

[0139] Fig. 8E FIG. 1 is a schematic diagram of a row of light emitting elements r1 of a display panel provided by another embodiment of the present disclosure. Fig. 8E As shown in the figure, the solid line indicates the second pattern layer, the dashed line indicates the first pattern layer, and the dotted line indicates the third pattern layer. The conductive parts of the same conductive line located in different layers are connected through vias. Fig. 8E As shown, in the area with dense wiring, in the second direction Y, adjacent conductive lines are located in different pattern layers. This arrangement is conducive to reducing interference between conductive lines.

[0140] For example, at least one of the plurality of first conductive lines La, one of the plurality of second conductive lines Lb, one of the plurality of third conductive lines Lc, and one of the plurality of fourth conductive lines Ld is formed by one conductive line as a whole, or by conductive parts located in different layers.

[0141] like Fig. 8E As shown, the conductive line Lb1 is formed by conductive parts located in different layers, and the conductive line Lc1 is formed by conductive parts located in different layers. Fig. 8E The other conductive lines in the are all formed by a conductive line as a whole and are distributed in three different pattern layers.

[0142] For example, Figure 1B As shown, the first display region R1 includes an auxiliary region Ra, a plurality of second type pixel circuits 20 are located in the auxiliary region Ra, and an area of ​​the auxiliary region Ra is smaller than an area of ​​the first display region R1 except the auxiliary region Ra.

[0143] For example, in order to facilitate the arrangement of the second type of pixel circuit 20 in the first display region R1, the size of the first type of pixel circuit 10 in the first direction is smaller than the size of the first area light emitting element 30 in the first direction. For example, the size of the second type of pixel circuit 20 in the first direction is smaller than the size of the first area light emitting element 30 in the first direction. For example, the size of the first type of pixel circuit 10 in the first direction is equal to or substantially equal to the size of the second type of pixel circuit 20 in the first direction.

[0144] Fig. 8A The display panel shown includes a fourth light emitting element. In other embodiments, the display panel may not include the fourth light emitting element. In the case where the display panel does not include the fourth light emitting element, the Fig. 8A The fourth light-emitting element and the pixel circuit connected to the fourth light-emitting element as shown, and the positions of other components can be adjusted accordingly.

[0145] Fig.9A A schematic diagram of another display panel provided according to an embodiment of the present disclosure. Fig. 9B A schematic diagram of a display panel provided by another embodiment of the present disclosure is shown in FIG. Fig.9A As shown, the fourth conductive line Ld and the first conductive line La are located on the same side of the row of light emitting elements. Fig.9A The fourth conductive line Ld and the first conductive line La are located on the upper side of the light emitting element in the row. Fig.9A As shown, the fourth conductive line Ld partially overlaps with the first conductive line La. That is, the orthographic projection of the fourth conductive line Ld on the substrate partially overlaps with the orthographic projection of the first conductive line La on the substrate. Fig. 9B As shown in FIG. 1 , the second conductive line Lb and the third conductive line Lc partially overlap. That is, the orthographic projection of the second conductive line Lb on the substrate and the orthographic projection of the third conductive line Lc on the substrate partially overlap. The overlapping arrangement of the conductive lines can help reduce the space in the second display area occupied by the conductive lines connected to the row of light-emitting elements in the second direction Y, which is conducive to arranging more conductive lines. Fig.9A and Fig. 9BAs shown, the same line type indicates that they are located in the same layer. For example, the portion indicated by the single-point dashed line indicates that they are located in the first pattern layer L11, the portion indicated by the solid line indicates that they are located in the second pattern layer L12, and the portion indicated by the dotted line indicates that they are located in the third pattern layer L13. For example, the first pattern layer L11 is closer to the base substrate than the second pattern layer L12, and the second pattern layer L12 is closer to the base substrate than the third pattern layer L13, but it is not limited thereto, and the manufacturing order of each pattern layer can also be adjusted as needed so that the distance between them and the base substrate is different from the above description.

[0146] FIG. 10A to FIG. 10E A schematic diagram of a display panel provided by an embodiment of the present disclosure. FIG. 10A to FIG. 10E As shown, a row of light-emitting elements includes 48 second-region light-emitting elements. For the sake of clarity, not all second-region light-emitting elements are shown in a single figure. Circles and numbers in the circles represent second-region light-emitting elements, and the numbers in the circles represent the serial numbers of the second-region light-emitting elements. Brackets and numbers in the brackets represent second-type pixel circuits, and the numbers in the brackets represent the serial numbers of the second-type pixel circuits. Fig. 10A As shown, the 48th column of second-region light-emitting elements is connected to the 25th column of the second-type pixel circuit via a conductive line, and the connection conditions of the remaining second-region light-emitting elements and the second-type pixel circuits can refer to the above description. FIG. 10A to FIG. 10E Taking the fourth light emitting element 44 and the first light emitting element 41 emitting green light, the second light emitting element 42 emitting red light, and the third light emitting element 43 emitting blue light as an example, the figure shows the second region light emitting elements arranged in the order of RGBG. Fig.10E G1 (which may refer to the first light emitting element 41) and G2 (which may refer to the fourth light emitting element 44) are shown, thereby forming a form of RG1BG2. FIG. 10A to FIG. 10E In the figure, the conductive line connected to the first light-emitting element 41 (G1 or G adjacent to B and located on the left side of B) is the first conductive line La, the conductive line connected to the second light-emitting element 42 (R) is the second conductive line Lb, the conductive line connected to the third light-emitting element 43 (B) is the third conductive line Lc, and the conductive line connected to the fourth light-emitting element 44 (G2 or G adjacent to B and located on the right side of B) is the fourth conductive line Ld.

[0147] Fig. 10A shows the conductive lines located in the first pattern layer L11, Fig. 10A A whole conductive line and a first conductive portion L01 used to form a conductive line are shown. The first conductive portion L01 is connected to the second type pixel circuits of the 14th column and the 22nd column respectively. Fig. 10A Thirteen full conductive lines and nine first conductive portions L01 are shown.

[0148] Fig. 10Bshows the conductive line located in the second pattern layer L12, Fig. 10B A whole conductive line and a second conductive portion L02 for forming a conductive line are shown. The second conductive portion L02 is respectively connected to Fig. 10A The nine second region light emitting elements (the odd-numbered light emitting elements in the 31st to 47th columns of light emitting elements) shown in FIG. Fig. 10B Thirteen full conductive lines and nine second conductive portions L02 are shown.

[0149] Fig. 10C shows the conductive line located in the third pattern layer L13, Fig. 10C Thirteen conductive lines are shown, and the 13 conductive lines are respectively connected to the second-region light-emitting elements in the first to thirteenth columns.

[0150] Fig. 10D Shows Fig. 10A The first conductive portion L01 and Fig. 10B The second conductive part L02 in the embodiment is connected through a via hole V0 penetrating the insulating layer to form a conductive line. Fig. 10D As shown, the third conductive line Lc may include a first conductive portion L01 and a second conductive portion L02 connected to each other, and the fourth conductive line Ld may include a first conductive portion L01 and a second conductive portion L02 connected to each other. Fig. 10D As shown, the first conductive portion L01 extends along the second direction Y, and the second conductive portion L02 extends along the first direction X. In order to make adjacent conductive lines have a smaller capacitance difference, the ends of the plurality of second conductive portions L02 away from the second region light emitting elements are flush. Fig. 10D As shown, the lengths of the plurality of first conductive portions L01 along the second direction Y are different.

[0151] refer to Fig.10E A group of light emitting elements includes a plurality of subgroup light emitting elements arranged in sequence along the first direction X, and the plurality of subgroup light emitting elements are located on the same side of the symmetry axis of the second display area extending along the second direction Y. For example, referring to Fig.10E A group of light emitting elements includes a first subgroup of light emitting elements GP01, a second subgroup of light emitting elements GP02, and a third subgroup of light emitting elements GP03. Of course, other groups of light emitting elements can also refer to the above-mentioned method of dividing into multiple subgroups of light emitting elements.

[0152] For example, Fig.10EAs shown, the first subgroup of light-emitting elements GP01 includes the first to thirteenth light-emitting elements in the same group of light-emitting elements (the same group of second-region light-emitting elements), the second subgroup of light-emitting elements GP02 includes the fourteenth to twenty-sixth light-emitting elements in the same group of light-emitting elements (the same group of second-region light-emitting elements), and the third subgroup of light-emitting elements GP03 includes the twenty-seventh to forty-eighth light-emitting elements in the same group of light-emitting elements (the same group of second-region light-emitting elements). Of course, in other embodiments, the same group of light-emitting elements (the same group of second-region light-emitting elements) may also be provided with other numbers of light-emitting elements, which may be provided as needed, for reference. Figure 7C and Fig.10E The embodiment of the present disclosure is described by taking the same group of light-emitting elements (the same group of second-region light-emitting elements) including forty-eight light-emitting elements located on the left side of the second symmetry axis X2 as an example.

[0153] For example, refer to Fig. 10C and Fig.10E , each light emitting element in the first subgroup of light emitting elements GP01 is connected to the conductive line L1 located in the third pattern layer L13; Fig. 10B and Fig.10E , the light emitting elements in the second subgroup of light emitting elements GP02 are connected to the conductive line L1 located in the second pattern layer L12; Fig. 10A , 10B and Fig.10E A part of the light emitting elements of the third subgroup of light emitting elements GP03 are connected through the conductive line L1 located on the first pattern layer L11, and another part of the light emitting elements of the third subgroup of light emitting elements GP03 are connected through a conductive line formed by a segment formed by a first conductive part L01 located on the first pattern layer L11 and a second conductive part L02 located on the second conductive layer L12.

[0154] refer to Fig.10E , a group of pixel circuits includes a plurality of sub-group pixel circuits arranged in sequence along the first direction X, and the plurality of sub-group pixel circuits are located on the same side of the symmetry axis extending along the second direction Y of the second display area. For example, referring to Fig.10E A group of pixel circuits includes the first subgroup pixel circuit GR01 to the seventh subgroup pixel circuit GR07, and the seventh subgroup pixel circuit GR07 is closer to the second display area than the first subgroup pixel circuit GR01. Of course, other groups of pixel circuits can also refer to the above method of being divided into multiple subgroup pixel circuits.

[0155] refer to Fig.10EThe conductive wires connected to the first subgroup light-emitting element GP01 are located on the same layer, the conductive wires connected to the second subgroup light-emitting element GP02 are located on the same layer, and the conductive wires connected to the third subgroup light-emitting element GP03 include conductive wires located on the same layer and also include conductive wires formed in segments, and the conductive wires formed in segments include parts located in different layers.

[0156] refer to Fig.10E The conductive wire connected to the first subgroup light-emitting element GP01 is located in the third pattern layer L13, the conductive wire connected to the second subgroup light-emitting element GP02 is located in the second pattern layer L12, and the conductive wire connected to the third subgroup light-emitting element GP03 includes the conductive wire located in the first pattern layer L11 and also includes the conductive wire formed in segments, and the conductive wire formed in segments includes the first conductive part L01 located in the first pattern layer L11 and the second conductive part L02 located in the second pattern layer L12.

[0157] refer to Fig.10E The second light-emitting element 42 and the third light-emitting element 43 in the first sub-group light-emitting element GP01 are connected to the second sub-group pixel circuit GR02, the second light-emitting element 42 and the third light-emitting element 43 in the second sub-group light-emitting element GP02 are connected to the first sub-group pixel circuit GR01, the second light-emitting element 42 and the third light-emitting element 43 in the third sub-group light-emitting element GP03 close to the second sub-group light-emitting element GP02 are connected to the fourth sub-group pixel circuit GR04, the second light-emitting element 42 and the third light-emitting element 43 in the third sub-group light-emitting element GP03 far from the second sub-group light-emitting element GP02 are connected to the third sub-group pixel circuit GR03, the first light-emitting element 41 and the fourth light-emitting element 44 in the first sub-group light-emitting element GP01 are connected to the seventh sub-group pixel circuit GR07, the first light-emitting element 41 and the fourth light-emitting element 44 in the second sub-group light-emitting element GP02 are connected to the sixth sub-group pixel circuit GR06, and the first light-emitting element 41 and the fourth light-emitting element 44 in the third sub-group light-emitting element GP03 are connected to the fifth sub-group pixel circuit GR05.

[0158] like Fig.10E As shown, in order to reduce the occupied area of ​​the conductive line, the portions of the two fourth conductive lines Ld located in different layers extending along the first direction X may at least partially overlap. That is, the orthographic projections of the portions of the two fourth conductive lines Ld located in different layers extending along the first direction X on the substrate at least partially overlap.

[0159] For example, in order to reduce the occupied area of ​​the conductive line, the portions of two first conductive lines La located in different layers extending along the first direction X may at least partially overlap. That is, the orthographic projections of the portions of two first conductive lines La located in different layers extending along the first direction X on the substrate at least partially overlap.

[0160] like Fig.10E As shown, in order to reduce the occupied area of ​​the conductive line, the portion of the fourth conductive line Ld extending along the first direction X may at least partially overlap with the portion of the first conductive line La located at a different layer thereof extending along the first direction X. That is, the orthographic projection of the portion of the fourth conductive line Ld extending along the first direction X on the substrate may at least partially overlap with the orthographic projection of the portion of the first conductive line La located at a different layer thereof extending along the first direction X on the substrate.

[0161] like Fig.10E As shown, in order to reduce the occupied area of ​​the conductive line, the second conductive line Lb and the third conductive line Lc located in different layers partially overlap. That is, the orthographic projection of the second conductive line Lb on the substrate and the orthographic projection of the third conductive line Lc on a different layer from the second conductive line Lb on the substrate partially overlap.

[0162] like Fig.10E As shown, the third conductive line Lc connected to the third sub-group light-emitting element GP03 and the second conductive line Lb connected to the first sub-group light-emitting element GP01 partially overlap, that is, the orthographic projection of the third conductive line Lc connected to the third sub-group light-emitting element GP03 on the substrate substrate and the orthographic projection of the second conductive line Lb connected to the first sub-group light-emitting element GP01 on the substrate substrate partially overlap.

[0163] like Fig.10E As shown in FIG. 1 , the first conductive line La and the fourth conductive line Ld are located on the same side of the group of light emitting elements. Fig.10E As shown, the orthographic projection of a portion of one of the plurality of first conductive lines La extending along the first direction X on the substrate substrate at least partially overlaps with the orthographic projection of another first conductive line La of a different layer from the first conductive line La extending along the first direction X on the substrate substrate, or the orthographic projection of a portion of one of the plurality of first conductive lines La extending along the first direction X on the substrate substrate at least partially overlaps with the orthographic projection of a portion of one of the plurality of fourth conductive lines Ld of a different layer from the first conductive line La extending along the first direction X on the substrate substrate.

[0164] like Fig.10E As shown, the orthographic projection of a portion of one of the plurality of second conductive lines Lb extending along the first direction X on the substrate and the orthographic projection of a portion of one of the plurality of third conductive lines Lc in a different layer from the second conductive line Lb extending along the first direction X on the substrate at least partially overlap.

[0165] like Fig.10EAs shown, the portion of the conductive line L1 connected to the second subgroup light-emitting element GP02 extending along the first direction does not overlap with the portions of other conductive lines extending along the first direction. Of course, the portion of the conductive line L1 connected to the second subgroup light-emitting element GP02 extending along the first direction may overlap with the portions of other conductive lines extending along the second direction. For example, the conductive line L1 connected to the second subgroup light-emitting element GP02 is located in the second pattern layer L12, and the conductive line L1 connected to the first subgroup light-emitting element GP01 is located in the third pattern layer L13; the conductive line L1 connected to the second light-emitting element 42 and the third light-emitting element 43 of the third subgroup light-emitting element GP03 close to the second subgroup light-emitting element GP02 is located in the first pattern layer L11. Fig.10E As shown, the overlapping parts of the two conductive lines where the part extending along the first direction of the conductive line L1 connected to the second subgroup light emitting element GP02 overlaps with the part extending along the first direction are alternately arranged. For example, the part extending along the first direction of the conductive line L1 connected to the second subgroup pixel circuit GR02 overlaps with the part extending along the first direction of the conductive line L1 connected to the fourth subgroup pixel circuit GR04, and the part extending along the first direction of the conductive line L1 connected to the first subgroup pixel circuit GR01 does not overlap with the part extending along the first direction of the conductive line L1 connected to the second subgroup pixel circuit GR02, and does not overlap with the part extending along the first direction of the conductive line L1 connected to the fourth subgroup pixel circuit GR04. Fig.10E The middle conductor includes a portion extending along a first direction X and portions extending along a second direction Y located on both sides of the portion extending along the first direction.

[0166] refer to Fig. 10C and Fig.10E The conductive line connected to the second subgroup pixel circuit GR02 is located on the third pattern layer L13, and the conductive line connected to the seventh subgroup pixel circuit GR07 is located on the second pattern layer L12.

[0167] refer to Fig. 10B , Fig. 10D and Fig.10E The conductive line connected to the first subgroup pixel circuit GR01 is located in the second pattern layer L12, the conductive line connected to the sixth subgroup pixel circuit GR06 is located in the second pattern layer L12, and the second conductive part L02 of the conductive line connected to the third subgroup pixel circuit GR03 is located in the second pattern layer L12.

[0168] refer to Fig. 10A and Fig.10E The conductive line connected to the fifth subgroup pixel circuit GR05 is located in the first pattern layer L11, the conductive line connected to the fourth subgroup pixel circuit GR04 is located in the first pattern layer L11, and the first conductive part L01 of the conductive line connected to the third subgroup pixel circuit GR03 is located in the first pattern layer L11.

[0169] refer to FIG. 10A to FIG. 10E The number of pixel circuits included in each sub-group pixel circuit is shown as the pixel circuit between the two vertical dashed lines in the figure. It should be noted that those skilled in the art can set the number of pixel circuits included in each sub-group pixel circuit as needed. FIG. 10A to FIG. 10E The example in which the second display area includes 48 second-region light-emitting elements is used for description, but it can be set as required.

[0170] refer to FIG. 10A to FIG. 10E For clarity of illustration, the first type of pixel circuit located between two second type pixel circuits is omitted in the figure, and the first area light emitting element connected to the first type pixel circuit is omitted.

[0171] refer to Fig. 8A , Fig.9A , Fig. 9B , FIG. 10A to FIG. 10E In a group of pixel units, or in a row of pixel units, the distance between two adjacent second-type pixel circuits is greater than the distance between two adjacent second-region light-emitting elements.

[0172] About FIG. 10A to FIG. 10E The arrangement of the second type of pixel circuit in the display panel shown in FIG. Fig. 7A , Fig. 8A , Fig.9A and Fig. 9B The arrangement manner and related description of the second type of pixel circuit shown are not repeated here. FIG. 10A to FIG. 10E The arrangement of the pixel circuit connected to the first light-emitting element in the display panel shown is closer to the second display area than other second-type pixel circuits, which is beneficial to reducing the capacitance of the conductive line of the first light-emitting element and reducing the capacitance difference of the conductive lines of adjacent first light-emitting elements, thereby improving display defects and achieving better display effects. FIG. 10A to FIG. 10E The arrangement of the pixel circuit connected to the second light-emitting element in the display panel shown is also beneficial to reducing the capacitance of the conductive line of the second light-emitting element and reducing the capacitance difference of the conductive lines of adjacent second light-emitting elements, thereby improving display defects. FIG. 10A to FIG. 10E The arrangement of the conductive wires connected to the third light-emitting elements in the display panel shown is also conducive to reducing the capacitance of the conductive wires of the third light-emitting elements and reducing the capacitance difference of the conductive wires of adjacent third light-emitting elements, thereby improving display defects. FIG. 10A to FIG. 10E Portions of the conductive lines extending along the first direction are overlapped to reduce the occupied area of ​​the conductive lines.

[0173] Fig.10FA schematic diagram of connection elements in a column of second-type pixel circuits in a display panel provided by an embodiment of the present disclosure. Fig.10F As shown, the second type of pixel circuit in this column may be Fig.10E A column of second type pixel circuits in the third subgroup pixel circuit GR03 shown in FIG. Fig.10F As shown, the sizes of the plurality of connection elements CE0 located in different groups of pixel circuits in the first direction X are equal to facilitate manufacturing. Fig.10F The pixel circuits in one column of the eight groups of pixel circuits GR arranged along the second direction Y are shown, corresponding to eight connection elements CE0 . Fig.10F The second type of pixel circuit in the 22nd column is taken as an example for description.

[0174] Figure 10G A schematic diagram of a conductive line connected to a column of second region light emitting elements in a display panel provided by an embodiment of the present disclosure. Figure 10G As shown, the second region light emitting elements of the column may be Fig.10E A column of light emitting elements in the third subgroup of light emitting elements GP03 is shown. Fig.10F The second region light emitting elements in the 31st column are used as an example for description. Fig.10F As shown, in the same column of light emitting elements, the connection position between the first electrode of the light emitting element and the conductive line L1 gradually moves away from the second symmetry axis X2 and then gradually approaches the second symmetry axis X2.

[0175] Fig. 10H A schematic diagram of connection elements in a column of second-type pixel circuits in a display panel provided by an embodiment of the present disclosure. Fig. 10H As shown, the second type of pixel circuit in this column may be Fig.10E A column of second type pixel circuits in the third subgroup pixel circuit GR03 shown in FIG. Fig. 10H As shown, the sizes of the multiple connection elements CE0 in different groups of pixel circuits in the first direction X gradually change, for example, gradually decrease and then gradually increase, so as to facilitate the arrangement of the conductive line L1 / the first conductive portion L01 of the conductive line L1. Fig. 10H The pixel circuits in one column of the eight groups of pixel circuits GR arranged along the second direction Y are shown, corresponding to eight connection elements CE0 . Fig. 10H The second type of pixel circuit in the 22nd column is taken as an example for description.

[0176] pass Fig.10F and Figure 10G ,or Fig. 10H and Figure 10G The arrangement shown can make the conductive lines corresponding to different groups of light-emitting elements be located on the same layer. FIG. 10A to FIG. 10G ,or Fig. 10H and Figure 10G The arrangement of the conductive wires in the display panel shown, those skilled in the art can know the arrangement of each group of light-emitting elements passing through the first display area and the second display area, and can know the arrangement of the conductive wires. For example, the overlap of the conductive wires described above refers to the overlap of the portions of the conductive wires extending along the first direction X, that is, having a larger overlap area or a larger overlap length.

[0177] like Fig.10E As shown, a whole conductive line located in the second pattern layer L12 does not overlap with other conductive lines in a large area. For example, a part of a whole conductive line located in the second pattern layer L12 extending along the first direction does not overlap with other conductive lines.

[0178] refer to Fig. 8A , Fig. 8E , Fig.9A , Fig. 9B as well as Fig.10E , the second display area includes a first edge R2a, a second edge R2b, a third edge R2c, and a fourth edge R2d. For example, the first edge R2a, the second edge R2b, the third edge R2c, and the fourth edge R2d are respectively the sides of a quadrilateral. A row of light-emitting elements overlaps with the first edge R2a. A portion of the plurality of conductive lines passes from the second display area through the second edge R2b intersecting with the first edge R2a to the first display area. For example, the segmented conductive lines pass from the second display area through the second edge R2b intersecting with the first edge R2a to the first display area.

[0179] For example, in the embodiments of the present disclosure, the conductive lines are not electrically connected, and the two overlapping conductive lines are located in different layers. An insulating layer is provided between the first pattern layer L11 and the second pattern layer L12, an insulating layer is provided between the third pattern layer L13 and the second pattern layer L12, and an insulating layer is provided between the first pattern layer L11 and the pixel circuit.

[0180] In the embodiments of the present disclosure, the row of light emitting elements or a row of light emitting elements may also be replaced by a group of light emitting elements or a group of pixel units. The row of pixel circuits or a row of pixel circuits may also be replaced by a group of pixel circuits or a group of pixel units.

[0181] Fig.11 A schematic diagram of a display panel provided by an embodiment of the present disclosure. Fig.11 As shown, in the auxiliary area Ra, the orthographic projection of the conductive line L1 on the base substrate BS overlaps with the orthographic projection of the first type pixel circuit 10 on the base substrate BS. Fig.11 The arrangement mode of G priority is shown. The auxiliary area Ra can also be regarded as an area where the conductive line L1 is arranged.

[0182] In the embodiments of the present disclosure, the first direction X and the second direction Y are both directions parallel to the main surface of the substrate, and the third direction Z is a direction perpendicular to the main surface of the substrate. For example, the main surface of the substrate refers to a surface used to manufacture various components.

[0183] The display panel provided by the embodiments shown in the various figures of the present disclosure is illustrated by taking an example in which a conductive line L1 is connected to a second type of pixel circuit and to a second area light-emitting element. In other embodiments, a conductive line may also be connected to multiple second area light-emitting elements.

[0184] Fig. 12A It is a schematic diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig. 12B It is a layout diagram of a pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig. 12C for Fig. 12B A cross-sectional view along line AB. Fig.12D It is a layout diagram of a pixel circuit in a display panel provided by another embodiment of the present disclosure. Fig.12E It is a layout diagram of a pixel circuit in a display panel provided by another embodiment of the present disclosure.

[0185] Fig. 12A The pixel circuit shown may be a pixel circuit of a low temperature polysilicon (LTPS) AMOLED commonly used in the related art.

[0186] Fig. 12A FIG. 4 shows a pixel circuit of a pixel unit of a display panel, such as Fig. 12A As shown, the pixel unit 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes six switch transistors (T2-T7), a drive transistor T1 and a storage capacitor Cst. The six switch transistors are respectively a data write transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, and a second reset transistor T7. The light-emitting element 100b includes a first pole E1 and a second pole E2 and a light-emitting functional layer located between the first pole E1 and the second pole E2. For example, the first pole E1 is an anode and the second pole E2 is a cathode. Typically, the threshold compensation transistor T3 and the first reset transistor T6 use a dual-gate thin film transistor (TFT) to reduce leakage.

[0187] like Fig. 12AAs shown, the display panel includes a gate line GT, a data line DT, a first power line PL1, a second power line PL2, a light-emitting control signal line EML, an initialization signal line INT, a reset control signal line RST, etc. For example, the reset control signal line RST includes a first reset control signal line RST1 and a second reset control signal line RST2. The first power line PL1 is configured to provide a constant first voltage signal VDD to the pixel unit 100, the second power line PL2 is configured to provide a constant second voltage signal VSS to the pixel unit 100, and the first voltage signal VDD is greater than the second voltage signal VSS. The gate line GT is configured to provide a scan signal SCAN to the pixel unit 100, the data line DT is configured to provide a data signal DATA (data voltage VDATA) to the pixel unit 100, the light-emitting control signal line EML is configured to provide a light-emitting control signal EM to the pixel unit 100, the first reset control signal line RST1 is configured to provide a first reset control signal RESET1 to the pixel unit 100, and the second reset control signal line RST2 is configured to provide a scan signal SCAN to the pixel unit 100. For example, in a row of pixel units, the second reset control signal line RST2 can be connected to the gate line GT to be input with the scan signal SCAN. Of course, the second reset control signal line RST2 can also be input with the second reset control signal RESET2. The first initialization signal line INT1 is configured to provide the first initialization signal Vinit1 to the pixel unit 100. The second initialization signal line INT2 is configured to provide the second initialization signal Vinit2 to the pixel unit 100. For example, the first initialization signal Vinit1 and the second initialization signal Vinit2 are constant voltage signals, and their magnitudes can be, for example, between the first voltage signal VDD and the second voltage signal VSS, but are not limited thereto, for example, the first initialization signal Vinit1 and the second initialization signal Vinit2 can both be less than or equal to the second voltage signal VSS. For example, in some embodiments, the first initialization signal line INT1 and the second initialization signal line INT1 are connected, and are both configured to provide the initialization signal Vinit to the pixel unit 100, that is, the first initialization signal line INT1 and the second initialization signal line INT2 are both called initialization signal lines INT, and the first initialization signal Vinit1 and the second initialization signal Vinit2 are equal, both Vinit.

[0188] like Fig. 12A As shown, the driving transistor T1 is electrically connected to the light emitting element 100b, and outputs a driving current to drive the light emitting element 100b to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal VDD, the second voltage signal VSS and other signals.

[0189] For example, the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit 100a. For example, a pixel includes a plurality of pixel units. A pixel may include a plurality of pixel units that emit light of different colors. For example, a pixel includes a pixel unit that emits red light, a pixel unit that emits green light, and a pixel unit that emits blue light, but is not limited thereto. The number of pixel units included in a pixel and the light emitting condition of each pixel unit may be determined as required.

[0190] For example, Fig. 12A As shown, the gate T20 of the data writing transistor T2 is connected to the gate line GT, the first electrode T21 of the data writing transistor T2 is connected to the data line DT, and the second electrode T22 of the data writing transistor T2 is connected to the first electrode T11 of the driving transistor T1.

[0191] For example, Fig. 12A As shown, the pixel circuit 100a further includes a threshold compensation transistor T3, a gate T30 of the threshold compensation transistor T3 is connected to the gate line GT, a first electrode T31 of the threshold compensation transistor T3 is connected to the second electrode T12 of the driving transistor T1, and a second electrode T32 of the threshold compensation transistor T3 is connected to the gate T10 of the driving transistor T1.

[0192] For example, Fig. 12A As shown, the display panel also includes a light-emitting control signal line EML, and the pixel circuit 100a also includes a first light-emitting control transistor T4 and a second light-emitting control transistor T5, a gate T40 of the first light-emitting control transistor T4 is connected to the light-emitting control signal line EML, a first electrode T41 of the first light-emitting control transistor T4 is connected to the first power line PL1, and a second electrode T42 of the first light-emitting control transistor T4 is connected to a first electrode T11 of the driving transistor T1; a gate T50 of the second light-emitting control transistor T5 is connected to the light-emitting control signal line EML, a first electrode T51 of the second light-emitting control transistor T5 is connected to a second electrode T12 of the driving transistor T1, and a second electrode T52 of the second light-emitting control transistor T5 is connected to a first electrode E1 of the light-emitting element 100b.

[0193] like Fig. 12AAs shown, the first reset transistor T6 is connected to the gate T10 of the driving transistor T1 and is configured to reset the gate of the driving transistor T1, and the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b and is configured to reset the first electrode E1 of the light emitting element 100b. The first initialization signal line INT1 is connected to the gate of the driving transistor T1 through the first reset transistor T6. The second initialization signal line INT2 is connected to the first electrode E1 of the light emitting element 100b through the second reset transistor T7. For example, the first initialization signal line INT1 and the second initialization signal line INT2 are connected to be input with the same initialization signal, but not limited to this. In some embodiments, the first initialization signal line INT1 and the second initialization signal line INT2 can also be insulated from each other and configured to input signals separately.

[0194] For example, Fig. 12A As shown, the first electrode T61 of the first reset transistor T6 is connected to the first initialization signal line INT1, the second electrode T62 of the first reset transistor T6 is connected to the gate T10 of the driving transistor T1, the first electrode T71 of the second reset transistor T7 is connected to the second initialization signal line INT2, and the second electrode T72 of the second reset transistor T7 is connected to the first electrode E1 of the light emitting element 100b. Fig. 12A As shown, the gate T60 of the first reset transistor T6 is connected to the first reset control signal line RST1, and the gate T70 of the second reset transistor T7 is connected to the second reset control signal line RST2.

[0195] like Fig. 12A As shown, the first power line PL1 is configured to provide a first voltage signal VDD to the pixel circuit 100a; the pixel circuit also includes a storage capacitor Cst, a first electrode Ca of the storage capacitor Cst is connected to the gate T10 of the driving transistor T1, and a second electrode Cb of the storage capacitor Cst is connected to the first power line PL1.

[0196] For example, Fig. 12A As shown, the display panel further includes a second power line PL2, and the second power line PL2 is connected to the second electrode E2 of the light emitting element 100b.

[0197] Fig. 12A , a first node N1, a second node N2, a third node N3, and a fourth node N4 are shown. For example, in some embodiments, reference Fig. 12A A capacitor is formed between the first node N1 and the conductive line L1, a capacitor is formed between the conductive line L1 and the fourth node N4, and the conductive line L1 is coupled with the first node N1 and the fourth node N4 respectively, thereby causing brightness differences and forming display defects such as stripes (Mura), which affects the display quality.

[0198] like Fig. 12B As shown, the pixel circuit includes a driving transistor T1, and the driving transistor includes a gate T10. Fig. 12B and 12C The second electrode Cb of the storage capacitor Cst has an opening OPN1, and one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the opening OPN1. The connection electrode CE1 may also be referred to as a first gate signal line SL1. Fig. 12B As shown, the first gate signal line SL1 is connected to the gate T10 of the driving transistor T1.

[0199] like Fig. 12B As shown, the first gate signal line SL1 is connected to the second gate signal line SL2. The gate T10 of the driving transistor T1, the first gate signal line SL1, and the second gate signal line SL2 constitute the gate signal portion PT1. The potential on the gate signal portion PT1 is the same. Of course, in other embodiments, the second gate signal line SL2 may not be provided. In this case, the gate T10 of the driving transistor T1 and the first gate signal line SL1 constitute the gate signal portion PT1. For example, the second gate signal line SL2 is the second electrode T62 of the first reset transistor T6.

[0200] refer to Fig. 12B and 12C In order to stabilize the potential on the gate signal portion PT1, the display panel provided by the embodiment of the present disclosure provides a shielding electrode SE and a constant voltage line L0, and the constant voltage line L0 is configured to provide a constant voltage to the pixel circuit. The shielding electrode SE is connected to the constant voltage line L0, so that the voltage on the shielding electrode SE is stable, which can play a shielding role and prevent the conductive line L1 from affecting the potential on the gate signal portion PT1. The positive projection of the first gate signal line SL1 on the base substrate BS falls within the positive projection of the shielding electrode SE on the base substrate BS.

[0201] refer to Fig. 12B , FIG. 12D to FIG. 12E In order to make the shielding electrode play a better shielding role and increase the shielding amount, the orthographic projection of the first gate signal line SL1 on the base substrate BS completely falls within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0202] For example, in order to reduce display defects (mura) and improve display effects, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 1.75 μm. Because the area occupied by the pixel unit is limited, the distance of the shielding electrode SE beyond the first gate signal line SL1 can be limited. For example, in some embodiments, in order to obtain a better shielding effect, the distance between the orthographic projection of the first gate signal line SL1 on the substrate BS and the boundary of the orthographic projection of the shielding electrode SE on the substrate BS is greater than or equal to 2.33 μm.

[0203] like Fig. 12B As shown, the display panel further includes a block BK, the block BK is connected to the first power line PL1, the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, the first channel CN1 and the second channel CN2 are connected through a conductive connection portion CP; the orthographic projection of the block BK on the base substrate BS at least partially overlaps with the orthographic projection of the conductive connection portion CP of the threshold compensation transistor T3 on the base substrate BS. Fig. 12B As shown, the blocking block BK of the adjacent column of pixel units is used to shield the conductive connection portion CP of the threshold compensation transistor T3 of the pixel unit in the same column.

[0204] For example, Fig. 12B As shown, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS falls within the orthographic projection of the block BK on the substrate BS. For example, the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75 μm. For example, the distance that the boundary of the orthographic projection of the block BK on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33 μm. Of course, in other embodiments, the shielding electrode SE can also be used to replace the function of the block BK, or the orthographic projection of the second gate signal line SL2 on the substrate BS falls within both the orthographic projection of the block BK on the substrate BS and the orthographic projection of the shielding electrode SE on the substrate BS.

[0205] For example, the first gate signal line SL1 and the second gate signal line SL2 are made of different materials. For example, the first gate signal line SL1 is made of metal, and the second gate signal line SL2 is made of a conductive material formed by converting a semiconductor material into a conductor.

[0206] For example, Fig. 12BAs shown, in order to save wiring, the first power line PL1 is used as the constant voltage line L0. In other embodiments, in order to save wiring, the first initialization signal line INL1 can also be used as the constant voltage line or the second initialization signal line INL2 can be used as the constant voltage line. The example of the constant voltage line L0 is not limited to the first power line PL1, the first initialization signal line INL1 and the second initialization signal line INL2. As long as it is a signal line that provides a constant voltage in the pixel circuit, it can be used as the constant voltage line L0. The embodiment of the present disclosure is explained by taking the first power line PL1 as the constant voltage line L0 as an example. When a signal line that provides a constant voltage other than the first power line PL1 is used as the constant voltage line L0, the shape of the shielding electrode SE can be adjusted so that it is connected to the signal line that provides the constant voltage.

[0207] For example, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the pixel circuit (first type pixel circuit 10) of the first pixel unit 101 on the base substrate BS. For example, the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1. In the embodiment of the present disclosure, after the pixel circuit is formed, the shielding electrode SE is formed, the conductive line L1 is formed, and then the light emitting element is formed, so that the shielding electrode SE is located between the conductive line L1 and the first gate signal line SL1, and the shielding electrode SE is located between the conductive line L1 and the gate T10 of the driving transistor.

[0208] For example, a conductive line L1 is arranged in the auxiliary area, and a conductive line L1 is not arranged in an area of ​​the first display area other than the auxiliary area. Thus, the orthographic projection of the pixel circuit (first type of pixel circuit) in the area of ​​the first display area other than the auxiliary area on the substrate BS does not overlap with the orthographic projection of the conductive line L1 on the substrate BS.

[0209] For example, the orthographic projection of the conductive line L1 on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 in the pixel circuit of the first pixel unit 101 .

[0210] Reference 12C and Fig. 12BA buffer layer BL is provided on the substrate BS, an isolation layer BR is provided on the buffer layer BL, an active layer LY0 is provided on the isolation layer BR, a first insulating layer ISL1 is provided on the active layer LY0, a first conductive layer LY1 is provided on the first insulating layer ISL1, a second insulating layer ISL2 is provided on the first conductive layer LY1, a second conductive layer LY2 is provided on the second insulating layer ISL2, a third insulating layer ISL3 is provided on the second conductive layer LY2, a third conductive layer LY3 is provided on the third insulating layer ISL3, the third conductive layer LY3 includes a connecting electrode CE01, and the connecting electrode CE01 passes through the first insulating layer ISL1. The via H3 of the second insulating layer ISL2 and the third insulating layer ISL3 is connected to the second electrode T52 of the second light-emitting control transistor T5, the fourth insulating layer and the fifth insulating layer are arranged on the third conductive layer LY3, the fourth conductive layer LY4 is arranged on the fourth insulating layer and the fifth insulating layer, the fourth conductive layer LY4 includes a connecting electrode CE02, the connecting electrode CE02 is connected to the connecting electrode CE01 through the via H22 penetrating the fourth insulating layer and the fifth insulating layer, the sixth insulating layer is arranged on the fourth conductive layer LY4, and the light-emitting element 100b (the second region light-emitting element 30) is connected to the connecting electrode CE02 through the via hole penetrating the sixth insulating layer. The light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer located between the first electrode E1 and the second electrode E2. For example, the connecting element CE0 includes a connecting electrode CE01 and a connecting electrode CE02.

[0211] like Fig. 12B As shown, one end of the connection electrode CE1 is connected to the gate T10 of the driving transistor T1 through the via H1, and the other end of the connection electrode CE1 is connected to the second electrode T62 of the first reset transistor T6 through the via H2. One end of the connection electrode CE2 is connected to the first initialization signal line INL1 through the via H4, and the other end of the connection electrode CE2 is connected to the first electrode T61 of the first reset transistor T6 through the via H5. One end of the connection electrode CE3 is connected to the second initialization signal line INL2 through the via H6, and the other end of the connection electrode CE3 is connected to the first electrode T71 of the second reset transistor T7 through the via H7. The first power line PL1 is connected to the first electrode T41 of the first light-emitting control transistor T4 through the via H8. The first power line PL1 is connected to the second electrode Cb of the storage capacitor Cst through the via H9. The first power line PL1 is connected to the block BK through the via Hk. The data line DT is connected to the first electrode T21 of the data writing transistor T2 through the via H0.

[0212] For example, in the manufacturing process of the display panel, a self-alignment process is adopted to conduct the semiconductor pattern layer using the first conductive layer LY1 as a mask. The semiconductor pattern layer can be formed by patterning a semiconductor thin film. For example, the semiconductor pattern layer is heavily doped by ion implantation, so that the portion of the semiconductor pattern layer not covered by the first conductive layer LY1 is conductive, forming the source region (first electrode T11) and drain region (second electrode T12) of the driving transistor T1, the source region (first electrode T21) and drain region (second electrode T22) of the data writing transistor T2, the source region (first electrode T31) and drain region (second electrode T32) of the threshold compensation transistor T3, the source region (first electrode T41) and drain region (second electrode T42) of the first light emission control transistor T4, the source region (first electrode T51) and drain region (second electrode T52) of the second light emission control transistor T5, the source region (first electrode T61) and drain region (second electrode T62) of the first reset transistor T6, and the source region (first electrode T71) and drain region (second electrode T72) of the second reset transistor T7. The portion of the semiconductor pattern layer covered by the first conductive layer LY1 retains semiconductor characteristics, forming a channel region of the driving transistor T1, a channel region of the data writing transistor T2, a channel region of the threshold compensation transistor T3, a channel region of the first light emission control transistor T4, a channel region of the second light emission control transistor T5, a channel region of the first reset transistor T6, and a channel region of the second reset transistor T7. For example, Fig. 12B As shown, the second electrode T72 of the second reset transistor T7 and the second electrode T52 of the second light-emitting control transistor T5 are formed in one piece; the first electrode T51 of the second light-emitting control transistor T5, the second electrode T12 of the driving transistor T1 and the first electrode T31 of the threshold compensation transistor T3 are formed in one piece; the first electrode T11 of the driving transistor T1, the second electrode T22 of the data writing transistor T2 and the second electrode T42 of the first light-emitting control transistor T4 are formed in one piece; the second electrode T32 of the threshold compensation transistor T3 and the second electrode T62 of the first reset transistor T6 are formed in one piece. In some embodiments, Fig. 12B As shown, the first electrode T71 of the second reset transistor T7 and the first electrode T61 of the first reset transistor T6 can be formed integrally.

[0213] For example, the channel region of the transistor used in the embodiment of the present disclosure may be single crystal silicon, polycrystalline silicon (e.g., low temperature polycrystalline silicon) or metal oxide semiconductor material (e.g., IGZO, AZO, etc.). In one embodiment, the transistors are all P-type low temperature polycrystalline silicon (LTPS) thin film transistors. In another embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are metal oxide semiconductor thin film transistors, that is, the channel material of the transistor is a metal oxide semiconductor material (e.g., IGZO, AZO, etc.), and the metal oxide semiconductor thin film transistor has a lower leakage current, which can help reduce the gate leakage current of the driving transistor T1.

[0214] For example, the transistors used in the embodiments of the present disclosure may include a variety of structures, such as top-gate, bottom-gate or dual-gate structures. In one embodiment, the threshold compensation transistor T3 and the first reset transistor T6 directly connected to the gate of the driving transistor T1 are dual-gate thin film transistors, which can help reduce the gate leakage current of the driving transistor T1.

[0215] For example, the display panel further includes a pixel definition layer and a spacer, wherein the pixel definition layer has an opening, and the opening of the pixel definition layer is configured to define the light emitting area (light emitting area, effective light emitting area) of the pixel unit. The spacer is configured to support the fine metal mask when forming the light emitting functional layer.

[0216] For example, the opening of the pixel definition layer is the light emitting area of ​​the pixel unit. The light emitting functional layer is located on the first electrode E1 of the light emitting element 100b, and the second electrode E2 of the light emitting element 100b is located on the light emitting functional layer. For example, an encapsulation layer is provided on the light emitting element 100b. The encapsulation layer includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer. For example, the first encapsulation layer and the third encapsulation layer are inorganic material layers, and the second encapsulation layer is an organic material layer. For example, the first electrode E1 is the anode of the light emitting element 100b, and the second electrode E2 is the cathode of the light emitting element 100b, but is not limited thereto.

[0217] Fig.12D A layout diagram of a first type of pixel circuit or a second type of pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig.12D As shown, the orthographic projection of the gate T10 of the driving transistor T1 on the substrate BS falls within the orthographic projection of the shielding electrode SE on the substrate BS.

[0218] For example, Fig.12DAs shown, in the case where the display panel includes a second gate signal line SL2, the second gate signal line SL2 is connected to the first gate signal line SL1, and the orthographic projection of the second gate signal line SL2 on the substrate BS also falls within the orthographic projection of the shielding electrode SE on the substrate BS. For example, the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 1.75μm. For example, the distance that the boundary of the orthographic projection of the shielding electrode SE on the substrate BS exceeds the boundary of the orthographic projection of the second gate signal line SL2 on the substrate BS is greater than or equal to 2.33μm.

[0219] For example, Fig.12D As shown, the orthographic projections of the gate T10 of the driving transistor T1 , the first gate signal line SL1 , and the second gate signal line SL2 on the base substrate BS all fall within the orthographic projection of the shielding electrode SE on the base substrate BS.

[0220] For example, Fig.12D As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS. Fig.12D In the display panel shown, the shielding electrode SE and the block BK form a double-layer shielding for the second gate signal line SL2.

[0221] For example, Fig.12D As shown, the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the block BK on the base substrate BS.

[0222] Of course, in other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0223] Fig.12E A layout diagram of a first type of pixel circuit or a second type of pixel circuit in a display panel provided by an embodiment of the present disclosure. Fig.12E As shown, the fourth conductive layer LY4 further includes a third power line PL3, which is integrally formed with the shielding electrode SE. The third power line PL3 is connected to the first power line PL1 through a via H21 to form a parallel structure to reduce resistance. The third power line PL3 extends along the second direction Y. Fig.12EAs shown, the dimension of the third power line PL3 in the second direction Y is greater than the dimension of the shielding electrode SE in the second direction Y.

[0224] For example, Fig. 12B , Fig.12E As shown, the orthographic projection of the block BK on the base substrate BS partially overlaps with the orthographic projection of the second gate signal line SL2 on the base substrate BS, and the orthographic projection of the shielding electrode SE on the base substrate BS partially overlaps with the orthographic projection of the first gate signal line SL1 on the base substrate BS, so that the block BK and the shielding electrode SE together play a role in shielding the gate signal portion PT1. Of course, in some other embodiments, the block BK may not be provided, or the orthographic projection of the block BK on the base substrate BS does not overlap with the orthographic projection of the second gate signal line SL2 on the base substrate BS.

[0225] For example, Fig. 12B , Fig.12E As shown, the left block BK extends to the pixel unit on the left side of the pixel unit shown in the figure to block the conductive connection portion CP of its threshold compensation transistor T3, and the right block BK extends from the block BK connected to the pixel unit on the right side of the pixel unit shown in the figure.

[0226] like Fig. 12B , Fig.12D ,as well as Fig.12E As shown, the channels of each transistor and the first and second electrodes on both sides of the channels are located in the active layer LY0; the first reset control signal line RST1, the gate line GT, the gate T10 of the driving transistor (the first electrode Ca of the storage capacitor Cst), the light emitting control signal line EML and the second reset control signal line RST2 are located in the first conductive layer LY1; the first initialization signal line INL1, the second electrode Cb of the storage capacitor Cst, and the second initialization signal line INL2 are located in the second conductive layer LY2; the data line DT, the first power line PL1, the connecting electrode CE1, the connecting electrode CE2, the connecting electrode CE3, and the connecting electrode CE01 are located in the third conductive layer LY3; the shielding electrode SE is located in the fourth conductive layer LY4. Fig.12E As shown, the shielding electrode SE and the third power line PL3 are located in the fourth conductive layer LY4.

[0227] like Fig. 12B , Fig.12D ,as well as Fig.12E As shown, the first initialization signal line INL1, the first reset control signal line RST1, the gate line GT, the light emitting control signal line EML, the second initialization signal line INL2 and the second reset control signal line RST2 all extend along the first direction X. Fig. 12B , Fig.12D ,as well as Fig.12EAs shown, the data line DT and the first power line PL1 both extend along the second direction Y.

[0228] In the embodiments of the present disclosure, the orthographic projection of component A on substrate BS falls within the orthographic projection of component B on substrate BS means that the orthographic projection of component A on substrate BS completely falls within the orthographic projection of component B on substrate BS, that is, the orthographic projection of component A on substrate BS covers the orthographic projection of component B on substrate BS, and the area of ​​the orthographic projection of component A on substrate BS is less than or equal to the area of ​​the orthographic projection of component B on substrate BS.

[0229] For example, in some embodiments of the present disclosure, each pixel circuit 100a is provided with any shielding electrode SE as described above. That is, no matter the first type of pixel circuit 10 of the first pixel unit 101 or the second type of pixel circuit 20 of the second pixel unit 102, any shielding electrode SE as described above is provided. However, it is not limited thereto. For example, in some embodiments, no shielding electrode SE is provided in each pixel circuit 100a.

[0230] For example, the transistors in the pixel circuit of the embodiment of the present disclosure are all thin film transistors. For example, the first conductive layer LY1, the second conductive layer LY2, the third conductive layer LY3, and the fourth conductive layer LY4 are all made of metal materials. For example, the first conductive layer LY1 and the second conductive layer LY2 are formed of metal materials such as nickel and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are formed of materials such as titanium and aluminum, but not limited thereto. For example, the third conductive layer LY3 and the fourth conductive layer LY4 are respectively formed of three sub-layers of Ti / AL / Ti, but not limited thereto. For example, the substrate substrate can be a glass substrate or a polyimide substrate, but not limited thereto, and can be selected as needed. For example, the buffer layer BL, the isolation layer BR, the first insulating layer ISL1, the second insulating layer ISL2, the third insulating layer ISL3, the fourth insulating layer IS4, the fifth insulating layer, and the sixth insulating layer are all made of insulating materials. The materials of the first pole E1 and the second pole E2 of the light-emitting element can be selected as needed. In some embodiments, the first pole E1 can be made of at least one of a transparent conductive metal oxide and silver, but not limited thereto. For example, the transparent conductive metal oxide includes indium tin oxide (ITO), but is not limited thereto. For example, the first electrode E1 may adopt a structure in which three sub-layers of ITO-Ag-ITO are stacked. In some embodiments, the second electrode E2 may be a metal with a low work function, and may be at least one of magnesium and silver, but is not limited thereto.

[0231] For example, referring to the layout diagram and the cross-sectional diagram of the embodiments of the present disclosure, the display panel provided by at least one embodiment of the present disclosure may be manufactured by the following method.

[0232] (1) A buffer layer BL and a spacer layer BR are formed on a base substrate BS.

[0233] (2) A semiconductor thin film is formed on the isolation layer BR.

[0234] (3) Patterning the semiconductor film to form a semiconductor pattern layer.

[0235] (4) A first insulating film is formed on the semiconductor pattern layer.

[0236] (5) A first conductive film is formed on the first insulating film, and the first conductive film is patterned to form a first conductive layer LY1.

[0237] (6) The semiconductor pattern layer is doped using the first conductive layer LY1 as a mask to form an active layer LY0.

[0238] (7) A second insulating film is formed on the first conductive layer LY1.

[0239] (8) A second conductive film is formed on the second insulating layer ISL2, and the second conductive film is patterned to form a second conductive layer LY2.

[0240] (9) A third insulating film is formed on the second conductive layer LY2.

[0241] (10) At least one of the first insulating film, the second insulating film, and the third insulating film is patterned to form a first insulating layer ISL1, a second insulating layer ISL2, and a third insulating layer ISL3 while forming via holes.

[0242] (11) A third conductive film is formed and patterned to form a third conductive layer LY3. Each component in the third conductive layer LY3 is connected to the components located therebelow through via holes.

[0243] (12) A fourth insulating film and a fifth insulating film are formed and patterned, and the fourth insulating film and the fifth insulating film are formed while forming the via hole.

[0244] (13) A fourth conductive film is formed and patterned to form a fourth conductive layer LY4.

[0245] (14) At least one insulating layer is formed and at least one transparent conductive layer is formed, wherein the transparent conductive layer includes the conductive line L1.

[0246] (15) The first electrode E1 of the light-emitting element is formed.

[0247] (16) A pixel definition layer and a spacer layer PS are formed.

[0248] (17) Forming a light-emitting functional layer.

[0249] (18) The second electrode E2 of the light-emitting element is formed.

[0250] (19) Forming an encapsulation layer.

[0251] Of course, in the display panel provided by the embodiment of the present disclosure, the shielding electrode SE may not be provided.

[0252] At least one embodiment of the present disclosure provides a display device, comprising any one of the above-mentioned display panels.

[0253] Fig.13A and Fig. 13B Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.13A and Fig. 13B As shown, the sensor SS is located on one side of the display panel DS and in the second display area R2. Ambient light can pass through the second display area R2 and be sensed by the sensor SS. Fig. 13B As shown, the side of the display panel where no sensor SS is provided is the display side, which can display images. For example, the sensor includes a photosensitive sensor, and the photosensitive sensor is located on one side of the display panel.

[0254] For example, the second display area R2 may be a rectangle, and the area of ​​the orthographic projection of the sensor SS on the base substrate BS may be less than or equal to the area of ​​the inscribed circle of the second display area R2. That is, the size of the area where the sensor SS is located may be less than or equal to the size of the inscribed circle of the second display area R2. For example, the size of the area where the sensor SS is located is equal to the size of the inscribed circle of the second display area R2, that is, the shape of the area where the sensor SS is located may be a circle, and accordingly, the area where the sensor SS is located may also be called a light-transmitting hole. Of course, in some embodiments, the second display area R2 may also be other shapes besides a rectangle, such as a circle or an ellipse.

[0255] For example, the display device is a full-screen display device with an under-screen camera. For example, the display device includes OLED or a product including OLED. For example, the display device includes any product or component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a laptop computer, a navigator, etc., containing the above display panel.

[0256] Fig.14 for Fig. 12A The working timing diagram of the pixel circuit is shown in FIG. Fig.14As shown, in one frame display period, the driving method of the pixel unit includes a first reset stage t1, data writing and threshold compensation, a second reset stage t2, and a light emitting stage t3. When the reset control signal RESET is at a low level, the gate of the driving transistor T1 is reset, and when the scan signal SCAN is at a low level, the first electrode E1 (for example, anode) of the light emitting element 100b is reset. For example, Fig. 12A As shown, when the scan signal SCAN is at a low level, the data voltage VDATA is written, and the threshold voltage Vth of the driving transistor T1 is obtained at the same time, and the data voltage VDADA containing the data information on the data line is stored in the capacitor Cst; when the light-emitting control signal line EML is at a low level, the light-emitting element 100b emits light, and the voltage of the first node N1 (gate point) is maintained (the light-emitting stability of the light-emitting element 100b) by the storage capacitor Cst. In the driving process of the pixel circuit 10, in the light-emitting stage, the storage capacitor is used to maintain the voltage signal so that the potential of its signal holding end can be kept constant, and a voltage is formed between the gate and the source of the driving transistor, thereby controlling the driving transistor to form a driving current, and then driving the light-emitting element 100b to emit light.

[0257] like Fig.14 As shown, in the reset stage t1 , the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-on voltage, and the scan signal SCAN is set to a turn-off voltage.

[0258] like Fig.14 As shown, in the data writing and threshold compensation stage and the second reset stage t2, the light emitting control signal EM is set to a turn-off voltage, the reset control signal RESET is set to a turn-off voltage, and the scan signal SCAN is set to a turn-on voltage.

[0259] like Fig.14 As shown, in the light emitting stage t3, the light emitting control signal EM is set to an on voltage, the reset control signal RESET is set to an off voltage, and the scan signal SCAN is set to an off voltage.

[0260] like Fig.14 As shown, the first voltage signal ELVDD and the second voltage signal ELVSS are both constant voltage signals. For example, the initialization signal Vinit is between the first voltage signal ELVDD and the second voltage signal ELVSS.

[0261] For example, the turn-on voltage in the embodiments of the present disclosure refers to a voltage that can turn on the first and second electrodes of the corresponding transistor, and the turn-off voltage refers to a voltage that can turn off the first and second electrodes of the corresponding transistor. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V) and the turn-off voltage is a high voltage (e.g., 5V); when the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V) and the turn-off voltage is a low voltage (e.g., 0V). Fig.14 The driving waveforms shown are all described by taking a P-type transistor as an example. For example, the turn-on voltage is a low voltage (eg, 0V), and the turn-off voltage is a high voltage (eg, 5V), but it is not limited thereto.

[0262] Please also read Fig. 12A and Fig.14 , in the first reset stage t1, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-on voltage, and the scan signal SCAN is a turn-off voltage. At this time, the first reset transistor T6 is in a conducting state, while the second reset transistor T7, the data writing transistor T2, the threshold compensation transistor T3, the first light control transistor T4, and the second light control transistor T5 are in a turn-off state. The first reset transistor T6 transmits the first initialization signal (initialization voltage Vinit) Vinit1 to the gate of the driving transistor T1 and is stored by the storage capacitor Cst, resetting the driving transistor T1 and eliminating the data stored in the last (previous frame) light emission.

[0263] In the data writing and threshold compensation and second reset stage t2, the light control signal EM is a turn-off voltage, the reset control signal RESET is a turn-off voltage, and the scan signal SCAN is an on voltage. At this time, the data writing transistor T2 and the threshold compensation transistor T3 are in an on state, the second reset transistor T7 is in an on state, and the second reset transistor T7 transmits the second initialization signal (initialization voltage Vinit) Vinit2 to the first pole E1 of the light emitting element 100b to reset the light emitting element 100b. The first light emitting control transistor T4, the second light emitting control transistor T5, and the first reset transistor T6 are in an off state. At this time, the data writing transistor T2 transmits the data voltage VDATA to the first pole of the driving transistor T1, that is, the data writing transistor T2 receives the scan signal SCAN and the data voltage VDATA and writes the data voltage VDATA to the first pole of the driving transistor T1 according to the scan signal SCAN. The threshold compensation transistor T3 is turned on to connect the driving transistor T1 into a diode structure, thereby charging the gate of the driving transistor T1. After charging is completed, the gate voltage of the driving transistor T1 is VDATA+Vth, where VDATA is the data voltage and Vth is the threshold voltage of the driving transistor T1, that is, the threshold compensation transistor T3 receives the scan signal SCAN and performs threshold voltage compensation on the gate voltage of the driving transistor T1 according to the scan signal SCAN. At this stage, the voltage difference across the storage capacitor Cst is ELVDD-VDATA-Vth.

[0264] In the light-emitting stage t3, the light-emitting control signal EM is the on voltage, the reset control signal RESET is the off voltage, and the scan signal SCAN is the off voltage. The first light-emitting control transistor T4 and the second light-emitting control transistor T5 are in the on state, while the data writing transistor T2, the threshold compensation transistor T3, the first reset transistor T6 and the second reset transistor T7 are in the off state. The first voltage signal ELVDD is transmitted to the first electrode of the driving transistor T1 through the first light-emitting control transistor T4, and the gate voltage of the driving transistor T1 is maintained at VDATA+Vth. The light-emitting current I flows into the light-emitting element 100b through the first light-emitting control transistor T4, the driving transistor T1 and the second light-emitting control transistor T5, and the light-emitting element 100b emits light. That is, the first light-emitting control transistor T4 and the second light-emitting control transistor T5 receive the light-emitting control signal EM, and control the light-emitting element 100b to emit light according to the light-emitting control signal EM. The light-emitting current I satisfies the following saturation current formula:

[0265] K(Vgs-Vth) 2 =K(VDATA+Vth-ELVDD-Vth) 2 =K(VDATA-ELVDD) 2

[0266] in, μ n is the channel mobility of the driving transistor, Cox is the channel capacitance per unit area of ​​the driving transistor T1, W and L are the channel width and channel length of the driving transistor T1 respectively, and Vgs is the voltage difference between the gate and the source (ie, the first electrode of the driving transistor T1 in this embodiment) of the driving transistor T1.

[0267] It can be seen from the above formula that the current flowing through the light emitting element 100b has nothing to do with the threshold voltage of the driving transistor T1. Therefore, the pixel circuit can very well compensate for the threshold voltage of the driving transistor T1.

[0268] For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted. In this way, the light brightness can be controlled by adjusting the proportion of the duration of the light-emitting stage t3 in one frame display time period. For example, the proportion of the duration of the light-emitting stage t3 in one frame display time period can be adjusted by controlling the scanning drive circuit in the display panel or an additional drive circuit.

[0269] For example, the present disclosure is not limited to Fig. 12A The specific pixel circuit shown may adopt other pixel circuits that can realize compensation for the driving transistor. Based on the description and teaching of the implementation method disclosed in this disclosure, other configuration methods that can be easily thought of by ordinary technicians in this field without creative work are all within the protection scope of this disclosure.

[0270] The above description is made using a 7T1C pixel circuit as an example, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin-film transistors and the number of capacitors included in the pixel circuit. For example, in some other embodiments, the pixel circuit of the display panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure or a 9T2C structure, and the embodiments of the present disclosure do not limit this. Of course, the display panel may also include a pixel circuit with less than 7 transistors.

[0271] Normally, for example, the first initialization signal Vinit1 and the second initialization signal Vinit2 both use a constant voltage of -3V. In the display panel provided in some embodiments of the present disclosure, the second initialization signal Vinit2 can be a constant voltage greater than or equal to -2V, that is, the second initialization signal Vinit2 is increased from -3V to -2V or above -2V, thereby increasing the light-emitting time of the first light-emitting element and improving the display defect. In the case where the display panel has a fourth light-emitting element, the light-emitting time of the first light-emitting element and the fourth light-emitting element is increased. For example, the light-emitting time of the first light-emitting element and the fourth light-emitting element can be increased by 12%.

[0272] In the related art, the pixel circuit (including the first type of pixel circuit 10 and the second type of pixel circuit 20) and the first area light emitting element 30 have the same size (pitch). For example, the general width is about 30 micrometers (μm) to 32μm, and the length is about 60μm to 65μm. In the embodiment of the present disclosure, in order to provide sufficient space for the arrangement of the second type of pixel circuit 20 without reducing the number of pixels in the first display area R1, each pixel circuit can be compressed along the first direction X (such as the gate line extension direction, which can also be called the horizontal direction) so that the width of the pixel circuit in the first direction is smaller than the width of the first area light emitting element 30; or, the first area light emitting element 30 can be extended along the first direction X so that the width of the first area light emitting element 30 in the first direction X is larger than the width of the first area light emitting element 30. In this way, under the premise that the size of the substrate BS is the same, more areas can be provided in the first display area R1, and accordingly, the second type of pixel circuit 20 for driving the second light emitting element 40 located in the second display area R2 can be provided in the more areas.

[0273] For example, the width of each pixel circuit may differ from the width of the first region light emitting element 30 by about 4 μm. Taking the compressed pixel circuit and the width difference of 4 μm as an example, Fig.15 The structure of the pixel circuit before and after compression is shown. Fig.15It can be seen that the pixel circuit may include a driving structure and a connecting element CE0 for connecting to the first pole (anode) of the light-emitting element, and the size of the connecting element CE0 may represent the size of the pixel circuit. The sizes of the pixel circuit and the light-emitting element before compression are both 1-100 μm in width and 2-100 μm in height. The size of the light-emitting element after compression may remain unchanged compared to that before compression. For example, the size of the second-region light-emitting element 40 may be equal to or less than the size of the first-region light-emitting element 20. The height of the compressed pixel circuit remains unchanged, but the width is narrowed by 1-20 μm. In this way, one or more columns of compressed pixel circuits will be added every few columns of compressed pixel circuits, and this design is adopted for the entire screen to achieve full-screen compression. Among them, these extra columns can be selected to connect the second-region light-emitting element 40 in the second display area R2 to control the second-region light-emitting element 40 to emit light. In some embodiments, the extra column pixel circuits near the periphery of the second display area R2 are selected as the second type of pixel circuit 20 connected to the second-region light-emitting element 40. In this way, normal display can be achieved without changing the resolution of the display panel. That is, the existing space of the display panel is fully utilized to achieve normal display. The effect achieved by compressing the size of the pixel circuit is that the number of light-emitting elements (including the first region light-emitting elements 30 and the second light-emitting elements 40) remains unchanged, and thus, there is no obvious difference in display effect compared with before compression, and the display effect of the display panel is better.

[0274] In the embodiments of the present disclosure, the components located in the same layer may be formed by the same film layer through the same patterning process. For example, the components located in the same layer may be located on a surface of the same component away from the base substrate.

[0275] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layer or region is exaggerated. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element, or there may be an intermediate element.

[0276] In the embodiments of the present disclosure, the patterning or patterning process may include only the photolithography process, or include the photolithography process and the etching step, or may include other processes such as printing and inkjetting for forming a predetermined pattern. The photolithography process refers to a process including film formation, exposure, and development, and a pattern is formed using a photoresist, a mask, an exposure machine, etc. The corresponding patterning process can be selected according to the structure formed in the embodiments of the present disclosure.

[0277] In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0278] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, comprising: A base substrate having a first display area and a second display area, wherein the first display area is located on at least one side of the second display area; A plurality of light-emitting elements, located in the first display area and the second display area, the plurality of light-emitting elements include a plurality of groups of light-emitting elements, the light-emitting elements in each group of the plurality of groups of light-emitting elements are arranged along a first direction, the plurality of groups of light-emitting elements are arranged along a second direction, at least one group of the plurality of groups of light-emitting elements includes a plurality of first-region light-emitting elements and a plurality of second-region light-emitting elements, the plurality of first-region light-emitting elements are located in the first display area, and the plurality of second-region light-emitting elements are located in the second display area; a plurality of pixel circuits, located in the first display area, the plurality of pixel circuits comprising a plurality of groups of pixel circuits, the pixel circuits in each group of the plurality of groups of pixel circuits being arranged along the first direction, the plurality of groups of pixel circuits being arranged along the second direction, at least one group of the plurality of groups of pixel circuits comprising a plurality of first-type pixel circuits and a plurality of second-type pixel circuits, the plurality of second-type pixel circuits being distributed at intervals between the plurality of first-type pixel circuits, At least one of the plurality of first-type pixel circuits is connected to at least one of the plurality of first-region light-emitting elements, and an orthographic projection of the at least one first-type pixel circuit on the substrate at least partially overlaps with an orthographic projection of the at least one first-region light-emitting element on the substrate; At least one second type pixel circuit among the plurality of second type pixel circuits is connected to at least one second area light emitting element among the plurality of second area light emitting elements through a conductive line; The plurality of second-region light-emitting elements include a plurality of first light-emitting elements and a plurality of second light-emitting elements, wherein the first light-emitting elements are configured to emit light of a first color, and the second light-emitting elements are configured to emit light of a second color, The plurality of second-type pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits, The conductive wires include a plurality of first conductive wires and a plurality of second conductive wires, the plurality of first light-emitting elements are connected to the plurality of first pixel circuits through the plurality of first conductive wires, and the plurality of second light-emitting elements are connected to the plurality of second pixel circuits through the plurality of second conductive wires. In the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first light-emitting elements are closer to the second display area than each of the plurality of second pixel circuits connected to the plurality of second light-emitting elements. A light emitting area of ​​each of the plurality of first-region light emitting elements is larger than a light emitting area of ​​at least one of the plurality of second-region light emitting elements.

2. The display panel according to claim 1, wherein: In the at least one group of light-emitting elements and the at least one group of pixel circuits, no other second-type pixel circuits are arranged between two first pixel circuits connected to two adjacent first conductive lines.

3. The display panel according to claim 1, wherein: One end of the conductive line is connected to the second-region light-emitting element, and the other end of the conductive line is connected to the second-type pixel circuit through a connecting element.

4. The display panel according to claim 1, wherein: In the at least one group of light emitting elements and the at least one group of pixel circuits, at least one of the plurality of first-type pixel circuits is disposed between two adjacent second-type pixel circuits.

5. The display panel according to claim 4, wherein: In the at least one group of light-emitting elements and the at least one group of pixel circuits, the multiple first pixel circuits connected to the multiple first conductive lines are arranged at intervals among the multiple first-type pixel circuits, and the multiple second pixel circuits connected to the multiple second conductive lines are arranged at intervals among the multiple first-type pixel circuits.

6. The display panel according to any one of claims 1 to 5, wherein: The orthographic projection of a portion of one of the plurality of first conductive lines extending along the first direction on the substrate substrate at least partially overlaps with the orthographic projection of a portion of another first conductive line of a different layer from the first conductive line extending along the first direction on the substrate substrate, or the orthographic projection of a portion of one of the plurality of first conductive lines extending along the first direction on the substrate substrate at least partially overlaps with the orthographic projection of a portion of one of the plurality of fourth conductive lines of a different layer from the first conductive line extending along the first direction on the substrate substrate.

7. The display panel according to any one of claims 1 to 5, wherein: The plurality of second region light emitting elements further include a plurality of third light emitting elements, wherein the third light emitting elements are configured to emit light of a third color. The plurality of second-type pixel circuits further include a plurality of third pixel circuits, The conductive wires further include a plurality of third conductive wires, and the plurality of third light emitting elements are connected to the plurality of third pixel circuits through the plurality of third conductive wires. In the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of first pixel circuits connected to the plurality of first conductive lines are closer to the second display area than each of the plurality of third pixel circuits connected to the plurality of third conductive lines. In the at least one group of light emitting elements and the at least one group of pixel circuits, the plurality of second pixel circuits connected to the plurality of second conductive lines and the plurality of third pixel circuits connected to the plurality of third conductive lines are alternately arranged.

8. The display panel according to claim 7, wherein: The plurality of second region light emitting elements further include a plurality of fourth light emitting elements, wherein the fourth light emitting elements are configured to emit fourth color light. The plurality of second-type pixel circuits further include a plurality of fourth pixel circuits, The conductive wires further include a plurality of fourth conductive wires, and the plurality of fourth light emitting elements are connected to the plurality of fourth pixel circuits through the plurality of fourth conductive wires. In the at least one group of light-emitting elements and the at least one group of pixel circuits, the plurality of fourth pixel circuits connected to the plurality of fourth conductive lines are closer to the second display area than each of the plurality of second pixel circuits connected to the plurality of second conductive lines.

9. The display panel according to claim 8, wherein: The plurality of fourth pixel circuits connected to the plurality of fourth conductive lines and the plurality of first pixel circuits connected to the plurality of first conductive lines are alternately arranged, An orthographic projection of a portion of one of the plurality of second conductive lines extending along the first direction on the substrate at least partially overlaps an orthographic projection of a portion of one of the plurality of third conductive lines on a different layer from the second conductive line extending along the first direction on the substrate.

10. The display panel according to claim 8 or 9, wherein: At least one of the plurality of groups of light emitting elements includes a first subgroup of light emitting elements, a second subgroup of light emitting elements, and a third subgroup of light emitting elements sequentially arranged along the first direction, at least one of the plurality of groups of pixel circuits includes a first subgroup of pixel circuits to a seventh subgroup of pixel circuits sequentially arranged along the first direction, the seventh subgroup of pixel circuits being closer to the second display area than the first subgroup of pixel circuits, The conductive wires connected to the first subgroup of light-emitting elements are located in the third pattern layer, the conductive wires connected to the second subgroup of light-emitting elements are located in the second pattern layer, the conductive wires connected to the third subgroup of light-emitting elements include conductive wires located in the first pattern layer and also include conductive wires formed in segments, the conductive wires formed in segments include a first conductive portion located in the first pattern layer and a second conductive portion located in the second pattern layer, The second light-emitting element and the third light-emitting element in the first subset of light-emitting elements are connected to the second subset of pixel circuits, the second light-emitting element and the third light-emitting element in the second subset of light-emitting elements are connected to the first subset of pixel circuits, the second light-emitting element and the third light-emitting element in the third subset of light-emitting elements close to the second subset of light-emitting elements are connected to the fourth subset of pixel circuits, the second light-emitting element and the third light-emitting element in the third subset of light-emitting elements far from the second subset of light-emitting elements are connected to the third subset of pixel circuits, the first light-emitting element and the fourth light-emitting element in the first subset of light-emitting elements are connected to the seventh subset of pixel circuits, the first light-emitting element and the fourth light-emitting element in the second subset of light-emitting elements are connected to the sixth subset of pixel circuits, and the first light-emitting element and the fourth light-emitting element in the third subset of light-emitting elements are connected to the fifth subset of pixel circuits.

11. The display panel according to claim 10, wherein: The orthographic projection of a portion of the second conductive line extending along the first direction on the substrate at least partially overlaps with the orthographic projection of a portion of a third conductive line located in a different layer from the second conductive line extending along the first direction on the substrate, The portion of the conductive line connected to the second subset of light emitting elements extending along the first direction does not overlap with the portion of other conductive lines extending along the first direction.

12. The display panel according to claim 10, wherein: The portion of the conductive line connected to the second sub-group pixel circuit extending along the first direction overlaps with the portion of the conductive line connected to the fourth sub-group pixel circuit extending along the first direction, and the portion of the conductive line connected to the first sub-group pixel circuit extending along the first direction does not overlap with the portion of the conductive line connected to the second sub-group pixel circuit extending along the first direction, and does not overlap with the portion of the conductive line connected to the fourth sub-group pixel circuit extending along the first direction.

13. The display panel according to claim 8 or 9, wherein: The fourth light emitting element and the first light emitting element are configured to emit light of the same color, The fourth light-emitting element and the first light-emitting element are configured to emit green light, one of the second light-emitting element and the third light-emitting element is configured to emit red light, and the other of the second light-emitting element and the third light-emitting element is configured to emit blue light.

14. The display panel according to any one of claims 1 to 5, wherein: The second display area is axisymmetric, having a first axis of symmetry extending along the first direction and a second axis of symmetry extending along the second direction, the conductive lines are provided in a plurality, the plurality of conductive lines are axisymmetric with respect to the first axis of symmetry and are axisymmetric with respect to the second axis of symmetry, The plurality of second-region light-emitting elements are axisymmetric with respect to the first symmetry axis and are axisymmetric with respect to the second symmetry axis.

15. The display panel according to any one of claims 1 to 5, wherein: The first display area includes an auxiliary area, the plurality of second-type pixel circuits are located in the auxiliary area, and the area of ​​the auxiliary area is smaller than the area of ​​the first display area except the auxiliary area. In the auxiliary area, an orthographic projection of the conductive line on the base substrate partially overlaps with an orthographic projection of the first type of pixel circuit on the base substrate.

16. The display panel according to claim 15, wherein: A size of the first type of pixel circuit in the first direction is smaller than a size of the first area light emitting element in the first direction.

17. The display panel according to any one of claims 1 to 5, wherein: The second display area includes a light-transmitting area, a resolution of the first display area is the same as a resolution of the second display area, and a density of light-emitting elements in the first area is the same as a density of light-emitting elements in the second area.

18. The display panel according to any one of claims 1 to 5, wherein: The pixel circuit includes a driving transistor and a reset transistor, and the display panel also includes a reset control signal line, the gate of the reset transistor is connected to the reset control signal line, the first electrode of the reset transistor is connected to the initialization signal line, the second electrode of the reset transistor is connected to the first electrode of the light-emitting element, and the initialization signal line is configured to provide a constant voltage, and the constant voltage is greater than or equal to -2V.

19. A display device comprising the display panel according to any one of claims 1-18.

20. The display device according to claim 19, further comprising a light-sensitive sensor, wherein: The photosensor is located on one side of the display panel.

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