Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate, a data signal line, a data fan-out line and a conductive structure, the conductive structure comprises a plurality of first power lines, a plurality of second power lines and a plurality of switching electrodes, and the first power lines extend in the first direction and are arranged in the second direction; the plurality of second power supply wires extend along the second direction and are arranged along the first direction, and the plurality of first power supply wires and the plurality of second power supply wires are connected through the switching electrodes and form a net structure for transmitting low-level signals; orthographic projections of the plurality of first power supply wires and the plurality of second power supply wires on the substrate form a plurality of overlapping regions; the second region comprises a plurality of sub-regions, each sub-region has the arrangement density of the switching electrodes, the arrangement density of the switching electrodes of the plurality of sub-regions is gradually increased in the direction away from the first region, and the arrangement density of the switching electrodes is the ratio of the number of the switching electrodes in the sub-region to the number of the overlapping regions; the brightness difference in a screen turn-off state can be avoided.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and thin film transistors (TFT) for signal control have become the mainstream products in the current display field.

[0003] Currently, some display substrates have a brightness difference problem when the screen is in the off state. Summary of the invention

[0004] The embodiments of the present disclosure provide a display substrate and a display device, which can solve the problem of brightness difference of the screen in the screen-off state existing in the existing display substrate.

[0005] In one aspect, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] A substrate, comprising a display area, wherein the display area comprises a first area and a second area;

[0007] A plurality of data signal lines are located in the display area, and the plurality of data signal lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects with the second direction and the plane formed by the first direction is parallel to the plane where the substrate is located;

[0008] a plurality of data fan-out lines, located in the first area and connected to the data signal lines;

[0009] A conductive structure, located in the second area, the conductive structure comprising a plurality of first power lines, a plurality of second power lines and a plurality of switching electrodes, the plurality of first power lines extending along the first direction and arranged at intervals along the second direction; the plurality of second power lines extending along the second direction and arranged at intervals along the first direction, and the plurality of first power lines and the plurality of second power lines are connected to each other via the switching electrodes to form a mesh structure for transmitting low-level signals; the plurality of first power lines and the plurality of second power lines are orthographically projected on the plane where the substrate is located to form a plurality of overlapping areas;

[0010] The second region includes multiple sub-regions, each of which has an arrangement density of the switching electrodes. The arrangement density of the switching electrodes in the multiple sub-regions gradually increases in the direction away from the first region, and the arrangement density of the switching electrodes is the ratio of the number of the switching electrodes in the sub-region to the number of the overlapping regions.

[0011] In some exemplary embodiments, the arrangement density of the switching electrodes in the sub-region farthest from the first region among the plurality of sub-regions is 1.0.

[0012] In some exemplary embodiments, an arrangement density of the switching electrodes in the sub-region adjacent to the first region among the plurality of sub-regions is greater than or equal to 0 and less than or equal to 0.7.

[0013] In some exemplary embodiments, a difference in arrangement density of the switching electrodes in any group of two adjacent sub-regions among the plurality of sub-regions is less than or equal to 0.7.

[0014] In some exemplary embodiments, a plurality of sub-pixels are further included, and the plurality of sub-pixels are located in the display area; the plurality of sub-pixels at least include a red sub-pixel, a blue sub-pixel, and a green sub-pixel, the red sub-pixel is configured to emit red light, the blue sub-pixel is configured to emit blue light, and the green sub-pixel is configured to emit green light;

[0015] In the second region, the plurality of overlapping regions are arranged in groups with the plurality of sub-pixels one by one; or, one overlapping region is arranged in a group with two sub-pixels.

[0016] In some exemplary embodiments, the first power line and the switching electrode are located in the same conductive layer and are an interconnected integral structure, the second power line and the first power line are located in a different conductive layer, and the orthographic projections of the second power line and the switching electrode on the plane where the substrate is located at least partially overlap.

[0017] In some exemplary embodiments, an orthographic projection of at least one of the second power traces on the plane where the substrate is located includes an orthographic projection of the transfer electrode on the plane where the substrate is located.

[0018] In some exemplary embodiments, at least one light-shielding portion is further included, and the light-shielding portion is located on a side of the conductive structure away from the substrate, and the light-shielding portion at least partially overlaps with the orthographic projection of the conductive structure on the plane where the substrate is located; in the visible light range, the reflectivity of the light-shielding portion is less than the reflectivity of the conductive structure.

[0019] In some exemplary embodiments, an orthographic projection of at least one of the light shielding portions on the plane where the substrate is located includes an orthographic projection of the switching electrode on the plane where the substrate is located.

[0020] In some exemplary embodiments, a plurality of sub-pixels are further included, and the plurality of sub-pixels are located in the display area; the plurality of sub-pixels include at least red sub-pixels, blue sub-pixels and green sub-pixels, the red sub-pixels are configured to emit red light, the blue sub-pixels are configured to emit blue light, and the green sub-pixels are configured to emit green light; each of the sub-pixels includes a light-emitting device, and the light-emitting device is located on a side of the conductive structure away from the substrate; the light-emitting device includes a stacked anode, an organic light-emitting layer and a cathode, and the light-shielding portion and the anode are located on the same conductive layer.

[0021] In some exemplary embodiments, the light shielding portion and the anode of the red sub-pixel are an integrated structure connected to each other, or the light shielding portion and the anode of the blue sub-pixel are an integrated structure connected to each other.

[0022] In some exemplary embodiments, at least one of the second power supply lines is located between two adjacent data signal lines.

[0023] In some exemplary embodiments, the light shielding portion and the anode of the green sub-pixel are an integrated structure connected to each other.

[0024] In some exemplary embodiments, at least two adjacent second power lines are respectively located on two sides of two adjacent data signal lines along the first direction.

[0025] On the other hand, an embodiment of the present disclosure provides a display device, comprising the display substrate described in any one of the aforementioned embodiments.

[0026] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0028] Figure 1 is a structural schematic diagram of a display device;

[0029] Figure 2 It is a structural schematic diagram of a display substrate;

[0030] Figure 3 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0031] Figure 4A for Figure 3 A partial enlarged schematic diagram of an embodiment at the position marked A in FIG.

[0032] Figure 4B for Figure 3 A partial enlarged schematic diagram of another embodiment at the mark A in FIG.

[0033] Figure 5A It is a partial enlarged schematic plan view of an overlapping area of ​​a display substrate according to an embodiment of the present disclosure;

[0034] Figure 5B for Figure 5A A cross-sectional view at the position marked BB;

[0035] Figure 5C is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 6 It is a partial enlarged schematic plan view of an overlapping region of a display substrate according to another embodiment of the present disclosure;

[0037] Fig. 7A It is a partial enlarged schematic plan view of an overlapping region of a display substrate according to another embodiment of the present disclosure;

[0038] Figure 7B for Fig. 7A A cross-sectional view at the position marked CC;

[0039] Figure 7C is a partial cross-sectional schematic diagram of an overlapping area of ​​a display substrate according to another embodiment of the present disclosure;

[0040] Figure 8 It is a partial enlarged schematic plan view of an overlapping area of ​​a display substrate according to another embodiment of the present disclosure;

[0041] Fig. 9 It is a partial enlarged schematic diagram of an anode layer of a display substrate according to an embodiment of the present disclosure;

[0042] Fig.10 It is a partial enlarged plan view of an anode layer of a display substrate according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person of ordinary skill in the art can easily understand the fact that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0044] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0045] The ordinal numbers such as "first", "second", and "third" in the present disclosure are provided to avoid confusion of constituent elements, rather than to limit the quantity. The "plurality" in the present disclosure includes two and more than two.

[0046] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which the constituent elements are described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0047] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0048] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0049] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0050] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0051] In the present disclosure, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° may be included. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0052] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0053] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0054] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using a clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller, where m may be a natural number. For example, the scan driver may sequentially provide a scan signal having a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo, where o may be a natural number. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner that sequentially transmits an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0055] Figure 2 FIG. 1 is a schematic diagram of the structure of a display substrate. Figure 2As shown, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. The display area 100 may include a plurality of sub-pixels, a plurality of data signal lines D, and a plurality of data fan-out lines 400, and the plurality of data signal lines D may extend along the second direction Y and be arranged at intervals along the first direction X. Each sub-pixel may include a circuit unit and a light-emitting unit, the circuit unit may include at least a pixel driving circuit, the light-emitting unit may include at least a light-emitting device, and the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0056] The display substrate may adopt a structure in which the fanout line is located in the panel (Fanout in Panel, referred to as FIP), and a plurality of data fanout lines 400 are arranged in the display area 100, one end of the plurality of data fanout lines 400 is correspondingly connected to a plurality of data signal lines D in the display area 100, and the other end of the plurality of data fanout lines 400 may be located in the binding area 200, and is correspondingly connected to the integrated circuit through a plurality of data lead lines. Since the binding area can reduce the number of fan-shaped oblique routing lines, the width of the binding area in the second direction Y is reduced, and the width of the lower frame of the display substrate is reduced, which is conducive to the narrow frame design of the display substrate.

[0057] At present, a display substrate with a fan-out in panel (FIP) structure is used. Since data fan-out lines are added in local areas of the display area, uneven surface reflected light occurs between areas of the display area where data fan-out lines are set and areas where data fan-out lines are not set, resulting in brightness differences on the display substrate when the screen is off.

[0058] Therefore, an embodiment of the present disclosure provides a display substrate, including:

[0059] A substrate, comprising a display area, wherein the display area comprises a first area and a second area;

[0060] A plurality of data signal lines are located in the display area, and the plurality of data signal lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects with the second direction and the plane formed by the first direction is parallel to the plane where the substrate is located;

[0061] a plurality of data fan-out lines, located in the first area and connected to the data signal lines;

[0062] A conductive structure, located in the second area, the conductive structure comprising a plurality of first power lines, a plurality of second power lines and a plurality of switching electrodes, the plurality of first power lines extending along the first direction and arranged at intervals along the second direction; the plurality of second power lines extending along the second direction and arranged at intervals along the first direction, and the plurality of first power lines and the plurality of second power lines are connected to each other via the switching electrodes to form a mesh structure for transmitting low-level signals; the plurality of first power lines and the plurality of second power lines are orthographically projected on the plane where the substrate is located to form a plurality of overlapping areas;

[0063] The second region includes multiple sub-regions, each of which has an arrangement density of the switching electrodes. The arrangement density of the switching electrodes in the multiple sub-regions gradually increases in the direction away from the first region, and the arrangement density of the switching electrodes is the ratio of the number of the switching electrodes in the sub-region to the number of the overlapping regions.

[0064] In the embodiment of the present disclosure, by configuring the second region to include a plurality of sub-regions, and limiting the arrangement density of the switching electrodes in the plurality of sub-regions to gradually increase in a direction away from the first region, a sudden change in the reflection area between the first region and the second region can be avoided, thereby improving the uniformity of the reflected light on the surface of the display substrate and improving the display quality.

[0065] Figure 3 FIG. 1 is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure. Figure 3 As shown, the display substrate includes a substrate, and the substrate includes a display area AA and a peripheral area BB surrounding the display area AA. The display area AA may include at least a first area AA1 and a second area AA2, the first area AA1 and the second area AA2 do not overlap each other, and the second area AA2 may surround at least one side of the first area AA1. The second area AA2 may include a plurality of sub-areas, and for example, the second area AA2 may include two sub-areas, the two sub-areas being a first sub-area AA2-1 and a second sub-area AA2-2.

[0066] The display substrate may include a plurality of sub-pixels located in the display area AA, a plurality of data signal lines DL, and a plurality of data fan-out lines 10, wherein the data fan-out line 10 may include a first end and a second end disposed oppositely, wherein the first end may be connected to the data signal line DL, and the second end may be close to the peripheral area BB relative to the first end. The data fan-out line 10 may include a first fan-out line 11 and a second fan-out line 12 connected to each other, wherein the first fan-out line 11 may extend along a first direction X, and the second fan-out line 12 may extend along a second direction Y. The first fan-out line 11 and the second fan-out line 12 each include a first end and a second end disposed oppositely, wherein the first end of the first fan-out line 11 may be connected to the data signal line DL, the second end of the first fan-out line 11 may be connected to the first end of the second fan-out line 12, and the second end of the second fan-out line 12 may be located in the peripheral area BB. Each sub-pixel may include a circuit unit and a light-emitting unit, wherein the circuit unit may include at least a pixel driving circuit, and the light-emitting unit may include at least a light-emitting device, wherein the pixel driving circuit is configured to output a corresponding current to the connected light-emitting device. The light emitting device is connected to the pixel driving circuit of the corresponding circuit unit, and the light emitting device is configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit. The plurality of data signal lines DL may extend along the second direction Y and be arranged at intervals along the first direction X, and the first direction X intersects with the second direction Y and the plane formed by them is parallel to the plane where the substrate is located. Figure 3 As shown, only fifteen data signal lines DL and six data fan-out lines 10 are schematically shown. A plurality of data fan-out lines 10 are located in the first area AA1.

[0067] The display substrate may further include a conductive structure 20, which may be used to transmit low-level signals. The display substrate may adopt a SIP (VSS In Pixel) design, and the conductive structure 20 is connected in the second area AA2 to form a mesh structure, which can reduce the voltage drop of the low-level signal in the display area, improve the uniformity of the voltage distribution, improve the display effect of the display device, and reduce the display power consumption. The structure combining the SIP design and the FIP design can improve the uniformity of the reflected light on the surface of the display substrate to a certain extent, and reduce the brightness difference problem of the display substrate in the off-screen state.

[0068] like Figure 3As shown, the conductive structure 20 may include a plurality of first power lines 21 and a plurality of second power lines 22, and the plurality of first power lines 21, the plurality of second power lines 22 and the plurality of data signal lines DL are illustrated with different line types for easy identification. The plurality of first power lines 21 may extend along the first direction X and be arranged at intervals along the second direction Y. The plurality of second power lines 22 may extend along the second direction Y and be arranged at intervals along the first direction X. The first power line 21 and the second power line 22 are located in different conductive layers. For example, the first power line 21 may be closer to the substrate than the second power line 22. For example, the first power line 21 may be located in the first source-drain metal layer (SD1), and the second power line 22 may be located in the second source-drain metal layer (SD2). Alternatively, the first power line 21 may be located in the second source-drain metal layer (SD2), and the second power line 22 may be located in the third source-drain metal layer (SD3). The first power line 21 and the first fan-out line 11 may be located in the same conductive layer. The second power line 22 and the second fan-out line 12 may be located in the same conductive layer.

[0069] In some exemplary embodiments, the display substrate may further include a power supply line VSS, the power supply line VSS is located in the peripheral area BB, and at least a portion of the power supply line VSS may surround the display area AA. The power supply line VSS is configured to transmit a low-level signal. At least a portion of the first power supply lines 21 of the plurality of first power supply lines 21 is connected to the power supply line VSS. At least a portion of the second power supply lines 22 of the plurality of second power supply lines 22 is connected to the power supply line VSS. In the disclosed embodiment, connecting the conductive structure 20 to the power supply line VSS can improve the uniformity of the low-level distribution.

[0070] In some exemplary embodiments, Figure 3 As shown, the peripheral area BB may include multiple border areas, and the multiple border areas may include a first border area B1 located on one side of the display area AA, and a second border area B2 arranged opposite to the first border area B1. Along the second direction Y, the first border area B1 and the second border area B2 are respectively located on both sides of the display area AA.

[0071] The plurality of frame regions may further include a third frame region B3 located on one side of the display region AA, and a fourth frame region B4 disposed opposite to the third frame region B3, and the third frame region B3 and the fourth frame region B4 are respectively located on both sides of the display region AA along the first direction X. In the disclosed embodiment, the first frame region B1 may also be referred to as the lower frame of the display substrate, the second frame region B2 may also be referred to as the upper frame of the display substrate, the third frame region B3 may also be referred to as the left frame of the display substrate, and the fourth frame region B4 may also be referred to as the right frame of the display substrate.

[0072] The peripheral area BB may further include at least one transition area, and at least one group of two adjacent frame areas are connected via a transition area. At least a portion of the boundary of at least one transition area close to the display area AA may be an arc-shaped boundary. Figure 3 In the figure, the peripheral area BB includes four transition areas, which are respectively the first transition area G1, the second transition area G2, the third transition area G3 and the fourth transition area G4. The first transition area G1 is located between the first frame area B1 and the third frame area B3, and the first frame area B1 and the third frame area B3 are connected via the first transition area G1. The second transition area G2 is located between the first frame area B1 and the fourth frame area B4, and the first frame area B1 and the fourth frame area B4 are connected via the second transition area G2. The third transition area G3 is located between the second frame area B2 and the fourth frame area B4, and the second frame area B2 and the fourth frame area B4 are connected via the third transition area G3. The fourth transition area G4 is located between the second frame area B2 and the third frame area B3, and the second frame area B2 and the third frame area B3 are connected via the fourth transition area G4.

[0073] Figure 4A for Figure 3 A partial enlarged schematic diagram of an embodiment of the invention is shown in FIG. Figure 4B for Figure 3 A partial enlarged schematic diagram of another embodiment at the mark A in FIG. Figure 4A , Figure 4BAs shown, the display area AA of the display substrate may include a plurality of pixel units arranged in a rectangular manner, at least one pixel unit may include a plurality of sub-pixels, and the plurality of sub-pixels may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit, the light-emitting unit may include at least a light-emitting device, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output the corresponding current to the light-emitting device. The light-emitting devices are respectively connected to the pixel driving circuits of the sub-pixels in which they are located, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which they are located. The first sub-pixel P1 is configured to emit a first color light, the second sub-pixel P2 and the fourth sub-pixel P4 are configured to emit a second color light, and the third sub-pixel P3 is configured to emit a third color light. For example, the first color may be red, the second color may be green, and the third color may be blue. Alternatively, the first color may be blue, and the third color may be red. Alternatively, the second sub-pixel P2 is configured to emit a second color light, and the fourth sub-pixel P4 is configured to emit a white light.

[0074] like Figure 4A As shown, a plurality of first power lines 21 may extend along a first direction X, and may be arranged at intervals along a second direction Y. A plurality of second power lines 22 may extend along a second direction Y, and may be arranged at intervals along the first direction X. In the second region, the orthographic projections of the plurality of first power lines 21 and the plurality of second power lines 22 on the plane where the substrate is located form a plurality of overlapping regions JD, and the plurality of overlapping regions JD are arranged in groups with the plurality of sub-pixels one by one, and the overlapping regions JD at least partially overlap with the orthographic projections of the sub-pixels on the plane where the substrate is located. For example, the overlapping regions JD are located within the orthographic projections of the sub-pixels arranged in groups on the plane where the substrate is located. Alternatively, an overlapping region JD is arranged in a group with two sub-pixels, and the overlapping region JD at least partially overlaps with the orthographic projections of the sub-pixels on the plane where the substrate is located. For example, the overlapping region JD is located within the orthographic projections of the sub-pixels arranged in groups on the plane where the substrate is located, as shown in FIG. Figure 4B shown.

[0075] In some exemplary embodiments, at least one pixel unit may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light.

[0076] In some exemplary embodiments, the orthographic projection of the sub-pixel on the plane where the substrate is located may be a rectangle, a diamond, a pentagon, or a hexagon.

[0077] Figure 5AFIG. 1 is a partial enlarged schematic plan view of an overlapping region of a display substrate according to an embodiment of the present disclosure. Figure 5B for Figure 5A The cross-sectional view at the position marked BB in FIG. Figure 5A As shown, only a portion of the first source-drain metal layer (SD1) and the second source-drain metal layer (SD2) is schematically shown, and the first power supply line 21 is located in the first source-drain metal layer (SD1), and the second power supply line 22 is located in the second source-drain metal layer (SD2) as an example. In the embodiment of the present disclosure, the direction perpendicular to the plane where the substrate is located is defined as the third direction and is marked as Z.

[0078] like Figure 5A , Figure 5B As shown, the conductive structure 20 may further include a plurality of transfer electrodes 23. The transfer electrodes 23 and the first power line 21 may be located in the first source-drain metal layer (SD1), and the second power line 22 and the data signal line DL may both be located in the second source-drain metal layer (SD2). The second power line 22 may be located between two adjacent data signal lines DL. The first power line 21 and the second power line 22 are connected via the transfer electrodes 23. Figure 5B As shown, the switching electrode 23 is connected to the first power supply line 21, and the second power supply line 22 is connected to the switching electrode 23 via a via provided in the first flat layer 34. The switching electrode 23 can extend along the second direction Y, and the switching electrode 23 can include a first end and a second end arranged oppositely, the first end is connected to the first power supply line 21, and the second end is located on the side opposite to the first end along the second direction Y, and the second end can be connected to the second power supply line 22. For example, the switching electrode 23 and the first power supply line 21 can be an integral structure connected to each other. The orthographic projection of the switching electrode 23 on the plane where the substrate is located overlaps at least partially with the orthographic projection of the second power supply line 22 on the plane where the substrate is located. Due to the provision of the switching electrode 23, the reflection surface of the second area AA2 is increased compared with the first area AA1, resulting in the phenomenon of uneven surface reflection light in the second area AA2 and the first area AA1, so that the display substrate has a brightness difference problem when the screen is off.

[0079] The second area AA2 may include a plurality of sub-areas, and the plurality of sub-areas may be arranged sequentially in a direction away from the first area AA1. Each sub-area has a switching electrode 23 arrangement density. In the embodiment of the present disclosure, the switching electrode 23 arrangement density is defined as the ratio of the number of switching electrodes 23 in the area to the number of overlapping areas JD. The switching electrode 23 arrangement density may be greater than or equal to 0, and less than or equal to 1. In the embodiment of the present disclosure, by configuring the second area AA2 to include a plurality of sub-areas, along the direction away from the first area AA1, and configuring the arrangement density of the switching electrodes of the plurality of sub-areas to gradually increase, a sudden change in the area of ​​the reflection surface can be avoided, the uniformity of the light reflected from the surface of the display substrate can be improved, and the display quality can be improved.

[0080] In some exemplary embodiments, the arrangement density of the switching electrodes in the sub-region farthest from the first region among the multiple sub-regions may be 1.0, which may reduce the voltage drop of the low-level signal in the display region and improve the uniformity of voltage distribution.

[0081] In some exemplary embodiments, the arrangement density of the switching electrodes in the sub-regions adjacent to the first region among the multiple sub-regions can be greater than or equal to 0 and less than or equal to 0.7, which can avoid the sudden change in the reflective surface area of ​​the first region and the second region and improve the uniformity of the reflected light on the surface of the display substrate.

[0082] In some exemplary embodiments, the difference in arrangement density of switching electrodes between any two adjacent sub-regions among the multiple sub-regions is less than or equal to 0.7, which can avoid a sudden change in the reflective surface area of ​​two adjacent sub-regions and improve the uniformity of reflected light on the display substrate surface.

[0083] In some exemplary embodiments, the second area AA2 may include two sub-areas, or the second area AA2 may include three sub-areas, or the second area AA2 may include four sub-areas, etc. For example, Figure 3 As shown, the second area AA2 may include two sub-areas, the two sub-areas are respectively the first sub-area AA2-1 and the second sub-area AA2-2, and the first sub-area AA2-1 and the second sub-area AA2-2 are arranged in sequence in the direction away from the first area AA1. The arrangement density of the switching electrodes in the first sub-area AA2-1 and the second sub-area AA2-2 gradually increases. For example, the arrangement density of the switching electrodes in the first sub-area AA2-1 may be 0.3, and the arrangement density of the switching electrodes in the second sub-area AA2-2 may be 0.5. Alternatively, the arrangement density of the switching electrodes in the first sub-area AA2-1 may be 0.5, and the arrangement density of the switching electrodes in the second sub-area AA2-2 may be 0.8. Alternatively, the arrangement density of the switching electrodes in the first sub-area AA2-1 may be 0.5, and the arrangement density of the switching electrodes in the second sub-area AA2-2 may be 1.0.

[0084] In some exemplary embodiments, the materials of the first source-drain metal layer and the second source-drain metal layer may be the same or different. The material of the first source-drain metal layer may be a metal material, such as any one or more of silver (Ag), aluminum (Al), gold (Au), platinum (Pt), nickel (Ni) and neodymium (Nd), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd). The first source-drain metal layer may be a single-layer structure, or a multi-layer composite structure.

[0085] Figure 5C FIG. 1 is a partial cross-sectional schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 5C As shown, in a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer, a light-emitting structure layer, and a packaging structure layer sequentially arranged on the substrate 30. The driving structure layer may include at least a pixel driving circuit of a plurality of sub-pixels, and the pixel driving circuit of each sub-pixel may include a plurality of transistors and at least one capacitor. The pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C or 9T2C structure, where the number before T represents the number of transistors, and the number before C represents the number of capacitors. For example, the transistor may be a thin film transistor. The light-emitting structure layer may include at least a plurality of light-emitting devices of sub-pixels. In other examples, a touch structure layer may be provided on the side of the packaging structure layer away from the substrate 30 to integrate a touch function.

[0086] like Figure 5C As shown, the driving structure layer may include a semiconductor layer, a first insulating layer 31, a first gate metal layer, a second insulating layer 32, a second gate metal layer, a third insulating layer 33, a first source-drain metal layer, a first planar layer 34, a second source-drain metal layer, and a second planar layer 35 stacked in sequence. The semiconductor layer in the display area may include: an active layer T10 of a transistor T of a pixel driving circuit. The active layer T10 of the transistor T may include: a first region, a second region, and a channel region between the first region and the second region. The first gate metal layer in the display area may include: a gate T11 of the transistor T and a first plate C11 of the capacitor C. The second gate metal layer may include a second plate C22 of the capacitor C. The orthographic projections of the second plate C22 and the first plate C11 on the plane where the substrate 30 is located may at least partially overlap, and for example, the two may overlap. The first source-drain metal layer in the display area may also include a source T12 and a drain T13 of the transistor T. The source electrode T12 of the transistor T may be electrically connected to the first region of the active layer T10, and the drain electrode T13 may be electrically connected to the second region of the active layer T10. The second source-drain metal layer of the display region may further include a connection electrode T14, and one of the source electrode T12 and the drain electrode T13 is electrically connected to the connection electrode T14 through a via hole provided in the first planar layer 34. For example, the drain electrode T13 is electrically connected to the connection electrode T14 through a via hole provided in the first planar layer 34. The connection electrode T14 is configured to be electrically connected to the light emitting device to achieve electrical connection between the light emitting device and the pixel driving circuit.

[0087] In some exemplary embodiments, the light emitting structure layer may include a pixel definition layer and a plurality of light emitting devices. Each light emitting device may include: a stacked first electrode, an organic light emitting layer, and a second electrode. The first electrode of the light emitting device may be electrically connected to the connection electrode T14 through a via provided in the second flat layer 35. The pixel definition layer is provided on a side of the first electrode away from the substrate 30, and the pixel definition layer may be provided with a plurality of pixel openings, and a pixel opening may expose at least a portion of the surface of a corresponding first electrode. At least a portion of the organic light emitting layer may be provided in a pixel opening and connected to the corresponding first electrode. The second electrode may be provided on a side of the organic light emitting layer away from the substrate 30 and connected to the organic light emitting layer. The organic light emitting layer may emit light of a corresponding color under the drive of the first electrode and the second electrode. The first electrode may also be referred to as an anode, and the second electrode may also be referred to as a cathode.

[0088] In some exemplary embodiments, the organic light-emitting layer of the light-emitting device may include at least one light-emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode and the second electrode, the organic light-emitting layer can emit light of a corresponding color.

[0089] In some exemplary embodiments, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0090] Figure 6 FIG. 1 is a partial enlarged schematic diagram of the overlapping area of ​​the display substrate of another embodiment of the present disclosure. Figure 6 As shown, at least part of the plurality of second power lines 22 and at least part of the plurality of data signal lines DL may be arranged in a group, and two second power lines 22 may be respectively located on both sides of two adjacent data signal lines DL along the first direction X. A first power line 21 is connected to one of the two second power lines 22 via a transfer electrode 23 .

[0091] Fig. 7A FIG. 1 is a partial enlarged plan view of an overlapping region of a display substrate according to another embodiment of the present disclosure. Figure 7B for Fig. 7A The cross-sectional view at the CC mark is shown in the figure. Figure 7C FIG. 1 is a partial cross-sectional schematic diagram of an overlapping region of a display substrate according to another embodiment of the present disclosure. Figure 8 FIG. 1 is a partial enlarged schematic diagram of the overlapping area of ​​the display substrate of another embodiment of the present disclosure. Fig. 7A , Figure 8 As shown, the display substrate may further include at least one light shielding portion 36, and the light shielding portion 36 is located in the second area AA2. Fig. 7A , Figure 8 The light shielding portion 36 is not filled with color to facilitate identification of the switching electrode 23 .

[0092] like Figure 7B As shown, due to the provision of the switching electrode 23 , the surface of the second power trace 22 overlapping with the orthographic projection of the switching electrode 23 on the plane where the substrate 30 is located is relatively flat, that is, the flatness is good. Figure 7C As shown, the surface flatness of the second power supply line 22 located between two adjacent first power supply lines 21 is relatively poor. Flatness affects the reflectivity of light, and the flatter the surface, the greater the reflectivity. Therefore, in the embodiment of the present disclosure, by setting a shading portion 36, the orthographic projection of the shading portion 36 on the plane where the substrate 30 is located overlaps with the orthographic projection of the conductive structure 20 on the plane where the substrate 30 is located at least partially, and the reflectivity of the shading portion 36 in the visible light range is less than the reflectivity of the conductive structure 20, the reflectivity of the second area can be reduced, and the uniformity of the surface reflected light of the first area and the second area can be improved. In the embodiment of the present disclosure, the reflectivity of the shading portion 36 is less than the reflectivity of the conductive structure 20, which is relative. For example, the reflectivity of the conductive structure 20 can be 80%, and the reflectivity of the shading portion 36 can be 70%, or the reflectivity of the conductive structure 20 can be 60%, and the reflectivity of the shading portion 36 can be 50%, etc. The present disclosure does not limit the reflectivity of the shading portion 36 and the conductive structure 20.

[0093] In some exemplary embodiments, the orthographic projection of the light shielding portion 36 on the plane where the substrate 30 is located at least partially overlaps with the orthographic projection of the first power line 21 on the plane where the substrate 30 is located, or the orthographic projection of the light shielding portion 36 on the plane where the substrate 30 is located at least partially overlaps with the orthographic projection of the second power line 22 on the plane where the substrate 30 is located, or the orthographic projection of the light shielding portion 36 on the plane where the substrate 30 is located at least partially overlaps with the orthographic projection of the transfer electrode 23 on the plane where the substrate 30 is located. For example, the orthographic projection of the light shielding portion 36 on the plane where the substrate 30 is located includes the orthographic projection of the transfer electrode 23 on the plane where the substrate 30 is located.

[0094] In some exemplary embodiments, the shading portion 36 and the switching electrodes 23 can be arranged in groups one by one, and the orthographic projection of the shading portion 36 on the plane where the substrate 30 is located at least partially overlaps with the orthographic projection of the switching electrodes 23 arranged in groups on the plane where the substrate 30 is located. For example, the orthographic projection of the shading portion 36 on the plane where the substrate 30 is located includes the orthographic projection of the switching electrodes 23 arranged in groups on the plane where the substrate 30 is located.

[0095] In some exemplary embodiments, the orthographic projection of the light shielding portion 36 on the plane where the substrate 30 is located may be a rectangle, a circle, a hexagon, etc., however, the present disclosure is not limited to this.

[0096] In some exemplary embodiments, the material of the light shielding portion 36 may be a metal material, such as copper (Cu) or molybdenum (Mo), or an alloy material of the above metals. Alternatively, the material of the light shielding portion 36 may be a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO) or aluminum-doped zinc oxide (AZO) or fluorine-doped tin oxide (FTO). Alternatively, the material of the light shielding portion 36 may be a dielectric material, such as silicon dioxide (SiO2) or silicon nitride (Si3N4) or magnesium fluoride (MgF2). The light shielding portion 36 may be a single-layer structure or a multi-layer composite structure.

[0097] Fig. 9 is a partial enlarged schematic plan view of an anode layer of a display substrate according to an embodiment of the present disclosure, Fig.10 FIG. 1 is a partial enlarged schematic diagram of an anode layer of a display substrate according to another embodiment of the present disclosure. Fig. 9 , Fig.10 As shown, in a direction perpendicular to the display substrate, the light emitting structure layer may include an anode layer, a light emitting material layer, and a cathode layer stacked in sequence. The anode layer includes a plurality of anodes, the light emitting material layer includes a plurality of organic light emitting layers, the cathode layer includes a plurality of cathodes, and the stacked anodes, organic light emitting layers, and cathodes constitute a light emitting device. The light shielding portion 36 may be located in the anode layer, without adding a new film layer, which may simplify the preparation process of the display substrate and reduce the preparation cost of the display substrate.

[0098] The display area AA of the display substrate may include a plurality of pixel units arranged in a rectangular manner, at least one pixel unit may include a plurality of sub-pixels, and the plurality of sub-pixels may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The red sub-pixel is configured to emit red light, the green sub-pixel is configured to emit green light, and the blue sub-pixel is configured to emit blue light. The shading portion 36 and the anode 37 of the light-emitting device of the red sub-pixel are an integrated structure connected to each other. Alternatively, the shading portion 36 and the anode 38 of the light-emitting device of the blue sub-pixel are an integrated structure connected to each other. Alternatively, the shading portion 36 and the anode 39 of the light-emitting device of the green sub-pixel are an integrated structure connected to each other. In the embodiment of the present disclosure, the shading portion is designed to be an integrated structure connected to the anode of the light-emitting device, which is conducive to increasing the area of ​​the anode and can improve the light emitting efficiency of the light-emitting device.

[0099] The embodiment of the present disclosure also provides a display device, which includes the display substrate of any of the above embodiments. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiment of the present disclosure is not limited thereto.

[0100] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating understanding of the present invention and are not intended to limit the present invention. It should be noted that the above embodiments or embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area, wherein the display area comprises a first area and a second area; A plurality of data signal lines are located in the display area, and the plurality of data signal lines are arranged at intervals along a first direction and extend along a second direction, the first direction intersects with the second direction and the plane formed by the first direction is parallel to the plane where the substrate is located; a plurality of data fan-out lines, located in the first area and connected to the data signal lines; A conductive structure, located in the second area, the conductive structure comprising a plurality of first power lines, a plurality of second power lines and a plurality of switching electrodes, the plurality of first power lines extending along the first direction and arranged at intervals along the second direction; the plurality of second power lines extending along the second direction and arranged at intervals along the first direction, and the plurality of first power lines and the plurality of second power lines are connected to each other via the switching electrodes to form a mesh structure for transmitting low-level signals; the plurality of first power lines and the plurality of second power lines are orthographically projected on the plane where the substrate is located to form a plurality of overlapping areas; The second region includes multiple sub-regions, each of which has an arrangement density of the switching electrodes. The arrangement density of the switching electrodes in the multiple sub-regions gradually increases in the direction away from the first region, and the arrangement density of the switching electrodes is the ratio of the number of the switching electrodes in the sub-region to the number of the overlapping regions.

2. The display substrate according to claim 1, wherein: The arrangement density of the switching electrodes in the sub-region farthest from the first region among the multiple sub-regions is 1.

0.

3. The display substrate according to claim 1, wherein: An arrangement density of the switching electrodes in the sub-region adjacent to the first region among the plurality of sub-regions is greater than or equal to 0 and less than or equal to 0.

7.

4. The display substrate according to claim 1, wherein: The difference in arrangement density of the switching electrodes of any group of two adjacent sub-regions among the multiple sub-regions is less than or equal to 0.

7.

5. The display substrate according to any one of claims 1 to 4, characterized in that: Also includes a plurality of sub-pixels, the plurality of sub-pixels are located in the display area; the plurality of sub-pixels include at least a red sub-pixel, a blue sub-pixel and a green sub-pixel, the red sub-pixel is configured to emit red light, the blue sub-pixel is configured to emit blue light, and the green sub-pixel is configured to emit green light; In the second region, the plurality of overlapping regions are arranged in groups with the plurality of sub-pixels one by one; or, one overlapping region is arranged in a group with two sub-pixels.

6. The display substrate according to any one of claims 1 to 4, characterized in that: The first power line and the switching electrode are located in the same conductive layer and are an integrated structure connected to each other. The second power line and the first power line are located in different conductive layers, and the orthographic projections of the second power line and the switching electrode on the plane where the substrate is located at least partially overlap.

7. The display substrate according to claim 6, wherein: The orthographic projection of at least one of the second power supply lines on the plane where the substrate is located includes the orthographic projection of the switching electrode on the plane where the substrate is located.

8. The display substrate according to any one of claims 1 to 4, characterized in that: It also includes at least one shading portion, and the shading portion is located on a side of the conductive structure away from the substrate, and the shading portion at least partially overlaps with the orthographic projection of the conductive structure on the plane where the substrate is located; in the visible light range, the reflectivity of the shading portion is less than the reflectivity of the conductive structure.

9. The display substrate according to claim 8, wherein: The orthographic projection of at least one of the light shielding portions on the plane where the substrate is located includes the orthographic projection of the switching electrode on the plane where the substrate is located.

10. The display substrate according to claim 8, wherein: It also includes a plurality of sub-pixels, which are located in the display area; the plurality of sub-pixels include at least red sub-pixels, blue sub-pixels and green sub-pixels, the red sub-pixels are configured to emit red light, the blue sub-pixels are configured to emit blue light, and the green sub-pixels are configured to emit green light; each of the sub-pixels includes a light-emitting device, which is located on a side of the conductive structure away from the substrate; the light-emitting device includes a stacked anode, an organic light-emitting layer and a cathode, and the light-shielding portion and the anode are located on the same conductive layer.

11. The display substrate according to claim 10, wherein: The light shielding portion and the anode of the red sub-pixel are connected to each other as an integral structure, or the light shielding portion and the anode of the blue sub-pixel are connected to each other as an integral structure.

12. The display substrate according to claim 11, wherein: At least one of the second power supply lines is located between two adjacent data signal lines.

13. The display substrate according to claim 10, wherein: The light shielding portion and the anode of the green sub-pixel are interconnected as an integral structure.

14. The display substrate according to claim 13, wherein: At least two adjacent second power lines are respectively located on two sides of two adjacent data signal lines along the first direction.

15. A display device, characterized in that: Comprising the display substrate according to any one of claims 1 to 14.

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