SFQ device flip structure, quantum chip and quantum computer

Abstract

The invention discloses an SFQ device flip structure, a quantum chip and a quantum computer, and the structure comprises a flip layer, a plurality of first flip pressure welding spots formed on the flip layer, a plurality of Josephson junctions formed in the flip layer, and a substrate layer, and a plurality of second flip pressure welding spots formed on the substrate layer. Wherein the structure of the substrate layer is matched with the structure of the inverted layer, and the substrate layer is used for wiring and placing the direct-current power layer, so that the influence of the direct-current power layer on the performance of the Josephson junction is reduced. The quantum chip comprises the above SFQ device flip structure. The quantum computer comprises the above SFQ device inversion structure. The substrate layer and the inverted layer are in modular design and can be manufactured independently at the same time, the preparation efficiency is effectively improved, and the Josephson junction is arranged in the substrate layer, so that the influence of the direct-current power layer in the substrate layer on the performance of the Josephson junction can be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of quantum chips, and in particular to a SFQ device flip-chip structure, a quantum chip and a quantum computer. Background Art

[0002] The components of mainstream semiconductor computers are CMOS, while the components of superconducting computers are Josephson junctions (JJ). The working principle and working state of the Josephson junction are completely different from those of the CMOS tube, and it has many excellent characteristics. The Josephson junction is a device whose switch is controlled by current. The Josephson junction has a current Ic. When the current flowing through the Josephson junction exceeds I(c), the Josephson junction is triggered, generating a voltage pulse and emitting a magnetic flux quantum, namely a single-flux quantum (SFQ). The SFQ will be induced by the inductor to obtain a stable current, thereby triggering the next Josephson junction or realizing other functions. In short, the Josephson junction is a device controlled by current, which has extremely low power consumption after being triggered and fast switching speed.

[0003] As the integration of SFQ gradually increases, its process requirements become more and more complex. Although the planarization process in the relevant technology can be used when the integration of SFQ is low, as the integration of SFQ increases, the use of planarization technology will make it difficult to control the yield and the cost is high. At the same time, the production process cycle is long, and the Josephson junction has high requirements for flatness, otherwise it will affect the stability of the SFQ device. Summary of the invention

[0004] The purpose of the present invention is to solve the above problems. The present invention provides a SFQ device flip-chip structure, a quantum chip and a quantum computer.

[0005] In order to achieve the above-mentioned purpose, the present invention specifically adopts the following technical solutions:

[0006] A SFQ device flip-chip structure, comprising:

[0007] providing a flip-chip layer;

[0008] forming a plurality of first flip-chip bonding pads on the flip-chip layer;

[0009] A plurality of Josephson junctions are formed in the inverted layer;

[0010] providing a base layer;

[0011] A plurality of second flip-chip bonding pads are formed on the base layer;

[0012] The first flip-chip solder joint and the second flip-chip solder joint are used for flip-chip soldering between the base layer and the flip-chip layer;

[0013] The structure of the base layer is compatible with the structure of the flip-chip layer, and the base layer is used for wiring and placing a DC power layer, thereby reducing the influence of the DC power layer on the performance of the Josephson junction.

[0014] Optionally, the base layer and the flip-chip layer are relatively independent layer structures before flip-chip bonding.

[0015] Optionally, the flip-chip layer includes a silicon substrate from top to bottom, a silicon dioxide layer is formed on the silicon substrate, a plurality of bias columns are formed in the silicon dioxide layer, bias resistors are formed on the bias column structure, and adjacent bias resistors are connected via parallel resistors.

[0016] Optionally, an oxide film layer is formed on the surface of the bias column, the oxide film layer is used to prevent short circuit, and a plurality of the Josephson junctions are formed on the oxide film layer.

[0017] Optionally, a first bias column and a second bias column are provided at the bottom of each bias resistor, wherein the first bias column is connected to the first flip-chip solder joint, and the second bias column is connected to the parallel resistor.

[0018] Optionally, the first flip-chip bonding point is a metal indium column.

[0019] Optionally, the base layer includes a silicon substrate from bottom to top, a silicon dioxide layer and a plurality of DC power layers are formed on the surface of the silicon substrate, and a passive transmission line layer, a main ground plane layer and a supplementary flat layer are formed in the silicon dioxide layer.

[0020] Optionally, the second flip-chip solder joint is disposed on a surface of the base layer away from the silicon substrate, and the second flip-chip solder joint is soldered to a bias column in the base layer.

[0021] A quantum chip comprising any of the above-mentioned SFQ device flip-chip structures.

[0022] A quantum computer comprises any one of the above-mentioned SFQ device flip-chip structures.

[0023] The beneficial effects of the present invention are as follows:

[0024] 1. The base layer and the flip-chip layer in the present invention are modularly designed and can be manufactured separately at the same time, which effectively improves the manufacturing efficiency.

[0025] 2. In the present invention, the Josephson junction is arranged in the flip-chip layer, which can effectively reduce the influence of the DC power layer in the base layer on the performance of the Josephson junction.

[0026] 3. In the present invention, the Josephson junction is arranged in the inverted layer with a higher bottom flatness, which can improve the stability of the Josephson junction.

[0027] 4. The base layer in the present invention is mainly used for wiring and placing the DC power layer, and can be independently designed according to the requirements of the technical indicators of the flip-chip layer on the device performance, which can improve the adaptability to the flip-chip layer.

[0028] In order to more clearly illustrate the structural features and functions of the present invention, the present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of the base layer and the flip-chip layer after flip-chip bonding of the present invention;

[0030] Figure 2 It is a schematic structural diagram of the flip-chip layer of the present invention;

[0031] Figure 3 It is a schematic structural diagram of the base layer of the present invention.

[0032] Figure numerals: 1. flip-chip layer; 2. first flip-chip solder joint; 3. silicon substrate; 4. silicon dioxide layer; 5. first bias column; 6. second bias column; 7. bias resistor; 8. parallel resistor; 9. oxide film layer; 10. base layer; 11. DC power layer; 12. passive transmission line layer; 13. main ground plane layer; 14. supplementary flat layer; 15. bias column; 16. second flip-chip solder joint; 17. Josephson junction. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation.

[0034] The embodiment of the present application provides a SFQ device flip-chip structure, which solves the problem in the related art that due to the improvement of SFQ integration and the increase in the number of Josephson junctions 17, the current planarization process design cannot meet the design and manufacturing requirements, and will also lead to the instability of the SFQ circuit. At present, the SFQ circuit process is mainly divided into NEC (niobium integrated circuit) standard process and advanced process (the advanced process, ADP), wherein the former includes the use of up to 4 Nb layers and a critical current density of 2.5kA / cm 2The advanced process has 6-10 Nb layers and Josephson junction 17. Its goal is to develop a SFQ circuit that can contain a junction area above 100K and a clock frequency of about 80GHz. In order to achieve such a high frequency, the superconducting critical current density of the Josephson junction 17 needs to reach 10KA / cm 2 This value is four times the value of the standard process. In order to achieve this value, the minimum Josephson junction 17 area must be reduced to 1.0μm 2 , while maintaining a critical current of 0.1mA with a standard deviation of less than 2%, the sheet resistance must also be increased to 2.4Ω. In order to achieve integration levels exceeding 100K junctions, in addition to shrinking the circuit design rules, the number of Nb layers needs to be increased. Therefore, the number of Nb layers is twice the number used in the current standard process. Therefore, the main issues of advanced processes are to increase the critical current density of the junction, reduce the design rules, and increase the number of Nb layers. Advanced processes have the disadvantages of longer manufacturing turnaround times and higher photomask costs, but it enables SFQ circuits to operate at higher frequencies and have higher density integration than standard processes, and have higher reliability than standard processes.

[0035] On the other hand, without changing the SFQ circuit layout: On the one hand, as the number of Josephson junctions 17 increases, the circuit gradually increases, the required bias current also gradually increases, and the magnetic field effect that affects the operation of SFQ gradually increases. Since superconductors are the best carriers for magnetic field shielding, more layers of Nb processes are needed to shield magnetic field signals. On the other hand, with the improvement of the integration of the ADP process, the number of Josephson junctions 17 per unit area is gradually increasing. When the critical current of a single Josephson junction 17 remains unchanged, the overall bias current also gradually increases, and more Nb layers of processes are also needed for magnetic field signal shielding. These undoubtedly put higher requirements on the ADP process.

[0036] In order to solve the above problems, the technical concept of the embodiment of the present application is as follows: the flip-chip structure includes a Flip structure (flip-chip layer 1) and a Base structure (base layer 10), wherein the base layer 10 includes a DC power layer 11, a passive transmission line layer 12, a main ground plane layer 13 and a supplementary flat layer 14. The flip-chip layer 1 includes structures such as a Josephson junction 17, a parallel resistor 8, a bias resistor 7 and a bias column 15. By setting a flip-chip solder joint on the base layer 10 and the flip-chip layer 1, the base layer 10 and the flip-chip layer 1 are flip-chip connected. Through the above-mentioned flip-chip structure, the base layer 10 and the flip-chip layer 1 can be made separately at the same time, which improves the efficiency of preparation compared with the prior art. At the same time, the base layer 10 can be independently designed according to the technical indicators of the flip-chip layer 1 and the performance requirements of the device, so that the base layer 10 and the flip-chip layer 1 are more compatible. And setting the Josephson junction 17 on the flip-chip layer 1 is conducive to improving the stability of the Josephson junction.

[0037] like Figure 1 As shown, in one embodiment, a SFQ device flip-chip structure includes:

[0038] Providing a flip layer 1, i.e., a Flip layer;

[0039] Forming a plurality of first flip-chip bonding pads 2 on the flip-chip layer 1;

[0040] A plurality of Josephson junctions 17 are formed in the flip layer 1. Specifically, the Josephson junctions 17 are formed by depositing a layer of superconducting material such as Nb (niobium) on a substrate, oxidizing the superconducting material to form a thin insulating layer such as aluminum oxide (Al2O3), and then depositing another layer of superconducting material on the insulating layer to form the Josephson junctions 17. By arranging the Josephson junctions 17 in the flip layer, it is more conducive to improving the stability of the Josephson junctions 17 when in use.

[0041] A base layer 10, i.e., a Base layer, is provided, and a plurality of second flip-chip solder joints 16 are formed on the base layer 10; the first flip-chip solder joints 2 and the second flip-chip solder joints 16 are used for flip-chip soldering between the base layer 10 and the flip-chip layer 1, wherein the first flip-chip solder joints 2 and the second flip-chip solder joints 16 can be superconducting materials such as indium. The number and position of the first flip-chip solder joints 2 and the second flip-chip solder joints 16 match, and in some embodiments, the flip-chip solder joints are arranged at the four corners of the base layer 10 or the flip-chip layer 1, and in some other embodiments, the flip-chip solder joints are arranged at the four corners and the center of the base layer 10 or the flip-chip layer 1.

[0042] Among them, the structure of the base layer 10 is compatible with the structure of the flip-chip layer 1. The base layer 10 is used for wiring and placing the DC power layer 11, reducing the performance impact of the DC power layer 11 on the Josephson junction 17. Specifically, the stability and noise level of the DC power layer 11 will directly affect the characteristics of the Josephson junction 17. If the power supply provided by the DC power layer 11 is unstable, it will cause current fluctuations in the Josephson junction 17, thereby affecting the coherence and stability of the quantum bit. In addition, the noise in the DC power layer 11 may also be transmitted to the Josephson junction 17 through coupling, increasing the decoherence rate of the quantum bit. The present disclosure reduces the performance impact on the Josephson junction 17 in the flip-chip layer 1 by setting the DC power layer 11 in the base layer 10.

[0043] Optionally, refer to Figure 2 and Figure 3 The base layer 10 and the flip-chip layer 1 are relatively independent hierarchical structures before flip-chip bonding, that is, the base layer 10 and the flip-chip layer 1 are independent modular structures, so that the base layer 10 and the flip-chip layer 1 can be manufactured separately at the same time, effectively improving the preparation efficiency of the SFQ device.

[0044] Optionally, refer to Figure 2 , the structure of the flip layer 1, i.e., the Flip layer, is described. The Flip layer includes a silicon substrate 3 from top to bottom. The silicon substrate 3 provides a solid physical support structure for the quantum chip. Silicon has good mechanical strength and stability, and can withstand various process steps in the manufacturing process as well as the stress and environmental conditions that the chip may face during use. A silicon dioxide layer 4 is formed on the silicon substrate 3. In some embodiments, the silicon dioxide layer 4 serves as a sacrificial layer, which can be removed in subsequent process steps to form a specific structure or space. After etching the corresponding space in the silicon dioxide layer 4, a plurality of bias columns 15 are formed in the space, and bias resistors 7 are formed on the bias columns 15. Adjacent bias resistors 7 are connected via parallel resistors 8.

[0045] Optionally, an oxide film layer 9 is formed on the surface of the bias column 15, and the oxide film layer 9 is used to prevent short circuits. A plurality of Josephson junctions 17 are formed on the surface of the oxide film layer 9. By arranging the Josephson junctions 17 inside the Flip layer, they can be isolated from the DC power layer 11 in the Base layer, and the influence of the DC power layer 11 on the performance of the Josephson junctions 17 can be effectively reduced. In some embodiments, the oxide film layer 9 is aluminum oxide (Al2O3), which has excellent insulation properties and can isolate different conductive areas.

[0046] Optionally, refer to Figure 2 A first bias column 5 and a second bias column 6 are provided at the bottom of each bias resistor 7. In some embodiments, the first bias column 5 is a GC structure, and the second bias column 6 is an RC structure, wherein the first bias column 5 is connected to the first flip-chip solder joint 2, and the second bias column 6 is connected to the parallel resistor 8. The first flip-chip solder joint 2 is a superconducting material indium column.

[0047] Optionally, refer to Figure 3 , the base layer 10 includes a silicon substrate 3 from bottom to top, a silicon dioxide layer 4 and a plurality of DC power layers 11 are formed on the surface of the silicon substrate 3, wherein a bias column 15 is formed on the surface of a DC power layer 11, and a passive transmission line layer 12 is formed in the silicon dioxide layer 4, and the passive transmission line layer 12 is mainly responsible for transmitting various signals in the quantum chip. In the process of quantum computing, quantum bits need to be precisely controlled and measured, which involves the transmission of a large number of electrical signals, microwave signals, etc. Passive transmission lines can transmit these signals from one location to another in a low-loss manner, ensuring the integrity and accuracy of the signals. At the same time, a main grounding layer 13 and a supplementary flat layer 14 are formed in the silicon dioxide layer 4, wherein a bias column 15 is formed on the main grounding layer 13.

[0048] In some embodiments, the main ground plane layer 13 provides a stable reference potential for various circuits and components in the quantum chip. In electronic circuits, the stability of the reference potential is crucial for the normal operation of the circuit. The quantum bits, control circuits, measurement circuits, etc. in the quantum chip all require a stable reference potential to ensure their accurate operation. The main ground plane layer 13 stabilizes the potential of the entire chip at a suitable level by connecting to the external grounding system to prevent potential fluctuations from adversely affecting the performance of the quantum chip.

[0049] In some embodiments, the supplementary flat layer 14 provides an extremely flat surface for the quantum chip. The manufacture of quantum chips requires extremely high precision, especially for the layout and operation of quantum bits and other key components. An uneven surface may cause uneven distances between quantum elements, affecting the coupling strength of quantum bits and the performance of quantum logic gates. The supplementary flat layer 14 ensures that the entire chip surface has a high degree of flatness by filling the unevenness of the surface, providing an ideal foundation for the precise manufacture and operation of quantum elements. In some other embodiments, the supplementary flat layer 14 may not be provided, and no specific limitation is made here.

[0050] Optionally, a corresponding second flip-chip solder joint 16 is welded on the bias column 15 of the base layer 10. In some embodiments, the second flip-chip solder joint 16 is an indium column. When performing flip-chip soldering, the first flip-chip solder joint 2 is welded to the corresponding second flip-chip solder joint 16 to obtain the following: Figure 3 The SFQ device shown is a flip-chip structure.

[0051] The present disclosure also provides an embodiment, a quantum chip, comprising any of the above-mentioned SFQ device flip-chip structures.

[0052] The present disclosure also provides an embodiment, a quantum computer, which includes any of the above-mentioned quantum chips and a SFQ device flip-chip structure.

[0053] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SFQ device flip-chip structure, characterized in that: include: providing a flip-chip layer; forming a plurality of first flip-chip bonding pads on the flip-chip layer; A plurality of Josephson junctions are formed in the inverted layer; providing a base layer; A plurality of second flip-chip bonding pads are formed on the base layer; The first flip-chip solder joint and the second flip-chip solder joint are used for flip-chip soldering between the base layer and the flip-chip layer; The structure of the base layer is compatible with the structure of the flip-chip layer, and the base layer is used for wiring and placing a DC power layer, thereby reducing the influence of the DC power layer on the performance of the Josephson junction.

2. The SFQ device flip-chip structure according to claim 1, characterized in that: The base layer and the flip-chip layer are relatively independent hierarchical structures before flip-chip bonding.

3. The SFQ device flip-chip structure according to claim 1, characterized in that: The flip-chip layer includes a silicon substrate from top to bottom, a silicon dioxide layer is formed on the silicon substrate, a plurality of bias columns are formed in the silicon dioxide layer, bias resistors are formed on the bias columns, and adjacent bias resistors are connected via parallel resistors.

4. The SFQ device flip-chip structure according to claim 3, characterized in that: An oxide film layer is formed on the surface of the bias column, the oxide film layer is used to prevent short circuit, and a plurality of Josephson junctions are formed on the oxide film layer.

5. The SFQ device flip-chip structure according to claim 3, characterized in that: A first bias column and a second bias column are disposed at the bottom of each bias resistor, wherein the first bias column is connected to the first flip-chip solder joint, and the second bias column is connected to the parallel resistor.

6. The SFQ device flip-chip structure according to claim 1, characterized in that: The first flip-chip bonding point is a metal indium column.

7. The SFQ device flip-chip structure according to claim 1, characterized in that: The base layer includes a silicon substrate from bottom to top, a silicon dioxide layer and a plurality of DC power layers are formed on the surface of the silicon substrate, and a passive transmission line layer, a main ground plane layer and a supplementary flat layer are formed in the silicon dioxide layer.

8. The SFQ device flip-chip structure according to claim 1, characterized in that: The second flip-chip solder joint is arranged on a surface of the base layer away from the silicon substrate, and the second flip-chip solder joint is soldered to a biasing column in the base layer.

9. A quantum chip, characterized in that: The invention comprises the SFQ device flip-chip structure according to any one of claims 1 to 8.

10. A quantum computer, characterized in that: The invention comprises the SFQ device flip-chip structure according to any one of claims 1 to 8.

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