Trench electrostatic discharge protection device

Abstract

A semiconductor device includes a trench formed in a semiconductor substrate. The trench includes a plurality of ESD protection devices formed of PN junctions or NP junctions between respective first doped regions (e.g., P doped regions) and second doped regions (e.g., N doped regions). The ESD protection devices are connected in series on the trenches through connection electrodes, and the connection electrodes are connected with the trenches at corresponding points. The two outer trenches include an ESD protection device connected in parallel to the first metal layer and the second metal layer. The first metal and the second metal between which the ESD protection device is connected may be, for example, a source metal layer and a gate metal layer. An ESD event causes a current to flow through the ESD protection device.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to semiconductor devices including an electrostatic protection device formed in a trench of a semiconductor device. Background Art

[0002] Electrostatic discharge (ESD) is a sudden transfer of charge between differently charged objects. Some electrical components (such as MOS-based transistor devices) formed as part of a semiconductor device are at risk of being damaged by ESD. This may particularly be the case where the gate oxide layer of the transistor device is thinned to provide a lower operating threshold voltage.

[0003] ESD protection devices can be used to prevent sudden ESD events to protect active components such as transistors from damage. Such ESD protection devices may include one or more diodes connected to the active electrical components. At least some of these diodes are arranged such that in the case of ESD, current flows through the diodes in the opposite direction, and thus the diodes conduct current only in the case of a sudden large voltage spike.

[0004] One electrical component for which it may be necessary to implement an ESD protection device is a trench gate transistor device. The trench gate transistor device is formed in a trench provided in a semiconductor substrate. Referring to FIG. 1, which illustrates a semiconductor device 100 in which a trench gate transistor device is formed. The semiconductor device 100 includes a substrate 102, the lower part 108 of the substrate 102 is an N-doped region 108, and the upper part 106 of the substrate is a P-doped region 106. The semiconductor device 100 further includes a trench 104 formed in the substrate 102. A gate electrode 112 is formed within the trench 104 in the substrate 102, and an insulating material 114 is formed on the side surfaces of the trench 104. A drain metal electrode 118 is formed on the lower side of the semiconductor substrate 102, and a source electrode 116 is formed on the upper side of the semiconductor substrate 102. When a positive voltage is applied to the gate electrode 112, the transistor device is turned on, and current can flow vertically between the source electrode 116 and the drain electrode 118.

[0005] One of the challenges involved in providing ESD protection for active components such as trench gate transistor devices is integrating the ESD protection device into the semiconductor device. One way to provide an ESD protection device is to form a polysilicon layer over the semiconductor substrate and form a plurality of P-doped regions and N-doped regions in the polysilicon layer such that pairs of P-doped regions and N-doped regions form PN junctions, thereby providing diodes for providing ESD protection. However, additional photomasks may be required to define the polysilicon layer pattern, resulting in a more expensive manufacturing process. Summary of the Invention

[0006] Therefore, it is necessary to integrate the ESD protection circuit together with the trench gate transistor device into the semiconductor device. One suggestion for achieving better integration is to form short trenches or wells in the semiconductor substrate, where each well includes a PN junction and / or an NP junction. The formation of these wells can eliminate the need for another polysilicon layer formed above the substrate. However, the process required to produce such wells is different from the process commonly used to produce trenches in the active region, such as the trenches for forming transistor gates. Forming such different trench geometries increases the complexity and cost associated with manufacturing the semiconductor device. In addition, the surface area utilization associated with using such wells may not be optimal.

[0007] According to a first aspect, there is provided a semiconductor device, comprising: a semiconductor substrate including a plurality of trenches arranged in parallel, each of the trenches including a semiconductor including a plurality of first doped regions and second doped regions; a plurality of trench electrostatic discharge protection devices formed in the trenches and connected between a first metal layer formed above the semiconductor substrate and a second metal layer formed above the semiconductor substrate, wherein each of the plurality of trenches includes two or more of the trench electrostatic discharge protection devices, wherein each of the plurality of trench electrostatic discharge protection devices includes at least one of a PN junction or an NP junction formed between one of the first doped regions and the second doped region in the first doped region of the corresponding trench, wherein the semiconductor device further includes a plurality of connection electrodes formed above the semiconductor substrate for connecting the electrostatic discharge protection device of each trench to the electrostatic protection device of at least one adjacent trench of the trench, wherein for the first outer trench in the trenches, the electrostatic discharge protection device of the first outer trench in the trenches is connected in parallel with the first metal layer, and wherein for the second outer trench in the trenches, the electrostatic discharge protection device of the second outer trench in the trenches is connected in parallel with the second metal layer.

[0008] Each trench in the trench includes a plurality of ESD protection devices, and the plurality of ESD protection devices are formed by a PN junction or an NP junction between a corresponding first doped region (e.g., a P-doped region) and a second doped region (e.g., an N-doped region). The ESD protection devices are connected in series on the trench through connecting electrodes, and the connecting electrodes connect the trench at corresponding points. The two outer trenches include ESD protection devices connected in parallel to the first metal layer and the second metal layer. The first metal and the second metal connecting the ESD protection devices therebetween can be, for example, a source metal layer and a gate metal layer. An ESD event causes current to flow through the ESD protection devices. The ESD protection devices are connected in parallel between the first metal layer and the second metal layer. The first metal layer can be connected to the source electrode of the transistor, and the second metal layer can be connected to the gate electrode of the transistor. Therefore, the ESD protection devices are formed in parallel on the trench, thereby achieving a greater surface area utilization rate and better integration with the technology of forming trenches in adjacent active regions. In addition, the strip-shaped arrangement of the trenches enables the network ESD protection devices to be designed to achieve appropriate current-carrying capacity and breakdown voltage.

[0009] Two regions can be defined in the semiconductor device. The first region is the active region where a trench gate transistor using a first trench is formed. The second region includes the trench (i.e., the second trench) where the ESD protection devices are formed. The second trench is arranged in parallel with the first trench and is used to form the ESD protection devices.

[0010] For each electrostatic protection device in the electrostatic protection device, the connecting electrode is configured to: provide a connection between the terminal of the corresponding electrostatic protection device and the terminal of the corresponding electrostatic protection device in at least one adjacent trench in the trench; and / or provide a connection between the terminal of the corresponding electrostatic protection device and the terminals of the plurality of electrostatic protection devices in at least one adjacent trench in the trench. If the electrostatic protection devices are located at equivalent positions in different trenches, they can be said to be corresponding.

[0011] In some embodiments, each of the connecting electrodes forms a connection between the following regions: the corresponding first doped regions in the first doped regions belonging to different trenches; or the second doped regions belonging to different trenches. If the first doped regions are located at equivalent positions in different trenches, they can be said to be corresponding.

[0012] In some embodiments, the semiconductor device further includes: an insulating layer on the plurality of trenches; and conductive contacts formed through the insulating layer and connected to the connecting electrodes.

[0013] In some embodiments, at least some of the conductive contacts contact the first doped regions in the first doped regions of the trenches.

[0014] In some embodiments, some of the conductive contact members in the conductive contact members are in contact with the second doped region in the trench.

[0015] In some embodiments, the plurality of trenches are a plurality of second trenches provided in a second region of the semiconductor substrate, wherein the semiconductor device further includes at least one first trench provided in a first region defined in the semiconductor substrate, and one or more trench gate transistor devices are provided in the first device region, and one or more trench gate transistor devices include gates provided in at least one first trench.

[0016] In some embodiments, the first metal layer is electrically connected to the first terminal of each trench gate transistor device in the trench gate transistor device, and the second metal layer is electrically connected to the second terminal of each trench gate transistor device in the trench gate transistor device.

[0017] In some embodiments, the second trenches are deeper than at least one of the first trenches.

[0018] In some embodiments, each of the connection electrodes in the connection electrodes is electrically connected between two corresponding first doped regions of adjacent trenches in the trench.

[0019] In some embodiments, some of the connection electrodes in the connection electrodes form connections with second doped regions belonging to different trenches.

[0020] In some embodiments, each of the trenches in the trench includes a third doped region, the third doped region is electrically connected to the connection electrode in the connection electrode connecting the corresponding trench, each of the third doped regions in the third doped region includes the same doping type as the first doped region, and the third doped region is more heavily doped than the first doped region.

[0021] In some embodiments, the first metal layer is a source metal layer connected to the source terminal of the transistor of the semiconductor device.

[0022] In some embodiments, the second metal layer is a gate metal layer connected to the gate terminal of the transistor of the semiconductor device.

[0023] According to a second aspect, there is provided a method of manufacturing a semiconductor device according to any one of the preceding claims, including producing each of the trenches in the trench by the following steps: etching a corresponding trench in the semiconductor substrate; implanting each of the first doped region and the second doped region into the corresponding trench; forming an insulating layer on the corresponding trench; and forming a conductive contact through the insulating layer between the first doped region and the second doped region in the corresponding trench, the method further including: forming connection electrodes to connect the trenches by connecting the connection electrodes to some of the conductive contacts; and forming the first metal layer and the second metal layer, including connecting them to other conductive contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] By referring to the drawings and describing the exemplary embodiments in detail, the features will be clearly understandable to those skilled in the art, wherein:

[0025] FIG. 1 illustrates a trench gate transistor of the prior art;

[0026] Figure 2A illustrates a semiconductor device having an active region for forming a trench gate transistor and another region for forming an electrostatic protection device in a trench;

[0027] Figure 2B illustrates another embodiment of a semiconductor device, wherein the trench for forming the ESD protection device is larger than the trench of the active region;

[0028] Figure 3 is a top view of a semiconductor device showing the arrangement of trenches;

[0029] Figure 4A is a top view of an ESD protection device trench showing a metal connection above and in electrical contact with the semiconductor material in the trench;

[0030] Figure 4B is a cross-section through one of the ESD protection device trenches in the ESD protection device trench showing different doped regions and metal contacts within the trench;

[0031] Figure 4C is another cross-section through one of the ESD protection device trenches in the ESD protection device trench showing different doped regions and metal contacts within the trench;

[0032] Figure 5 illustrates a circuit diagram showing a circuit connecting a source metal layer and a gate metal layer and further illustrates which PN junctions of the trenches form elements of the circuit;

[0033] Figure 6 is a cross-section through an ESD protection device trench according to another exemplary embodiment, wherein additional PN junctions are formed in the trench;

[0034] Figure 7 illustrates showing according to Figure 6 a circuit diagram of a circuit connecting a source metal layer and a gate metal layer formed by an ESD trench according to the embodiment represented;

[0035] Figure 8 is a cross-section through an ESD protection device trench according to another exemplary embodiment, wherein the trench includes a heavily doped region; and

[0036] Figure 9Illustrates the construction steps of the ESD protection device trench. Detailed implementation

[0037] The embodiments will be described in more detail with reference to the accompanying drawings.

[0038] Reference Figure 2A , which illustrates a cross-section of a semiconductor device 200 according to an embodiment of the present application. The semiconductor device 100 includes a substrate 102 that may be formed of silicon. The semiconductor device includes a first region 210 of the substrate 102, which is an active region 210 where trench gate transistors are formed. A trench 104 for forming a transistor gate is shown to be formed within the first region 210. The transistors formed within this region 210 may be the same as those shown in FIG. 1. A drain metal layer 118 is shown on the back surface of the substrate 102, which provides the drain terminal of the transistor.

[0039] In Figure 2A , an insulating layer 110 belonging to the semiconductor device 200 and located on top of the semiconductor substrate 102 is shown. The insulating layer 110 is a dielectric layer, for example, made of a silicate glass material. A plurality of conductive contacts 208 are formed above the first region 210 and within the insulating layer 110, which connect between the source metal layer 214 and the region 106 of the substrate. The source metal layer 214 provides a source voltage to be applied to the source terminal of the transistor via the contacts 208.

[0040] As Figure 2A shown, in addition to the active region 210, the semiconductor device 200 also includes a second region 212 of the substrate 102. The second region 212 includes an ESD protection device, which is also formed in a trench.

[0041] The second region 212 includes an ESD protection device, which is also formed in a trench 202. In Figure 2A the illustrated embodiment, the trench 202 may be formed to have the same trench geometry as the trench 104 of the first region 210, such as the same width, depth, and length. Inside the trench is an insulating material 206, which separates the semiconductor material 204 formed in the trench from the material of the semiconductor substrate 102. The semiconductor material 204 may be polysilicon 204. The semiconductor material 204 formed in the trench includes a first doped region 216 and a second doped region 218. In the multiple examples described herein, the first doped region 216 is a P-doped region, while the second doped region 218 is an N-doped region. However, in an embodiment, the P-doped region and the N-doped region may be reversed, that is, the first doped region 216 described as P-doped in the example may be N-doped, and the second doped region 218 described as N-doped in the example may be P-doped.

[0042] A conductive contact 220 is formed within the insulating layer 110 and is in electrical contact with the P-doped region 216 of the trench 202. Some of these contacts 220 are in electrical contact with a metal layer 222 (the gate metal layer 222 in the Figure 2A example), thereby forming an electrical connection between the gate metal layer 222 and the corresponding P-doped region 216. Some of the contacts 220 are in electrical contact with a metal layer 214 (the source metal layer 214 in the Figure 2A example), thereby forming an electrical connection between the source metal layer 214 and the corresponding P-doped region 216.

[0043] Although the metal layers 214, 222 are shown as the source metal layer 214 and the gate metal layer 222 in the Figure 2A example, the metal layers 214, 222 can be connected to other components other than the source and gate terminals of the transistor. In other embodiments, one of the metal layers 214, 222 can be a drain metal layer for connecting to the drain electrode 118 of the transistor, and the other of the metal layers 214 and 222 can be a gate metal layer. Therefore, the metal layer 214 is described herein as the first metal layer 214, and the metal layer 222 is described herein as the second metal layer 222.

[0044] In addition to the contacts 220 shown in Figure 2A , other contacts can be formed to form connections between the P-doped regions or N-doped regions of different trenches 202, thereby forming a series connection between the ESD protection devices implemented in different trenches 202. These connections will be described in more detail with reference to Figure 4A and Figure 4B .

[0045] Referring to Figure 2B , which illustrates another exemplary embodiment of a semiconductor device, wherein the trench 202 for forming the ESD protection device is larger than the trench 104. The smaller-sized trenches range from 0.6. The trench 202 in this embodiment is a deep trench isolation (DTI) trench. The deep isolation trench can provide a higher breakdown voltage for the resulting ESD protection device. Figure 2A The depth of the smaller-sized trench 202 shown in Figure 2B can be between 0.6 μm and 1.8 μm.

[0046] Referring to Figure 3, which illustrates a top view of the semiconductor device 200. As illustrated, two sets of trenches 104 and 202 extend through the device 200 in another direction (i.e., the Z direction), which is perpendicular to the vertical direction (i.e., the Y direction) in which the trenches are formed in the substrate 102. The trenches 104, 202 are arranged parallel to each other. The gate electrodes 114 are shown as being formed in the trenches 104. As shown, each of the trenches 202 includes a plurality of P-doped regions 216, which are separated from each other by N-doped regions 218.

[0047] Reference Figure 4A , Figure 4B and Figure 4C , which illustrates a view of the second region 212 of the semiconductor device 200. In the example shown, the semiconductor device 100 includes four trenches 202a-d. However, this is just an example, and the number of trenches 202 can be a different number greater than or equal to two. Additionally, the number of the first doped regions 216 is shown as being equal to three, but can be a different number.

[0048] Figure 4A is a top view showing the trenches 202a-d and the conductive structures above the trenches 202. The conductive structures can be made of copper. These conductive structures include the source metal layer 220 and the second metal layer 222 discussed in Reference Figure 2A and Figure 2B . The source metal layer 220 is connected to the P-doped region 216 of the first outer trench 202a, while the second metal layer 222 is connected to the P-doped region 216 of the second outer trench 202d. The conductive structures also include connection electrodes 402 for forming connections between adjacent trenches in the trenches 402a-d. The connection electrodes 402 can also be referred to as connection structures 402 and form another metal layer for forming connections between the trenches 202a-d. Each of the trenches 202a-d is connected to its adjacent trench (one or two of them) through the connection electrode 402. When the potential difference between the first metal layer 214 and the second metal layer 222 is such that no current flows between the metal layers 214, 222, then the connection electrode 402 is at a floating potential.

[0049] The first trench 202a located at one edge of the group of trenches 220a-d is electrically connected to the first metal layer 214 at multiple points. In this example, the semiconductor device 200 includes three contacts 220 implemented in the insulating layer 110, which connect the corresponding P-doped regions 216 of the trench 202a to the corresponding portions of the first metal layer 214.

[0050] The second trench 202b positioned adjacent to the first trench 202a is electrically connected to the first trench 202a at multiple points. A plurality of contacts 400 are formed through the insulating layer 110 for connecting the N-doped regions 218 of the first trench 202a and the second trench 202b to the connection electrodes 402. The connection electrodes 402 are part of another metal layer for forming connections between the trenches 202a-d. In Figure 4A -C example, the device 200 includes three contacts 400 that form an electrical connection between the N-doped region 218 of the trench 202a and the connection structure 402, and three contacts 400 that form an electrical connection between the N-doped region 218 of the trench 202b and the same connection structure 402. Thus, at these three points, the N-doped regions 218 of the trenches 202a, 202b are electrically connected.

[0051] The third trench 202c is positioned adjacent to the second trench 202b and is electrically connected to the second trench 202. The connection is formed between the corresponding P-doped regions 216 of the two trenches 202b, 202c. Contacts formed through the insulating layer 110 connect the P-doped regions of the trenches 202b, 202c to the corresponding connection structures 400. Thus, an electrical connection is formed between the corresponding P-doped regions of the trenches 202b, 202c via the contacts 400 and the connection structures 402.

[0052] The fourth trench 202d is positioned adjacent to the third trench 202c and is located at the edge of the set of trenches opposite to the edge where the first trench 202a is located. A plurality of contacts 400 are formed through the insulating layer 110 for connecting the N-doped regions 218 of the third trench 202a and the fourth trench 202b to the connection electrodes 402, thereby electrically connecting the N-doped regions of the third trench 202c and the fourth trench 202d. Above the fourth trench 202d, a plurality of contacts 220 are formed in contact with the P-doped region 216 of the fourth trench 202d. These contacts 220 are connected to the second metal layer 222.

[0053] By forming the connections between the trenches 202a-d in the described manner, a plurality of parallel electrical connections are formed between the second metal layer 222 and the first metal layer 214. Each parallel connection includes a plurality of ESD protection devices arranged in series for providing a high breakdown voltage such that current flows only in response to a large potential difference, such as the potential difference caused by an ESD event.

[0054] Reference Figure 4B illustrates a further view of the trench 202 and its corresponding contacts 220 / 400, 400. The trench 202 can be Figure 4AAny one of the trenches 202a-d shown in. However, if the trench 202 is one of the outer trenches 202a, d, the contact marked 220 / 400 is the contact 220. On the other hand, if the trench 202 is one of the inner trenches 202b, c, the contact 220 / 400 is the contact 400.

[0055] From Figure 4B It can be seen that a plurality of PN junctions are formed in the trench 202 at each interface between the P-doped region 216 and the corresponding N-doped region 218. This results in the formation of a plurality of ESD protection devices 404 in the trench 202. The ESD protection devices 404 are connected in parallel with each other. In Figure 4A -C example, each ESD protection device 404 includes a single PN junction and is therefore a diode.

[0056] Referring to Figure 5 , which shows an example circuit diagram 500 showing the connection between the second metal layer (represented by "G") and the first metal layer (represented by "S"). Between the second metal layer and the first metal layer, there are a plurality of ESD protection devices 404a-l in the form of diodes. Figure 5 The positions of the ESD protection devices 404a-l in different trenches 202a-d are also shown in. As shown, the ESD protection devices 404a, b, c include PN junctions formed in the trench 202a. Therefore, the ESD protection devices 404a, b, c are connected in parallel with each other between the first metal layer 214 and the N-doped region 218 of the trench 202b.

[0057] The ESD protection devices 404d, e, f include PN junctions formed in the trench 202b. In addition, the ESD protection devices 404g, h, i include PN junctions formed in the trench 202c. Due to the connection electrode 402 between the trenches 202b, c, the ESD protection devices 404d, g form a first pair of ESD protection devices connected in series between the trenches 202b, c, the ESD protection devices 404e, h form a second pair of ESD protection devices connected in series between the trenches 202b, c, and the ESD protection devices 404f, i form a third pair of ESD protection devices connected in series between the trenches 202b, c. Each pair of ESD protection devices in these pairs of ESD protection devices is connected in parallel between the trenches 202b, c.

[0058] The ESD protection devices 404j, k, l include PN junctions formed in the trench 202d. Therefore, the ESD protection devices 404j, k, l are connected in parallel with each other between the second metal layer 222 and the N-doped region 218 of the trench 202d.

[0059] Has been referred to Figure 4A -C andFigure 5 Embodiments are described where only some of the contacts 400 are positioned to contact the P-doped region 216, while other contacts in the contacts 400 are positioned to contact the N-doped region 218. Thus, on the current path through each of the trenches 202a-d between the first metal layer 214 and the second metal layer 222, only a set of parallel PN junctions are present. However, in other embodiments, more P-doped regions may be implemented in each of the trenches 202a-d to add more ESD protection devices to the semiconductor device 200.

[0060] When there is a large potential difference between the first metal layer 214 and the second metal layer 222, the ESD protection devices 404a-l provide protection against ESD events by allowing current to flow through the circuit 500 formed by these devices 404a-l. Since the devices 404a-l include a plurality of diodes 404a-l implemented with different polarities, a relatively large potential difference is required to cause current (flowing from layer 214 to layer 222 or from layer 222 to layer 214) to flow in the opposite direction through some of the diodes. The number of diodes 404a-l connected in series can be increased to increase the breakdown voltage for current to flow between the metal layers 214 and 222 through the circuit 500. The number of diodes 404a-l can be increased by adding more trenches 202 to a set of trenches 202, or by adding additional P-doped regions connected to the connection electrodes 400 (as described below with reference to Figure 6 ). The total current-carrying capacity of the circuit 500 can be increased by adding additional ESD devices connected in parallel. The example circuit 500 has multiple sets of three ESD devices connected in parallel. However, this number can be increased by adding additional P-doped regions and connection electrodes.

[0061] As described above (and as illustrated in Figure 2A and Figure 2B ), the first metal layer 214 can be connected to the source terminal of a transistor formed in the active region. Additionally, the second metal layer 222 can be connected to the gate terminal of a transistor formed in the active region. In the case where there is a large potential difference between the gate terminal and the source terminal of the transistor, current flows through the circuit provided by the ESD protection device trenches 202, and thus the transistor is protected.

[0062] Reference Figure 6 illustrates another example embodiment where additional P-doped regions 216a are implemented in each of the trenches 202 of the device. Due to these additional P-doped regions 216a, multiple PN junctions and multiple NP junctions are implemented in each trench 202.

[0063] Reference Figure 7 illustrates another circuit diagram 700, which represents when, as inFigure 6 When additional P-doped regions 216a are implemented in each of the shown trenches, a circuit is implemented between the first metal layer 214 and the second metal layer 222. As shown, a first group 600a of ESD protection devices are arranged in parallel. These ESD protection devices are formed by PN junctions formed between the P-doped regions 216 and N-doped regions in the first trench 202a. Each ESD protection device in the first group 600a of ESD protection devices is connected to an ESD protection device in a second group 600b of ESD protection devices arranged in parallel. The ESD protection devices in the second group 600b are formed by NP junctions formed between the N-doped regions 218 and additional P-doped regions 216a in the first trench 202a. Assuming that the junctions in the second group 600b are reverse with respect to the junctions in the first group 600a (i.e., the second group 600b is formed by NP junctions while the first group 600a is formed by PN junctions), the polarity of the diodes in the second group 600b is reverse with respect to the polarity of the diodes in the first group 600a.

[0064] The second trench 202b includes a third group 600c of ESD protection devices 202 arranged in parallel, and it is formed by a PN junction between the P-doped region 216 and the N-doped region 218 in this trench 202b. As shown, the associated ESD protection device pairs belonging to the second group 600b and the third group 600c are arranged in series with each other because they are connected through corresponding connection electrodes in a connection electrode 402. The second trench 202b also includes a fourth group 600d of ESD protection devices arranged in parallel, and it is formed by an NP junction between the N-doped region 218 in this trench 202b and the P-doped region in this trench 202b.

[0065] The third trench 202c includes a fifth group 600e of ESD protection devices 202 arranged in parallel, and it is formed by a PN junction between the P-doped region 216 and the N-doped region 218 in this trench 202c. As shown, the paired ESD protection devices belonging to the fourth group 600b and the fifth group 600e are arranged in series with each other because they are connected through corresponding connection electrodes in the connection electrode 402. The third trench 202b also includes a sixth group 600f of ESD protection devices arranged in parallel, and it is formed by an NP junction between the N-doped region 218 in this trench 202c and the P-doped region 216 in this trench 202c.

[0066] The fourth trench 202d includes a seventh group 600g of ESD protection devices 202 arranged in parallel, and is formed by a PN junction between a P-doped region 216 and an N-doped region 218 of the trench 202d. As shown, pairs of ESD protection devices 202 belonging to the sixth group 600f and the seventh group 600g are arranged in series with each other because they are connected by corresponding connection electrodes in the connection electrodes 402. The fourth trench 202d also includes an eighth group 600h of ESD protection devices arranged parallel to each other, and is formed by an NP junction between the N-doped region 218 of the trench 202d and the P-doped region 216 of the trench 202d. The eighth group 600h of ESD protection devices is connected to the second metal layer 222.

[0067] Reference Figure 8 , which illustrates an example trench 202 according to another embodiment of the present application. The trench 202 may be the same as the example trench 202 described above with respect to Figure 4B but further includes additional P-doped regions 804. These are heavily P-doped regions 804. The additional P-doped regions 804 are more heavily doped than the P-doped region 216. The additional P-doped regions 804 may be a byproduct of the trench gate transistor manufacturing process and can thus enable better integration with the trench gate transistor. The additional P-doped regions 804 may be of the same material as the P-doped region that contacts the source terminal 116 of the trench gate transistor. The combination of the lighter P-doped region 216 and the heavier P-doped region 804 provides a higher breakdown voltage for the ESD protection device.

[0068] A number of different example embodiments have been described. Different aspects of these embodiments may be combined. For example, Figure 2A and Figure 2B describe the use of different trench geometries for the trench 202. Any of these trench geometries can be used for Figure 4A -C, Figure 6 or Figure 8 in any of the embodiments. Additionally, Figure 8 describes an example embodiment in which additional heavily doped regions are added to the trench 202. These additional heavily doped regions can also be applied to embodiments in which additional first doped regions 216a are present in each trench 202 (e.g., as shown in Figure 6 ).

[0069] Reference Figure 9 , which illustrates stages as part of a process for fabricating the trench 202 for the ESD protection device. Figure 9 The example trench shown in

[0070] In stage 1, a substrate 102 is provided. The substrate 102 is a semiconductor substrate 102, which may be a silicon substrate.

[0071] In stage 2, trenches 202 are formed in the substrate 102 by trench etching. After etching the trenches, a sacrificial oxide layer is grown on the walls of the trenches 202 and then removed. Then an oxide liner 206 can be formed on the walls of the trenches 202. The oxide liner 206 formed in the trenches 202 is the same material as the gate oxide 114 that provides the insulating layer 114 for the gate trench 104 and is deposited in the same manner. The oxide layer 206 forms an insulating layer 206. Then a polysilicon layer 204 is deposited to fill the trenches 202 by intrinsic polysilicon deposition.

[0072] In stage 3, a second doped region 218 of the trenches 202 is implanted. Then a contact mask is used to define a first doped region 216 and the first doped region is implanted. Then, an electrically insulating layer 110 is formed on the surface of the substrate 102.

[0073] In stage 4, contacts 900 are etched through the insulating layer 110 to form connections with the first doped region 216 and the second doped region 218 through the insulating layer 110. Each contact in the contacts 900 is one of the contacts 220 / 400 discussed above. Then, a metal layer 902 is deposited on each contact in the contacts. Each metal layer in the metal layer 902 is a connecting electrode 402 or a part of the first metal layer 214 or the second metal layer 222.

[0074] Figure 9 The process for constructing one trench 202 is illustrated, but a similar process can also be followed for constructing other similar trenches 202. The metal layer 902 is formed on different trenches 202 to connect the trenches 202 between the first metal layer 214 and the second metal layer 222, for example, as discussed with respect to Figure 4A 、 Figure 5 or Figure 7 discussed.

[0075] A process similar to that illustrated with Figure 9 can be applied to produce Figure 6 and Figure 8 the example trenches 202 shown. In the case of the embodiment of Figure 6 , the process may be the same, but an additional first doped region implantation 216a is added in stage 3. In the case of the embodiment of Figure 8 , the process may be the same, but a heavily doped region implantation 804 is added in Figure 8 .

[0076] It should be understood that the embodiments have been described by way of example.

Claims

1. A semiconductor device, comprising: A semiconductor substrate, the semiconductor substrate comprising a plurality of trenches arranged in parallel, each of the trenches comprising a semiconductor, and the semiconductor comprising a plurality of first doping regions and second doping regions; and a plurality of trench electrostatic discharge protection devices, wherein the plurality of trench electrostatic discharge protection devices are formed in the trench and connected between a first metal layer formed above the semiconductor substrate and a second metal layer formed above the semiconductor substrate, wherein each of the plurality of trenches comprises two or more of the trench electrostatic discharge protection devices, wherein each of the plurality of trench electrostatic discharge protection devices comprises at least one of a PN junction or an NP junction formed between one of the first doping regions and the second doping region in the corresponding trench, The semiconductor device further comprises a plurality of connection electrodes formed above the semiconductor substrate for connecting the electrostatic discharge protection device of each trench to the electrostatic protection device of at least one adjacent trench of the trench, wherein for a first outer trench among the trenches, the electrostatic discharge protection device of the first outer trench among the trenches is connected in parallel with the first metal layer, Wherein for a second outer trench in the trench, the electrostatic discharge protection device of the second outer trench in the trench is connected in parallel with the second metal layer.

2. The semiconductor device according to claim 1 , wherein the plurality of trenches are a plurality of second trenches provided in a second region of the semiconductor substrate, The semiconductor device further comprises at least one first trench arranged in a first region defined in the semiconductor substrate, wherein one or more trench gate transistor devices are arranged in the first device region, and the one or more trench gate transistor devices comprise a gate arranged in the at least one first trench.

3. The semiconductor device of claim 2 , wherein the first metal layer is electrically connected to a first terminal of each of the trench gate transistor devices, Wherein the second metal layer is electrically connected to a second terminal of each of the trench gate transistor devices. 4 . The semiconductor device according to claim 2 , wherein the second trench is deeper than the at least one first trench. 5 . The semiconductor device according to claim 1 , wherein each of the connecting electrodes is electrically connected between two corresponding first doping regions of adjacent ones of the trenches. 6 . The semiconductor device according to claim 1 , wherein some of the connection electrodes are connected to the second doping regions belonging to different trenches.

7. A semiconductor device according to any one of claims 1 to 4, wherein each of the grooves includes a third doping region, the third doping region is electrically connected to a connecting electrode in the connecting electrodes connecting the corresponding grooves, wherein each of the third doping regions includes the same doping type as the first doping region, and wherein the third doping region is more heavily doped than the first doping region.

8. A semiconductor device according to any preceding claim, wherein the first metal layer is a source metal layer connected to a source terminal of a transistor of the semiconductor device.

9. A semiconductor device according to any preceding claim, wherein the second metal layer is a gate metal layer connected to a gate terminal of a transistor of the semiconductor device.

10. A method of manufacturing a semiconductor device according to any preceding claim, comprising producing each of the trenches by the following steps: etching the corresponding trenches in the semiconductor substrate; implanting each of the first doped region and the second doped region into the corresponding trench; forming an insulating layer on the corresponding trench; forming an electrical contact through the insulating layer between the first doped region and the second doped region of the corresponding trench, the method further comprising: forming the connection electrodes to connect the trenches by connecting the connection electrodes to some of the electrical contacts; as well as The first metal layer and the second metal layer are formed, including connecting them to others of the electrical contacts.

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